lib/gen8_render.h

   1 #ifndef GEN7_RENDER_H
   2 #define GEN7_RENDER_H
   3
   4 #include "gen6_render.h"
   5
   6 #define GEN7_3DSTATE_URB_VS (0x7830 << 16)
   7 #define GEN7_3DSTATE_URB_HS (0x7831 << 16)
   8 #define GEN7_3DSTATE_URB_DS (0x7832 << 16)
   9 #define GEN7_3DSTATE_URB_GS (0x7833 << 16)
  10
  11 #define GEN6_3DSTATE_SCISSOR_STATE_POINTERS     GEN6_3D(3, 0, 0xf)
  12 #define GEN7_3DSTATE_CLEAR_PARAMS               GEN6_3D(3, 0, 0x04)
  13 #define GEN7_3DSTATE_DEPTH_BUFFER               GEN6_3D(3, 0, 0x05)
  14 #define GEN7_3DSTATE_STENCIL_BUFFER             GEN6_3D(3, 0, 0x06)
  15 #define GEN7_3DSTATE_HIER_DEPTH_BUFFER          GEN6_3D(3, 0, 0x07)
  16
  17 #define GEN7_3DSTATE_GS                         GEN6_3D(3, 0, 0x11)
  18 #define GEN7_3DSTATE_CONSTANT_GS                GEN6_3D(3, 0, 0x16)
  19 #define GEN7_3DSTATE_CONSTANT_HS                GEN6_3D(3, 0, 0x19)
  20 #define GEN7_3DSTATE_CONSTANT_DS                GEN6_3D(3, 0, 0x1a)
  21 #define GEN7_3DSTATE_HS                         GEN6_3D(3, 0, 0x1b)
  22 #define GEN7_3DSTATE_TE                         GEN6_3D(3, 0, 0x1c)
  23 #define GEN7_3DSTATE_DS                         GEN6_3D(3, 0, 0x1d)
  24 #define GEN7_3DSTATE_STREAMOUT                  GEN6_3D(3, 0, 0x1e)
  25 #define GEN7_3DSTATE_SBE                        GEN6_3D(3, 0, 0x1f)
  26 #define GEN7_3DSTATE_PS                         GEN6_3D(3, 0, 0x20)
  27 #define GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP    \
  28                                                 GEN6_3D(3, 0, 0x21)
  29 #define GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC GEN6_3D(3, 0, 0x23)
  30 #define GEN7_3DSTATE_BLEND_STATE_POINTERS       GEN6_3D(3, 0, 0x24)
  31 #define GEN7_3DSTATE_DS_STATE_POINTERS          GEN6_3D(3, 0, 0x25)
  32 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS  GEN6_3D(3, 0, 0x26)
  33 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS  GEN6_3D(3, 0, 0x27)
  34 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS  GEN6_3D(3, 0, 0x28)
  35 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS  GEN6_3D(3, 0, 0x29)
  36 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS  GEN6_3D(3, 0, 0x2a)
  37
  38 #define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS  GEN6_3D(3, 0, 0x2b)
  39 #define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_HS  GEN6_3D(3, 0, 0x2c)
  40 #define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_DS  GEN6_3D(3, 0, 0x2d)
  41 #define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_GS  GEN6_3D(3, 0, 0x2e)
  42 #define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS  GEN6_3D(3, 0, 0x2f)
  43
  44 #define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS     GEN6_3D(3, 1, 0x12)
  45 #define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_HS     GEN6_3D(3, 1, 0x13)
  46 #define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_DS     GEN6_3D(3, 1, 0x14)
  47 #define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_GS     GEN6_3D(3, 1, 0x15)
  48 #define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS     GEN6_3D(3, 1, 0x16)
  49
  50 /* Some random bits that we care about */
  51 #define GEN7_VB0_BUFFER_ADDR_MOD_EN             (1 << 14)
  52 #define GEN7_WM_DISPATCH_ENABLE                 (1 << 29)
  53 #define GEN7_3DSTATE_PS_PERSPECTIVE_PIXEL_BARYCENTRIC (1 << 11)
  54 #define GEN7_3DSTATE_PS_ATTRIBUTE_ENABLED        (1 << 10)
  55
  56 /* Random shifts */
  57 #define GEN7_3DSTATE_WM_MAX_THREADS_SHIFT 24
  58 #define HSW_3DSTATE_WM_MAX_THREADS_SHIFT 23
  59
  60 /* Shamelessly ripped from mesa */
  61 struct gen8_surface_state
  62 {
  63         struct {
  64                 uint32_t cube_pos_z:1;
  65                 uint32_t cube_neg_z:1;
  66                 uint32_t cube_pos_y:1;
  67                 uint32_t cube_neg_y:1;
  68                 uint32_t cube_pos_x:1;
  69                 uint32_t cube_neg_x:1;
  70                 uint32_t media_boundary_pixel_mode:2;
  71                 uint32_t render_cache_read_write:1;
  72                 uint32_t smapler_l2_bypass:1;
  73                 uint32_t vert_line_stride_ofs:1;
  74                 uint32_t vert_line_stride:1;
  75                 uint32_t tiled_mode:2;
  76                 uint32_t horizontal_alignment:2;
  77                 uint32_t vertical_alignment:2;
  78                 uint32_t surface_format:9;     /**< BRW_SURFACEFORMAT_x */
  79                 uint32_t pad0:1;
  80                 uint32_t is_array:1;
  81                 uint32_t surface_type:3;       /**< BRW_SURFACE_1D/2D/3D/CUBE */
  82         } ss0;
  83
  84         struct {
  85                 uint32_t qpitch:15;
  86                 uint32_t pad1:4;
  87                 uint32_t base_mip_level:5;
  88                 uint32_t memory_object_control:7;
  89                 uint32_t pad0:1;
  90         } ss1;
  91
  92         struct {
  93                 uint32_t width:14;
  94                 uint32_t pad1:2;
  95                 uint32_t height:14;
  96                 uint32_t pad0:2;
  97         } ss2;
  98
  99         struct {
 100                 uint32_t pitch:18;
 101                 uint32_t pad:3;
 102                 uint32_t depth:11;
 103         } ss3;
 104
 105         struct {
 106                 uint32_t minimum_array_element:27;
 107                 uint32_t pad0:5;
 108         } ss4;
 109
 110         struct {
 111                 uint32_t mip_count:4;
 112                 uint32_t min_lod:4;
 113                 uint32_t pad3:6;
 114                 uint32_t coherency_type:1;
 115                 uint32_t pad2:5;
 116                 uint32_t ewa_disable_for_cube:1;
 117                 uint32_t y_offset:3;
 118                 uint32_t pad0:1;
 119                 uint32_t x_offset:7;
 120         } ss5;
 121
 122         struct {
 123                 uint32_t pad; /* Multisample Control Surface stuff */
 124         } ss6;
 125
 126         struct {
 127                 uint32_t resource_min_lod:12;
 128
 129                 /* Only on Haswell */
 130                 uint32_t pad0:4;
 131                 uint32_t shader_chanel_select_a:3;
 132                 uint32_t shader_chanel_select_b:3;
 133                 uint32_t shader_chanel_select_g:3;
 134                 uint32_t shader_chanel_select_r:3;
 135
 136                 uint32_t alpha_clear_color:1;
 137                 uint32_t blue_clear_color:1;
 138                 uint32_t green_clear_color:1;
 139                 uint32_t red_clear_color:1;
 140         } ss7;
 141
 142         struct {
 143                 uint32_t base_addr;
 144         } ss8;
 145
 146         struct {
 147                 uint32_t base_addr_hi:16;
 148                 uint32_t pad0:16;
 149         } ss9;
 150
 151         struct {
 152                 uint32_t pad0:12;
 153                 uint32_t aux_base_addr:20;
 154         } ss10;
 155
 156         struct {
 157                 uint32_t aux_base_addr_hi:16;
 158                 uint32_t pad:16;
 159         } ss11;
 160
 161         struct {
 162                 uint32_t hiz_depth_clear_value;
 163         } ss12;
 164
 165         struct {
 166                 uint32_t reserved;
 167         } ss13;
 168
 169         struct {
 170                 uint32_t reserved;
 171         } ss14;
 172
 173         struct {
 174                 uint32_t reserved;
 175         } ss15;
 176 };
 177
 178 struct gen8_sampler_state
 179 {
 180         struct
 181         {
 182                 uint32_t aniso_algorithm:1;
 183                 uint32_t lod_bias:13;
 184                 uint32_t min_filter:3;
 185                 uint32_t mag_filter:3;
 186                 uint32_t mip_filter:2;
 187                 uint32_t base_level:5;
 188                 uint32_t lod_preclamp:2;
 189                 uint32_t default_color_mode:1;
 190                 uint32_t pad0:1;
 191                 uint32_t disable:1;
 192         } ss0;
 193
 194         struct
 195         {
 196                 uint32_t cube_control_mode:1;
 197                 uint32_t shadow_function:3;
 198                 uint32_t chromakey_mode:1;
 199                 uint32_t chromakey_index:2;
 200                 uint32_t chromakey_enable:1;
 201                 uint32_t max_lod:12;
 202                 uint32_t min_lod:12;
 203         } ss1;
 204
 205         struct
 206         {
 207                 uint32_t lod_clamp_mag_mode:1;
 208                 uint32_t flexible_filter_valign:1;
 209                 uint32_t flexible_filter_halign:1;
 210                 uint32_t flexible_filter_coeff_size:1;
 211                 uint32_t flexible_filter_mode:1;
 212                 uint32_t pad1:1;
 213                 uint32_t indirect_state_ptr:18;
 214                 uint32_t pad0:2;
 215                 uint32_t sep_filter_height:2;
 216                 uint32_t sep_filter_width:2;
 217                 uint32_t sep_filter_coeff_table_size:2;
 218         } ss2;
 219
 220         struct
 221         {
 222                 uint32_t r_wrap_mode:3;
 223                 uint32_t t_wrap_mode:3;
 224                 uint32_t s_wrap_mode:3;
 225                 uint32_t pad:1;
 226                 uint32_t non_normalized_coord:1;
 227                 uint32_t trilinear_quality:2;
 228                 uint32_t address_round:6;
 229                 uint32_t max_aniso:3;
 230                 uint32_t pad0:2;
 231                 uint32_t non_sep_filter_footprint_mask:8;
 232         } ss3;
 233 };
 234
 235 struct gen8_blend_state {
 236         struct {
 237                 uint32_t pad0:19;
 238                 uint32_t y_dither_offset:2;
 239                 uint32_t x_dither_offset:2;
 240                 uint32_t dither_enable:1;
 241                 uint32_t alpha_test_func:3;
 242                 uint32_t alpha_test:1;
 243                 uint32_t alpha_to_coverage_dither:1;
 244                 uint32_t alpha_to_one:1;
 245                 uint32_t ia_blend:1;
 246                 uint32_t alpha_to_coverage:1;
 247         } bs0;
 248
 249         struct {
 250                 uint64_t write_disable_blue:1;
 251                 uint64_t write_disable_green:1;
 252                 uint64_t write_disable_red:1;
 253                 uint64_t write_disable_alpha:1;
 254                 uint64_t pad1:1;
 255                 uint64_t alpha_blend_func:3;
 256                 uint64_t dest_alpha_blend_factor:5;
 257                 uint64_t source_alpha_blend_factor:5;
 258                 uint64_t color_blend_func:3;
 259                 uint64_t dest_blend_factor:5;
 260                 uint64_t source_blend_factor:5;
 261                 uint64_t color_buffer_blend:1;
 262                 uint64_t post_blend_color_clamp:1;
 263                 uint64_t pre_blend_color_clamp:1;
 264                 uint64_t color_clamp_range:2;
 265                 uint64_t pre_blend_source_only_clamp:1;
 266                 uint64_t pad0:22;
 267                 uint64_t logic_op_func:4;
 268                 uint64_t logic_op_enable:1;
 269         } bs[16];
 270 };
 271
 272 struct gen7_sf_clip_viewport {
 273         struct {
 274                 float m00;
 275                 float m11;
 276                 float m22;
 277                 float m30;
 278                 float m31;
 279                 float m32;
 280         } viewport;
 281
 282         uint32_t pad0[2];
 283
 284         struct {
 285                 float xmin;
 286                 float xmax;
 287                 float ymin;
 288                 float ymax;
 289         } guardband;
 290
 291         float pad1[4];
 292 };
 293
 294 struct gen6_scissor_rect
 295 {
 296         uint32_t xmin:16;
 297         uint32_t ymin:16;
 298         uint32_t xmax:16;
 299         uint32_t ymax:16;
 300 };
 301
 302 #endif