1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2011 The Chromium OS Authors.
15 #include <dm/of_extra.h>
19 #include <fdt_support.h>
22 #include <linux/libfdt.h>
24 #include <asm/global_data.h>
25 #include <asm/sections.h>
26 #include <linux/ctype.h>
27 #include <linux/lzo.h>
28 #include <linux/ioport.h>
30 DECLARE_GLOBAL_DATA_PTR;
33 * Here are the type we know about. One day we might allow drivers to
34 * register. For now we just put them here. The COMPAT macro allows us to
35 * turn this into a sparse list later, and keeps the ID with the name.
37 * NOTE: This list is basically a TODO list for things that need to be
38 * converted to driver model. So don't add new things here unless there is a
39 * good reason why driver-model conversion is infeasible. Examples include
40 * things which are used before driver model is available.
42 #define COMPAT(id, name) name
43 static const char * const compat_names[COMPAT_COUNT] = {
44 COMPAT(UNKNOWN, "<none>"),
45 COMPAT(NVIDIA_TEGRA20_EMC, "nvidia,tegra20-emc"),
46 COMPAT(NVIDIA_TEGRA20_EMC_TABLE, "nvidia,tegra20-emc-table"),
47 COMPAT(NVIDIA_TEGRA20_NAND, "nvidia,tegra20-nand"),
48 COMPAT(NVIDIA_TEGRA124_XUSB_PADCTL, "nvidia,tegra124-xusb-padctl"),
49 COMPAT(NVIDIA_TEGRA210_XUSB_PADCTL, "nvidia,tegra210-xusb-padctl"),
50 COMPAT(SMSC_LAN9215, "smsc,lan9215"),
51 COMPAT(SAMSUNG_EXYNOS5_SROMC, "samsung,exynos-sromc"),
52 COMPAT(SAMSUNG_EXYNOS_USB_PHY, "samsung,exynos-usb-phy"),
53 COMPAT(SAMSUNG_EXYNOS5_USB3_PHY, "samsung,exynos5250-usb3-phy"),
54 COMPAT(SAMSUNG_EXYNOS_TMU, "samsung,exynos-tmu"),
55 COMPAT(SAMSUNG_EXYNOS_MIPI_DSI, "samsung,exynos-mipi-dsi"),
56 COMPAT(SAMSUNG_EXYNOS_DWMMC, "samsung,exynos-dwmmc"),
57 COMPAT(GENERIC_SPI_FLASH, "jedec,spi-nor"),
58 COMPAT(SAMSUNG_EXYNOS_SYSMMU, "samsung,sysmmu-v3.3"),
59 COMPAT(INTEL_MICROCODE, "intel,microcode"),
60 COMPAT(INTEL_QRK_MRC, "intel,quark-mrc"),
61 COMPAT(ALTERA_SOCFPGA_DWMAC, "altr,socfpga-stmmac"),
62 COMPAT(ALTERA_SOCFPGA_DWMMC, "altr,socfpga-dw-mshc"),
63 COMPAT(ALTERA_SOCFPGA_DWC2USB, "snps,dwc2"),
64 COMPAT(INTEL_BAYTRAIL_FSP, "intel,baytrail-fsp"),
65 COMPAT(INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
66 COMPAT(INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"),
67 COMPAT(COMPAT_SUNXI_NAND, "allwinner,sun4i-a10-nand"),
68 COMPAT(ALTERA_SOCFPGA_CLK, "altr,clk-mgr"),
69 COMPAT(ALTERA_SOCFPGA_PINCTRL_SINGLE, "pinctrl-single"),
70 COMPAT(ALTERA_SOCFPGA_H2F_BRG, "altr,socfpga-hps2fpga-bridge"),
71 COMPAT(ALTERA_SOCFPGA_LWH2F_BRG, "altr,socfpga-lwhps2fpga-bridge"),
72 COMPAT(ALTERA_SOCFPGA_F2H_BRG, "altr,socfpga-fpga2hps-bridge"),
73 COMPAT(ALTERA_SOCFPGA_F2SDR0, "altr,socfpga-fpga2sdram0-bridge"),
74 COMPAT(ALTERA_SOCFPGA_F2SDR1, "altr,socfpga-fpga2sdram1-bridge"),
75 COMPAT(ALTERA_SOCFPGA_F2SDR2, "altr,socfpga-fpga2sdram2-bridge"),
76 COMPAT(ALTERA_SOCFPGA_FPGA0, "altr,socfpga-a10-fpga-mgr"),
77 COMPAT(ALTERA_SOCFPGA_NOC, "altr,socfpga-a10-noc"),
78 COMPAT(ALTERA_SOCFPGA_CLK_INIT, "altr,socfpga-a10-clk-init")
81 const char *fdtdec_get_compatible(enum fdt_compat_id id)
83 /* We allow reading of the 'unknown' ID for testing purposes */
84 assert(id >= 0 && id < COMPAT_COUNT);
85 return compat_names[id];
88 fdt_addr_t fdtdec_get_addr_size_fixed(const void *blob, int node,
89 const char *prop_name, int index, int na,
90 int ns, fdt_size_t *sizep,
93 const fdt32_t *prop, *prop_end;
94 const fdt32_t *prop_addr, *prop_size, *prop_after_size;
98 debug("%s: %s: ", __func__, prop_name);
100 prop = fdt_getprop(blob, node, prop_name, &len);
102 debug("(not found)\n");
103 return FDT_ADDR_T_NONE;
105 prop_end = prop + (len / sizeof(*prop));
107 prop_addr = prop + (index * (na + ns));
108 prop_size = prop_addr + na;
109 prop_after_size = prop_size + ns;
110 if (prop_after_size > prop_end) {
111 debug("(not enough data: expected >= %d cells, got %d cells)\n",
112 (u32)(prop_after_size - prop), ((u32)(prop_end - prop)));
113 return FDT_ADDR_T_NONE;
116 #if CONFIG_IS_ENABLED(OF_TRANSLATE)
118 addr = fdt_translate_address(blob, node, prop_addr);
121 addr = fdtdec_get_number(prop_addr, na);
124 *sizep = fdtdec_get_number(prop_size, ns);
125 debug("addr=%08llx, size=%llx\n", (unsigned long long)addr,
126 (unsigned long long)*sizep);
128 debug("addr=%08llx\n", (unsigned long long)addr);
134 fdt_addr_t fdtdec_get_addr_size_auto_parent(const void *blob, int parent,
135 int node, const char *prop_name,
136 int index, fdt_size_t *sizep,
141 debug("%s: ", __func__);
143 na = fdt_address_cells(blob, parent);
145 debug("(bad #address-cells)\n");
146 return FDT_ADDR_T_NONE;
149 ns = fdt_size_cells(blob, parent);
151 debug("(bad #size-cells)\n");
152 return FDT_ADDR_T_NONE;
155 debug("na=%d, ns=%d, ", na, ns);
157 return fdtdec_get_addr_size_fixed(blob, node, prop_name, index, na,
158 ns, sizep, translate);
161 fdt_addr_t fdtdec_get_addr_size_auto_noparent(const void *blob, int node,
162 const char *prop_name, int index,
168 debug("%s: ", __func__);
170 parent = fdt_parent_offset(blob, node);
172 debug("(no parent found)\n");
173 return FDT_ADDR_T_NONE;
176 return fdtdec_get_addr_size_auto_parent(blob, parent, node, prop_name,
177 index, sizep, translate);
180 fdt_addr_t fdtdec_get_addr_size(const void *blob, int node,
181 const char *prop_name, fdt_size_t *sizep)
183 int ns = sizep ? (sizeof(fdt_size_t) / sizeof(fdt32_t)) : 0;
185 return fdtdec_get_addr_size_fixed(blob, node, prop_name, 0,
186 sizeof(fdt_addr_t) / sizeof(fdt32_t),
190 fdt_addr_t fdtdec_get_addr(const void *blob, int node, const char *prop_name)
192 return fdtdec_get_addr_size(blob, node, prop_name, NULL);
195 #if CONFIG_IS_ENABLED(PCI) && defined(CONFIG_DM_PCI)
196 int fdtdec_get_pci_vendev(const void *blob, int node, u16 *vendor, u16 *device)
198 const char *list, *end;
201 list = fdt_getprop(blob, node, "compatible", &len);
208 if (len >= strlen("pciVVVV,DDDD")) {
209 char *s = strstr(list, "pci");
212 * check if the string is something like pciVVVV,DDDD.RR
213 * or just pciVVVV,DDDD
215 if (s && s[7] == ',' &&
216 (s[12] == '.' || s[12] == 0)) {
218 *vendor = simple_strtol(s, NULL, 16);
221 *device = simple_strtol(s, NULL, 16);
232 int fdtdec_get_pci_bar32(const struct udevice *dev, struct fdt_pci_addr *addr,
237 /* extract the bar number from fdt_pci_addr */
238 barnum = addr->phys_hi & 0xff;
239 if (barnum < PCI_BASE_ADDRESS_0 || barnum > PCI_CARDBUS_CIS)
242 barnum = (barnum - PCI_BASE_ADDRESS_0) / 4;
243 *bar = dm_pci_read_bar32(dev, barnum);
248 int fdtdec_get_pci_bus_range(const void *blob, int node,
249 struct fdt_resource *res)
254 values = fdt_getprop(blob, node, "bus-range", &len);
255 if (!values || len < sizeof(*values) * 2)
258 res->start = fdt32_to_cpu(*values++);
259 res->end = fdt32_to_cpu(*values);
265 uint64_t fdtdec_get_uint64(const void *blob, int node, const char *prop_name,
266 uint64_t default_val)
268 const unaligned_fdt64_t *cell64;
271 cell64 = fdt_getprop(blob, node, prop_name, &length);
272 if (!cell64 || length < sizeof(*cell64))
275 return fdt64_to_cpu(*cell64);
278 int fdtdec_get_is_enabled(const void *blob, int node)
283 * It should say "okay", so only allow that. Some fdts use "ok" but
284 * this is a bug. Please fix your device tree source file. See here
287 * http://www.mail-archive.com/u-boot@lists.denx.de/msg71598.html
289 cell = fdt_getprop(blob, node, "status", NULL);
291 return strcmp(cell, "okay") == 0;
295 enum fdt_compat_id fdtdec_lookup(const void *blob, int node)
297 enum fdt_compat_id id;
299 /* Search our drivers */
300 for (id = COMPAT_UNKNOWN; id < COMPAT_COUNT; id++)
301 if (fdt_node_check_compatible(blob, node,
302 compat_names[id]) == 0)
304 return COMPAT_UNKNOWN;
307 int fdtdec_next_compatible(const void *blob, int node, enum fdt_compat_id id)
309 return fdt_node_offset_by_compatible(blob, node, compat_names[id]);
312 int fdtdec_next_compatible_subnode(const void *blob, int node,
313 enum fdt_compat_id id, int *depthp)
316 node = fdt_next_node(blob, node, depthp);
317 } while (*depthp > 1);
319 /* If this is a direct subnode, and compatible, return it */
320 if (*depthp == 1 && 0 == fdt_node_check_compatible(
321 blob, node, compat_names[id]))
324 return -FDT_ERR_NOTFOUND;
327 int fdtdec_next_alias(const void *blob, const char *name, enum fdt_compat_id id,
330 #define MAX_STR_LEN 20
331 char str[MAX_STR_LEN + 20];
334 /* snprintf() is not available */
335 assert(strlen(name) < MAX_STR_LEN);
336 sprintf(str, "%.*s%d", MAX_STR_LEN, name, *upto);
337 node = fdt_path_offset(blob, str);
340 err = fdt_node_check_compatible(blob, node, compat_names[id]);
344 return -FDT_ERR_NOTFOUND;
349 int fdtdec_find_aliases_for_id(const void *blob, const char *name,
350 enum fdt_compat_id id, int *node_list,
353 memset(node_list, '\0', sizeof(*node_list) * maxcount);
355 return fdtdec_add_aliases_for_id(blob, name, id, node_list, maxcount);
358 /* TODO: Can we tighten this code up a little? */
359 int fdtdec_add_aliases_for_id(const void *blob, const char *name,
360 enum fdt_compat_id id, int *node_list,
363 int name_len = strlen(name);
371 /* find the alias node if present */
372 alias_node = fdt_path_offset(blob, "/aliases");
375 * start with nothing, and we can assume that the root node can't
378 memset(nodes, '\0', sizeof(nodes));
380 /* First find all the compatible nodes */
381 for (node = count = 0; node >= 0 && count < maxcount;) {
382 node = fdtdec_next_compatible(blob, node, id);
384 nodes[count++] = node;
387 debug("%s: warning: maxcount exceeded with alias '%s'\n",
390 /* Now find all the aliases */
391 for (offset = fdt_first_property_offset(blob, alias_node);
393 offset = fdt_next_property_offset(blob, offset)) {
394 const struct fdt_property *prop;
400 prop = fdt_get_property_by_offset(blob, offset, NULL);
401 path = fdt_string(blob, fdt32_to_cpu(prop->nameoff));
402 if (prop->len && 0 == strncmp(path, name, name_len))
403 node = fdt_path_offset(blob, prop->data);
407 /* Get the alias number */
408 number = simple_strtoul(path + name_len, NULL, 10);
409 if (number < 0 || number >= maxcount) {
410 debug("%s: warning: alias '%s' is out of range\n",
415 /* Make sure the node we found is actually in our list! */
417 for (j = 0; j < count; j++)
418 if (nodes[j] == node) {
424 debug("%s: warning: alias '%s' points to a node "
425 "'%s' that is missing or is not compatible "
426 " with '%s'\n", __func__, path,
427 fdt_get_name(blob, node, NULL),
433 * Add this node to our list in the right place, and mark
436 if (fdtdec_get_is_enabled(blob, node)) {
437 if (node_list[number]) {
438 debug("%s: warning: alias '%s' requires that "
439 "a node be placed in the list in a "
440 "position which is already filled by "
441 "node '%s'\n", __func__, path,
442 fdt_get_name(blob, node, NULL));
445 node_list[number] = node;
446 if (number >= num_found)
447 num_found = number + 1;
452 /* Add any nodes not mentioned by an alias */
453 for (i = j = 0; i < maxcount; i++) {
455 for (; j < maxcount; j++)
457 fdtdec_get_is_enabled(blob, nodes[j]))
460 /* Have we run out of nodes to add? */
464 assert(!node_list[i]);
465 node_list[i] = nodes[j++];
474 int fdtdec_get_alias_seq(const void *blob, const char *base, int offset,
477 int base_len = strlen(base);
478 const char *find_name;
483 find_name = fdt_get_name(blob, offset, &find_namelen);
484 debug("Looking for '%s' at %d, name %s\n", base, offset, find_name);
486 aliases = fdt_path_offset(blob, "/aliases");
487 for (prop_offset = fdt_first_property_offset(blob, aliases);
489 prop_offset = fdt_next_property_offset(blob, prop_offset)) {
495 prop = fdt_getprop_by_offset(blob, prop_offset, &name, &len);
496 debug(" - %s, %s\n", name, prop);
497 if (len < find_namelen || *prop != '/' || prop[len - 1] ||
498 strncmp(name, base, base_len))
501 slash = strrchr(prop, '/');
502 if (strcmp(slash + 1, find_name))
506 * Adding an extra check to distinguish DT nodes with
509 if (IS_ENABLED(CONFIG_PHANDLE_CHECK_SEQ)) {
510 if (fdt_get_phandle(blob, offset) !=
511 fdt_get_phandle(blob, fdt_path_offset(blob, prop)))
515 val = trailing_strtol(name);
518 debug("Found seq %d\n", *seqp);
523 debug("Not found\n");
527 int fdtdec_get_alias_highest_id(const void *blob, const char *base)
529 int base_len = strlen(base);
534 debug("Looking for highest alias id for '%s'\n", base);
536 aliases = fdt_path_offset(blob, "/aliases");
537 for (prop_offset = fdt_first_property_offset(blob, aliases);
539 prop_offset = fdt_next_property_offset(blob, prop_offset)) {
544 prop = fdt_getprop_by_offset(blob, prop_offset, &name, &len);
545 debug(" - %s, %s\n", name, prop);
546 if (*prop != '/' || prop[len - 1] ||
547 strncmp(name, base, base_len))
550 val = trailing_strtol(name);
552 debug("Found seq %d\n", val);
560 const char *fdtdec_get_chosen_prop(const void *blob, const char *name)
566 chosen_node = fdt_path_offset(blob, "/chosen");
567 return fdt_getprop(blob, chosen_node, name, NULL);
570 int fdtdec_get_chosen_node(const void *blob, const char *name)
574 prop = fdtdec_get_chosen_prop(blob, name);
576 return -FDT_ERR_NOTFOUND;
577 return fdt_path_offset(blob, prop);
580 int fdtdec_check_fdt(void)
583 * We must have an FDT, but we cannot panic() yet since the console
584 * is not ready. So for now, just assert(). Boards which need an early
585 * FDT (prior to console ready) will need to make their own
586 * arrangements and do their own checks.
588 assert(!fdtdec_prepare_fdt());
593 * This function is a little odd in that it accesses global data. At some
594 * point if the architecture board.c files merge this will make more sense.
595 * Even now, it is common code.
597 int fdtdec_prepare_fdt(void)
599 if (!gd->fdt_blob || ((uintptr_t)gd->fdt_blob & 3) ||
600 fdt_check_header(gd->fdt_blob)) {
601 #ifdef CONFIG_SPL_BUILD
602 puts("Missing DTB\n");
604 printf("No valid device tree binary found at %p\n",
608 printf("fdt_blob=%p\n", gd->fdt_blob);
609 print_buffer((ulong)gd->fdt_blob, gd->fdt_blob, 4,
619 int fdtdec_lookup_phandle(const void *blob, int node, const char *prop_name)
624 debug("%s: %s\n", __func__, prop_name);
625 phandle = fdt_getprop(blob, node, prop_name, NULL);
627 return -FDT_ERR_NOTFOUND;
629 lookup = fdt_node_offset_by_phandle(blob, fdt32_to_cpu(*phandle));
634 * Look up a property in a node and check that it has a minimum length.
636 * @param blob FDT blob
637 * @param node node to examine
638 * @param prop_name name of property to find
639 * @param min_len minimum property length in bytes
640 * @param err 0 if ok, or -FDT_ERR_NOTFOUND if the property is not
641 found, or -FDT_ERR_BADLAYOUT if not enough data
642 * @return pointer to cell, which is only valid if err == 0
644 static const void *get_prop_check_min_len(const void *blob, int node,
645 const char *prop_name, int min_len,
651 debug("%s: %s\n", __func__, prop_name);
652 cell = fdt_getprop(blob, node, prop_name, &len);
654 *err = -FDT_ERR_NOTFOUND;
655 else if (len < min_len)
656 *err = -FDT_ERR_BADLAYOUT;
662 int fdtdec_get_int_array(const void *blob, int node, const char *prop_name,
663 u32 *array, int count)
668 debug("%s: %s\n", __func__, prop_name);
669 cell = get_prop_check_min_len(blob, node, prop_name,
670 sizeof(u32) * count, &err);
674 for (i = 0; i < count; i++)
675 array[i] = fdt32_to_cpu(cell[i]);
680 int fdtdec_get_int_array_count(const void *blob, int node,
681 const char *prop_name, u32 *array, int count)
687 debug("%s: %s\n", __func__, prop_name);
688 cell = fdt_getprop(blob, node, prop_name, &len);
690 return -FDT_ERR_NOTFOUND;
691 elems = len / sizeof(u32);
694 for (i = 0; i < count; i++)
695 array[i] = fdt32_to_cpu(cell[i]);
700 const u32 *fdtdec_locate_array(const void *blob, int node,
701 const char *prop_name, int count)
706 cell = get_prop_check_min_len(blob, node, prop_name,
707 sizeof(u32) * count, &err);
708 return err ? NULL : cell;
711 int fdtdec_get_bool(const void *blob, int node, const char *prop_name)
716 debug("%s: %s\n", __func__, prop_name);
717 cell = fdt_getprop(blob, node, prop_name, &len);
721 int fdtdec_parse_phandle_with_args(const void *blob, int src_node,
722 const char *list_name,
723 const char *cells_name,
724 int cell_count, int index,
725 struct fdtdec_phandle_args *out_args)
727 const __be32 *list, *list_end;
728 int rc = 0, size, cur_index = 0;
733 /* Retrieve the phandle list property */
734 list = fdt_getprop(blob, src_node, list_name, &size);
737 list_end = list + size / sizeof(*list);
739 /* Loop over the phandles until all the requested entry is found */
740 while (list < list_end) {
745 * If phandle is 0, then it is an empty entry with no
746 * arguments. Skip forward to the next entry.
748 phandle = be32_to_cpup(list++);
751 * Find the provider node and parse the #*-cells
752 * property to determine the argument length.
754 * This is not needed if the cell count is hard-coded
755 * (i.e. cells_name not set, but cell_count is set),
756 * except when we're going to return the found node
759 if (cells_name || cur_index == index) {
760 node = fdt_node_offset_by_phandle(blob,
763 debug("%s: could not find phandle\n",
764 fdt_get_name(blob, src_node,
771 count = fdtdec_get_int(blob, node, cells_name,
774 debug("%s: could not get %s for %s\n",
775 fdt_get_name(blob, src_node,
778 fdt_get_name(blob, node,
787 * Make sure that the arguments actually fit in the
788 * remaining property data length
790 if (list + count > list_end) {
791 debug("%s: arguments longer than property\n",
792 fdt_get_name(blob, src_node, NULL));
798 * All of the error cases above bail out of the loop, so at
799 * this point, the parsing is successful. If the requested
800 * index matches, then fill the out_args structure and return,
801 * or return -ENOENT for an empty entry.
804 if (cur_index == index) {
811 if (count > MAX_PHANDLE_ARGS) {
812 debug("%s: too many arguments %d\n",
813 fdt_get_name(blob, src_node,
815 count = MAX_PHANDLE_ARGS;
817 out_args->node = node;
818 out_args->args_count = count;
819 for (i = 0; i < count; i++) {
821 be32_to_cpup(list++);
825 /* Found it! return success */
835 * Result will be one of:
836 * -ENOENT : index is for empty phandle
837 * -EINVAL : parsing error on data
838 * [1..n] : Number of phandle (count mode; when index = -1)
840 rc = index < 0 ? cur_index : -ENOENT;
845 int fdtdec_get_byte_array(const void *blob, int node, const char *prop_name,
846 u8 *array, int count)
851 cell = get_prop_check_min_len(blob, node, prop_name, count, &err);
853 memcpy(array, cell, count);
857 const u8 *fdtdec_locate_byte_array(const void *blob, int node,
858 const char *prop_name, int count)
863 cell = get_prop_check_min_len(blob, node, prop_name, count, &err);
869 int fdtdec_get_config_int(const void *blob, const char *prop_name,
874 debug("%s: %s\n", __func__, prop_name);
875 config_node = fdt_path_offset(blob, "/config");
878 return fdtdec_get_int(blob, config_node, prop_name, default_val);
881 int fdtdec_get_config_bool(const void *blob, const char *prop_name)
886 debug("%s: %s\n", __func__, prop_name);
887 config_node = fdt_path_offset(blob, "/config");
890 prop = fdt_get_property(blob, config_node, prop_name, NULL);
895 char *fdtdec_get_config_string(const void *blob, const char *prop_name)
901 debug("%s: %s\n", __func__, prop_name);
902 nodeoffset = fdt_path_offset(blob, "/config");
906 nodep = fdt_getprop(blob, nodeoffset, prop_name, &len);
910 return (char *)nodep;
913 u64 fdtdec_get_number(const fdt32_t *ptr, unsigned int cells)
918 number = (number << 32) | fdt32_to_cpu(*ptr++);
923 int fdt_get_resource(const void *fdt, int node, const char *property,
924 unsigned int index, struct fdt_resource *res)
926 const fdt32_t *ptr, *end;
927 int na, ns, len, parent;
930 parent = fdt_parent_offset(fdt, node);
934 na = fdt_address_cells(fdt, parent);
935 ns = fdt_size_cells(fdt, parent);
937 ptr = fdt_getprop(fdt, node, property, &len);
941 end = ptr + len / sizeof(*ptr);
943 while (ptr + na + ns <= end) {
945 res->start = fdtdec_get_number(ptr, na);
946 res->end = res->start;
947 res->end += fdtdec_get_number(&ptr[na], ns) - 1;
955 return -FDT_ERR_NOTFOUND;
958 int fdt_get_named_resource(const void *fdt, int node, const char *property,
959 const char *prop_names, const char *name,
960 struct fdt_resource *res)
964 index = fdt_stringlist_search(fdt, node, prop_names, name);
968 return fdt_get_resource(fdt, node, property, index, res);
971 static int decode_timing_property(const void *blob, int node, const char *name,
972 struct timing_entry *result)
977 prop = fdt_getprop(blob, node, name, &length);
979 debug("%s: could not find property %s\n",
980 fdt_get_name(blob, node, NULL), name);
984 if (length == sizeof(u32)) {
985 result->typ = fdtdec_get_int(blob, node, name, 0);
986 result->min = result->typ;
987 result->max = result->typ;
989 ret = fdtdec_get_int_array(blob, node, name, &result->min, 3);
995 int fdtdec_decode_display_timing(const void *blob, int parent, int index,
996 struct display_timing *dt)
998 int i, node, timings_node;
1002 timings_node = fdt_subnode_offset(blob, parent, "display-timings");
1003 if (timings_node < 0)
1004 return timings_node;
1006 for (i = 0, node = fdt_first_subnode(blob, timings_node);
1007 node > 0 && i != index;
1008 node = fdt_next_subnode(blob, node))
1014 memset(dt, 0, sizeof(*dt));
1016 ret |= decode_timing_property(blob, node, "hback-porch",
1018 ret |= decode_timing_property(blob, node, "hfront-porch",
1020 ret |= decode_timing_property(blob, node, "hactive", &dt->hactive);
1021 ret |= decode_timing_property(blob, node, "hsync-len", &dt->hsync_len);
1022 ret |= decode_timing_property(blob, node, "vback-porch",
1024 ret |= decode_timing_property(blob, node, "vfront-porch",
1026 ret |= decode_timing_property(blob, node, "vactive", &dt->vactive);
1027 ret |= decode_timing_property(blob, node, "vsync-len", &dt->vsync_len);
1028 ret |= decode_timing_property(blob, node, "clock-frequency",
1032 val = fdtdec_get_int(blob, node, "vsync-active", -1);
1034 dt->flags |= val ? DISPLAY_FLAGS_VSYNC_HIGH :
1035 DISPLAY_FLAGS_VSYNC_LOW;
1037 val = fdtdec_get_int(blob, node, "hsync-active", -1);
1039 dt->flags |= val ? DISPLAY_FLAGS_HSYNC_HIGH :
1040 DISPLAY_FLAGS_HSYNC_LOW;
1042 val = fdtdec_get_int(blob, node, "de-active", -1);
1044 dt->flags |= val ? DISPLAY_FLAGS_DE_HIGH :
1045 DISPLAY_FLAGS_DE_LOW;
1047 val = fdtdec_get_int(blob, node, "pixelclk-active", -1);
1049 dt->flags |= val ? DISPLAY_FLAGS_PIXDATA_POSEDGE :
1050 DISPLAY_FLAGS_PIXDATA_NEGEDGE;
1053 if (fdtdec_get_bool(blob, node, "interlaced"))
1054 dt->flags |= DISPLAY_FLAGS_INTERLACED;
1055 if (fdtdec_get_bool(blob, node, "doublescan"))
1056 dt->flags |= DISPLAY_FLAGS_DOUBLESCAN;
1057 if (fdtdec_get_bool(blob, node, "doubleclk"))
1058 dt->flags |= DISPLAY_FLAGS_DOUBLECLK;
1063 int fdtdec_setup_mem_size_base(void)
1067 struct resource res;
1069 mem = ofnode_path("/memory");
1070 if (!ofnode_valid(mem)) {
1071 debug("%s: Missing /memory node\n", __func__);
1075 ret = ofnode_read_resource(mem, 0, &res);
1077 debug("%s: Unable to decode first memory bank\n", __func__);
1081 gd->ram_size = (phys_size_t)(res.end - res.start + 1);
1082 gd->ram_base = (unsigned long)res.start;
1083 debug("%s: Initial DRAM size %llx\n", __func__,
1084 (unsigned long long)gd->ram_size);
1089 ofnode get_next_memory_node(ofnode mem)
1092 mem = ofnode_by_prop_value(mem, "device_type", "memory", 7);
1093 } while (!ofnode_is_available(mem));
1098 int fdtdec_setup_memory_banksize(void)
1100 int bank, ret, reg = 0;
1101 struct resource res;
1102 ofnode mem = ofnode_null();
1104 mem = get_next_memory_node(mem);
1105 if (!ofnode_valid(mem)) {
1106 debug("%s: Missing /memory node\n", __func__);
1110 for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
1111 ret = ofnode_read_resource(mem, reg++, &res);
1114 mem = get_next_memory_node(mem);
1115 if (!ofnode_valid(mem))
1118 ret = ofnode_read_resource(mem, reg++, &res);
1126 gd->bd->bi_dram[bank].start = (phys_addr_t)res.start;
1127 gd->bd->bi_dram[bank].size =
1128 (phys_size_t)(res.end - res.start + 1);
1130 debug("%s: DRAM Bank #%d: start = 0x%llx, size = 0x%llx\n",
1132 (unsigned long long)gd->bd->bi_dram[bank].start,
1133 (unsigned long long)gd->bd->bi_dram[bank].size);
1139 int fdtdec_setup_mem_size_base_lowest(void)
1141 int bank, ret, reg = 0;
1142 struct resource res;
1145 ofnode mem = ofnode_null();
1147 gd->ram_base = (unsigned long)~0;
1149 mem = get_next_memory_node(mem);
1150 if (!ofnode_valid(mem)) {
1151 debug("%s: Missing /memory node\n", __func__);
1155 for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
1156 ret = ofnode_read_resource(mem, reg++, &res);
1159 mem = get_next_memory_node(mem);
1160 if (!ofnode_valid(mem))
1163 ret = ofnode_read_resource(mem, reg++, &res);
1171 base = (unsigned long)res.start;
1172 size = (phys_size_t)(res.end - res.start + 1);
1174 if (gd->ram_base > base && size) {
1175 gd->ram_base = base;
1176 gd->ram_size = size;
1177 debug("%s: Initial DRAM base %lx size %lx\n",
1178 __func__, base, (unsigned long)size);
1185 #if CONFIG_IS_ENABLED(MULTI_DTB_FIT)
1186 # if CONFIG_IS_ENABLED(MULTI_DTB_FIT_GZIP) ||\
1187 CONFIG_IS_ENABLED(MULTI_DTB_FIT_LZO)
1188 static int uncompress_blob(const void *src, ulong sz_src, void **dstp)
1190 size_t sz_out = CONFIG_VAL(MULTI_DTB_FIT_UNCOMPRESS_SZ);
1191 bool gzip = 0, lzo = 0;
1192 ulong sz_in = sz_src;
1196 if (CONFIG_IS_ENABLED(GZIP))
1197 if (gzip_parse_header(src, sz_in) >= 0)
1199 if (CONFIG_IS_ENABLED(LZO))
1200 if (!gzip && lzop_is_valid_header(src))
1207 if (CONFIG_IS_ENABLED(MULTI_DTB_FIT_DYN_ALLOC)) {
1208 dst = malloc(sz_out);
1210 puts("uncompress_blob: Unable to allocate memory\n");
1214 # if CONFIG_IS_ENABLED(MULTI_DTB_FIT_USER_DEFINED_AREA)
1215 dst = (void *)CONFIG_VAL(MULTI_DTB_FIT_USER_DEF_ADDR);
1221 if (CONFIG_IS_ENABLED(GZIP) && gzip)
1222 rc = gunzip(dst, sz_out, (u8 *)src, &sz_in);
1223 else if (CONFIG_IS_ENABLED(LZO) && lzo)
1224 rc = lzop_decompress(src, sz_in, dst, &sz_out);
1229 /* not a valid compressed blob */
1230 puts("uncompress_blob: Unable to uncompress\n");
1231 if (CONFIG_IS_ENABLED(MULTI_DTB_FIT_DYN_ALLOC))
1239 static int uncompress_blob(const void *src, ulong sz_src, void **dstp)
1241 *dstp = (void *)src;
1247 #if defined(CONFIG_OF_BOARD) || defined(CONFIG_OF_SEPARATE)
1249 * For CONFIG_OF_SEPARATE, the board may optionally implement this to
1250 * provide and/or fixup the fdt.
1252 __weak void *board_fdt_blob_setup(void)
1254 void *fdt_blob = NULL;
1255 #ifdef CONFIG_SPL_BUILD
1256 /* FDT is at end of BSS unless it is in a different memory region */
1257 if (IS_ENABLED(CONFIG_SPL_SEPARATE_BSS))
1258 fdt_blob = (ulong *)&_image_binary_end;
1260 fdt_blob = (ulong *)&__bss_end;
1262 /* FDT is at end of image */
1263 fdt_blob = (ulong *)&_end;
1269 int fdtdec_set_ethernet_mac_address(void *fdt, const u8 *mac, size_t size)
1274 if (!is_valid_ethaddr(mac))
1277 path = fdt_get_alias(fdt, "ethernet");
1281 debug("ethernet alias found: %s\n", path);
1283 offset = fdt_path_offset(fdt, path);
1285 debug("ethernet alias points to absent node %s\n", path);
1289 err = fdt_setprop_inplace(fdt, offset, "local-mac-address", mac, size);
1293 debug("MAC address: %pM\n", mac);
1298 static int fdtdec_init_reserved_memory(void *blob)
1300 int na, ns, node, err;
1303 /* inherit #address-cells and #size-cells from the root node */
1304 na = fdt_address_cells(blob, 0);
1305 ns = fdt_size_cells(blob, 0);
1307 node = fdt_add_subnode(blob, 0, "reserved-memory");
1311 err = fdt_setprop(blob, node, "ranges", NULL, 0);
1315 value = cpu_to_fdt32(ns);
1317 err = fdt_setprop(blob, node, "#size-cells", &value, sizeof(value));
1321 value = cpu_to_fdt32(na);
1323 err = fdt_setprop(blob, node, "#address-cells", &value, sizeof(value));
1330 int fdtdec_add_reserved_memory(void *blob, const char *basename,
1331 const struct fdt_memory *carveout,
1332 uint32_t *phandlep, bool no_map)
1334 fdt32_t cells[4] = {}, *ptr = cells;
1335 uint32_t upper, lower, phandle;
1336 int parent, node, na, ns, err;
1340 /* create an empty /reserved-memory node if one doesn't exist */
1341 parent = fdt_path_offset(blob, "/reserved-memory");
1343 parent = fdtdec_init_reserved_memory(blob);
1348 /* only 1 or 2 #address-cells and #size-cells are supported */
1349 na = fdt_address_cells(blob, parent);
1350 if (na < 1 || na > 2)
1351 return -FDT_ERR_BADNCELLS;
1353 ns = fdt_size_cells(blob, parent);
1354 if (ns < 1 || ns > 2)
1355 return -FDT_ERR_BADNCELLS;
1357 /* find a matching node and return the phandle to that */
1358 fdt_for_each_subnode(node, blob, parent) {
1359 const char *name = fdt_get_name(blob, node, NULL);
1363 addr = fdtdec_get_addr_size_fixed(blob, node, "reg", 0, na, ns,
1365 if (addr == FDT_ADDR_T_NONE) {
1366 debug("failed to read address/size for %s\n", name);
1370 if (addr == carveout->start && (addr + size - 1) ==
1373 *phandlep = fdt_get_phandle(blob, node);
1379 * Unpack the start address and generate the name of the new node
1380 * base on the basename and the unit-address.
1382 upper = upper_32_bits(carveout->start);
1383 lower = lower_32_bits(carveout->start);
1385 if (na > 1 && upper > 0)
1386 snprintf(name, sizeof(name), "%s@%x,%x", basename, upper,
1390 debug("address %08x:%08x exceeds addressable space\n",
1392 return -FDT_ERR_BADVALUE;
1395 snprintf(name, sizeof(name), "%s@%x", basename, lower);
1398 node = fdt_add_subnode(blob, parent, name);
1403 err = fdt_generate_phandle(blob, &phandle);
1407 err = fdtdec_set_phandle(blob, node, phandle);
1412 /* store one or two address cells */
1414 *ptr++ = cpu_to_fdt32(upper);
1416 *ptr++ = cpu_to_fdt32(lower);
1418 /* store one or two size cells */
1419 size = carveout->end - carveout->start + 1;
1420 upper = upper_32_bits(size);
1421 lower = lower_32_bits(size);
1424 *ptr++ = cpu_to_fdt32(upper);
1426 *ptr++ = cpu_to_fdt32(lower);
1428 err = fdt_setprop(blob, node, "reg", cells, (na + ns) * sizeof(*cells));
1433 err = fdt_setprop(blob, node, "no-map", NULL, 0);
1438 /* return the phandle for the new node for the caller to use */
1440 *phandlep = phandle;
1445 int fdtdec_get_carveout(const void *blob, const char *node, const char *name,
1446 unsigned int index, struct fdt_memory *carveout)
1448 const fdt32_t *prop;
1453 offset = fdt_path_offset(blob, node);
1457 prop = fdt_getprop(blob, offset, name, &len);
1459 debug("failed to get %s for %s\n", name, node);
1460 return -FDT_ERR_NOTFOUND;
1463 if ((len % sizeof(phandle)) != 0) {
1464 debug("invalid phandle property\n");
1465 return -FDT_ERR_BADPHANDLE;
1468 if (len < (sizeof(phandle) * (index + 1))) {
1469 debug("invalid phandle index\n");
1470 return -FDT_ERR_BADPHANDLE;
1473 phandle = fdt32_to_cpu(prop[index]);
1475 offset = fdt_node_offset_by_phandle(blob, phandle);
1477 debug("failed to find node for phandle %u\n", phandle);
1481 carveout->start = fdtdec_get_addr_size_auto_noparent(blob, offset,
1484 if (carveout->start == FDT_ADDR_T_NONE) {
1485 debug("failed to read address/size from \"reg\" property\n");
1486 return -FDT_ERR_NOTFOUND;
1489 carveout->end = carveout->start + size - 1;
1494 int fdtdec_set_carveout(void *blob, const char *node, const char *prop_name,
1495 unsigned int index, const char *name,
1496 const struct fdt_memory *carveout)
1499 int err, offset, len;
1503 err = fdtdec_add_reserved_memory(blob, name, carveout, &phandle, false);
1505 debug("failed to add reserved memory: %d\n", err);
1509 offset = fdt_path_offset(blob, node);
1511 debug("failed to find offset for node %s: %d\n", node, offset);
1515 value = cpu_to_fdt32(phandle);
1517 if (!fdt_getprop(blob, offset, prop_name, &len)) {
1518 if (len == -FDT_ERR_NOTFOUND)
1524 if ((index + 1) * sizeof(value) > len) {
1525 err = fdt_setprop_placeholder(blob, offset, prop_name,
1526 (index + 1) * sizeof(value),
1529 debug("failed to resize reserved memory property: %s\n",
1535 err = fdt_setprop_inplace_namelen_partial(blob, offset, prop_name,
1537 index * sizeof(value),
1538 &value, sizeof(value));
1540 debug("failed to update %s property for node %s: %s\n",
1541 prop_name, node, fdt_strerror(err));
1548 __weak int fdtdec_board_setup(const void *fdt_blob)
1553 int fdtdec_setup(void)
1556 #if CONFIG_IS_ENABLED(OF_CONTROL)
1557 # if CONFIG_IS_ENABLED(MULTI_DTB_FIT)
1560 # ifdef CONFIG_OF_EMBED
1561 /* Get a pointer to the FDT */
1562 # ifdef CONFIG_SPL_BUILD
1563 gd->fdt_blob = __dtb_dt_spl_begin;
1565 gd->fdt_blob = __dtb_dt_begin;
1567 # elif defined(CONFIG_OF_BOARD) || defined(CONFIG_OF_SEPARATE)
1568 /* Allow the board to override the fdt address. */
1569 gd->fdt_blob = board_fdt_blob_setup();
1570 # elif defined(CONFIG_OF_HOSTFILE)
1571 if (sandbox_read_fdt_from_file()) {
1572 puts("Failed to read control FDT\n");
1575 # elif defined(CONFIG_OF_PRIOR_STAGE)
1576 gd->fdt_blob = (void *)(uintptr_t)prior_stage_fdt_address;
1578 # ifndef CONFIG_SPL_BUILD
1579 /* Allow the early environment to override the fdt address */
1580 gd->fdt_blob = map_sysmem
1581 (env_get_ulong("fdtcontroladdr", 16,
1582 (unsigned long)map_to_sysmem(gd->fdt_blob)), 0);
1585 # if CONFIG_IS_ENABLED(MULTI_DTB_FIT)
1587 * Try and uncompress the blob.
1588 * Unfortunately there is no way to know how big the input blob really
1589 * is. So let us set the maximum input size arbitrarily high. 16MB
1590 * ought to be more than enough for packed DTBs.
1592 if (uncompress_blob(gd->fdt_blob, 0x1000000, &fdt_blob) == 0)
1593 gd->fdt_blob = fdt_blob;
1596 * Check if blob is a FIT images containings DTBs.
1597 * If so, pick the most relevant
1599 fdt_blob = locate_dtb_in_fit(gd->fdt_blob);
1601 gd->multi_dtb_fit = gd->fdt_blob;
1602 gd->fdt_blob = fdt_blob;
1608 ret = fdtdec_prepare_fdt();
1610 ret = fdtdec_board_setup(gd->fdt_blob);
1614 #if CONFIG_IS_ENABLED(MULTI_DTB_FIT)
1615 int fdtdec_resetup(int *rescan)
1620 * If the current DTB is part of a compressed FIT image,
1621 * try to locate the best match from the uncompressed
1622 * FIT image stillpresent there. Save the time and space
1623 * required to uncompress it again.
1625 if (gd->multi_dtb_fit) {
1626 fdt_blob = locate_dtb_in_fit(gd->multi_dtb_fit);
1628 if (fdt_blob == gd->fdt_blob) {
1630 * The best match did not change. no need to tear down
1631 * the DM and rescan the fdt.
1638 gd->fdt_blob = fdt_blob;
1639 return fdtdec_prepare_fdt();
1643 * If multi_dtb_fit is NULL, it means that blob appended to u-boot is
1644 * not a FIT image containings DTB, but a single DTB. There is no need
1645 * to teard down DM and rescan the DT in this case.
1652 int fdtdec_decode_ram_size(const void *blob, const char *area, int board_id,
1653 phys_addr_t *basep, phys_size_t *sizep,
1656 int addr_cells, size_cells;
1657 const u32 *cell, *end;
1658 u64 total_size, size, addr;
1664 debug("%s: board_id=%d\n", __func__, board_id);
1667 node = fdt_path_offset(blob, area);
1669 debug("No %s node found\n", area);
1673 cell = fdt_getprop(blob, node, "reg", &len);
1675 debug("No reg property found\n");
1679 addr_cells = fdt_address_cells(blob, node);
1680 size_cells = fdt_size_cells(blob, node);
1682 /* Check the board id and mask */
1683 for (child = fdt_first_subnode(blob, node);
1685 child = fdt_next_subnode(blob, child)) {
1686 int match_mask, match_value;
1688 match_mask = fdtdec_get_int(blob, child, "match-mask", -1);
1689 match_value = fdtdec_get_int(blob, child, "match-value", -1);
1691 if (match_value >= 0 &&
1692 ((board_id & match_mask) == match_value)) {
1693 /* Found matching mask */
1694 debug("Found matching mask %d\n", match_mask);
1696 cell = fdt_getprop(blob, node, "reg", &len);
1698 debug("No memory-banks property found\n");
1704 /* Note: if no matching subnode was found we use the parent node */
1707 memset(bd->bi_dram, '\0', sizeof(bd->bi_dram[0]) *
1708 CONFIG_NR_DRAM_BANKS);
1711 auto_size = fdtdec_get_bool(blob, node, "auto-size");
1714 end = cell + len / 4 - addr_cells - size_cells;
1715 debug("cell at %p, end %p\n", cell, end);
1716 for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
1720 if (addr_cells == 2)
1721 addr += (u64)fdt32_to_cpu(*cell++) << 32UL;
1722 addr += fdt32_to_cpu(*cell++);
1724 bd->bi_dram[bank].start = addr;
1726 *basep = (phys_addr_t)addr;
1729 if (size_cells == 2)
1730 size += (u64)fdt32_to_cpu(*cell++) << 32UL;
1731 size += fdt32_to_cpu(*cell++);
1736 debug("Auto-sizing %llx, size %llx: ", addr, size);
1737 new_size = get_ram_size((long *)(uintptr_t)addr, size);
1738 if (new_size == size) {
1741 debug("sized to %llx\n", new_size);
1747 bd->bi_dram[bank].size = size;
1751 debug("Memory size %llu\n", total_size);
1753 *sizep = (phys_size_t)total_size;
1758 #endif /* !USE_HOSTCC */