1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2011 The Chromium OS Authors.
9 #include <display_options.h>
20 #include <fdt_support.h>
23 #include <linux/libfdt.h>
25 #include <asm/global_data.h>
26 #include <asm/sections.h>
27 #include <dm/ofnode.h>
28 #include <dm/of_extra.h>
29 #include <linux/ctype.h>
30 #include <linux/lzo.h>
31 #include <linux/ioport.h>
33 DECLARE_GLOBAL_DATA_PTR;
36 * Here are the type we know about. One day we might allow drivers to
37 * register. For now we just put them here. The COMPAT macro allows us to
38 * turn this into a sparse list later, and keeps the ID with the name.
40 * NOTE: This list is basically a TODO list for things that need to be
41 * converted to driver model. So don't add new things here unless there is a
42 * good reason why driver-model conversion is infeasible. Examples include
43 * things which are used before driver model is available.
45 #define COMPAT(id, name) name
46 static const char * const compat_names[COMPAT_COUNT] = {
47 COMPAT(UNKNOWN, "<none>"),
48 COMPAT(NVIDIA_TEGRA20_EMC, "nvidia,tegra20-emc"),
49 COMPAT(NVIDIA_TEGRA20_EMC_TABLE, "nvidia,tegra20-emc-table"),
50 COMPAT(NVIDIA_TEGRA20_NAND, "nvidia,tegra20-nand"),
51 COMPAT(NVIDIA_TEGRA124_XUSB_PADCTL, "nvidia,tegra124-xusb-padctl"),
52 COMPAT(NVIDIA_TEGRA210_XUSB_PADCTL, "nvidia,tegra210-xusb-padctl"),
53 COMPAT(SAMSUNG_EXYNOS_USB_PHY, "samsung,exynos-usb-phy"),
54 COMPAT(SAMSUNG_EXYNOS5_USB3_PHY, "samsung,exynos5250-usb3-phy"),
55 COMPAT(SAMSUNG_EXYNOS_TMU, "samsung,exynos-tmu"),
56 COMPAT(SAMSUNG_EXYNOS_MIPI_DSI, "samsung,exynos-mipi-dsi"),
57 COMPAT(SAMSUNG_EXYNOS_DWMMC, "samsung,exynos-dwmmc"),
58 COMPAT(GENERIC_SPI_FLASH, "jedec,spi-nor"),
59 COMPAT(SAMSUNG_EXYNOS_SYSMMU, "samsung,sysmmu-v3.3"),
60 COMPAT(INTEL_MICROCODE, "intel,microcode"),
61 COMPAT(INTEL_QRK_MRC, "intel,quark-mrc"),
62 COMPAT(ALTERA_SOCFPGA_DWMAC, "altr,socfpga-stmmac"),
63 COMPAT(ALTERA_SOCFPGA_DWMMC, "altr,socfpga-dw-mshc"),
64 COMPAT(ALTERA_SOCFPGA_DWC2USB, "snps,dwc2"),
65 COMPAT(INTEL_BAYTRAIL_FSP, "intel,baytrail-fsp"),
66 COMPAT(INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
67 COMPAT(INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"),
68 COMPAT(COMPAT_SUNXI_NAND, "allwinner,sun4i-a10-nand"),
69 COMPAT(ALTERA_SOCFPGA_CLK, "altr,clk-mgr"),
70 COMPAT(ALTERA_SOCFPGA_PINCTRL_SINGLE, "pinctrl-single"),
71 COMPAT(ALTERA_SOCFPGA_H2F_BRG, "altr,socfpga-hps2fpga-bridge"),
72 COMPAT(ALTERA_SOCFPGA_LWH2F_BRG, "altr,socfpga-lwhps2fpga-bridge"),
73 COMPAT(ALTERA_SOCFPGA_F2H_BRG, "altr,socfpga-fpga2hps-bridge"),
74 COMPAT(ALTERA_SOCFPGA_F2SDR0, "altr,socfpga-fpga2sdram0-bridge"),
75 COMPAT(ALTERA_SOCFPGA_F2SDR1, "altr,socfpga-fpga2sdram1-bridge"),
76 COMPAT(ALTERA_SOCFPGA_F2SDR2, "altr,socfpga-fpga2sdram2-bridge"),
77 COMPAT(ALTERA_SOCFPGA_FPGA0, "altr,socfpga-a10-fpga-mgr"),
78 COMPAT(ALTERA_SOCFPGA_NOC, "altr,socfpga-a10-noc"),
79 COMPAT(ALTERA_SOCFPGA_CLK_INIT, "altr,socfpga-a10-clk-init")
82 static const char *const fdt_src_name[] = {
83 [FDTSRC_SEPARATE] = "separate",
85 [FDTSRC_BOARD] = "board",
86 [FDTSRC_EMBED] = "embed",
90 const char *fdtdec_get_srcname(void)
92 return fdt_src_name[gd->fdt_src];
95 const char *fdtdec_get_compatible(enum fdt_compat_id id)
97 /* We allow reading of the 'unknown' ID for testing purposes */
98 assert(id >= 0 && id < COMPAT_COUNT);
99 return compat_names[id];
102 fdt_addr_t fdtdec_get_addr_size_fixed(const void *blob, int node,
103 const char *prop_name, int index, int na,
104 int ns, fdt_size_t *sizep,
107 const fdt32_t *prop, *prop_end;
108 const fdt32_t *prop_addr, *prop_size, *prop_after_size;
112 debug("%s: %s: ", __func__, prop_name);
114 prop = fdt_getprop(blob, node, prop_name, &len);
116 debug("(not found)\n");
117 return FDT_ADDR_T_NONE;
119 prop_end = prop + (len / sizeof(*prop));
121 prop_addr = prop + (index * (na + ns));
122 prop_size = prop_addr + na;
123 prop_after_size = prop_size + ns;
124 if (prop_after_size > prop_end) {
125 debug("(not enough data: expected >= %d cells, got %d cells)\n",
126 (u32)(prop_after_size - prop), ((u32)(prop_end - prop)));
127 return FDT_ADDR_T_NONE;
130 #if CONFIG_IS_ENABLED(OF_TRANSLATE)
132 addr = fdt_translate_address(blob, node, prop_addr);
135 addr = fdtdec_get_number(prop_addr, na);
138 *sizep = fdtdec_get_number(prop_size, ns);
139 debug("addr=%08llx, size=%llx\n", (unsigned long long)addr,
140 (unsigned long long)*sizep);
142 debug("addr=%08llx\n", (unsigned long long)addr);
148 fdt_addr_t fdtdec_get_addr_size_auto_parent(const void *blob, int parent,
149 int node, const char *prop_name,
150 int index, fdt_size_t *sizep,
155 debug("%s: ", __func__);
157 na = fdt_address_cells(blob, parent);
159 debug("(bad #address-cells)\n");
160 return FDT_ADDR_T_NONE;
163 ns = fdt_size_cells(blob, parent);
165 debug("(bad #size-cells)\n");
166 return FDT_ADDR_T_NONE;
169 debug("na=%d, ns=%d, ", na, ns);
171 return fdtdec_get_addr_size_fixed(blob, node, prop_name, index, na,
172 ns, sizep, translate);
175 fdt_addr_t fdtdec_get_addr_size_auto_noparent(const void *blob, int node,
176 const char *prop_name, int index,
182 debug("%s: ", __func__);
184 parent = fdt_parent_offset(blob, node);
186 debug("(no parent found)\n");
187 return FDT_ADDR_T_NONE;
190 return fdtdec_get_addr_size_auto_parent(blob, parent, node, prop_name,
191 index, sizep, translate);
194 fdt_addr_t fdtdec_get_addr_size(const void *blob, int node,
195 const char *prop_name, fdt_size_t *sizep)
197 int ns = sizep ? (sizeof(fdt_size_t) / sizeof(fdt32_t)) : 0;
199 return fdtdec_get_addr_size_fixed(blob, node, prop_name, 0,
200 sizeof(fdt_addr_t) / sizeof(fdt32_t),
204 fdt_addr_t fdtdec_get_addr(const void *blob, int node, const char *prop_name)
206 return fdtdec_get_addr_size(blob, node, prop_name, NULL);
209 int fdtdec_get_pci_vendev(const void *blob, int node, u16 *vendor, u16 *device)
211 const char *list, *end;
214 list = fdt_getprop(blob, node, "compatible", &len);
221 if (len >= strlen("pciVVVV,DDDD")) {
222 char *s = strstr(list, "pci");
225 * check if the string is something like pciVVVV,DDDD.RR
226 * or just pciVVVV,DDDD
228 if (s && s[7] == ',' &&
229 (s[12] == '.' || s[12] == 0)) {
231 *vendor = simple_strtol(s, NULL, 16);
234 *device = simple_strtol(s, NULL, 16);
245 int fdtdec_get_pci_bar32(const struct udevice *dev, struct fdt_pci_addr *addr,
250 /* extract the bar number from fdt_pci_addr */
251 barnum = addr->phys_hi & 0xff;
252 if (barnum < PCI_BASE_ADDRESS_0 || barnum > PCI_CARDBUS_CIS)
255 barnum = (barnum - PCI_BASE_ADDRESS_0) / 4;
257 *bar = dm_pci_read_bar32(dev, barnum);
262 int fdtdec_get_pci_bus_range(const void *blob, int node,
263 struct fdt_resource *res)
268 values = fdt_getprop(blob, node, "bus-range", &len);
269 if (!values || len < sizeof(*values) * 2)
272 res->start = fdt32_to_cpu(*values++);
273 res->end = fdt32_to_cpu(*values);
278 uint64_t fdtdec_get_uint64(const void *blob, int node, const char *prop_name,
279 uint64_t default_val)
281 const unaligned_fdt64_t *cell64;
284 cell64 = fdt_getprop(blob, node, prop_name, &length);
285 if (!cell64 || length < sizeof(*cell64))
288 return fdt64_to_cpu(*cell64);
291 int fdtdec_get_is_enabled(const void *blob, int node)
296 * It should say "okay", so only allow that. Some fdts use "ok" but
297 * this is a bug. Please fix your device tree source file. See here
300 * http://www.mail-archive.com/u-boot@lists.denx.de/msg71598.html
302 cell = fdt_getprop(blob, node, "status", NULL);
304 return strcmp(cell, "okay") == 0;
308 enum fdt_compat_id fdtdec_lookup(const void *blob, int node)
310 enum fdt_compat_id id;
312 /* Search our drivers */
313 for (id = COMPAT_UNKNOWN; id < COMPAT_COUNT; id++)
314 if (fdt_node_check_compatible(blob, node,
315 compat_names[id]) == 0)
317 return COMPAT_UNKNOWN;
320 int fdtdec_next_compatible(const void *blob, int node, enum fdt_compat_id id)
322 return fdt_node_offset_by_compatible(blob, node, compat_names[id]);
325 int fdtdec_next_compatible_subnode(const void *blob, int node,
326 enum fdt_compat_id id, int *depthp)
329 node = fdt_next_node(blob, node, depthp);
330 } while (*depthp > 1);
332 /* If this is a direct subnode, and compatible, return it */
333 if (*depthp == 1 && 0 == fdt_node_check_compatible(
334 blob, node, compat_names[id]))
337 return -FDT_ERR_NOTFOUND;
340 int fdtdec_next_alias(const void *blob, const char *name, enum fdt_compat_id id,
343 #define MAX_STR_LEN 20
344 char str[MAX_STR_LEN + 20];
347 /* snprintf() is not available */
348 assert(strlen(name) < MAX_STR_LEN);
349 sprintf(str, "%.*s%d", MAX_STR_LEN, name, *upto);
350 node = fdt_path_offset(blob, str);
353 err = fdt_node_check_compatible(blob, node, compat_names[id]);
357 return -FDT_ERR_NOTFOUND;
362 int fdtdec_find_aliases_for_id(const void *blob, const char *name,
363 enum fdt_compat_id id, int *node_list,
366 memset(node_list, '\0', sizeof(*node_list) * maxcount);
368 return fdtdec_add_aliases_for_id(blob, name, id, node_list, maxcount);
371 /* TODO: Can we tighten this code up a little? */
372 int fdtdec_add_aliases_for_id(const void *blob, const char *name,
373 enum fdt_compat_id id, int *node_list,
376 int name_len = strlen(name);
384 /* find the alias node if present */
385 alias_node = fdt_path_offset(blob, "/aliases");
388 * start with nothing, and we can assume that the root node can't
391 memset(nodes, '\0', sizeof(nodes));
393 /* First find all the compatible nodes */
394 for (node = count = 0; node >= 0 && count < maxcount;) {
395 node = fdtdec_next_compatible(blob, node, id);
397 nodes[count++] = node;
400 debug("%s: warning: maxcount exceeded with alias '%s'\n",
403 /* Now find all the aliases */
404 for (offset = fdt_first_property_offset(blob, alias_node);
406 offset = fdt_next_property_offset(blob, offset)) {
407 const struct fdt_property *prop;
413 prop = fdt_get_property_by_offset(blob, offset, NULL);
414 path = fdt_string(blob, fdt32_to_cpu(prop->nameoff));
415 if (prop->len && 0 == strncmp(path, name, name_len))
416 node = fdt_path_offset(blob, prop->data);
420 /* Get the alias number */
421 number = dectoul(path + name_len, NULL);
422 if (number < 0 || number >= maxcount) {
423 debug("%s: warning: alias '%s' is out of range\n",
428 /* Make sure the node we found is actually in our list! */
430 for (j = 0; j < count; j++)
431 if (nodes[j] == node) {
437 debug("%s: warning: alias '%s' points to a node "
438 "'%s' that is missing or is not compatible "
439 " with '%s'\n", __func__, path,
440 fdt_get_name(blob, node, NULL),
446 * Add this node to our list in the right place, and mark
449 if (fdtdec_get_is_enabled(blob, node)) {
450 if (node_list[number]) {
451 debug("%s: warning: alias '%s' requires that "
452 "a node be placed in the list in a "
453 "position which is already filled by "
454 "node '%s'\n", __func__, path,
455 fdt_get_name(blob, node, NULL));
458 node_list[number] = node;
459 if (number >= num_found)
460 num_found = number + 1;
465 /* Add any nodes not mentioned by an alias */
466 for (i = j = 0; i < maxcount; i++) {
468 for (; j < maxcount; j++)
470 fdtdec_get_is_enabled(blob, nodes[j]))
473 /* Have we run out of nodes to add? */
477 assert(!node_list[i]);
478 node_list[i] = nodes[j++];
487 int fdtdec_get_alias_seq(const void *blob, const char *base, int offset,
490 int base_len = strlen(base);
491 const char *find_name;
496 find_name = fdt_get_name(blob, offset, &find_namelen);
497 debug("Looking for '%s' at %d, name %s\n", base, offset, find_name);
499 aliases = fdt_path_offset(blob, "/aliases");
500 for (prop_offset = fdt_first_property_offset(blob, aliases);
502 prop_offset = fdt_next_property_offset(blob, prop_offset)) {
508 prop = fdt_getprop_by_offset(blob, prop_offset, &name, &len);
509 debug(" - %s, %s\n", name, prop);
510 if (len < find_namelen || *prop != '/' || prop[len - 1] ||
511 strncmp(name, base, base_len))
514 slash = strrchr(prop, '/');
515 if (strcmp(slash + 1, find_name))
519 * Adding an extra check to distinguish DT nodes with
522 if (IS_ENABLED(CONFIG_PHANDLE_CHECK_SEQ)) {
523 if (fdt_get_phandle(blob, offset) !=
524 fdt_get_phandle(blob, fdt_path_offset(blob, prop)))
528 val = trailing_strtol(name);
531 debug("Found seq %d\n", *seqp);
536 debug("Not found\n");
540 int fdtdec_get_alias_highest_id(const void *blob, const char *base)
542 int base_len = strlen(base);
547 debug("Looking for highest alias id for '%s'\n", base);
549 aliases = fdt_path_offset(blob, "/aliases");
550 for (prop_offset = fdt_first_property_offset(blob, aliases);
552 prop_offset = fdt_next_property_offset(blob, prop_offset)) {
557 prop = fdt_getprop_by_offset(blob, prop_offset, &name, &len);
558 debug(" - %s, %s\n", name, prop);
559 if (*prop != '/' || prop[len - 1] ||
560 strncmp(name, base, base_len))
563 val = trailing_strtol(name);
565 debug("Found seq %d\n", val);
573 const char *fdtdec_get_chosen_prop(const void *blob, const char *name)
579 chosen_node = fdt_path_offset(blob, "/chosen");
580 return fdt_getprop(blob, chosen_node, name, NULL);
583 int fdtdec_get_chosen_node(const void *blob, const char *name)
587 prop = fdtdec_get_chosen_prop(blob, name);
589 return -FDT_ERR_NOTFOUND;
590 return fdt_path_offset(blob, prop);
594 * fdtdec_prepare_fdt() - Check we have a valid fdt available to control U-Boot
596 * @blob: Blob to check
598 * If not, a message is printed to the console if the console is ready.
600 * Return: 0 if all ok, -ENOENT if not
602 static int fdtdec_prepare_fdt(const void *blob)
604 if (!blob || ((uintptr_t)blob & 3) || fdt_check_header(blob)) {
605 if (spl_phase() <= PHASE_SPL) {
606 puts("Missing DTB\n");
608 printf("No valid device tree binary found at %p\n",
610 if (_DEBUG && blob) {
611 printf("fdt_blob=%p\n", blob);
612 print_buffer((ulong)blob, blob, 4, 32, 0);
621 int fdtdec_check_fdt(void)
624 * We must have an FDT, but we cannot panic() yet since the console
625 * is not ready. So for now, just assert(). Boards which need an early
626 * FDT (prior to console ready) will need to make their own
627 * arrangements and do their own checks.
629 assert(!fdtdec_prepare_fdt(gd->fdt_blob));
633 int fdtdec_lookup_phandle(const void *blob, int node, const char *prop_name)
638 debug("%s: %s\n", __func__, prop_name);
639 phandle = fdt_getprop(blob, node, prop_name, NULL);
641 return -FDT_ERR_NOTFOUND;
643 lookup = fdt_node_offset_by_phandle(blob, fdt32_to_cpu(*phandle));
648 * Look up a property in a node and check that it has a minimum length.
650 * @param blob FDT blob
651 * @param node node to examine
652 * @param prop_name name of property to find
653 * @param min_len minimum property length in bytes
654 * @param err 0 if ok, or -FDT_ERR_NOTFOUND if the property is not
655 found, or -FDT_ERR_BADLAYOUT if not enough data
656 * Return: pointer to cell, which is only valid if err == 0
658 static const void *get_prop_check_min_len(const void *blob, int node,
659 const char *prop_name, int min_len,
665 debug("%s: %s\n", __func__, prop_name);
666 cell = fdt_getprop(blob, node, prop_name, &len);
668 *err = -FDT_ERR_NOTFOUND;
669 else if (len < min_len)
670 *err = -FDT_ERR_BADLAYOUT;
676 int fdtdec_get_int_array(const void *blob, int node, const char *prop_name,
677 u32 *array, int count)
682 debug("%s: %s\n", __func__, prop_name);
683 cell = get_prop_check_min_len(blob, node, prop_name,
684 sizeof(u32) * count, &err);
688 for (i = 0; i < count; i++)
689 array[i] = fdt32_to_cpu(cell[i]);
694 int fdtdec_get_int_array_count(const void *blob, int node,
695 const char *prop_name, u32 *array, int count)
701 debug("%s: %s\n", __func__, prop_name);
702 cell = fdt_getprop(blob, node, prop_name, &len);
704 return -FDT_ERR_NOTFOUND;
705 elems = len / sizeof(u32);
708 for (i = 0; i < count; i++)
709 array[i] = fdt32_to_cpu(cell[i]);
714 const u32 *fdtdec_locate_array(const void *blob, int node,
715 const char *prop_name, int count)
720 cell = get_prop_check_min_len(blob, node, prop_name,
721 sizeof(u32) * count, &err);
722 return err ? NULL : cell;
725 int fdtdec_get_bool(const void *blob, int node, const char *prop_name)
730 debug("%s: %s\n", __func__, prop_name);
731 cell = fdt_getprop(blob, node, prop_name, &len);
735 int fdtdec_parse_phandle_with_args(const void *blob, int src_node,
736 const char *list_name,
737 const char *cells_name,
738 int cell_count, int index,
739 struct fdtdec_phandle_args *out_args)
741 const __be32 *list, *list_end;
742 int rc = 0, size, cur_index = 0;
747 /* Retrieve the phandle list property */
748 list = fdt_getprop(blob, src_node, list_name, &size);
751 list_end = list + size / sizeof(*list);
753 /* Loop over the phandles until all the requested entry is found */
754 while (list < list_end) {
759 * If phandle is 0, then it is an empty entry with no
760 * arguments. Skip forward to the next entry.
762 phandle = be32_to_cpup(list++);
765 * Find the provider node and parse the #*-cells
766 * property to determine the argument length.
768 * This is not needed if the cell count is hard-coded
769 * (i.e. cells_name not set, but cell_count is set),
770 * except when we're going to return the found node
773 if (cells_name || cur_index == index) {
774 node = fdt_node_offset_by_phandle(blob,
777 debug("%s: could not find phandle\n",
778 fdt_get_name(blob, src_node,
785 count = fdtdec_get_int(blob, node, cells_name,
788 debug("%s: could not get %s for %s\n",
789 fdt_get_name(blob, src_node,
792 fdt_get_name(blob, node,
801 * Make sure that the arguments actually fit in the
802 * remaining property data length
804 if (list + count > list_end) {
805 debug("%s: arguments longer than property\n",
806 fdt_get_name(blob, src_node, NULL));
812 * All of the error cases above bail out of the loop, so at
813 * this point, the parsing is successful. If the requested
814 * index matches, then fill the out_args structure and return,
815 * or return -ENOENT for an empty entry.
818 if (cur_index == index) {
825 if (count > MAX_PHANDLE_ARGS) {
826 debug("%s: too many arguments %d\n",
827 fdt_get_name(blob, src_node,
829 count = MAX_PHANDLE_ARGS;
831 out_args->node = node;
832 out_args->args_count = count;
833 for (i = 0; i < count; i++) {
835 be32_to_cpup(list++);
839 /* Found it! return success */
849 * Result will be one of:
850 * -ENOENT : index is for empty phandle
851 * -EINVAL : parsing error on data
852 * [1..n] : Number of phandle (count mode; when index = -1)
854 rc = index < 0 ? cur_index : -ENOENT;
859 int fdtdec_get_byte_array(const void *blob, int node, const char *prop_name,
860 u8 *array, int count)
865 cell = get_prop_check_min_len(blob, node, prop_name, count, &err);
867 memcpy(array, cell, count);
871 const u8 *fdtdec_locate_byte_array(const void *blob, int node,
872 const char *prop_name, int count)
877 cell = get_prop_check_min_len(blob, node, prop_name, count, &err);
883 u64 fdtdec_get_number(const fdt32_t *ptr, unsigned int cells)
888 number = (number << 32) | fdt32_to_cpu(*ptr++);
893 int fdt_get_resource(const void *fdt, int node, const char *property,
894 unsigned int index, struct fdt_resource *res)
896 const fdt32_t *ptr, *end;
897 int na, ns, len, parent;
900 parent = fdt_parent_offset(fdt, node);
904 na = fdt_address_cells(fdt, parent);
905 ns = fdt_size_cells(fdt, parent);
907 ptr = fdt_getprop(fdt, node, property, &len);
911 end = ptr + len / sizeof(*ptr);
913 while (ptr + na + ns <= end) {
915 if (CONFIG_IS_ENABLED(OF_TRANSLATE))
916 res->start = fdt_translate_address(fdt, node, ptr);
918 res->start = fdtdec_get_number(ptr, na);
920 res->end = res->start;
921 res->end += fdtdec_get_number(&ptr[na], ns) - 1;
929 return -FDT_ERR_NOTFOUND;
932 int fdt_get_named_resource(const void *fdt, int node, const char *property,
933 const char *prop_names, const char *name,
934 struct fdt_resource *res)
938 index = fdt_stringlist_search(fdt, node, prop_names, name);
942 return fdt_get_resource(fdt, node, property, index, res);
945 static int decode_timing_property(const void *blob, int node, const char *name,
946 struct timing_entry *result)
951 prop = fdt_getprop(blob, node, name, &length);
953 debug("%s: could not find property %s\n",
954 fdt_get_name(blob, node, NULL), name);
958 if (length == sizeof(u32)) {
959 result->typ = fdtdec_get_int(blob, node, name, 0);
960 result->min = result->typ;
961 result->max = result->typ;
963 ret = fdtdec_get_int_array(blob, node, name, &result->min, 3);
969 int fdtdec_decode_display_timing(const void *blob, int parent, int index,
970 struct display_timing *dt)
972 int i, node, timings_node;
976 timings_node = fdt_subnode_offset(blob, parent, "display-timings");
977 if (timings_node < 0)
980 for (i = 0, node = fdt_first_subnode(blob, timings_node);
981 node > 0 && i != index;
982 node = fdt_next_subnode(blob, node))
988 memset(dt, 0, sizeof(*dt));
990 ret |= decode_timing_property(blob, node, "hback-porch",
992 ret |= decode_timing_property(blob, node, "hfront-porch",
994 ret |= decode_timing_property(blob, node, "hactive", &dt->hactive);
995 ret |= decode_timing_property(blob, node, "hsync-len", &dt->hsync_len);
996 ret |= decode_timing_property(blob, node, "vback-porch",
998 ret |= decode_timing_property(blob, node, "vfront-porch",
1000 ret |= decode_timing_property(blob, node, "vactive", &dt->vactive);
1001 ret |= decode_timing_property(blob, node, "vsync-len", &dt->vsync_len);
1002 ret |= decode_timing_property(blob, node, "clock-frequency",
1006 val = fdtdec_get_int(blob, node, "vsync-active", -1);
1008 dt->flags |= val ? DISPLAY_FLAGS_VSYNC_HIGH :
1009 DISPLAY_FLAGS_VSYNC_LOW;
1011 val = fdtdec_get_int(blob, node, "hsync-active", -1);
1013 dt->flags |= val ? DISPLAY_FLAGS_HSYNC_HIGH :
1014 DISPLAY_FLAGS_HSYNC_LOW;
1016 val = fdtdec_get_int(blob, node, "de-active", -1);
1018 dt->flags |= val ? DISPLAY_FLAGS_DE_HIGH :
1019 DISPLAY_FLAGS_DE_LOW;
1021 val = fdtdec_get_int(blob, node, "pixelclk-active", -1);
1023 dt->flags |= val ? DISPLAY_FLAGS_PIXDATA_POSEDGE :
1024 DISPLAY_FLAGS_PIXDATA_NEGEDGE;
1027 if (fdtdec_get_bool(blob, node, "interlaced"))
1028 dt->flags |= DISPLAY_FLAGS_INTERLACED;
1029 if (fdtdec_get_bool(blob, node, "doublescan"))
1030 dt->flags |= DISPLAY_FLAGS_DOUBLESCAN;
1031 if (fdtdec_get_bool(blob, node, "doubleclk"))
1032 dt->flags |= DISPLAY_FLAGS_DOUBLECLK;
1037 int fdtdec_setup_mem_size_base(void)
1041 struct resource res;
1043 mem = ofnode_path("/memory");
1044 if (!ofnode_valid(mem)) {
1045 debug("%s: Missing /memory node\n", __func__);
1049 ret = ofnode_read_resource(mem, 0, &res);
1051 debug("%s: Unable to decode first memory bank\n", __func__);
1055 gd->ram_size = (phys_size_t)(res.end - res.start + 1);
1056 gd->ram_base = (unsigned long)res.start;
1057 debug("%s: Initial DRAM size %llx\n", __func__,
1058 (unsigned long long)gd->ram_size);
1063 ofnode get_next_memory_node(ofnode mem)
1066 mem = ofnode_by_prop_value(mem, "device_type", "memory", 7);
1067 } while (!ofnode_is_enabled(mem));
1072 int fdtdec_setup_memory_banksize(void)
1074 int bank, ret, reg = 0;
1075 struct resource res;
1076 ofnode mem = ofnode_null();
1078 mem = get_next_memory_node(mem);
1079 if (!ofnode_valid(mem)) {
1080 debug("%s: Missing /memory node\n", __func__);
1084 for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
1085 ret = ofnode_read_resource(mem, reg++, &res);
1088 mem = get_next_memory_node(mem);
1089 if (!ofnode_valid(mem))
1092 ret = ofnode_read_resource(mem, reg++, &res);
1100 gd->bd->bi_dram[bank].start = (phys_addr_t)res.start;
1101 gd->bd->bi_dram[bank].size =
1102 (phys_size_t)(res.end - res.start + 1);
1104 debug("%s: DRAM Bank #%d: start = 0x%llx, size = 0x%llx\n",
1106 (unsigned long long)gd->bd->bi_dram[bank].start,
1107 (unsigned long long)gd->bd->bi_dram[bank].size);
1113 int fdtdec_setup_mem_size_base_lowest(void)
1115 int bank, ret, reg = 0;
1116 struct resource res;
1119 ofnode mem = ofnode_null();
1121 gd->ram_base = (unsigned long)~0;
1123 mem = get_next_memory_node(mem);
1124 if (!ofnode_valid(mem)) {
1125 debug("%s: Missing /memory node\n", __func__);
1129 for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
1130 ret = ofnode_read_resource(mem, reg++, &res);
1133 mem = get_next_memory_node(mem);
1134 if (!ofnode_valid(mem))
1137 ret = ofnode_read_resource(mem, reg++, &res);
1145 base = (unsigned long)res.start;
1146 size = (phys_size_t)(res.end - res.start + 1);
1148 if (gd->ram_base > base && size) {
1149 gd->ram_base = base;
1150 gd->ram_size = size;
1151 debug("%s: Initial DRAM base %lx size %lx\n",
1152 __func__, base, (unsigned long)size);
1159 static int uncompress_blob(const void *src, ulong sz_src, void **dstp)
1161 #if CONFIG_IS_ENABLED(MULTI_DTB_FIT_GZIP) ||\
1162 CONFIG_IS_ENABLED(MULTI_DTB_FIT_LZO)
1163 size_t sz_out = CONFIG_VAL(MULTI_DTB_FIT_UNCOMPRESS_SZ);
1164 bool gzip = 0, lzo = 0;
1165 ulong sz_in = sz_src;
1169 if (CONFIG_IS_ENABLED(GZIP))
1170 if (gzip_parse_header(src, sz_in) >= 0)
1172 if (CONFIG_IS_ENABLED(LZO))
1173 if (!gzip && lzop_is_valid_header(src))
1180 if (CONFIG_IS_ENABLED(MULTI_DTB_FIT_DYN_ALLOC)) {
1181 dst = malloc(sz_out);
1183 puts("uncompress_blob: Unable to allocate memory\n");
1187 # if CONFIG_IS_ENABLED(MULTI_DTB_FIT_USER_DEFINED_AREA)
1188 dst = (void *)CONFIG_VAL(MULTI_DTB_FIT_USER_DEF_ADDR);
1194 if (CONFIG_IS_ENABLED(GZIP) && gzip)
1195 rc = gunzip(dst, sz_out, (u8 *)src, &sz_in);
1196 else if (CONFIG_IS_ENABLED(LZO) && lzo)
1197 rc = lzop_decompress(src, sz_in, dst, &sz_out);
1202 /* not a valid compressed blob */
1203 puts("uncompress_blob: Unable to uncompress\n");
1204 if (CONFIG_IS_ENABLED(MULTI_DTB_FIT_DYN_ALLOC))
1210 *dstp = (void *)src;
1211 *dstp = (void *)src;
1217 * fdt_find_separate() - Find a devicetree at the end of the image
1219 * Return: pointer to FDT blob
1221 static void *fdt_find_separate(void)
1223 void *fdt_blob = NULL;
1225 if (IS_ENABLED(CONFIG_SANDBOX))
1228 #ifdef CONFIG_SPL_BUILD
1229 /* FDT is at end of BSS unless it is in a different memory region */
1230 if (IS_ENABLED(CONFIG_SPL_SEPARATE_BSS))
1231 fdt_blob = (ulong *)&_image_binary_end;
1233 fdt_blob = (ulong *)&__bss_end;
1235 /* FDT is at end of image */
1236 fdt_blob = (ulong *)&_end;
1238 if (_DEBUG && !fdtdec_prepare_fdt(fdt_blob)) {
1240 const void *top = fdt_blob + fdt_totalsize(fdt_blob);
1243 * Perform a sanity check on the memory layout. If this fails,
1244 * it indicates that the device tree is positioned above the
1245 * global data pointer or the stack pointer. This should not
1248 * If this fails, check that SYS_INIT_SP_ADDR has enough space
1249 * below it for SYS_MALLOC_F_LEN and global_data, as well as the
1250 * stack, without overwriting the device tree or U-Boot itself.
1251 * Since the device tree is sitting at _end (the start of the
1252 * BSS region), we need the top of the device tree to be below
1253 * any memory allocated by board_init_f_alloc_reserve().
1255 if (top > (void *)gd || top > (void *)&stack_ptr) {
1256 printf("FDT %p gd %p\n", fdt_blob, gd);
1257 panic("FDT overlap");
1265 int fdtdec_set_ethernet_mac_address(void *fdt, const u8 *mac, size_t size)
1270 if (!is_valid_ethaddr(mac))
1273 path = fdt_get_alias(fdt, "ethernet");
1277 debug("ethernet alias found: %s\n", path);
1279 offset = fdt_path_offset(fdt, path);
1281 debug("ethernet alias points to absent node %s\n", path);
1285 err = fdt_setprop_inplace(fdt, offset, "local-mac-address", mac, size);
1289 debug("MAC address: %pM\n", mac);
1294 static int fdtdec_init_reserved_memory(void *blob)
1296 int na, ns, node, err;
1299 /* inherit #address-cells and #size-cells from the root node */
1300 na = fdt_address_cells(blob, 0);
1301 ns = fdt_size_cells(blob, 0);
1303 node = fdt_add_subnode(blob, 0, "reserved-memory");
1307 err = fdt_setprop(blob, node, "ranges", NULL, 0);
1311 value = cpu_to_fdt32(ns);
1313 err = fdt_setprop(blob, node, "#size-cells", &value, sizeof(value));
1317 value = cpu_to_fdt32(na);
1319 err = fdt_setprop(blob, node, "#address-cells", &value, sizeof(value));
1326 int fdtdec_add_reserved_memory(void *blob, const char *basename,
1327 const struct fdt_memory *carveout,
1328 const char **compatibles, unsigned int count,
1329 uint32_t *phandlep, unsigned long flags)
1331 fdt32_t cells[4] = {}, *ptr = cells;
1332 uint32_t upper, lower, phandle;
1333 int parent, node, na, ns, err;
1337 /* create an empty /reserved-memory node if one doesn't exist */
1338 parent = fdt_path_offset(blob, "/reserved-memory");
1340 parent = fdtdec_init_reserved_memory(blob);
1345 /* only 1 or 2 #address-cells and #size-cells are supported */
1346 na = fdt_address_cells(blob, parent);
1347 if (na < 1 || na > 2)
1348 return -FDT_ERR_BADNCELLS;
1350 ns = fdt_size_cells(blob, parent);
1351 if (ns < 1 || ns > 2)
1352 return -FDT_ERR_BADNCELLS;
1354 /* find a matching node and return the phandle to that */
1355 fdt_for_each_subnode(node, blob, parent) {
1356 const char *name = fdt_get_name(blob, node, NULL);
1360 addr = fdtdec_get_addr_size_fixed(blob, node, "reg", 0, na, ns,
1362 if (addr == FDT_ADDR_T_NONE) {
1363 debug("failed to read address/size for %s\n", name);
1367 if (addr == carveout->start && (addr + size - 1) ==
1370 *phandlep = fdt_get_phandle(blob, node);
1376 * Unpack the start address and generate the name of the new node
1377 * base on the basename and the unit-address.
1379 upper = upper_32_bits(carveout->start);
1380 lower = lower_32_bits(carveout->start);
1382 if (na > 1 && upper > 0)
1383 snprintf(name, sizeof(name), "%s@%x,%x", basename, upper,
1387 debug("address %08x:%08x exceeds addressable space\n",
1389 return -FDT_ERR_BADVALUE;
1392 snprintf(name, sizeof(name), "%s@%x", basename, lower);
1395 node = fdt_add_subnode(blob, parent, name);
1399 if (flags & FDTDEC_RESERVED_MEMORY_NO_MAP) {
1400 err = fdt_setprop(blob, node, "no-map", NULL, 0);
1406 err = fdt_generate_phandle(blob, &phandle);
1410 err = fdtdec_set_phandle(blob, node, phandle);
1415 /* store one or two address cells */
1417 *ptr++ = cpu_to_fdt32(upper);
1419 *ptr++ = cpu_to_fdt32(lower);
1421 /* store one or two size cells */
1422 size = carveout->end - carveout->start + 1;
1423 upper = upper_32_bits(size);
1424 lower = lower_32_bits(size);
1427 *ptr++ = cpu_to_fdt32(upper);
1429 *ptr++ = cpu_to_fdt32(lower);
1431 err = fdt_setprop(blob, node, "reg", cells, (na + ns) * sizeof(*cells));
1435 if (compatibles && count > 0) {
1436 size_t length = 0, len = 0;
1440 for (i = 0; i < count; i++)
1441 length += strlen(compatibles[i]) + 1;
1443 buffer = malloc(length);
1445 return -FDT_ERR_INTERNAL;
1447 for (i = 0; i < count; i++)
1448 len += strlcpy(buffer + len, compatibles[i],
1451 err = fdt_setprop(blob, node, "compatible", buffer, length);
1457 /* return the phandle for the new node for the caller to use */
1459 *phandlep = phandle;
1464 int fdtdec_get_carveout(const void *blob, const char *node,
1465 const char *prop_name, unsigned int index,
1466 struct fdt_memory *carveout, const char **name,
1467 const char ***compatiblesp, unsigned int *countp,
1468 unsigned long *flags)
1470 const fdt32_t *prop;
1475 offset = fdt_path_offset(blob, node);
1479 prop = fdt_getprop(blob, offset, prop_name, &len);
1481 debug("failed to get %s for %s\n", prop_name, node);
1482 return -FDT_ERR_NOTFOUND;
1485 if ((len % sizeof(phandle)) != 0) {
1486 debug("invalid phandle property\n");
1487 return -FDT_ERR_BADPHANDLE;
1490 if (len < (sizeof(phandle) * (index + 1))) {
1491 debug("invalid phandle index\n");
1492 return -FDT_ERR_NOTFOUND;
1495 phandle = fdt32_to_cpu(prop[index]);
1497 offset = fdt_node_offset_by_phandle(blob, phandle);
1499 debug("failed to find node for phandle %u\n", phandle);
1504 *name = fdt_get_name(blob, offset, NULL);
1507 const char **compatibles = NULL;
1508 const char *start, *end, *ptr;
1509 unsigned int count = 0;
1511 prop = fdt_getprop(blob, offset, "compatible", &len);
1515 start = ptr = (const char *)prop;
1519 ptr = strchrnul(ptr, '\0');
1524 compatibles = malloc(sizeof(ptr) * count);
1526 return -FDT_ERR_INTERNAL;
1532 compatibles[count] = ptr;
1533 ptr = strchrnul(ptr, '\0');
1539 *compatiblesp = compatibles;
1545 carveout->start = fdtdec_get_addr_size_auto_noparent(blob, offset,
1548 if (carveout->start == FDT_ADDR_T_NONE) {
1549 debug("failed to read address/size from \"reg\" property\n");
1550 return -FDT_ERR_NOTFOUND;
1553 carveout->end = carveout->start + size - 1;
1558 if (fdtdec_get_bool(blob, offset, "no-map"))
1559 *flags |= FDTDEC_RESERVED_MEMORY_NO_MAP;
1565 int fdtdec_set_carveout(void *blob, const char *node, const char *prop_name,
1566 unsigned int index, const struct fdt_memory *carveout,
1567 const char *name, const char **compatibles,
1568 unsigned int count, unsigned long flags)
1571 int err, offset, len;
1575 err = fdtdec_add_reserved_memory(blob, name, carveout, compatibles,
1576 count, &phandle, flags);
1578 debug("failed to add reserved memory: %d\n", err);
1582 offset = fdt_path_offset(blob, node);
1584 debug("failed to find offset for node %s: %d\n", node, offset);
1588 value = cpu_to_fdt32(phandle);
1590 if (!fdt_getprop(blob, offset, prop_name, &len)) {
1591 if (len == -FDT_ERR_NOTFOUND)
1597 if ((index + 1) * sizeof(value) > len) {
1598 err = fdt_setprop_placeholder(blob, offset, prop_name,
1599 (index + 1) * sizeof(value),
1602 debug("failed to resize reserved memory property: %s\n",
1608 err = fdt_setprop_inplace_namelen_partial(blob, offset, prop_name,
1610 index * sizeof(value),
1611 &value, sizeof(value));
1613 debug("failed to update %s property for node %s: %s\n",
1614 prop_name, node, fdt_strerror(err));
1621 /* TODO(sjg@chromium.org): This function should not be weak */
1622 __weak int fdtdec_board_setup(const void *fdt_blob)
1628 * setup_multi_dtb_fit() - locate the correct dtb from a FIT
1630 * This supports the CONFIG_MULTI_DTB_FIT feature, looking for the dtb in a
1633 * It accepts the current value of gd->fdt_blob, which points to the FIT, then
1634 * updates that gd->fdt_blob, to point to the chosen dtb so that U-Boot uses the
1637 static void setup_multi_dtb_fit(void)
1642 * Try and uncompress the blob.
1643 * Unfortunately there is no way to know how big the input blob really
1644 * is. So let us set the maximum input size arbitrarily high. 16MB
1645 * ought to be more than enough for packed DTBs.
1647 if (uncompress_blob(gd->fdt_blob, 0x1000000, &blob) == 0)
1648 gd->fdt_blob = blob;
1651 * Check if blob is a FIT images containings DTBs.
1652 * If so, pick the most relevant
1654 blob = locate_dtb_in_fit(gd->fdt_blob);
1656 gd_set_multi_dtb_fit(gd->fdt_blob);
1657 gd->fdt_blob = blob;
1658 gd->fdt_src = FDTSRC_FIT;
1662 int fdtdec_setup(void)
1666 /* The devicetree is typically appended to U-Boot */
1667 if (IS_ENABLED(CONFIG_OF_SEPARATE)) {
1668 gd->fdt_blob = fdt_find_separate();
1669 gd->fdt_src = FDTSRC_SEPARATE;
1670 } else { /* embed dtb in ELF file for testing / development */
1671 gd->fdt_blob = dtb_dt_embedded();
1672 gd->fdt_src = FDTSRC_EMBED;
1675 /* Allow the board to override the fdt address. */
1676 if (IS_ENABLED(CONFIG_OF_BOARD)) {
1677 gd->fdt_blob = board_fdt_blob_setup(&ret);
1680 gd->fdt_src = FDTSRC_BOARD;
1683 /* Allow the early environment to override the fdt address */
1684 if (!IS_ENABLED(CONFIG_SPL_BUILD)) {
1687 addr = env_get_hex("fdtcontroladdr", 0);
1689 gd->fdt_blob = map_sysmem(addr, 0);
1690 gd->fdt_src = FDTSRC_ENV;
1694 if (CONFIG_IS_ENABLED(MULTI_DTB_FIT))
1695 setup_multi_dtb_fit();
1697 ret = fdtdec_prepare_fdt(gd->fdt_blob);
1699 ret = fdtdec_board_setup(gd->fdt_blob);
1705 int fdtdec_resetup(int *rescan)
1710 * If the current DTB is part of a compressed FIT image,
1711 * try to locate the best match from the uncompressed
1712 * FIT image stillpresent there. Save the time and space
1713 * required to uncompress it again.
1715 if (gd_multi_dtb_fit()) {
1716 fdt_blob = locate_dtb_in_fit(gd_multi_dtb_fit());
1718 if (fdt_blob == gd->fdt_blob) {
1720 * The best match did not change. no need to tear down
1721 * the DM and rescan the fdt.
1728 gd->fdt_blob = fdt_blob;
1729 return fdtdec_prepare_fdt(fdt_blob);
1733 * If multi_dtb_fit is NULL, it means that blob appended to u-boot is
1734 * not a FIT image containings DTB, but a single DTB. There is no need
1735 * to teard down DM and rescan the DT in this case.
1741 int fdtdec_decode_ram_size(const void *blob, const char *area, int board_id,
1742 phys_addr_t *basep, phys_size_t *sizep,
1745 int addr_cells, size_cells;
1746 const u32 *cell, *end;
1747 u64 total_size, size, addr;
1753 debug("%s: board_id=%d\n", __func__, board_id);
1756 node = fdt_path_offset(blob, area);
1758 debug("No %s node found\n", area);
1762 cell = fdt_getprop(blob, node, "reg", &len);
1764 debug("No reg property found\n");
1768 addr_cells = fdt_address_cells(blob, node);
1769 size_cells = fdt_size_cells(blob, node);
1771 /* Check the board id and mask */
1772 for (child = fdt_first_subnode(blob, node);
1774 child = fdt_next_subnode(blob, child)) {
1775 int match_mask, match_value;
1777 match_mask = fdtdec_get_int(blob, child, "match-mask", -1);
1778 match_value = fdtdec_get_int(blob, child, "match-value", -1);
1780 if (match_value >= 0 &&
1781 ((board_id & match_mask) == match_value)) {
1782 /* Found matching mask */
1783 debug("Found matching mask %d\n", match_mask);
1785 cell = fdt_getprop(blob, node, "reg", &len);
1787 debug("No memory-banks property found\n");
1793 /* Note: if no matching subnode was found we use the parent node */
1796 memset(bd->bi_dram, '\0', sizeof(bd->bi_dram[0]) *
1797 CONFIG_NR_DRAM_BANKS);
1800 auto_size = fdtdec_get_bool(blob, node, "auto-size");
1803 end = cell + len / 4 - addr_cells - size_cells;
1804 debug("cell at %p, end %p\n", cell, end);
1805 for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
1809 if (addr_cells == 2)
1810 addr += (u64)fdt32_to_cpu(*cell++) << 32UL;
1811 addr += fdt32_to_cpu(*cell++);
1813 bd->bi_dram[bank].start = addr;
1815 *basep = (phys_addr_t)addr;
1818 if (size_cells == 2)
1819 size += (u64)fdt32_to_cpu(*cell++) << 32UL;
1820 size += fdt32_to_cpu(*cell++);
1825 debug("Auto-sizing %llx, size %llx: ", addr, size);
1826 new_size = get_ram_size((long *)(uintptr_t)addr, size);
1827 if (new_size == size) {
1830 debug("sized to %llx\n", new_size);
1836 bd->bi_dram[bank].size = size;
1840 debug("Memory size %llu\n", total_size);
1842 *sizep = (phys_size_t)total_size;
1847 #endif /* !USE_HOSTCC */