kprobe/arch/asm-arm/dbi_kprobes.h

   1 #ifndef _DBI_ASM_ARM_KPROBES_H
   2 #define _DBI_ASM_ARM_KPROBES_H
   3
   4 /*
   5  *  Dynamic Binary Instrumentation Module based on KProbes
   6  *  modules/kprobe/arch/asm-arm/dbi_kprobes.h
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  21  *
  22  * Copyright (C) Samsung Electronics, 2006-2010
  23  *
  24  * 2006-2007    Ekaterina Gorelkina <e.gorelkina@samsung.com>: initial implementation for ARM/MIPS
  25  * 2008-2009    Alexey Gerenkov <a.gerenkov@samsung.com> User-Space
  26  *              Probes initial implementation; Support x86/ARM/MIPS for both user and kernel spaces.
  27  * 2010         Ekaterina Gorelkina <e.gorelkina@samsung.com>: redesign module for separating core and arch parts
  28  *
  29  * 2010-2011    Alexander Shirshikov <a.shirshikov@samsung.com>: initial implementation for Thumb
  30  */
  31
  32 #include <linux/sched.h>
  33 #include "../../dbi_kprobes_deps.h"
  34 #include "../dbi_kprobes.h"
  35 #include "dbi_kprobes_arm.h"
  36 #include "dbi_kprobes_thumb.h"
  37
  38 typedef unsigned long kprobe_opcode_t;
  39
  40 #ifdef CONFIG_CPU_S3C2443
  41 #define BREAKPOINT_INSTRUCTION          0xe1200070
  42 #else
  43 #define BREAKPOINT_INSTRUCTION          0xffffdeff
  44 #endif /* CONFIG_CPU_S3C2443 */
  45
  46 #ifndef KPROBES_RET_PROBE_TRAMP
  47
  48 #ifdef CONFIG_CPU_S3C2443
  49 #define UNDEF_INSTRUCTION               0xe1200071
  50 #else
  51 #define UNDEF_INSTRUCTION               0xfffffffe
  52 #endif /* CONFIG_CPU_S3C2443 */
  53
  54 #endif /* KPROBES_RET_PROBE_TRAMP */
  55
  56 #define MAX_INSN_SIZE                   1
  57
  58 # define UPROBES_TRAMP_LEN              9
  59 # define UPROBES_TRAMP_INSN_IDX         2
  60 # define UPROBES_TRAMP_SS_BREAK_IDX     4
  61 # define UPROBES_TRAMP_RET_BREAK_IDX    5
  62 # define KPROBES_TRAMP_LEN              9
  63 # define KPROBES_TRAMP_INSN_IDX         UPROBES_TRAMP_INSN_IDX
  64 # define KPROBES_TRAMP_SS_BREAK_IDX     UPROBES_TRAMP_SS_BREAK_IDX
  65 # define KPROBES_TRAMP_RET_BREAK_IDX    UPROBES_TRAMP_RET_BREAK_IDX
  66
  67 #define UREGS_OFFSET 8
  68
  69 static inline unsigned long *arch_get_patch_addr(struct task_struct *p,
  70                                                  struct pt_regs *regs)
  71 {
  72         return &task_thread_info(p)->cpu_context.pc;
  73 }
  74
  75 static inline unsigned long arch_get_task_pc(struct task_struct *p)
  76 {
  77         return task_thread_info(p)->cpu_context.pc;
  78 }
  79
  80 static inline void arch_set_task_pc(struct task_struct *p, unsigned long val)
  81 {
  82         task_thread_info(p)->cpu_context.pc = val;
  83 }
  84
  85 static inline struct pt_regs *dbi_get_syscall_uregs(unsigned long sp)
  86 {
  87         return (struct pt_regs *)(sp + UREGS_OFFSET);
  88 }
  89
  90 static inline unsigned long dbi_get_stack_ptr(struct pt_regs *regs)
  91 {
  92         return regs->ARM_sp;
  93 }
  94
  95 static inline unsigned long dbi_get_instr_ptr(struct pt_regs *regs)
  96 {
  97         return regs->ARM_pc;
  98 }
  99
 100 static inline void dbi_set_instr_ptr(struct pt_regs *regs, unsigned long val)
 101 {
 102         regs->ARM_pc = val;
 103 }
 104
 105 static inline unsigned long dbi_get_ret_addr(struct pt_regs *regs)
 106 {
 107         return regs->ARM_lr;
 108 }
 109
 110 static inline void dbi_set_ret_addr(struct pt_regs *regs, unsigned long val)
 111 {
 112         regs->ARM_lr = val;
 113 }
 114
 115 static inline unsigned long dbi_get_arg(struct pt_regs *regs, int num)
 116 {
 117         return regs->uregs[num];
 118 }
 119
 120 static inline void dbi_set_arg(struct pt_regs *regs, int num, unsigned long val)
 121 {
 122         regs->uregs[num] = val;
 123 }
 124
 125 static inline int dbi_fp_backtrace(struct task_struct *task, unsigned long *buf,
 126                 int max_cnt)
 127 {
 128         int i = 0;
 129         struct pt_regs *regs;
 130
 131         struct {
 132                 unsigned long next;
 133                 unsigned long raddr;
 134         } frame;
 135
 136         regs = task_pt_regs(task);
 137         frame.next = regs->ARM_fp;
 138         frame.raddr = dbi_get_ret_addr(regs);
 139
 140         while (frame.next && i < max_cnt) {
 141                 if (read_proc_vm_atomic(task, frame.next - 4, &frame, sizeof(frame))
 142                                 == sizeof(frame))
 143                         buf[i++] = frame.raddr;
 144                 else
 145                         break;
 146         }
 147
 148         return i;
 149 }
 150
 151 #define NOTIFIER_CALL_CHAIN_INDEX       3
 152
 153 // undefined
 154 # define MASK_ARM_INSN_UNDEF            0x0FF00000              // xxxx1111 1111xxxx xxxxxxxx xxxxxxxx
 155 # define PTRN_ARM_INSN_UNDEF            0x03000000              // cccc0011 0000xxxx xxxxxxxx xxxxxxxx
 156
 157 # define MASK_THUMB_INSN_UNDEF          0xFE00                  // 11111111xxxxxxxx
 158 # define PTRN_THUMB_INSN_UNDEF          0xDE00                  // 11011110xxxxxxxx
 159
 160 // architecturally undefined
 161 # define MASK_ARM_INSN_AUNDEF           0x0FF000F0
 162 # define PTRN_ARM_INSN_AUNDEF           0x07F000F0
 163
 164 // branches
 165 # define MASK_ARM_INSN_B                0x0E000000              // xxxx111xxxxxxxxxxxxxxxxxxxxxxxxx
 166 # define PTRN_ARM_INSN_B                0x0A000000              // cccc101xxxxxxxxxxxxxxxxxxxxxxxxx
 167
 168 # define MASK_THUMB_INSN_B1             0xF000                  // 1111xxxxxxxxxxxx
 169 # define PTRN_THUMB_INSN_B1             0xD000                  // 1101xxxxxxxxxxxx                                             // b<cond> label
 170
 171 # define MASK_THUMB_INSN_B2             0xF800                  // 11111xxxxxxxxxxx
 172 # define PTRN_THUMB_INSN_B2             0xE000                  // 11100xxxxxxxxxxx                                             // b label
 173
 174 # define MASK_THUMB_INSN_CBZ            0xF500                  // 1111x1x1xxxxxxxx
 175 # define PTRN_THUMB_INSN_CBZ            0xB100                  // 1011x0x1xxxxxxxx                                             // CBZ/CBNZ
 176
 177 # define MASK_THUMB2_INSN_B1            0xD000F800              // 11x1xxxxxxxxxxxx 11111xxxxxxxxxxx                            // swapped
 178 # define PTRN_THUMB2_INSN_B1            0x8000F000              // 10x0xxxxxxxxxxxx 11110xxxxxxxxxxx                            // swapped
 179
 180 # define MASK_THUMB2_INSN_B2            0xD000F800              // 11x1xxxxxxxxxxxx 11111xxxxxxxxxxx                            // swapped
 181 # define PTRN_THUMB2_INSN_B2            0x9000F000              // 10x1xxxxxxxxxxxx 11110xxxxxxxxxxx                            // swapped
 182
 183 # define MASK_ARM_INSN_BL               0x0E000000              // xxxx111xxxxxxxxxxxxxxxxxxxxxxxxx
 184 # define PTRN_ARM_INSN_BL               0x0B000000              // cccc1011xxxxxxxxxxxxxxxxxxxxxxxx
 185
 186 //# define MASK_THUMB_INSN_BL           0xF800                  // 11111xxxxxxxxxxx
 187 //# define PTRN_THUMB_INSN_BL           0xF000                  // 11110xxxxxxxxxxx                                             // shared between BL and BLX
 188 //# define PTRN_THUMB_INSN_BL           0xF800                  // 11111xxxxxxxxxxx
 189
 190 # define MASK_THUMB2_INSN_BL            0xD000F800              // 11x1xxxxxxxxxxxx 11111xxxxxxxxxxx                            // swapped
 191 # define PTRN_THUMB2_INSN_BL            0xD000F000              // 11x1xxxxxxxxxxxx 11110xxxxxxxxxxx                            // bl imm  swapped
 192
 193 # define MASK_ARM_INSN_BLX1             0xFF000000              // 11111111xxxxxxxxxxxxxxxxxxxxxxxx
 194 # define PTRN_ARM_INSN_BLX1             0xFA000000              // 11111011xxxxxxxxxxxxxxxxxxxxxxxx
 195
 196 //# define MASK_THUMB_INSN_BLX1         0xF800                  // 11111xxxxxxxxxxx                                             / blx imm
 197 //# define PTRN_THUMB_INSN_BLX1         0xF000                  // 11101xxxxxxxxxxx
 198
 199 # define MASK_THUMB2_INSN_BLX1          0xD001F800              // 11x1xxxxxxxxxxx1 11111xxxxxxxxxxx                            // swapped
 200 # define PTRN_THUMB2_INSN_BLX1          0xC000F000              // 11x0xxxxxxxxxxx0 11110xxxxxxxxxxx                            // swapped
 201
 202 # define MASK_ARM_INSN_BLX2             0x0FF000F0              // xxxx11111111xxxxxxxxxxxx1111xxxx
 203 # define PTRN_ARM_INSN_BLX2             0x01200030              // cccc00010010xxxxxxxxxxxx0011xxxx
 204
 205 # define MASK_THUMB_INSN_BLX2           0xFF80                  // 111111111xxxxxxx                                             / blx reg
 206 # define PTRN_THUMB_INSN_BLX2           0x4780                  // 010001111xxxxxxx
 207
 208 # define MASK_ARM_INSN_BX               0x0FF000F0              // cccc11111111xxxxxxxxxxxx1111xxxx
 209 # define PTRN_ARM_INSN_BX               0x01200010              // cccc00010010xxxxxxxxxxxx0001xxxx
 210
 211 # define MASK_THUMB_INSN_BX             0xFF80                  // 111111111xxxxxxx
 212 # define PTRN_THUMB_INSN_BX             0x4700                  // 010001110xxxxxxx
 213
 214 # define MASK_ARM_INSN_BXJ              0x0FF000F0              // xxxx11111111xxxxxxxxxxxx1111xxxx
 215 # define PTRN_ARM_INSN_BXJ              0x01200020              // cccc00010010xxxxxxxxxxxx0010xxxx
 216
 217 # define MASK_THUMB2_INSN_BXJ           0xD000FFF0              // 11x1xxxxxxxxxxxx 111111111111xxxx                            // swapped
 218 # define PTRN_THUMB2_INSN_BXJ           0x8000F3C0              // 10x0xxxxxxxxxxxx 111100111100xxxx                            // swapped
 219
 220
 221 // software interrupts
 222 # define MASK_ARM_INSN_SWI              0x0F000000              // cccc1111xxxxxxxxxxxxxxxxxxxxxxxx
 223 # define PTRN_ARM_INSN_SWI              0x0F000000              // cccc1111xxxxxxxxxxxxxxxxxxxxxxxx
 224
 225 # define MASK_THUMB_INSN_SWI            0xFF00                  // 11111111xxxxxxxx
 226 # define PTRN_THUMB_INSN_SWI            0xDF00                  // 11011111xxxxxxxx
 227
 228 // break
 229 # define MASK_ARM_INSN_BREAK            0xFFF000F0              // 111111111111xxxxxxxxxxxx1111xxxx
 230 # define PTRN_ARM_INSN_BREAK            0xE1200070              // 111000010010xxxxxxxxxxxx0111xxxx                             /? A8-56 ARM DDI 046B if cond != ‘1110’ then UNPREDICTABLE;
 231
 232 # define MASK_THUMB_INSN_BREAK          0xFF00                  // 11111111xxxxxxxx
 233 # define PTRN_THUMB_INSN_BREAK          0xBE00                  // 10111110xxxxxxxx
 234
 235 // Data processing immediate shift
 236 # define MASK_ARM_INSN_DPIS             0x0E000010
 237 # define PTRN_ARM_INSN_DPIS             0x00000000
 238 // Data processing register shift
 239 # define MASK_ARM_INSN_DPRS             0x0E000090
 240 # define PTRN_ARM_INSN_DPRS             0x00000010
 241
 242 # define MASK_THUMB2_INSN_DPRS          0xFFE00000              // 11111111111xxxxxxxxxxxxxxxxxxxxx
 243 # define PTRN_THUMB2_INSN_DPRS          0xEA000000              // 1110101xxxxxxxxxxxxxxxxxxxxxxxxx
 244
 245 // Data processing immediate
 246 # define MASK_ARM_INSN_DPI              0x0E000000
 247 # define PTRN_ARM_INSN_DPI              0x02000000
 248
 249 # define MASK_THUMB_INSN_DP             0xFC00                  // 111111xxxxxxxxxx
 250 # define PTRN_THUMB_INSN_DP             0x4000                  // 010000xxxxxxxxxx
 251
 252 # define MASK_THUMB_INSN_APC            0xF800                  // 11111xxxxxxxxxxx
 253 # define PTRN_THUMB_INSN_APC            0xA000                  // 10100xxxxxxxxxxx     ADD Rd, [PC, #<imm8> * 4]
 254
 255 # define MASK_THUMB2_INSN_DPI           0xFBE08000              // 11111x11111xxxxx 1xxxxxxxxxxxxxxx
 256 //# define PTRN_THUMB2_INSN_DPI         0xF0000000              // 11110x0xxxxxxxxx 0xxxxxxxxxxxxxxx                            /? A6-19 ARM DDI 0406B
 257 # define PTRN_THUMB2_INSN_DPI           0xF2000000              // 11110x1xxxxxxxxx 0xxxxxxxxxxxxxxx                            /? A6-19 ARM DDI 0406B
 258
 259 # define MASK_THUMB_INSN_MOV3           0xFF00                  // 11111111xxxxxxxx
 260 # define PTRN_THUMB_INSN_MOV3           0x4600                  // 01000110xxxxxxxx     MOV Rd, PC
 261
 262 # define MASK_THUMB2_INSN_RSBW          0x8000fbe0              // 1xxxxxxxxxxxxxxx 11111x11111xxxxx    // swapped
 263 # define PTRN_THUMB2_INSN_RSBW          0x0000f1c0              // 0xxxxxxxxxxxxxxx 11110x01110xxxxx    RSB{S}.W Rd, Rn, #<const> // swapped
 264
 265 # define MASK_THUMB2_INSN_RORW          0xf0f0ffe0              // 1111xxxx1111xxxx 11111111111xxxxx    // swapped
 266 # define PTRN_THUMB2_INSN_RORW          0xf000fa60              // 1111xxxx0000xxxx 11111010011xxxxx    ROR{S}.W Rd, Rn, Rm // swapped
 267
 268 # define MASK_THUMB2_INSN_ROR           0x0030ffef              // xxxxxxxxxx11xxxx 11111111111x1111    // swapped
 269 # define PTRN_THUMB2_INSN_ROR           0x0030ea4f              // xxxxxxxxxx11xxxx 11101010010x1111    ROR{S} Rd, Rm, #<imm> // swapped
 270
 271 # define MASK_THUMB2_INSN_LSLW1         0xf0f0ffe0              // 1111xxxx1111xxxx 11111111111xxxxx    // swapped
 272 # define PTRN_THUMB2_INSN_LSLW1         0xf000fa00              // 1111xxxx0000xxxx 11111010000xxxxx    LSL{S}.W Rd, Rn, Rm // swapped
 273
 274 # define MASK_THUMB2_INSN_LSLW2         0x0030ffef              // xxxxxxxxxx11xxxx 11111111111x1111    // swapped
 275 # define PTRN_THUMB2_INSN_LSLW2         0x0000ea4f              // xxxxxxxxxx00xxxx 11101010010x1111    LSL{S}.W Rd, Rm, #<imm5> // swapped
 276
 277 # define MASK_THUMB2_INSN_LSRW1         0xf0f0ffe0              // 1111xxxx1111xxxx 11111111111xxxxx    // swapped
 278 # define PTRN_THUMB2_INSN_LSRW1         0xf000fa20              // 1111xxxx0000xxxx 11111010001xxxxx    LSR{S}.W Rd, Rn, Rm // swapped
 279
 280 # define MASK_THUMB2_INSN_LSRW2         0x0030ffef              // xxxxxxxxxx11xxxx 11111111111x1111    // swapped
 281 # define PTRN_THUMB2_INSN_LSRW2         0x0010ea4f              // xxxxxxxxxx01xxxx 11101010010x1111    LSR{S}.W Rd, Rm, #<imm5> // swapped
 282
 283 # define MASK_THUMB2_INSN_TEQ1          0x8f00fbf0              // 1xxx1111xxxxxxxx 11111x111111xxxx    // swapped
 284 # define PTRN_THUMB2_INSN_TEQ1          0x0f00f090              // 0xxx1111xxxxxxxx 11110x001001xxxx    TEQ Rn, #<const> // swapped
 285
 286 # define MASK_THUMB2_INSN_TEQ2          0x0f00fff0              // xxxx1111xxxxxxxx 111111111111xxxx    // swapped
 287 # define PTRN_THUMB2_INSN_TEQ2          0x0f00ea90              // xxxx1111xxxxxxxx 111010101001xxxx    TEQ Rn, Rm{,<shift>} // swapped
 288
 289 # define MASK_THUMB2_INSN_TST1          0x8f00fbf0              // 1xxx1111xxxxxxxx 11111x111111xxxx    // swapped
 290 # define PTRN_THUMB2_INSN_TST1          0x0f00f010              // 0xxx1111xxxxxxxx 11110x000001xxxx    TST Rn, #<const> // swapped
 291
 292 # define MASK_THUMB2_INSN_TST2          0x0f00fff0              // xxxx1111xxxxxxxx 111111111111xxxx    // swapped
 293 # define PTRN_THUMB2_INSN_TST2          0x0f00ea10              // xxxx1111xxxxxxxx 111010100001xxxx    TST Rn, Rm{,<shift>} // swapped
 294
 295
 296 // Load immediate offset
 297 # define MASK_ARM_INSN_LIO              0x0E100000
 298 # define PTRN_ARM_INSN_LIO              0x04100000
 299
 300 # define MASK_THUMB_INSN_LIO1           0xF800                  // 11111xxxxxxxxxxx
 301 # define PTRN_THUMB_INSN_LIO1           0x6800                  // 01101xxxxxxxxxxx     LDR
 302
 303 # define MASK_THUMB_INSN_LIO2           MASK_THUMB_INSN_LIO1
 304 # define PTRN_THUMB_INSN_LIO2           0x7800                  // 01111xxxxxxxxxxx     LDRB
 305
 306 # define MASK_THUMB_INSN_LIO3           MASK_THUMB_INSN_LIO1
 307 # define PTRN_THUMB_INSN_LIO3           0x8800                  // 10001xxxxxxxxxxx     LDRH
 308
 309 # define MASK_THUMB_INSN_LIO4           MASK_THUMB_INSN_LIO1
 310 # define PTRN_THUMB_INSN_LIO4           0x9800                  // 10011xxxxxxxxxxx     LDR SP relative
 311
 312 # define MASK_THUMB2_INSN_LDRW          0x0000fff0              // xxxxxxxxxxxxxxxx 111111111111xxxx    // swapped
 313 # define PTRN_THUMB2_INSN_LDRW          0x0000f850              // xxxxxxxxxxxxxxxx 111110000101xxxx    LDR.W Rt, [Rn, #-<imm12>]// swapped
 314
 315 # define MASK_THUMB2_INSN_LDRW1         MASK_THUMB2_INSN_LDRW
 316 # define PTRN_THUMB2_INSN_LDRW1         0x0000f8d0              // xxxxxxxxxxxxxxxx 111110001101xxxx    LDR.W Rt, [Rn, #<imm12>]// swapped
 317
 318 # define MASK_THUMB2_INSN_LDRBW         MASK_THUMB2_INSN_LDRW
 319 # define PTRN_THUMB2_INSN_LDRBW         0x0000f810              // xxxxxxxxxxxxxxxx 111110000001xxxx    LDRB.W Rt, [Rn, #-<imm8>]// swapped
 320
 321 # define MASK_THUMB2_INSN_LDRBW1        MASK_THUMB2_INSN_LDRW
 322 # define PTRN_THUMB2_INSN_LDRBW1        0x0000f890              // xxxxxxxxxxxxxxxx 111110001001xxxx    LDRB.W Rt, [Rn, #<imm12>]// swapped
 323
 324 # define MASK_THUMB2_INSN_LDRHW         MASK_THUMB2_INSN_LDRW
 325 # define PTRN_THUMB2_INSN_LDRHW         0x0000f830              // xxxxxxxxxxxxxxxx 111110000011xxxx    LDRH.W Rt, [Rn, #-<imm8>]// swapped
 326
 327 # define MASK_THUMB2_INSN_LDRHW1        MASK_THUMB2_INSN_LDRW
 328 # define PTRN_THUMB2_INSN_LDRHW1        0x0000f8b0              // xxxxxxxxxxxxxxxx 111110001011xxxx    LDRH.W Rt, [Rn, #<imm12>]// swapped
 329
 330 # define MASK_THUMB2_INSN_LDRD          0x0000fed0              // xxxxxxxxxxxxxxxx 1111111x11x1xxxx    // swapped
 331 # define PTRN_THUMB2_INSN_LDRD          0x0000e850              // xxxxxxxxxxxxxxxx 1110100x01x1xxxx    LDRD Rt, Rt2, [Rn, #-<imm8>]// swapped
 332
 333 # define MASK_THUMB2_INSN_LDRD1         MASK_THUMB2_INSN_LDRD
 334 # define PTRN_THUMB2_INSN_LDRD1         0x0000e8d0              // xxxxxxxxxxxxxxxx 1110100x11x1xxxx    LDRD Rt, Rt2, [Rn, #<imm8>]// swapped
 335
 336 # define MASK_THUMB2_INSN_LDRWL         0x0fc0fff0              // xxxx111111xxxxxx 111111111111xxxx    // swapped
 337 # define PTRN_THUMB2_INSN_LDRWL         0x0000f850              // xxxxxxxxxxxxxxxx 111110000101xxxx    LDR.W Rt, [Rn, Rm, LSL #<imm2>]// swapped
 338
 339 # define MASK_THUMB2_INSN_LDREX         0x0f00ffff              // xxxx1111xxxxxxxx 1111111111111111    // swapped
 340 # define PTRN_THUMB2_INSN_LDREX         0x0f00e85f              // xxxx1111xxxxxxxx 1110100001011111    LDREX Rt, [PC, #<imm8>]// swapped
 341
 342 # define MASK_THUMB2_INSN_MUL           0xf0f0fff0              // 1111xxxx1111xxxx 111111111111xxxx    // swapped
 343 # define PTRN_THUMB2_INSN_MUL           0xf000fb00              // 1111xxxx0000xxxx 111110110000xxxx    MUL Rd, Rn, Rm// swapped
 344
 345 # define MASK_THUMB2_INSN_DP            0x0000ff00              // xxxxxxxxxxxxxxxx 11111111xxxxxxxx    // swapped
 346 # define PTRN_THUMB2_INSN_DP            0x0000eb00              // xxxxxxxxxxxxxxxx 11101011xxxxxxxx    // swapped      ADD/SUB/SBC/...Rd, Rn, Rm{,<shift>}
 347
 348
 349
 350
 351 // Store immediate offset
 352 # define MASK_ARM_INSN_SIO              MASK_ARM_INSN_LIO
 353 # define PTRN_ARM_INSN_SIO              0x04000000
 354
 355 # define MASK_THUMB_INSN_SIO1           MASK_THUMB_INSN_LIO1
 356 # define PTRN_THUMB_INSN_SIO1           0x6000                  // 01100xxxxxxxxxxx     STR
 357
 358 # define MASK_THUMB_INSN_SIO2           MASK_THUMB_INSN_LIO1
 359 # define PTRN_THUMB_INSN_SIO2           0x7000                  // 01110xxxxxxxxxxx     STRB
 360
 361 # define MASK_THUMB_INSN_SIO3           MASK_THUMB_INSN_LIO1
 362 # define PTRN_THUMB_INSN_SIO3           0x8000                  // 10000xxxxxxxxxxx     STRH
 363
 364 # define MASK_THUMB_INSN_SIO4           MASK_THUMB_INSN_LIO1
 365 # define PTRN_THUMB_INSN_SIO4           0x9000                  // 10010xxxxxxxxxxx     STR SP relative
 366
 367 # define MASK_THUMB2_INSN_STRW          0x0fc0fff0              // xxxx111111xxxxxx 111111111111xxxx    // swapped
 368 # define PTRN_THUMB2_INSN_STRW          0x0000f840              // xxxx000000xxxxxx 111110000100xxxx    STR.W Rt, [Rn, Rm, {LSL #<imm2>}]// swapped
 369
 370 # define MASK_THUMB2_INSN_STRW1         0x0000fff0              // xxxxxxxxxxxxxxxx 111111111111xxxx    // swapped
 371 # define PTRN_THUMB2_INSN_STRW1         0x0000f8c0              // xxxxxxxxxxxxxxxx 111110001100xxxx    STR.W Rt, [Rn, #imm12]// swapped                                // STR.W Rt, [PC, #imm12] shall be skipped, because it hangs on Tegra. WTF
 372
 373 # define MASK_THUMB2_INSN_STRHW         MASK_THUMB2_INSN_STRW
 374 # define PTRN_THUMB2_INSN_STRHW         0x0000f820              // xxxx000000xxxxxx 111110000010xxxx    STRH.W Rt, [Rn, Rm, {LSL #<imm2>}]// swapped
 375
 376 # define MASK_THUMB2_INSN_STRHW1        0x0000fff0              // xxxxxxxxxxxxxxxx 111111111111xxxx    // swapped
 377 # define PTRN_THUMB2_INSN_STRHW1        0x0000f8a0              // xxxxxxxxxxxxxxxx 111110001010xxxx    STRH.W Rt, [Rn, #<imm12>]// swapped
 378
 379 # define MASK_THUMB2_INSN_STRHT         0x0f00fff0              // xxxx1111xxxxxxxx 111111111111xxxx    // swapped                                                      // strht r1, [pc, #imm] illegal instruction on Tegra. WTF
 380 # define PTRN_THUMB2_INSN_STRHT         0x0e00f820              // xxxx1110xxxxxxxx 111110000010xxxx    STRHT Rt, [Rn, #<imm8>]// swapped
 381
 382 # define MASK_THUMB2_INSN_STRT          0x0f00fff0              // xxxx1111xxxxxxxx 111111111111xxxx    // swapped
 383 # define PTRN_THUMB2_INSN_STRT          0x0e00f840              // xxxx1110xxxxxxxx 111110000100xxxx    STRT Rt, [Rn, #<imm8>]// swapped
 384
 385 # define MASK_THUMB2_INSN_STRBW         MASK_THUMB2_INSN_STRW   // xxxx111111xxxxxx 111111111111xxxx    // swapped
 386 # define PTRN_THUMB2_INSN_STRBW         0x0000f800              // xxxx000000xxxxxx 111110000100xxxx    STRB.W Rt, [Rn, Rm, {LSL #<imm2>}]// swapped
 387
 388 # define MASK_THUMB2_INSN_STRBW1        0x0000fff0              // xxxxxxxxxxxxxxxx 111111111111xxxx    // swapped
 389 # define PTRN_THUMB2_INSN_STRBW1        0x0000f880              // xxxxxxxxxxxxxxxx 111110001000xxxx    STRB.W Rt, [Rn, #<imm12>]// swapped                             // STRB.W Rt, [PC, #imm12] shall be skipped, because it hangs on Tegra. WTF
 390
 391 # define MASK_THUMB2_INSN_STRBT         0x0f00fff0              // xxxx1111xxxxxxxx 111111111111xxxx    // swapped
 392 # define PTRN_THUMB2_INSN_STRBT         0x0e00f800              // xxxx1110xxxxxxxx 111110000000xxxx    STRBT Rt, [Rn, #<imm8>}]// swapped
 393
 394 # define MASK_THUMB2_INSN_STRD          0x0000fe50              // xxxxxxxxxxxxxxxx 1111111xx1x1xxxx    // swapped
 395 # define PTRN_THUMB2_INSN_STRD          0x0000e840              // xxxxxxxxxxxxxxxx 1110100xx1x0xxxx    STR{D, EX, EXB, EXH, EXD} Rt, Rt2, [Rn, #<imm8>]// swapped
 396
 397
 398 // Load register offset
 399 # define MASK_ARM_INSN_LRO              0x0E100010
 400 # define PTRN_ARM_INSN_LRO              0x06100000
 401
 402 # define MASK_THUMB_INSN_LRO1           0xFE00                  // 1111111xxxxxxxxx
 403 # define PTRN_THUMB_INSN_LRO1           0x5600                  // 0101011xxxxxxxxx     LDRSB
 404
 405 # define MASK_THUMB_INSN_LRO2           MASK_THUMB_INSN_LRO1
 406 # define PTRN_THUMB_INSN_LRO2           0x5800                  // 0101100xxxxxxxxx     LDR
 407
 408 # define MASK_THUMB_INSN_LRO3           0xf800                  // 11111xxxxxxxxxxx
 409 # define PTRN_THUMB_INSN_LRO3           0x4800                  // 01001xxxxxxxxxxx     LDR Rd, [PC, #<imm8> * 4]
 410
 411 # define MASK_THUMB_INSN_LRO4           MASK_THUMB_INSN_LRO1
 412 # define PTRN_THUMB_INSN_LRO4           0x5A00                  // 0101101xxxxxxxxx     LDRH
 413
 414 # define MASK_THUMB_INSN_LRO5           MASK_THUMB_INSN_LRO1
 415 # define PTRN_THUMB_INSN_LRO5           0x5C00                  // 0101110xxxxxxxxx     LDRB
 416
 417 # define MASK_THUMB_INSN_LRO6           MASK_THUMB_INSN_LRO1
 418 # define PTRN_THUMB_INSN_LRO6           0x5E00                  // 0101111xxxxxxxxx     LDRSH
 419
 420 # define MASK_THUMB2_INSN_ADR           0x8000fa1f              // 1xxxxxxxxxxxxxxx 11111x1xxxx11111    // swapped
 421 # define PTRN_THUMB2_INSN_ADR           0x0000f20f              // 0xxxxxxxxxxxxxxx 11110x1xxxx01111    // swapped
 422
 423
 424
 425 // Store register offset
 426 # define MASK_ARM_INSN_SRO              MASK_ARM_INSN_LRO
 427 # define PTRN_ARM_INSN_SRO              0x06000000
 428
 429 # define MASK_THUMB_INSN_SRO1           MASK_THUMB_INSN_LRO1
 430 # define PTRN_THUMB_INSN_SRO1           0x5000                  // 0101000xxxxxxxxx     STR
 431
 432 # define MASK_THUMB_INSN_SRO2           MASK_THUMB_INSN_LRO1
 433 # define PTRN_THUMB_INSN_SRO2           0x5200                  // 0101001xxxxxxxxx     STRH
 434
 435 # define MASK_THUMB_INSN_SRO3           MASK_THUMB_INSN_LRO1
 436 # define PTRN_THUMB_INSN_SRO3           0x5400                  // 0101010xxxxxxxxx     STRB
 437
 438 // Load multiple
 439 # define MASK_ARM_INSN_LM               0x0E100000
 440 # define PTRN_ARM_INSN_LM               0x08100000
 441
 442 # define MASK_THUMB2_INSN_LDMIA         0x8000ffd0              // 1xxxxxxxxxxxxxxx 1111111111x1xxxx    // swapped
 443 # define PTRN_THUMB2_INSN_LDMIA         0x8000e890              // 1xxxxxxxxxxxxxxx 1110100010x1xxxx    LDMIA(.W) Rn(!), {Rx, ..., PC}// swapped
 444
 445 # define MASK_THUMB2_INSN_LDMDB         0x8000ffd0              // 1xxxxxxxxxxxxxxx 1111111111x1xxxx    // swapped
 446 # define PTRN_THUMB2_INSN_LDMDB         0x8000e910              // 1xxxxxxxxxxxxxxx 1110100100x1xxxx    LDMDB(.W) Rn(!), {Rx, ..., PC}// swapped
 447
 448 // Store multiple
 449 # define MASK_ARM_INSN_SM               MASK_ARM_INSN_LM
 450 # define PTRN_ARM_INSN_SM               0x08000000
 451
 452
 453 // Coprocessor load/store and double register transfers
 454 # define MASK_ARM_INSN_CLS              0x0E000000
 455 # define PTRN_ARM_INSN_CLS              0x0C000000
 456 // Coprocessor register transfers
 457 # define MASK_ARM_INSN_CRT              0x0F000010
 458 # define PTRN_ARM_INSN_CRT              0x0E000010
 459
 460 # define ARM_INSN_MATCH(name, insn)             ((insn & MASK_ARM_INSN_##name) == PTRN_ARM_INSN_##name)
 461 # define THUMB_INSN_MATCH(name, insn)           (((insn & 0x0000FFFF) & MASK_THUMB_INSN_##name) == PTRN_THUMB_INSN_##name)
 462 # define THUMB2_INSN_MATCH(name, insn)          ((insn & MASK_THUMB2_INSN_##name) == PTRN_THUMB2_INSN_##name)
 463
 464 # define ARM_INSN_REG_RN(insn)                  ((insn & 0x000F0000)>>16)
 465
 466 # define ARM_INSN_REG_SET_RN(insn, nreg)        {insn &= ~0x000F0000; insn |= nreg<<16;}
 467
 468 # define ARM_INSN_REG_RD(insn)                  ((insn & 0x0000F000)>>12)
 469
 470 # define ARM_INSN_REG_SET_RD(insn, nreg)        {insn &= ~0x0000F000; insn |= nreg<<12;}
 471
 472 # define ARM_INSN_REG_RS(insn)                  ((insn & 0x00000F00)>>8)
 473
 474 # define ARM_INSN_REG_SET_RS(insn, nreg)        {insn &= ~0x00000F00; insn |= nreg<<8;}
 475
 476 # define ARM_INSN_REG_RM(insn)                  (insn & 0x0000000F)
 477
 478 # define ARM_INSN_REG_SET_RM(insn, nreg)        {insn &= ~0x0000000F; insn |= nreg;}
 479
 480 # define ARM_INSN_REG_MR(insn, nreg)            (insn & (1 << nreg))
 481
 482 # define ARM_INSN_REG_SET_MR(insn, nreg)        {insn |= (1 << nreg);}
 483
 484 # define ARM_INSN_REG_CLEAR_MR(insn, nreg)      {insn &= ~(1 << nreg);}
 485
 486 # define THUMB2_INSN_REG_RT(insn)               ((insn & 0xf0000000) >> 28)
 487 # define THUMB2_INSN_REG_RT2(insn)              ((insn & 0x0f000000) >> 24)
 488 # define THUMB2_INSN_REG_RN(insn)               (insn & 0x0000000f)
 489 # define THUMB2_INSN_REG_RD(insn)               ((insn & 0x0f000000) >> 24)
 490 # define THUMB2_INSN_REG_RM(insn)               ((insn & 0x000f0000) >> 16)
 491
 492
 493 /* per-cpu kprobe control block */
 494 struct kprobe_ctlblk {
 495         unsigned long kprobe_status;
 496         struct prev_kprobe prev_kprobe;
 497 };
 498
 499 /* Architecture specific copy of original instruction */
 500 struct arch_specific_insn {
 501         /* copy of the original instruction */
 502         kprobe_opcode_t *insn;
 503         kprobe_opcode_t *insn_arm;
 504         kprobe_opcode_t *insn_thumb;
 505 };
 506
 507 typedef kprobe_opcode_t (*entry_point_t) (unsigned long, unsigned long, unsigned long, unsigned long, unsigned long, unsigned long);
 508
 509 //void gen_insn_execbuf (void);
 510 //void pc_dep_insn_execbuf (void);
 511 //void gen_insn_execbuf_holder (void);
 512 //void pc_dep_insn_execbuf_holder (void);
 513
 514 #endif /* _DBI_ASM_ARM_KPROBES_H */