kprobe/arch/asm-arm/dbi_kprobes.h

   1 #ifndef _DBI_ASM_ARM_KPROBES_H
   2 #define _DBI_ASM_ARM_KPROBES_H
   3
   4 /*
   5  *  Dynamic Binary Instrumentation Module based on KProbes
   6  *  modules/kprobe/arch/asm-arm/dbi_kprobes.h
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  21  *
  22  * Copyright (C) Samsung Electronics, 2006-2010
  23  *
  24  * 2006-2007    Ekaterina Gorelkina <e.gorelkina@samsung.com>: initial implementation for ARM/MIPS
  25  * 2008-2009    Alexey Gerenkov <a.gerenkov@samsung.com> User-Space
  26  *              Probes initial implementation; Support x86/ARM/MIPS for both user and kernel spaces.
  27  * 2010         Ekaterina Gorelkina <e.gorelkina@samsung.com>: redesign module for separating core and arch parts
  28  *
  29  * 2010-2011    Alexander Shirshikov <a.shirshikov@samsung.com>: initial implementation for Thumb
  30  */
  31
  32 #include <linux/sched.h>
  33 #include "../../dbi_kprobes_deps.h"
  34 #include "../dbi_kprobes.h"
  35 #include "dbi_kprobes_arm.h"
  36 #include "dbi_kprobes_thumb.h"
  37
  38 typedef unsigned long kprobe_opcode_t;
  39
  40 #ifdef CONFIG_CPU_S3C2443
  41 #define BREAKPOINT_INSTRUCTION          0xe1200070
  42 #else
  43 #define BREAKPOINT_INSTRUCTION          0xffffdeff
  44 #endif /* CONFIG_CPU_S3C2443 */
  45
  46 #ifndef KPROBES_RET_PROBE_TRAMP
  47
  48 #ifdef CONFIG_CPU_S3C2443
  49 #define UNDEF_INSTRUCTION               0xe1200071
  50 #else
  51 #define UNDEF_INSTRUCTION               0xfffffffe
  52 #endif /* CONFIG_CPU_S3C2443 */
  53
  54 #endif /* KPROBES_RET_PROBE_TRAMP */
  55
  56 #define MAX_INSN_SIZE                   1
  57
  58 # define UPROBES_TRAMP_LEN              9
  59 # define UPROBES_TRAMP_INSN_IDX         2
  60 # define UPROBES_TRAMP_SS_BREAK_IDX     4
  61 # define UPROBES_TRAMP_RET_BREAK_IDX    5
  62 # define KPROBES_TRAMP_LEN              9
  63 # define KPROBES_TRAMP_INSN_IDX         UPROBES_TRAMP_INSN_IDX
  64 # define KPROBES_TRAMP_SS_BREAK_IDX     UPROBES_TRAMP_SS_BREAK_IDX
  65 # define KPROBES_TRAMP_RET_BREAK_IDX    UPROBES_TRAMP_RET_BREAK_IDX
  66
  67 static inline unsigned long arch_get_task_pc(struct task_struct *p)
  68 {
  69         return task_thread_info(p)->cpu_context.pc;
  70 }
  71
  72 static inline void arch_set_task_pc(struct task_struct *p, unsigned long val)
  73 {
  74         task_thread_info(p)->cpu_context.pc = val;
  75 }
  76
  77 static inline unsigned long dbi_get_stack_ptr(struct pt_regs *regs)
  78 {
  79         return regs->ARM_sp;
  80 }
  81
  82 static inline unsigned long dbi_get_instr_ptr(struct pt_regs *regs)
  83 {
  84         return regs->ARM_pc;
  85 }
  86
  87 static inline void dbi_set_instr_ptr(struct pt_regs *regs, unsigned long val)
  88 {
  89         regs->ARM_pc = val;
  90 }
  91
  92 static inline unsigned long dbi_get_ret_addr(struct pt_regs *regs)
  93 {
  94         return regs->ARM_lr;
  95 }
  96
  97 static inline unsigned long dbi_get_arg(struct pt_regs *regs, int num)
  98 {
  99         return regs->uregs[num];
 100 }
 101
 102 static inline void dbi_set_arg(struct pt_regs *regs, int num, unsigned long val)
 103 {
 104         regs->uregs[num] = val;
 105 }
 106
 107 static inline int dbi_fp_backtrace(struct task_struct *task, unsigned long *buf,
 108                 int max_cnt)
 109 {
 110         int i = 0;
 111         struct pt_regs *regs;
 112
 113         struct {
 114                 unsigned long next;
 115                 unsigned long raddr;
 116         } frame;
 117
 118         regs = task_pt_regs(task);
 119         frame.next = regs->ARM_fp;
 120         frame.raddr = dbi_get_ret_addr(regs);
 121
 122         while (frame.next && i < max_cnt) {
 123                 if (read_proc_vm_atomic(task, frame.next - 4, &frame, sizeof(frame))
 124                                 == sizeof(frame))
 125                         buf[i++] = frame.raddr;
 126                 else
 127                         break;
 128         }
 129
 130         return i;
 131 }
 132
 133 #define NOTIFIER_CALL_CHAIN_INDEX       3
 134
 135 // undefined
 136 # define MASK_ARM_INSN_UNDEF            0x0FF00000              // xxxx1111 1111xxxx xxxxxxxx xxxxxxxx
 137 # define PTRN_ARM_INSN_UNDEF            0x03000000              // cccc0011 0000xxxx xxxxxxxx xxxxxxxx
 138
 139 # define MASK_THUMB_INSN_UNDEF          0xFE00                  // 11111111xxxxxxxx
 140 # define PTRN_THUMB_INSN_UNDEF          0xDE00                  // 11011110xxxxxxxx
 141
 142 // architecturally undefined
 143 # define MASK_ARM_INSN_AUNDEF           0x0FF000F0
 144 # define PTRN_ARM_INSN_AUNDEF           0x07F000F0
 145
 146 // branches
 147 # define MASK_ARM_INSN_B                0x0E000000              // xxxx111xxxxxxxxxxxxxxxxxxxxxxxxx
 148 # define PTRN_ARM_INSN_B                0x0A000000              // cccc101xxxxxxxxxxxxxxxxxxxxxxxxx
 149
 150 # define MASK_THUMB_INSN_B1             0xF000                  // 1111xxxxxxxxxxxx
 151 # define PTRN_THUMB_INSN_B1             0xD000                  // 1101xxxxxxxxxxxx                                             // b<cond> label
 152
 153 # define MASK_THUMB_INSN_B2             0xF800                  // 11111xxxxxxxxxxx
 154 # define PTRN_THUMB_INSN_B2             0xE000                  // 11100xxxxxxxxxxx                                             // b label
 155
 156 # define MASK_THUMB_INSN_CBZ            0xF500                  // 1111x1x1xxxxxxxx
 157 # define PTRN_THUMB_INSN_CBZ            0xB100                  // 1011x0x1xxxxxxxx                                             // CBZ/CBNZ
 158
 159 # define MASK_THUMB2_INSN_B1            0xD000F800              // 11x1xxxxxxxxxxxx 11111xxxxxxxxxxx                            // swapped
 160 # define PTRN_THUMB2_INSN_B1            0x8000F000              // 10x0xxxxxxxxxxxx 11110xxxxxxxxxxx                            // swapped
 161
 162 # define MASK_THUMB2_INSN_B2            0xD000F800              // 11x1xxxxxxxxxxxx 11111xxxxxxxxxxx                            // swapped
 163 # define PTRN_THUMB2_INSN_B2            0x9000F000              // 10x1xxxxxxxxxxxx 11110xxxxxxxxxxx                            // swapped
 164
 165 # define MASK_ARM_INSN_BL               0x0E000000              // xxxx111xxxxxxxxxxxxxxxxxxxxxxxxx
 166 # define PTRN_ARM_INSN_BL               0x0B000000              // cccc1011xxxxxxxxxxxxxxxxxxxxxxxx
 167
 168 //# define MASK_THUMB_INSN_BL           0xF800                  // 11111xxxxxxxxxxx
 169 //# define PTRN_THUMB_INSN_BL           0xF000                  // 11110xxxxxxxxxxx                                             // shared between BL and BLX
 170 //# define PTRN_THUMB_INSN_BL           0xF800                  // 11111xxxxxxxxxxx
 171
 172 # define MASK_THUMB2_INSN_BL            0xD000F800              // 11x1xxxxxxxxxxxx 11111xxxxxxxxxxx                            // swapped
 173 # define PTRN_THUMB2_INSN_BL            0xD000F000              // 11x1xxxxxxxxxxxx 11110xxxxxxxxxxx                            // bl imm  swapped
 174
 175 # define MASK_ARM_INSN_BLX1             0xFF000000              // 11111111xxxxxxxxxxxxxxxxxxxxxxxx
 176 # define PTRN_ARM_INSN_BLX1             0xFA000000              // 11111011xxxxxxxxxxxxxxxxxxxxxxxx
 177
 178 //# define MASK_THUMB_INSN_BLX1         0xF800                  // 11111xxxxxxxxxxx                                             / blx imm
 179 //# define PTRN_THUMB_INSN_BLX1         0xF000                  // 11101xxxxxxxxxxx
 180
 181 # define MASK_THUMB2_INSN_BLX1          0xD001F800              // 11x1xxxxxxxxxxx1 11111xxxxxxxxxxx                            // swapped
 182 # define PTRN_THUMB2_INSN_BLX1          0xC000F000              // 11x0xxxxxxxxxxx0 11110xxxxxxxxxxx                            // swapped
 183
 184 # define MASK_ARM_INSN_BLX2             0x0FF000F0              // xxxx11111111xxxxxxxxxxxx1111xxxx
 185 # define PTRN_ARM_INSN_BLX2             0x01200030              // cccc00010010xxxxxxxxxxxx0011xxxx
 186
 187 # define MASK_THUMB_INSN_BLX2           0xFF80                  // 111111111xxxxxxx                                             / blx reg
 188 # define PTRN_THUMB_INSN_BLX2           0x4780                  // 010001111xxxxxxx
 189
 190 # define MASK_ARM_INSN_BX               0x0FF000F0              // cccc11111111xxxxxxxxxxxx1111xxxx
 191 # define PTRN_ARM_INSN_BX               0x01200010              // cccc00010010xxxxxxxxxxxx0001xxxx
 192
 193 # define MASK_THUMB_INSN_BX             0xFF80                  // 111111111xxxxxxx
 194 # define PTRN_THUMB_INSN_BX             0x4700                  // 010001110xxxxxxx
 195
 196 # define MASK_ARM_INSN_BXJ              0x0FF000F0              // xxxx11111111xxxxxxxxxxxx1111xxxx
 197 # define PTRN_ARM_INSN_BXJ              0x01200020              // cccc00010010xxxxxxxxxxxx0010xxxx
 198
 199 # define MASK_THUMB2_INSN_BXJ           0xD000FFF0              // 11x1xxxxxxxxxxxx 111111111111xxxx                            // swapped
 200 # define PTRN_THUMB2_INSN_BXJ           0x8000F3C0              // 10x0xxxxxxxxxxxx 111100111100xxxx                            // swapped
 201
 202
 203 // software interrupts
 204 # define MASK_ARM_INSN_SWI              0x0F000000              // cccc1111xxxxxxxxxxxxxxxxxxxxxxxx
 205 # define PTRN_ARM_INSN_SWI              0x0F000000              // cccc1111xxxxxxxxxxxxxxxxxxxxxxxx
 206
 207 # define MASK_THUMB_INSN_SWI            0xFF00                  // 11111111xxxxxxxx
 208 # define PTRN_THUMB_INSN_SWI            0xDF00                  // 11011111xxxxxxxx
 209
 210 // break
 211 # define MASK_ARM_INSN_BREAK            0xFFF000F0              // 111111111111xxxxxxxxxxxx1111xxxx
 212 # define PTRN_ARM_INSN_BREAK            0xE1200070              // 111000010010xxxxxxxxxxxx0111xxxx                             /? A8-56 ARM DDI 046B if cond != ‘1110’ then UNPREDICTABLE;
 213
 214 # define MASK_THUMB_INSN_BREAK          0xFF00                  // 11111111xxxxxxxx
 215 # define PTRN_THUMB_INSN_BREAK          0xBE00                  // 10111110xxxxxxxx
 216
 217 // Data processing immediate shift
 218 # define MASK_ARM_INSN_DPIS             0x0E000010
 219 # define PTRN_ARM_INSN_DPIS             0x00000000
 220 // Data processing register shift
 221 # define MASK_ARM_INSN_DPRS             0x0E000090
 222 # define PTRN_ARM_INSN_DPRS             0x00000010
 223
 224 # define MASK_THUMB2_INSN_DPRS          0xFFE00000              // 11111111111xxxxxxxxxxxxxxxxxxxxx
 225 # define PTRN_THUMB2_INSN_DPRS          0xEA000000              // 1110101xxxxxxxxxxxxxxxxxxxxxxxxx
 226
 227 // Data processing immediate
 228 # define MASK_ARM_INSN_DPI              0x0E000000
 229 # define PTRN_ARM_INSN_DPI              0x02000000
 230
 231 # define MASK_THUMB_INSN_DP             0xFC00                  // 111111xxxxxxxxxx
 232 # define PTRN_THUMB_INSN_DP             0x4000                  // 010000xxxxxxxxxx
 233
 234 # define MASK_THUMB_INSN_APC            0xF800                  // 11111xxxxxxxxxxx
 235 # define PTRN_THUMB_INSN_APC            0xA000                  // 10100xxxxxxxxxxx     ADD Rd, [PC, #<imm8> * 4]
 236
 237 # define MASK_THUMB2_INSN_DPI           0xFBE08000              // 11111x11111xxxxx 1xxxxxxxxxxxxxxx
 238 //# define PTRN_THUMB2_INSN_DPI         0xF0000000              // 11110x0xxxxxxxxx 0xxxxxxxxxxxxxxx                            /? A6-19 ARM DDI 0406B
 239 # define PTRN_THUMB2_INSN_DPI           0xF2000000              // 11110x1xxxxxxxxx 0xxxxxxxxxxxxxxx                            /? A6-19 ARM DDI 0406B
 240
 241 # define MASK_THUMB_INSN_MOV3           0xFF00                  // 11111111xxxxxxxx
 242 # define PTRN_THUMB_INSN_MOV3           0x4600                  // 01000110xxxxxxxx     MOV Rd, PC
 243
 244 # define MASK_THUMB2_INSN_RSBW          0x8000fbe0              // 1xxxxxxxxxxxxxxx 11111x11111xxxxx    // swapped
 245 # define PTRN_THUMB2_INSN_RSBW          0x0000f1c0              // 0xxxxxxxxxxxxxxx 11110x01110xxxxx    RSB{S}.W Rd, Rn, #<const> // swapped
 246
 247 # define MASK_THUMB2_INSN_RORW          0xf0f0ffe0              // 1111xxxx1111xxxx 11111111111xxxxx    // swapped
 248 # define PTRN_THUMB2_INSN_RORW          0xf000fa60              // 1111xxxx0000xxxx 11111010011xxxxx    ROR{S}.W Rd, Rn, Rm // swapped
 249
 250 # define MASK_THUMB2_INSN_ROR           0x0030ffef              // xxxxxxxxxx11xxxx 11111111111x1111    // swapped
 251 # define PTRN_THUMB2_INSN_ROR           0x0030ea4f              // xxxxxxxxxx11xxxx 11101010010x1111    ROR{S} Rd, Rm, #<imm> // swapped
 252
 253 # define MASK_THUMB2_INSN_LSLW1         0xf0f0ffe0              // 1111xxxx1111xxxx 11111111111xxxxx    // swapped
 254 # define PTRN_THUMB2_INSN_LSLW1         0xf000fa00              // 1111xxxx0000xxxx 11111010000xxxxx    LSL{S}.W Rd, Rn, Rm // swapped
 255
 256 # define MASK_THUMB2_INSN_LSLW2         0x0030ffef              // xxxxxxxxxx11xxxx 11111111111x1111    // swapped
 257 # define PTRN_THUMB2_INSN_LSLW2         0x0000ea4f              // xxxxxxxxxx00xxxx 11101010010x1111    LSL{S}.W Rd, Rm, #<imm5> // swapped
 258
 259 # define MASK_THUMB2_INSN_LSRW1         0xf0f0ffe0              // 1111xxxx1111xxxx 11111111111xxxxx    // swapped
 260 # define PTRN_THUMB2_INSN_LSRW1         0xf000fa20              // 1111xxxx0000xxxx 11111010001xxxxx    LSR{S}.W Rd, Rn, Rm // swapped
 261
 262 # define MASK_THUMB2_INSN_LSRW2         0x0030ffef              // xxxxxxxxxx11xxxx 11111111111x1111    // swapped
 263 # define PTRN_THUMB2_INSN_LSRW2         0x0010ea4f              // xxxxxxxxxx01xxxx 11101010010x1111    LSR{S}.W Rd, Rm, #<imm5> // swapped
 264
 265 # define MASK_THUMB2_INSN_TEQ1          0x8f00fbf0              // 1xxx1111xxxxxxxx 11111x111111xxxx    // swapped
 266 # define PTRN_THUMB2_INSN_TEQ1          0x0f00f090              // 0xxx1111xxxxxxxx 11110x001001xxxx    TEQ Rn, #<const> // swapped
 267
 268 # define MASK_THUMB2_INSN_TEQ2          0x0f00fff0              // xxxx1111xxxxxxxx 111111111111xxxx    // swapped
 269 # define PTRN_THUMB2_INSN_TEQ2          0x0f00ea90              // xxxx1111xxxxxxxx 111010101001xxxx    TEQ Rn, Rm{,<shift>} // swapped
 270
 271 # define MASK_THUMB2_INSN_TST1          0x8f00fbf0              // 1xxx1111xxxxxxxx 11111x111111xxxx    // swapped
 272 # define PTRN_THUMB2_INSN_TST1          0x0f00f010              // 0xxx1111xxxxxxxx 11110x000001xxxx    TST Rn, #<const> // swapped
 273
 274 # define MASK_THUMB2_INSN_TST2          0x0f00fff0              // xxxx1111xxxxxxxx 111111111111xxxx    // swapped
 275 # define PTRN_THUMB2_INSN_TST2          0x0f00ea10              // xxxx1111xxxxxxxx 111010100001xxxx    TST Rn, Rm{,<shift>} // swapped
 276
 277
 278 // Load immediate offset
 279 # define MASK_ARM_INSN_LIO              0x0E100000
 280 # define PTRN_ARM_INSN_LIO              0x04100000
 281
 282 # define MASK_THUMB_INSN_LIO1           0xF800                  // 11111xxxxxxxxxxx
 283 # define PTRN_THUMB_INSN_LIO1           0x6800                  // 01101xxxxxxxxxxx     LDR
 284
 285 # define MASK_THUMB_INSN_LIO2           MASK_THUMB_INSN_LIO1
 286 # define PTRN_THUMB_INSN_LIO2           0x7800                  // 01111xxxxxxxxxxx     LDRB
 287
 288 # define MASK_THUMB_INSN_LIO3           MASK_THUMB_INSN_LIO1
 289 # define PTRN_THUMB_INSN_LIO3           0x8800                  // 10001xxxxxxxxxxx     LDRH
 290
 291 # define MASK_THUMB_INSN_LIO4           MASK_THUMB_INSN_LIO1
 292 # define PTRN_THUMB_INSN_LIO4           0x9800                  // 10011xxxxxxxxxxx     LDR SP relative
 293
 294 # define MASK_THUMB2_INSN_LDRW          0x0000fff0              // xxxxxxxxxxxxxxxx 111111111111xxxx    // swapped
 295 # define PTRN_THUMB2_INSN_LDRW          0x0000f850              // xxxxxxxxxxxxxxxx 111110000101xxxx    LDR.W Rt, [Rn, #-<imm12>]// swapped
 296
 297 # define MASK_THUMB2_INSN_LDRW1         MASK_THUMB2_INSN_LDRW
 298 # define PTRN_THUMB2_INSN_LDRW1         0x0000f8d0              // xxxxxxxxxxxxxxxx 111110001101xxxx    LDR.W Rt, [Rn, #<imm12>]// swapped
 299
 300 # define MASK_THUMB2_INSN_LDRBW         MASK_THUMB2_INSN_LDRW
 301 # define PTRN_THUMB2_INSN_LDRBW         0x0000f810              // xxxxxxxxxxxxxxxx 111110000001xxxx    LDRB.W Rt, [Rn, #-<imm8>]// swapped
 302
 303 # define MASK_THUMB2_INSN_LDRBW1        MASK_THUMB2_INSN_LDRW
 304 # define PTRN_THUMB2_INSN_LDRBW1        0x0000f890              // xxxxxxxxxxxxxxxx 111110001001xxxx    LDRB.W Rt, [Rn, #<imm12>]// swapped
 305
 306 # define MASK_THUMB2_INSN_LDRHW         MASK_THUMB2_INSN_LDRW
 307 # define PTRN_THUMB2_INSN_LDRHW         0x0000f830              // xxxxxxxxxxxxxxxx 111110000011xxxx    LDRH.W Rt, [Rn, #-<imm8>]// swapped
 308
 309 # define MASK_THUMB2_INSN_LDRHW1        MASK_THUMB2_INSN_LDRW
 310 # define PTRN_THUMB2_INSN_LDRHW1        0x0000f8b0              // xxxxxxxxxxxxxxxx 111110001011xxxx    LDRH.W Rt, [Rn, #<imm12>]// swapped
 311
 312 # define MASK_THUMB2_INSN_LDRD          0x0000fed0              // xxxxxxxxxxxxxxxx 1111111x11x1xxxx    // swapped
 313 # define PTRN_THUMB2_INSN_LDRD          0x0000e850              // xxxxxxxxxxxxxxxx 1110100x01x1xxxx    LDRD Rt, Rt2, [Rn, #-<imm8>]// swapped
 314
 315 # define MASK_THUMB2_INSN_LDRD1         MASK_THUMB2_INSN_LDRD
 316 # define PTRN_THUMB2_INSN_LDRD1         0x0000e8d0              // xxxxxxxxxxxxxxxx 1110100x11x1xxxx    LDRD Rt, Rt2, [Rn, #<imm8>]// swapped
 317
 318 # define MASK_THUMB2_INSN_LDRWL         0x0fc0fff0              // xxxx111111xxxxxx 111111111111xxxx    // swapped
 319 # define PTRN_THUMB2_INSN_LDRWL         0x0000f850              // xxxxxxxxxxxxxxxx 111110000101xxxx    LDR.W Rt, [Rn, Rm, LSL #<imm2>]// swapped
 320
 321 # define MASK_THUMB2_INSN_LDREX         0x0f00ffff              // xxxx1111xxxxxxxx 1111111111111111    // swapped
 322 # define PTRN_THUMB2_INSN_LDREX         0x0f00e85f              // xxxx1111xxxxxxxx 1110100001011111    LDREX Rt, [PC, #<imm8>]// swapped
 323
 324 # define MASK_THUMB2_INSN_MUL           0xf0f0fff0              // 1111xxxx1111xxxx 111111111111xxxx    // swapped
 325 # define PTRN_THUMB2_INSN_MUL           0xf000fb00              // 1111xxxx0000xxxx 111110110000xxxx    MUL Rd, Rn, Rm// swapped
 326
 327 # define MASK_THUMB2_INSN_DP            0x0000ff00              // xxxxxxxxxxxxxxxx 11111111xxxxxxxx    // swapped
 328 # define PTRN_THUMB2_INSN_DP            0x0000eb00              // xxxxxxxxxxxxxxxx 11101011xxxxxxxx    // swapped      ADD/SUB/SBC/...Rd, Rn, Rm{,<shift>}
 329
 330
 331
 332
 333 // Store immediate offset
 334 # define MASK_ARM_INSN_SIO              MASK_ARM_INSN_LIO
 335 # define PTRN_ARM_INSN_SIO              0x04000000
 336
 337 # define MASK_THUMB_INSN_SIO1           MASK_THUMB_INSN_LIO1
 338 # define PTRN_THUMB_INSN_SIO1           0x6000                  // 01100xxxxxxxxxxx     STR
 339
 340 # define MASK_THUMB_INSN_SIO2           MASK_THUMB_INSN_LIO1
 341 # define PTRN_THUMB_INSN_SIO2           0x7000                  // 01110xxxxxxxxxxx     STRB
 342
 343 # define MASK_THUMB_INSN_SIO3           MASK_THUMB_INSN_LIO1
 344 # define PTRN_THUMB_INSN_SIO3           0x8000                  // 10000xxxxxxxxxxx     STRH
 345
 346 # define MASK_THUMB_INSN_SIO4           MASK_THUMB_INSN_LIO1
 347 # define PTRN_THUMB_INSN_SIO4           0x9000                  // 10010xxxxxxxxxxx     STR SP relative
 348
 349 # define MASK_THUMB2_INSN_STRW          0x0fc0fff0              // xxxx111111xxxxxx 111111111111xxxx    // swapped
 350 # define PTRN_THUMB2_INSN_STRW          0x0000f840              // xxxx000000xxxxxx 111110000100xxxx    STR.W Rt, [Rn, Rm, {LSL #<imm2>}]// swapped
 351
 352 # define MASK_THUMB2_INSN_STRW1         0x0000fff0              // xxxxxxxxxxxxxxxx 111111111111xxxx    // swapped
 353 # define PTRN_THUMB2_INSN_STRW1         0x0000f8c0              // xxxxxxxxxxxxxxxx 111110001100xxxx    STR.W Rt, [Rn, #imm12]// swapped                                // STR.W Rt, [PC, #imm12] shall be skipped, because it hangs on Tegra. WTF
 354
 355 # define MASK_THUMB2_INSN_STRHW         MASK_THUMB2_INSN_STRW
 356 # define PTRN_THUMB2_INSN_STRHW         0x0000f820              // xxxx000000xxxxxx 111110000010xxxx    STRH.W Rt, [Rn, Rm, {LSL #<imm2>}]// swapped
 357
 358 # define MASK_THUMB2_INSN_STRHW1        0x0000fff0              // xxxxxxxxxxxxxxxx 111111111111xxxx    // swapped
 359 # define PTRN_THUMB2_INSN_STRHW1        0x0000f8a0              // xxxxxxxxxxxxxxxx 111110001010xxxx    STRH.W Rt, [Rn, #<imm12>]// swapped
 360
 361 # define MASK_THUMB2_INSN_STRHT         0x0f00fff0              // xxxx1111xxxxxxxx 111111111111xxxx    // swapped                                                      // strht r1, [pc, #imm] illegal instruction on Tegra. WTF
 362 # define PTRN_THUMB2_INSN_STRHT         0x0e00f820              // xxxx1110xxxxxxxx 111110000010xxxx    STRHT Rt, [Rn, #<imm8>]// swapped
 363
 364 # define MASK_THUMB2_INSN_STRT          0x0f00fff0              // xxxx1111xxxxxxxx 111111111111xxxx    // swapped
 365 # define PTRN_THUMB2_INSN_STRT          0x0e00f840              // xxxx1110xxxxxxxx 111110000100xxxx    STRT Rt, [Rn, #<imm8>]// swapped
 366
 367 # define MASK_THUMB2_INSN_STRBW         MASK_THUMB2_INSN_STRW   // xxxx111111xxxxxx 111111111111xxxx    // swapped
 368 # define PTRN_THUMB2_INSN_STRBW         0x0000f800              // xxxx000000xxxxxx 111110000100xxxx    STRB.W Rt, [Rn, Rm, {LSL #<imm2>}]// swapped
 369
 370 # define MASK_THUMB2_INSN_STRBW1        0x0000fff0              // xxxxxxxxxxxxxxxx 111111111111xxxx    // swapped
 371 # define PTRN_THUMB2_INSN_STRBW1        0x0000f880              // xxxxxxxxxxxxxxxx 111110001000xxxx    STRB.W Rt, [Rn, #<imm12>]// swapped                             // STRB.W Rt, [PC, #imm12] shall be skipped, because it hangs on Tegra. WTF
 372
 373 # define MASK_THUMB2_INSN_STRBT         0x0f00fff0              // xxxx1111xxxxxxxx 111111111111xxxx    // swapped
 374 # define PTRN_THUMB2_INSN_STRBT         0x0e00f800              // xxxx1110xxxxxxxx 111110000000xxxx    STRBT Rt, [Rn, #<imm8>}]// swapped
 375
 376 # define MASK_THUMB2_INSN_STRD          0x0000fe50              // xxxxxxxxxxxxxxxx 1111111xx1x1xxxx    // swapped
 377 # define PTRN_THUMB2_INSN_STRD          0x0000e840              // xxxxxxxxxxxxxxxx 1110100xx1x0xxxx    STR{D, EX, EXB, EXH, EXD} Rt, Rt2, [Rn, #<imm8>]// swapped
 378
 379
 380 // Load register offset
 381 # define MASK_ARM_INSN_LRO              0x0E100010
 382 # define PTRN_ARM_INSN_LRO              0x06100000
 383
 384 # define MASK_THUMB_INSN_LRO1           0xFE00                  // 1111111xxxxxxxxx
 385 # define PTRN_THUMB_INSN_LRO1           0x5600                  // 0101011xxxxxxxxx     LDRSB
 386
 387 # define MASK_THUMB_INSN_LRO2           MASK_THUMB_INSN_LRO1
 388 # define PTRN_THUMB_INSN_LRO2           0x5800                  // 0101100xxxxxxxxx     LDR
 389
 390 # define MASK_THUMB_INSN_LRO3           0xf800                  // 11111xxxxxxxxxxx
 391 # define PTRN_THUMB_INSN_LRO3           0x4800                  // 01001xxxxxxxxxxx     LDR Rd, [PC, #<imm8> * 4]
 392
 393 # define MASK_THUMB_INSN_LRO4           MASK_THUMB_INSN_LRO1
 394 # define PTRN_THUMB_INSN_LRO4           0x5A00                  // 0101101xxxxxxxxx     LDRH
 395
 396 # define MASK_THUMB_INSN_LRO5           MASK_THUMB_INSN_LRO1
 397 # define PTRN_THUMB_INSN_LRO5           0x5C00                  // 0101110xxxxxxxxx     LDRB
 398
 399 # define MASK_THUMB_INSN_LRO6           MASK_THUMB_INSN_LRO1
 400 # define PTRN_THUMB_INSN_LRO6           0x5E00                  // 0101111xxxxxxxxx     LDRSH
 401
 402 # define MASK_THUMB2_INSN_ADR           0x8000fa1f              // 1xxxxxxxxxxxxxxx 11111x1xxxx11111    // swapped
 403 # define PTRN_THUMB2_INSN_ADR           0x0000f20f              // 0xxxxxxxxxxxxxxx 11110x1xxxx01111    // swapped
 404
 405
 406
 407 // Store register offset
 408 # define MASK_ARM_INSN_SRO              MASK_ARM_INSN_LRO
 409 # define PTRN_ARM_INSN_SRO              0x06000000
 410
 411 # define MASK_THUMB_INSN_SRO1           MASK_THUMB_INSN_LRO1
 412 # define PTRN_THUMB_INSN_SRO1           0x5000                  // 0101000xxxxxxxxx     STR
 413
 414 # define MASK_THUMB_INSN_SRO2           MASK_THUMB_INSN_LRO1
 415 # define PTRN_THUMB_INSN_SRO2           0x5200                  // 0101001xxxxxxxxx     STRH
 416
 417 # define MASK_THUMB_INSN_SRO3           MASK_THUMB_INSN_LRO1
 418 # define PTRN_THUMB_INSN_SRO3           0x5400                  // 0101010xxxxxxxxx     STRB
 419
 420 // Load multiple
 421 # define MASK_ARM_INSN_LM               0x0E100000
 422 # define PTRN_ARM_INSN_LM               0x08100000
 423
 424 # define MASK_THUMB2_INSN_LDMIA         0x8000ffd0              // 1xxxxxxxxxxxxxxx 1111111111x1xxxx    // swapped
 425 # define PTRN_THUMB2_INSN_LDMIA         0x8000e890              // 1xxxxxxxxxxxxxxx 1110100010x1xxxx    LDMIA(.W) Rn(!), {Rx, ..., PC}// swapped
 426
 427 # define MASK_THUMB2_INSN_LDMDB         0x8000ffd0              // 1xxxxxxxxxxxxxxx 1111111111x1xxxx    // swapped
 428 # define PTRN_THUMB2_INSN_LDMDB         0x8000e910              // 1xxxxxxxxxxxxxxx 1110100100x1xxxx    LDMDB(.W) Rn(!), {Rx, ..., PC}// swapped
 429
 430 // Store multiple
 431 # define MASK_ARM_INSN_SM               MASK_ARM_INSN_LM
 432 # define PTRN_ARM_INSN_SM               0x08000000
 433
 434
 435 // Coprocessor load/store and double register transfers
 436 # define MASK_ARM_INSN_CLS              0x0E000000
 437 # define PTRN_ARM_INSN_CLS              0x0C000000
 438 // Coprocessor register transfers
 439 # define MASK_ARM_INSN_CRT              0x0F000010
 440 # define PTRN_ARM_INSN_CRT              0x0E000010
 441
 442 # define ARM_INSN_MATCH(name, insn)             ((insn & MASK_ARM_INSN_##name) == PTRN_ARM_INSN_##name)
 443 # define THUMB_INSN_MATCH(name, insn)           (((insn & 0x0000FFFF) & MASK_THUMB_INSN_##name) == PTRN_THUMB_INSN_##name)
 444 # define THUMB2_INSN_MATCH(name, insn)          ((insn & MASK_THUMB2_INSN_##name) == PTRN_THUMB2_INSN_##name)
 445
 446 # define ARM_INSN_REG_RN(insn)                  ((insn & 0x000F0000)>>16)
 447
 448 # define ARM_INSN_REG_SET_RN(insn, nreg)        {insn &= ~0x000F0000; insn |= nreg<<16;}
 449
 450 # define ARM_INSN_REG_RD(insn)                  ((insn & 0x0000F000)>>12)
 451
 452 # define ARM_INSN_REG_SET_RD(insn, nreg)        {insn &= ~0x0000F000; insn |= nreg<<12;}
 453
 454 # define ARM_INSN_REG_RS(insn)                  ((insn & 0x00000F00)>>8)
 455
 456 # define ARM_INSN_REG_SET_RS(insn, nreg)        {insn &= ~0x00000F00; insn |= nreg<<8;}
 457
 458 # define ARM_INSN_REG_RM(insn)                  (insn & 0x0000000F)
 459
 460 # define ARM_INSN_REG_SET_RM(insn, nreg)        {insn &= ~0x0000000F; insn |= nreg;}
 461
 462 # define ARM_INSN_REG_MR(insn, nreg)            (insn & (1 << nreg))
 463
 464 # define ARM_INSN_REG_SET_MR(insn, nreg)        {insn |= (1 << nreg);}
 465
 466 # define ARM_INSN_REG_CLEAR_MR(insn, nreg)      {insn &= ~(1 << nreg);}
 467
 468 # define THUMB2_INSN_REG_RT(insn)               ((insn & 0xf0000000) >> 28)
 469 # define THUMB2_INSN_REG_RT2(insn)              ((insn & 0x0f000000) >> 24)
 470 # define THUMB2_INSN_REG_RN(insn)               (insn & 0x0000000f)
 471 # define THUMB2_INSN_REG_RD(insn)               ((insn & 0x0f000000) >> 24)
 472 # define THUMB2_INSN_REG_RM(insn)               ((insn & 0x000f0000) >> 16)
 473
 474
 475 /* per-cpu kprobe control block */
 476 struct kprobe_ctlblk {
 477         unsigned long kprobe_status;
 478         struct prev_kprobe prev_kprobe;
 479 };
 480
 481 /* Architecture specific copy of original instruction */
 482 struct arch_specific_insn {
 483         /* copy of the original instruction */
 484         kprobe_opcode_t *insn;
 485         kprobe_opcode_t *insn_arm;
 486         kprobe_opcode_t *insn_thumb;
 487 };
 488
 489 typedef kprobe_opcode_t (*entry_point_t) (unsigned long, unsigned long, unsigned long, unsigned long, unsigned long, unsigned long);
 490
 491 //void gen_insn_execbuf (void);
 492 //void pc_dep_insn_execbuf (void);
 493 //void gen_insn_execbuf_holder (void);
 494 //void pc_dep_insn_execbuf_holder (void);
 495
 496 #endif /* _DBI_ASM_ARM_KPROBES_H */