1 #ifndef _DBI_ASM_ARM_KPROBES_H
2 #define _DBI_ASM_ARM_KPROBES_H
5 * Dynamic Binary Instrumentation Module based on KProbes
6 * modules/kprobe/arch/asm-arm/dbi_kprobes.h
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 * Copyright (C) Samsung Electronics, 2006-2010
24 * 2006-2007 Ekaterina Gorelkina <e.gorelkina@samsung.com>: initial implementation for ARM/MIPS
25 * 2008-2009 Alexey Gerenkov <a.gerenkov@samsung.com> User-Space
26 * Probes initial implementation; Support x86/ARM/MIPS for both user and kernel spaces.
27 * 2010 Ekaterina Gorelkina <e.gorelkina@samsung.com>: redesign module for separating core and arch parts
29 * 2010-2011 Alexander Shirshikov <a.shirshikov@samsung.com>: initial implementation for Thumb
32 #include <linux/sched.h>
33 #include "../../dbi_kprobes_deps.h"
34 #include "../dbi_kprobes.h"
36 typedef unsigned long kprobe_opcode_t;
38 #ifdef CONFIG_CPU_S3C2443
39 #define BREAKPOINT_INSTRUCTION 0xe1200070
41 #define BREAKPOINT_INSTRUCTION 0xffffdeff
42 #endif /* CONFIG_CPU_S3C2443 */
44 #ifndef KPROBES_RET_PROBE_TRAMP
46 #ifdef CONFIG_CPU_S3C2443
47 #define UNDEF_INSTRUCTION 0xe1200071
49 #define UNDEF_INSTRUCTION 0xfffffffe
50 #endif /* CONFIG_CPU_S3C2443 */
52 #endif /* KPROBES_RET_PROBE_TRAMP */
54 #define MAX_INSN_SIZE 1
56 # define UPROBES_TRAMP_LEN 9
57 # define UPROBES_TRAMP_INSN_IDX 2
58 # define UPROBES_TRAMP_SS_BREAK_IDX 4
59 # define UPROBES_TRAMP_RET_BREAK_IDX 5
60 # define KPROBES_TRAMP_LEN 9
61 # define KPROBES_TRAMP_INSN_IDX UPROBES_TRAMP_INSN_IDX
62 # define KPROBES_TRAMP_SS_BREAK_IDX UPROBES_TRAMP_SS_BREAK_IDX
63 # define KPROBES_TRAMP_RET_BREAK_IDX UPROBES_TRAMP_RET_BREAK_IDX
65 #define UREGS_OFFSET 8
67 static inline unsigned long arch_get_task_pc(struct task_struct *p)
69 return task_thread_info(p)->cpu_context.pc;
72 static inline void arch_set_task_pc(struct task_struct *p, unsigned long val)
74 task_thread_info(p)->cpu_context.pc = val;
77 static inline struct pt_regs *dbi_get_syscall_uregs(unsigned long sp)
79 return (struct pt_regs *)(sp + UREGS_OFFSET);
82 static inline unsigned long dbi_get_stack_ptr(struct pt_regs *regs)
87 static inline unsigned long dbi_get_instr_ptr(struct pt_regs *regs)
92 static inline void dbi_set_instr_ptr(struct pt_regs *regs, unsigned long val)
97 static inline unsigned long dbi_get_ret_addr(struct pt_regs *regs)
102 static inline void dbi_set_ret_addr(struct pt_regs *regs, unsigned long val)
107 static inline unsigned long dbi_get_arg(struct pt_regs *regs, int num)
109 return regs->uregs[num];
112 static inline void dbi_set_arg(struct pt_regs *regs, int num, unsigned long val)
114 regs->uregs[num] = val;
117 static inline int dbi_fp_backtrace(struct task_struct *task, unsigned long *buf,
121 struct pt_regs *regs;
128 regs = task_pt_regs(task);
129 frame.next = regs->ARM_fp;
130 frame.raddr = dbi_get_ret_addr(regs);
132 while (frame.next && i < max_cnt) {
133 if (read_proc_vm_atomic(task, frame.next - 4, &frame, sizeof(frame))
135 buf[i++] = frame.raddr;
144 # define MASK_ARM_INSN_UNDEF 0x0FF00000 // xxxx1111 1111xxxx xxxxxxxx xxxxxxxx
145 # define PTRN_ARM_INSN_UNDEF 0x03000000 // cccc0011 0000xxxx xxxxxxxx xxxxxxxx
147 # define MASK_THUMB_INSN_UNDEF 0xFE00 // 11111111xxxxxxxx
148 # define PTRN_THUMB_INSN_UNDEF 0xDE00 // 11011110xxxxxxxx
150 // architecturally undefined
151 # define MASK_ARM_INSN_AUNDEF 0x0FF000F0
152 # define PTRN_ARM_INSN_AUNDEF 0x07F000F0
155 # define MASK_ARM_INSN_B 0x0E000000 // xxxx111xxxxxxxxxxxxxxxxxxxxxxxxx
156 # define PTRN_ARM_INSN_B 0x0A000000 // cccc101xxxxxxxxxxxxxxxxxxxxxxxxx
158 # define MASK_THUMB_INSN_B1 0xF000 // 1111xxxxxxxxxxxx
159 # define PTRN_THUMB_INSN_B1 0xD000 // 1101xxxxxxxxxxxx // b<cond> label
161 # define MASK_THUMB_INSN_B2 0xF800 // 11111xxxxxxxxxxx
162 # define PTRN_THUMB_INSN_B2 0xE000 // 11100xxxxxxxxxxx // b label
164 # define MASK_THUMB_INSN_CBZ 0xF500 // 1111x1x1xxxxxxxx
165 # define PTRN_THUMB_INSN_CBZ 0xB100 // 1011x0x1xxxxxxxx // CBZ/CBNZ
167 # define MASK_THUMB2_INSN_B1 0xD000F800 // 11x1xxxxxxxxxxxx 11111xxxxxxxxxxx // swapped
168 # define PTRN_THUMB2_INSN_B1 0x8000F000 // 10x0xxxxxxxxxxxx 11110xxxxxxxxxxx // swapped
170 # define MASK_THUMB2_INSN_B2 0xD000F800 // 11x1xxxxxxxxxxxx 11111xxxxxxxxxxx // swapped
171 # define PTRN_THUMB2_INSN_B2 0x9000F000 // 10x1xxxxxxxxxxxx 11110xxxxxxxxxxx // swapped
173 # define MASK_ARM_INSN_BL 0x0E000000 // xxxx111xxxxxxxxxxxxxxxxxxxxxxxxx
174 # define PTRN_ARM_INSN_BL 0x0B000000 // cccc1011xxxxxxxxxxxxxxxxxxxxxxxx
176 //# define MASK_THUMB_INSN_BL 0xF800 // 11111xxxxxxxxxxx
177 //# define PTRN_THUMB_INSN_BL 0xF000 // 11110xxxxxxxxxxx // shared between BL and BLX
178 //# define PTRN_THUMB_INSN_BL 0xF800 // 11111xxxxxxxxxxx
180 # define MASK_THUMB2_INSN_BL 0xD000F800 // 11x1xxxxxxxxxxxx 11111xxxxxxxxxxx // swapped
181 # define PTRN_THUMB2_INSN_BL 0xD000F000 // 11x1xxxxxxxxxxxx 11110xxxxxxxxxxx // bl imm swapped
183 # define MASK_ARM_INSN_BLX1 0xFF000000 // 11111111xxxxxxxxxxxxxxxxxxxxxxxx
184 # define PTRN_ARM_INSN_BLX1 0xFA000000 // 11111011xxxxxxxxxxxxxxxxxxxxxxxx
186 //# define MASK_THUMB_INSN_BLX1 0xF800 // 11111xxxxxxxxxxx / blx imm
187 //# define PTRN_THUMB_INSN_BLX1 0xF000 // 11101xxxxxxxxxxx
189 # define MASK_THUMB2_INSN_BLX1 0xD001F800 // 11x1xxxxxxxxxxx1 11111xxxxxxxxxxx // swapped
190 # define PTRN_THUMB2_INSN_BLX1 0xC000F000 // 11x0xxxxxxxxxxx0 11110xxxxxxxxxxx // swapped
192 # define MASK_ARM_INSN_BLX2 0x0FF000F0 // xxxx11111111xxxxxxxxxxxx1111xxxx
193 # define PTRN_ARM_INSN_BLX2 0x01200030 // cccc00010010xxxxxxxxxxxx0011xxxx
195 # define MASK_THUMB_INSN_BLX2 0xFF80 // 111111111xxxxxxx / blx reg
196 # define PTRN_THUMB_INSN_BLX2 0x4780 // 010001111xxxxxxx
198 # define MASK_ARM_INSN_BX 0x0FF000F0 // cccc11111111xxxxxxxxxxxx1111xxxx
199 # define PTRN_ARM_INSN_BX 0x01200010 // cccc00010010xxxxxxxxxxxx0001xxxx
201 # define MASK_THUMB_INSN_BX 0xFF80 // 111111111xxxxxxx
202 # define PTRN_THUMB_INSN_BX 0x4700 // 010001110xxxxxxx
204 # define MASK_ARM_INSN_BXJ 0x0FF000F0 // xxxx11111111xxxxxxxxxxxx1111xxxx
205 # define PTRN_ARM_INSN_BXJ 0x01200020 // cccc00010010xxxxxxxxxxxx0010xxxx
207 # define MASK_THUMB2_INSN_BXJ 0xD000FFF0 // 11x1xxxxxxxxxxxx 111111111111xxxx // swapped
208 # define PTRN_THUMB2_INSN_BXJ 0x8000F3C0 // 10x0xxxxxxxxxxxx 111100111100xxxx // swapped
211 // software interrupts
212 # define MASK_ARM_INSN_SWI 0x0F000000 // cccc1111xxxxxxxxxxxxxxxxxxxxxxxx
213 # define PTRN_ARM_INSN_SWI 0x0F000000 // cccc1111xxxxxxxxxxxxxxxxxxxxxxxx
215 # define MASK_THUMB_INSN_SWI 0xFF00 // 11111111xxxxxxxx
216 # define PTRN_THUMB_INSN_SWI 0xDF00 // 11011111xxxxxxxx
219 # define MASK_ARM_INSN_BREAK 0xFFF000F0 // 111111111111xxxxxxxxxxxx1111xxxx
220 # define PTRN_ARM_INSN_BREAK 0xE1200070 // 111000010010xxxxxxxxxxxx0111xxxx /? A8-56 ARM DDI 046B if cond != ‘1110’ then UNPREDICTABLE;
222 # define MASK_THUMB_INSN_BREAK 0xFF00 // 11111111xxxxxxxx
223 # define PTRN_THUMB_INSN_BREAK 0xBE00 // 10111110xxxxxxxx
225 // Data processing immediate shift
226 # define MASK_ARM_INSN_DPIS 0x0E000010
227 # define PTRN_ARM_INSN_DPIS 0x00000000
228 // Data processing register shift
229 # define MASK_ARM_INSN_DPRS 0x0E000090
230 # define PTRN_ARM_INSN_DPRS 0x00000010
232 # define MASK_THUMB2_INSN_DPRS 0xFFE00000 // 11111111111xxxxxxxxxxxxxxxxxxxxx
233 # define PTRN_THUMB2_INSN_DPRS 0xEA000000 // 1110101xxxxxxxxxxxxxxxxxxxxxxxxx
235 // Data processing immediate
236 # define MASK_ARM_INSN_DPI 0x0E000000
237 # define PTRN_ARM_INSN_DPI 0x02000000
239 # define MASK_THUMB_INSN_DP 0xFC00 // 111111xxxxxxxxxx
240 # define PTRN_THUMB_INSN_DP 0x4000 // 010000xxxxxxxxxx
242 # define MASK_THUMB_INSN_APC 0xF800 // 11111xxxxxxxxxxx
243 # define PTRN_THUMB_INSN_APC 0xA000 // 10100xxxxxxxxxxx ADD Rd, [PC, #<imm8> * 4]
245 # define MASK_THUMB2_INSN_DPI 0xFBE08000 // 11111x11111xxxxx 1xxxxxxxxxxxxxxx
246 //# define PTRN_THUMB2_INSN_DPI 0xF0000000 // 11110x0xxxxxxxxx 0xxxxxxxxxxxxxxx /? A6-19 ARM DDI 0406B
247 # define PTRN_THUMB2_INSN_DPI 0xF2000000 // 11110x1xxxxxxxxx 0xxxxxxxxxxxxxxx /? A6-19 ARM DDI 0406B
249 # define MASK_THUMB_INSN_MOV3 0xFF00 // 11111111xxxxxxxx
250 # define PTRN_THUMB_INSN_MOV3 0x4600 // 01000110xxxxxxxx MOV Rd, PC
252 # define MASK_THUMB2_INSN_RSBW 0x8000fbe0 // 1xxxxxxxxxxxxxxx 11111x11111xxxxx // swapped
253 # define PTRN_THUMB2_INSN_RSBW 0x0000f1c0 // 0xxxxxxxxxxxxxxx 11110x01110xxxxx RSB{S}.W Rd, Rn, #<const> // swapped
255 # define MASK_THUMB2_INSN_RORW 0xf0f0ffe0 // 1111xxxx1111xxxx 11111111111xxxxx // swapped
256 # define PTRN_THUMB2_INSN_RORW 0xf000fa60 // 1111xxxx0000xxxx 11111010011xxxxx ROR{S}.W Rd, Rn, Rm // swapped
258 # define MASK_THUMB2_INSN_ROR 0x0030ffef // xxxxxxxxxx11xxxx 11111111111x1111 // swapped
259 # define PTRN_THUMB2_INSN_ROR 0x0030ea4f // xxxxxxxxxx11xxxx 11101010010x1111 ROR{S} Rd, Rm, #<imm> // swapped
261 # define MASK_THUMB2_INSN_LSLW1 0xf0f0ffe0 // 1111xxxx1111xxxx 11111111111xxxxx // swapped
262 # define PTRN_THUMB2_INSN_LSLW1 0xf000fa00 // 1111xxxx0000xxxx 11111010000xxxxx LSL{S}.W Rd, Rn, Rm // swapped
264 # define MASK_THUMB2_INSN_LSLW2 0x0030ffef // xxxxxxxxxx11xxxx 11111111111x1111 // swapped
265 # define PTRN_THUMB2_INSN_LSLW2 0x0000ea4f // xxxxxxxxxx00xxxx 11101010010x1111 LSL{S}.W Rd, Rm, #<imm5> // swapped
267 # define MASK_THUMB2_INSN_LSRW1 0xf0f0ffe0 // 1111xxxx1111xxxx 11111111111xxxxx // swapped
268 # define PTRN_THUMB2_INSN_LSRW1 0xf000fa20 // 1111xxxx0000xxxx 11111010001xxxxx LSR{S}.W Rd, Rn, Rm // swapped
270 # define MASK_THUMB2_INSN_LSRW2 0x0030ffef // xxxxxxxxxx11xxxx 11111111111x1111 // swapped
271 # define PTRN_THUMB2_INSN_LSRW2 0x0010ea4f // xxxxxxxxxx01xxxx 11101010010x1111 LSR{S}.W Rd, Rm, #<imm5> // swapped
273 # define MASK_THUMB2_INSN_TEQ1 0x8f00fbf0 // 1xxx1111xxxxxxxx 11111x111111xxxx // swapped
274 # define PTRN_THUMB2_INSN_TEQ1 0x0f00f090 // 0xxx1111xxxxxxxx 11110x001001xxxx TEQ Rn, #<const> // swapped
276 # define MASK_THUMB2_INSN_TEQ2 0x0f00fff0 // xxxx1111xxxxxxxx 111111111111xxxx // swapped
277 # define PTRN_THUMB2_INSN_TEQ2 0x0f00ea90 // xxxx1111xxxxxxxx 111010101001xxxx TEQ Rn, Rm{,<shift>} // swapped
279 # define MASK_THUMB2_INSN_TST1 0x8f00fbf0 // 1xxx1111xxxxxxxx 11111x111111xxxx // swapped
280 # define PTRN_THUMB2_INSN_TST1 0x0f00f010 // 0xxx1111xxxxxxxx 11110x000001xxxx TST Rn, #<const> // swapped
282 # define MASK_THUMB2_INSN_TST2 0x0f00fff0 // xxxx1111xxxxxxxx 111111111111xxxx // swapped
283 # define PTRN_THUMB2_INSN_TST2 0x0f00ea10 // xxxx1111xxxxxxxx 111010100001xxxx TST Rn, Rm{,<shift>} // swapped
286 // Load immediate offset
287 # define MASK_ARM_INSN_LIO 0x0E100000
288 # define PTRN_ARM_INSN_LIO 0x04100000
290 # define MASK_THUMB_INSN_LIO1 0xF800 // 11111xxxxxxxxxxx
291 # define PTRN_THUMB_INSN_LIO1 0x6800 // 01101xxxxxxxxxxx LDR
293 # define MASK_THUMB_INSN_LIO2 MASK_THUMB_INSN_LIO1
294 # define PTRN_THUMB_INSN_LIO2 0x7800 // 01111xxxxxxxxxxx LDRB
296 # define MASK_THUMB_INSN_LIO3 MASK_THUMB_INSN_LIO1
297 # define PTRN_THUMB_INSN_LIO3 0x8800 // 10001xxxxxxxxxxx LDRH
299 # define MASK_THUMB_INSN_LIO4 MASK_THUMB_INSN_LIO1
300 # define PTRN_THUMB_INSN_LIO4 0x9800 // 10011xxxxxxxxxxx LDR SP relative
302 # define MASK_THUMB2_INSN_LDRW 0x0000fff0 // xxxxxxxxxxxxxxxx 111111111111xxxx // swapped
303 # define PTRN_THUMB2_INSN_LDRW 0x0000f850 // xxxxxxxxxxxxxxxx 111110000101xxxx LDR.W Rt, [Rn, #-<imm12>]// swapped
305 # define MASK_THUMB2_INSN_LDRW1 MASK_THUMB2_INSN_LDRW
306 # define PTRN_THUMB2_INSN_LDRW1 0x0000f8d0 // xxxxxxxxxxxxxxxx 111110001101xxxx LDR.W Rt, [Rn, #<imm12>]// swapped
308 # define MASK_THUMB2_INSN_LDRBW MASK_THUMB2_INSN_LDRW
309 # define PTRN_THUMB2_INSN_LDRBW 0x0000f810 // xxxxxxxxxxxxxxxx 111110000001xxxx LDRB.W Rt, [Rn, #-<imm8>]// swapped
311 # define MASK_THUMB2_INSN_LDRBW1 MASK_THUMB2_INSN_LDRW
312 # define PTRN_THUMB2_INSN_LDRBW1 0x0000f890 // xxxxxxxxxxxxxxxx 111110001001xxxx LDRB.W Rt, [Rn, #<imm12>]// swapped
314 # define MASK_THUMB2_INSN_LDRHW MASK_THUMB2_INSN_LDRW
315 # define PTRN_THUMB2_INSN_LDRHW 0x0000f830 // xxxxxxxxxxxxxxxx 111110000011xxxx LDRH.W Rt, [Rn, #-<imm8>]// swapped
317 # define MASK_THUMB2_INSN_LDRHW1 MASK_THUMB2_INSN_LDRW
318 # define PTRN_THUMB2_INSN_LDRHW1 0x0000f8b0 // xxxxxxxxxxxxxxxx 111110001011xxxx LDRH.W Rt, [Rn, #<imm12>]// swapped
320 # define MASK_THUMB2_INSN_LDRD 0x0000fed0 // xxxxxxxxxxxxxxxx 1111111x11x1xxxx // swapped
321 # define PTRN_THUMB2_INSN_LDRD 0x0000e850 // xxxxxxxxxxxxxxxx 1110100x01x1xxxx LDRD Rt, Rt2, [Rn, #-<imm8>]// swapped
323 # define MASK_THUMB2_INSN_LDRD1 MASK_THUMB2_INSN_LDRD
324 # define PTRN_THUMB2_INSN_LDRD1 0x0000e8d0 // xxxxxxxxxxxxxxxx 1110100x11x1xxxx LDRD Rt, Rt2, [Rn, #<imm8>]// swapped
326 # define MASK_THUMB2_INSN_LDRWL 0x0fc0fff0 // xxxx111111xxxxxx 111111111111xxxx // swapped
327 # define PTRN_THUMB2_INSN_LDRWL 0x0000f850 // xxxxxxxxxxxxxxxx 111110000101xxxx LDR.W Rt, [Rn, Rm, LSL #<imm2>]// swapped
329 # define MASK_THUMB2_INSN_LDREX 0x0f00ffff // xxxx1111xxxxxxxx 1111111111111111 // swapped
330 # define PTRN_THUMB2_INSN_LDREX 0x0f00e85f // xxxx1111xxxxxxxx 1110100001011111 LDREX Rt, [PC, #<imm8>]// swapped
332 # define MASK_THUMB2_INSN_MUL 0xf0f0fff0 // 1111xxxx1111xxxx 111111111111xxxx // swapped
333 # define PTRN_THUMB2_INSN_MUL 0xf000fb00 // 1111xxxx0000xxxx 111110110000xxxx MUL Rd, Rn, Rm// swapped
335 # define MASK_THUMB2_INSN_DP 0x0000ff00 // xxxxxxxxxxxxxxxx 11111111xxxxxxxx // swapped
336 # define PTRN_THUMB2_INSN_DP 0x0000eb00 // xxxxxxxxxxxxxxxx 11101011xxxxxxxx // swapped ADD/SUB/SBC/...Rd, Rn, Rm{,<shift>}
341 // Store immediate offset
342 # define MASK_ARM_INSN_SIO MASK_ARM_INSN_LIO
343 # define PTRN_ARM_INSN_SIO 0x04000000
345 # define MASK_THUMB_INSN_SIO1 MASK_THUMB_INSN_LIO1
346 # define PTRN_THUMB_INSN_SIO1 0x6000 // 01100xxxxxxxxxxx STR
348 # define MASK_THUMB_INSN_SIO2 MASK_THUMB_INSN_LIO1
349 # define PTRN_THUMB_INSN_SIO2 0x7000 // 01110xxxxxxxxxxx STRB
351 # define MASK_THUMB_INSN_SIO3 MASK_THUMB_INSN_LIO1
352 # define PTRN_THUMB_INSN_SIO3 0x8000 // 10000xxxxxxxxxxx STRH
354 # define MASK_THUMB_INSN_SIO4 MASK_THUMB_INSN_LIO1
355 # define PTRN_THUMB_INSN_SIO4 0x9000 // 10010xxxxxxxxxxx STR SP relative
357 # define MASK_THUMB2_INSN_STRW 0x0fc0fff0 // xxxx111111xxxxxx 111111111111xxxx // swapped
358 # define PTRN_THUMB2_INSN_STRW 0x0000f840 // xxxx000000xxxxxx 111110000100xxxx STR.W Rt, [Rn, Rm, {LSL #<imm2>}]// swapped
360 # define MASK_THUMB2_INSN_STRW1 0x0000fff0 // xxxxxxxxxxxxxxxx 111111111111xxxx // swapped
361 # define PTRN_THUMB2_INSN_STRW1 0x0000f8c0 // xxxxxxxxxxxxxxxx 111110001100xxxx STR.W Rt, [Rn, #imm12]// swapped // STR.W Rt, [PC, #imm12] shall be skipped, because it hangs on Tegra. WTF
363 # define MASK_THUMB2_INSN_STRHW MASK_THUMB2_INSN_STRW
364 # define PTRN_THUMB2_INSN_STRHW 0x0000f820 // xxxx000000xxxxxx 111110000010xxxx STRH.W Rt, [Rn, Rm, {LSL #<imm2>}]// swapped
366 # define MASK_THUMB2_INSN_STRHW1 0x0000fff0 // xxxxxxxxxxxxxxxx 111111111111xxxx // swapped
367 # define PTRN_THUMB2_INSN_STRHW1 0x0000f8a0 // xxxxxxxxxxxxxxxx 111110001010xxxx STRH.W Rt, [Rn, #<imm12>]// swapped
369 # define MASK_THUMB2_INSN_STRHT 0x0f00fff0 // xxxx1111xxxxxxxx 111111111111xxxx // swapped // strht r1, [pc, #imm] illegal instruction on Tegra. WTF
370 # define PTRN_THUMB2_INSN_STRHT 0x0e00f820 // xxxx1110xxxxxxxx 111110000010xxxx STRHT Rt, [Rn, #<imm8>]// swapped
372 # define MASK_THUMB2_INSN_STRT 0x0f00fff0 // xxxx1111xxxxxxxx 111111111111xxxx // swapped
373 # define PTRN_THUMB2_INSN_STRT 0x0e00f840 // xxxx1110xxxxxxxx 111110000100xxxx STRT Rt, [Rn, #<imm8>]// swapped
375 # define MASK_THUMB2_INSN_STRBW MASK_THUMB2_INSN_STRW // xxxx111111xxxxxx 111111111111xxxx // swapped
376 # define PTRN_THUMB2_INSN_STRBW 0x0000f800 // xxxx000000xxxxxx 111110000100xxxx STRB.W Rt, [Rn, Rm, {LSL #<imm2>}]// swapped
378 # define MASK_THUMB2_INSN_STRBW1 0x0000fff0 // xxxxxxxxxxxxxxxx 111111111111xxxx // swapped
379 # define PTRN_THUMB2_INSN_STRBW1 0x0000f880 // xxxxxxxxxxxxxxxx 111110001000xxxx STRB.W Rt, [Rn, #<imm12>]// swapped // STRB.W Rt, [PC, #imm12] shall be skipped, because it hangs on Tegra. WTF
381 # define MASK_THUMB2_INSN_STRBT 0x0f00fff0 // xxxx1111xxxxxxxx 111111111111xxxx // swapped
382 # define PTRN_THUMB2_INSN_STRBT 0x0e00f800 // xxxx1110xxxxxxxx 111110000000xxxx STRBT Rt, [Rn, #<imm8>}]// swapped
384 # define MASK_THUMB2_INSN_STRD 0x0000fe50 // xxxxxxxxxxxxxxxx 1111111xx1x1xxxx // swapped
385 # define PTRN_THUMB2_INSN_STRD 0x0000e840 // xxxxxxxxxxxxxxxx 1110100xx1x0xxxx STR{D, EX, EXB, EXH, EXD} Rt, Rt2, [Rn, #<imm8>]// swapped
388 // Load register offset
389 # define MASK_ARM_INSN_LRO 0x0E100010
390 # define PTRN_ARM_INSN_LRO 0x06100000
392 # define MASK_THUMB_INSN_LRO1 0xFE00 // 1111111xxxxxxxxx
393 # define PTRN_THUMB_INSN_LRO1 0x5600 // 0101011xxxxxxxxx LDRSB
395 # define MASK_THUMB_INSN_LRO2 MASK_THUMB_INSN_LRO1
396 # define PTRN_THUMB_INSN_LRO2 0x5800 // 0101100xxxxxxxxx LDR
398 # define MASK_THUMB_INSN_LRO3 0xf800 // 11111xxxxxxxxxxx
399 # define PTRN_THUMB_INSN_LRO3 0x4800 // 01001xxxxxxxxxxx LDR Rd, [PC, #<imm8> * 4]
401 # define MASK_THUMB_INSN_LRO4 MASK_THUMB_INSN_LRO1
402 # define PTRN_THUMB_INSN_LRO4 0x5A00 // 0101101xxxxxxxxx LDRH
404 # define MASK_THUMB_INSN_LRO5 MASK_THUMB_INSN_LRO1
405 # define PTRN_THUMB_INSN_LRO5 0x5C00 // 0101110xxxxxxxxx LDRB
407 # define MASK_THUMB_INSN_LRO6 MASK_THUMB_INSN_LRO1
408 # define PTRN_THUMB_INSN_LRO6 0x5E00 // 0101111xxxxxxxxx LDRSH
410 # define MASK_THUMB2_INSN_ADR 0x8000fa1f // 1xxxxxxxxxxxxxxx 11111x1xxxx11111 // swapped
411 # define PTRN_THUMB2_INSN_ADR 0x0000f20f // 0xxxxxxxxxxxxxxx 11110x1xxxx01111 // swapped
415 // Store register offset
416 # define MASK_ARM_INSN_SRO MASK_ARM_INSN_LRO
417 # define PTRN_ARM_INSN_SRO 0x06000000
419 # define MASK_THUMB_INSN_SRO1 MASK_THUMB_INSN_LRO1
420 # define PTRN_THUMB_INSN_SRO1 0x5000 // 0101000xxxxxxxxx STR
422 # define MASK_THUMB_INSN_SRO2 MASK_THUMB_INSN_LRO1
423 # define PTRN_THUMB_INSN_SRO2 0x5200 // 0101001xxxxxxxxx STRH
425 # define MASK_THUMB_INSN_SRO3 MASK_THUMB_INSN_LRO1
426 # define PTRN_THUMB_INSN_SRO3 0x5400 // 0101010xxxxxxxxx STRB
429 # define MASK_ARM_INSN_LM 0x0E100000
430 # define PTRN_ARM_INSN_LM 0x08100000
432 # define MASK_THUMB2_INSN_LDMIA 0x8000ffd0 // 1xxxxxxxxxxxxxxx 1111111111x1xxxx // swapped
433 # define PTRN_THUMB2_INSN_LDMIA 0x8000e890 // 1xxxxxxxxxxxxxxx 1110100010x1xxxx LDMIA(.W) Rn(!), {Rx, ..., PC}// swapped
435 # define MASK_THUMB2_INSN_LDMDB 0x8000ffd0 // 1xxxxxxxxxxxxxxx 1111111111x1xxxx // swapped
436 # define PTRN_THUMB2_INSN_LDMDB 0x8000e910 // 1xxxxxxxxxxxxxxx 1110100100x1xxxx LDMDB(.W) Rn(!), {Rx, ..., PC}// swapped
439 # define MASK_ARM_INSN_SM MASK_ARM_INSN_LM
440 # define PTRN_ARM_INSN_SM 0x08000000
443 // Coprocessor load/store and double register transfers
444 # define MASK_ARM_INSN_CLS 0x0E000000
445 # define PTRN_ARM_INSN_CLS 0x0C000000
446 // Coprocessor register transfers
447 # define MASK_ARM_INSN_CRT 0x0F000010
448 # define PTRN_ARM_INSN_CRT 0x0E000010
450 # define ARM_INSN_MATCH(name, insn) ((insn & MASK_ARM_INSN_##name) == PTRN_ARM_INSN_##name)
451 # define THUMB_INSN_MATCH(name, insn) (((insn & 0x0000FFFF) & MASK_THUMB_INSN_##name) == PTRN_THUMB_INSN_##name)
452 # define THUMB2_INSN_MATCH(name, insn) ((insn & MASK_THUMB2_INSN_##name) == PTRN_THUMB2_INSN_##name)
454 # define ARM_INSN_REG_RN(insn) ((insn & 0x000F0000)>>16)
456 # define ARM_INSN_REG_SET_RN(insn, nreg) {insn &= ~0x000F0000; insn |= nreg<<16;}
458 # define ARM_INSN_REG_RD(insn) ((insn & 0x0000F000)>>12)
460 # define ARM_INSN_REG_SET_RD(insn, nreg) {insn &= ~0x0000F000; insn |= nreg<<12;}
462 # define ARM_INSN_REG_RS(insn) ((insn & 0x00000F00)>>8)
464 # define ARM_INSN_REG_SET_RS(insn, nreg) {insn &= ~0x00000F00; insn |= nreg<<8;}
466 # define ARM_INSN_REG_RM(insn) (insn & 0x0000000F)
468 # define ARM_INSN_REG_SET_RM(insn, nreg) {insn &= ~0x0000000F; insn |= nreg;}
470 # define ARM_INSN_REG_MR(insn, nreg) (insn & (1 << nreg))
472 # define ARM_INSN_REG_SET_MR(insn, nreg) {insn |= (1 << nreg);}
474 # define ARM_INSN_REG_CLEAR_MR(insn, nreg) {insn &= ~(1 << nreg);}
476 # define THUMB2_INSN_REG_RT(insn) ((insn & 0xf0000000) >> 28)
477 # define THUMB2_INSN_REG_RT2(insn) ((insn & 0x0f000000) >> 24)
478 # define THUMB2_INSN_REG_RN(insn) (insn & 0x0000000f)
479 # define THUMB2_INSN_REG_RD(insn) ((insn & 0x0f000000) >> 24)
480 # define THUMB2_INSN_REG_RM(insn) ((insn & 0x000f0000) >> 16)
483 /* per-cpu kprobe control block */
484 struct kprobe_ctlblk {
485 unsigned long kprobe_status;
486 struct prev_kprobe prev_kprobe;
489 /* Architecture specific copy of original instruction */
490 struct arch_specific_insn {
491 /* copy of the original instruction */
492 kprobe_opcode_t *insn;
493 kprobe_opcode_t *insn_arm;
494 kprobe_opcode_t *insn_thumb;
497 typedef kprobe_opcode_t (*entry_point_t) (unsigned long, unsigned long, unsigned long, unsigned long, unsigned long, unsigned long);
501 void swap_register_undef_hook(struct undef_hook *hook);
502 void swap_unregister_undef_hook(struct undef_hook *hook);
504 int arch_check_insn_arm(struct arch_specific_insn *ainsn);
505 int prep_pc_dep_insn_execbuf(kprobe_opcode_t *insns, kprobe_opcode_t insn, int uregs);
507 //void gen_insn_execbuf (void);
508 //void pc_dep_insn_execbuf (void);
509 //void gen_insn_execbuf_holder (void);
510 //void pc_dep_insn_execbuf_holder (void);
512 #endif /* _DBI_ASM_ARM_KPROBES_H */