[REFACTOR] Buffer: move getting next queue element into separate function
[kernel/swap-modules.git] / kprobe / arch / asm-arm / dbi_kprobes.h
1 #ifndef _DBI_ASM_ARM_KPROBES_H
2 #define _DBI_ASM_ARM_KPROBES_H
3
4 /*
5  *  Dynamic Binary Instrumentation Module based on KProbes
6  *  modules/kprobe/arch/asm-arm/dbi_kprobes.h
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21  *
22  * Copyright (C) Samsung Electronics, 2006-2010
23  *
24  * 2006-2007    Ekaterina Gorelkina <e.gorelkina@samsung.com>: initial implementation for ARM/MIPS
25  * 2008-2009    Alexey Gerenkov <a.gerenkov@samsung.com> User-Space
26  *              Probes initial implementation; Support x86/ARM/MIPS for both user and kernel spaces.
27  * 2010         Ekaterina Gorelkina <e.gorelkina@samsung.com>: redesign module for separating core and arch parts
28  *
29  * 2010-2011    Alexander Shirshikov <a.shirshikov@samsung.com>: initial implementation for Thumb
30  */
31
32 #include <linux/sched.h>
33 #include <linux/compiler.h>
34
35 typedef unsigned long kprobe_opcode_t;
36
37 #ifdef CONFIG_CPU_S3C2443
38 #define BREAKPOINT_INSTRUCTION          0xe1200070
39 #else
40 #define BREAKPOINT_INSTRUCTION          0xffffdeff
41 #endif /* CONFIG_CPU_S3C2443 */
42
43 #ifndef KPROBES_RET_PROBE_TRAMP
44
45 #ifdef CONFIG_CPU_S3C2443
46 #define UNDEF_INSTRUCTION               0xe1200071
47 #else
48 #define UNDEF_INSTRUCTION               0xfffffffe
49 #endif /* CONFIG_CPU_S3C2443 */
50
51 #endif /* KPROBES_RET_PROBE_TRAMP */
52
53 #define MAX_INSN_SIZE                   1
54
55 # define UPROBES_TRAMP_LEN              9
56 # define UPROBES_TRAMP_INSN_IDX         2
57 # define UPROBES_TRAMP_SS_BREAK_IDX     4
58 # define UPROBES_TRAMP_RET_BREAK_IDX    5
59 # define KPROBES_TRAMP_LEN              9
60 # define KPROBES_TRAMP_INSN_IDX         UPROBES_TRAMP_INSN_IDX
61 # define KPROBES_TRAMP_SS_BREAK_IDX     UPROBES_TRAMP_SS_BREAK_IDX
62 # define KPROBES_TRAMP_RET_BREAK_IDX    UPROBES_TRAMP_RET_BREAK_IDX
63
64 #define UREGS_OFFSET 8
65
66 struct prev_kprobe {
67         struct kprobe *kp;
68         unsigned long status;
69 };
70
71 static inline unsigned long arch_get_task_pc(struct task_struct *p)
72 {
73         return task_thread_info(p)->cpu_context.pc;
74 }
75
76 static inline void arch_set_task_pc(struct task_struct *p, unsigned long val)
77 {
78         task_thread_info(p)->cpu_context.pc = val;
79 }
80
81 static inline struct pt_regs *dbi_get_syscall_uregs(unsigned long sp)
82 {
83         return (struct pt_regs *)(sp + UREGS_OFFSET);
84 }
85
86 static inline unsigned long dbi_get_stack_ptr(struct pt_regs *regs)
87 {
88         return regs->ARM_sp;
89 }
90
91 static inline unsigned long dbi_get_instr_ptr(struct pt_regs *regs)
92 {
93         return regs->ARM_pc;
94 }
95
96 static inline void dbi_set_instr_ptr(struct pt_regs *regs, unsigned long val)
97 {
98         regs->ARM_pc = val;
99 }
100
101 static inline unsigned long dbi_get_ret_addr(struct pt_regs *regs)
102 {
103         return regs->ARM_lr;
104 }
105
106 static inline void dbi_set_ret_addr(struct pt_regs *regs, unsigned long val)
107 {
108         regs->ARM_lr = val;
109 }
110
111 static inline unsigned long dbi_get_arg(struct pt_regs *regs, int num)
112 {
113         return regs->uregs[num];
114 }
115
116 static inline void dbi_set_arg(struct pt_regs *regs, int num, unsigned long val)
117 {
118         regs->uregs[num] = val;
119 }
120
121 // undefined
122 # define MASK_ARM_INSN_UNDEF            0x0FF00000              // xxxx1111 1111xxxx xxxxxxxx xxxxxxxx
123 # define PTRN_ARM_INSN_UNDEF            0x03000000              // cccc0011 0000xxxx xxxxxxxx xxxxxxxx
124
125 # define MASK_THUMB_INSN_UNDEF          0xFE00                  // 11111111xxxxxxxx
126 # define PTRN_THUMB_INSN_UNDEF          0xDE00                  // 11011110xxxxxxxx
127
128 // architecturally undefined
129 # define MASK_ARM_INSN_AUNDEF           0x0FF000F0
130 # define PTRN_ARM_INSN_AUNDEF           0x07F000F0
131
132 // branches
133 # define MASK_ARM_INSN_B                0x0F000000              // xxxx1111xxxxxxxxxxxxxxxxxxxxxxxx
134 # define PTRN_ARM_INSN_B                0x0A000000              // cccc1010xxxxxxxxxxxxxxxxxxxxxxxx
135
136 # define MASK_THUMB_INSN_B1             0xF000                  // 1111xxxxxxxxxxxx
137 # define PTRN_THUMB_INSN_B1             0xD000                  // 1101xxxxxxxxxxxx                                             // b<cond> label
138
139 # define MASK_THUMB_INSN_B2             0xF800                  // 11111xxxxxxxxxxx
140 # define PTRN_THUMB_INSN_B2             0xE000                  // 11100xxxxxxxxxxx                                             // b label
141
142 # define MASK_THUMB_INSN_CBZ            0xF500                  // 1111x1x1xxxxxxxx
143 # define PTRN_THUMB_INSN_CBZ            0xB100                  // 1011x0x1xxxxxxxx                                             // CBZ/CBNZ
144
145 # define MASK_THUMB2_INSN_B1            0xD000F800              // 11x1xxxxxxxxxxxx 11111xxxxxxxxxxx                            // swapped
146 # define PTRN_THUMB2_INSN_B1            0x8000F000              // 10x0xxxxxxxxxxxx 11110xxxxxxxxxxx                            // swapped
147
148 # define MASK_THUMB2_INSN_B2            0xD000F800              // 11x1xxxxxxxxxxxx 11111xxxxxxxxxxx                            // swapped
149 # define PTRN_THUMB2_INSN_B2            0x9000F000              // 10x1xxxxxxxxxxxx 11110xxxxxxxxxxx                            // swapped
150
151 # define MASK_ARM_INSN_BL               0x0F000000              // xxxx1111xxxxxxxxxxxxxxxxxxxxxxxx
152 # define PTRN_ARM_INSN_BL               0x0B000000              // cccc1011xxxxxxxxxxxxxxxxxxxxxxxx
153
154 //# define MASK_THUMB_INSN_BL           0xF800                  // 11111xxxxxxxxxxx
155 //# define PTRN_THUMB_INSN_BL           0xF000                  // 11110xxxxxxxxxxx                                             // shared between BL and BLX
156 //# define PTRN_THUMB_INSN_BL           0xF800                  // 11111xxxxxxxxxxx
157
158 # define MASK_THUMB2_INSN_BL            0xD000F800              // 11x1xxxxxxxxxxxx 11111xxxxxxxxxxx                            // swapped
159 # define PTRN_THUMB2_INSN_BL            0xD000F000              // 11x1xxxxxxxxxxxx 11110xxxxxxxxxxx                            // bl imm  swapped
160
161 # define MASK_ARM_INSN_BLX1             0xFE000000              // 1111111axxxxxxxxxxxxxxxxxxxxxxxx
162 # define PTRN_ARM_INSN_BLX1             0xFA000000              // 1111101axxxxxxxxxxxxxxxxxxxxxxxx
163
164 //# define MASK_THUMB_INSN_BLX1         0xF800                  // 11111xxxxxxxxxxx                                             / blx imm
165 //# define PTRN_THUMB_INSN_BLX1         0xF000                  // 11101xxxxxxxxxxx
166
167 # define MASK_THUMB2_INSN_BLX1          0xD001F800              // 11x1xxxxxxxxxxx1 11111xxxxxxxxxxx                            // swapped
168 # define PTRN_THUMB2_INSN_BLX1          0xC000F000              // 11x0xxxxxxxxxxx0 11110xxxxxxxxxxx                            // swapped
169
170 # define MASK_ARM_INSN_BLX2             0x0FF000F0              // xxxx11111111xxxxxxxxxxxx1111xxxx
171 # define PTRN_ARM_INSN_BLX2             0x01200030              // cccc00010010xxxxxxxxxxxx0011xxxx
172
173 # define MASK_THUMB_INSN_BLX2           0xFF80                  // 111111111xxxxxxx                                             / blx reg
174 # define PTRN_THUMB_INSN_BLX2           0x4780                  // 010001111xxxxxxx
175
176 # define MASK_ARM_INSN_BX               0x0FF000F0              // cccc11111111xxxxxxxxxxxx1111xxxx
177 # define PTRN_ARM_INSN_BX               0x01200010              // cccc00010010xxxxxxxxxxxx0001xxxx
178
179 # define MASK_THUMB_INSN_BX             0xFF80                  // 111111111xxxxxxx
180 # define PTRN_THUMB_INSN_BX             0x4700                  // 010001110xxxxxxx
181
182 # define MASK_ARM_INSN_BXJ              0x0FF000F0              // xxxx11111111xxxxxxxxxxxx1111xxxx
183 # define PTRN_ARM_INSN_BXJ              0x01200020              // cccc00010010xxxxxxxxxxxx0010xxxx
184
185 # define MASK_THUMB2_INSN_BXJ           0xD000FFF0              // 11x1xxxxxxxxxxxx 111111111111xxxx                            // swapped
186 # define PTRN_THUMB2_INSN_BXJ           0x8000F3C0              // 10x0xxxxxxxxxxxx 111100111100xxxx                            // swapped
187
188
189 // software interrupts
190 # define MASK_ARM_INSN_SWI              0x0F000000              // cccc1111xxxxxxxxxxxxxxxxxxxxxxxx
191 # define PTRN_ARM_INSN_SWI              0x0F000000              // cccc1111xxxxxxxxxxxxxxxxxxxxxxxx
192
193 # define MASK_THUMB_INSN_SWI            0xFF00                  // 11111111xxxxxxxx
194 # define PTRN_THUMB_INSN_SWI            0xDF00                  // 11011111xxxxxxxx
195
196 // break
197 # define MASK_ARM_INSN_BREAK            0xFFF000F0              // 111111111111xxxxxxxxxxxx1111xxxx
198 # define PTRN_ARM_INSN_BREAK            0xE1200070              // 111000010010xxxxxxxxxxxx0111xxxx                             /? A8-56 ARM DDI 046B if cond != â€˜1110’ then UNPREDICTABLE;
199
200 # define MASK_THUMB_INSN_BREAK          0xFF00                  // 11111111xxxxxxxx
201 # define PTRN_THUMB_INSN_BREAK          0xBE00                  // 10111110xxxxxxxx
202
203 // Data processing immediate shift
204 # define MASK_ARM_INSN_DPIS             0x0E000010
205 # define PTRN_ARM_INSN_DPIS             0x00000000
206 // Data processing register shift
207 # define MASK_ARM_INSN_DPRS             0x0E000090
208 # define PTRN_ARM_INSN_DPRS             0x00000010
209
210 # define MASK_THUMB2_INSN_DPRS          0xFFE00000              // 11111111111xxxxxxxxxxxxxxxxxxxxx
211 # define PTRN_THUMB2_INSN_DPRS          0xEA000000              // 1110101xxxxxxxxxxxxxxxxxxxxxxxxx
212
213 // Data processing immediate
214 # define MASK_ARM_INSN_DPI              0x0E000000
215 # define PTRN_ARM_INSN_DPI              0x02000000
216
217 # define MASK_THUMB_INSN_DP             0xFC00                  // 111111xxxxxxxxxx
218 # define PTRN_THUMB_INSN_DP             0x4000                  // 010000xxxxxxxxxx
219
220 # define MASK_THUMB_INSN_APC            0xF800                  // 11111xxxxxxxxxxx
221 # define PTRN_THUMB_INSN_APC            0xA000                  // 10100xxxxxxxxxxx     ADD Rd, [PC, #<imm8> * 4]
222
223 # define MASK_THUMB2_INSN_DPI           0xFBE08000              // 11111x11111xxxxx 1xxxxxxxxxxxxxxx
224 //# define PTRN_THUMB2_INSN_DPI         0xF0000000              // 11110x0xxxxxxxxx 0xxxxxxxxxxxxxxx                            /? A6-19 ARM DDI 0406B
225 # define PTRN_THUMB2_INSN_DPI           0xF2000000              // 11110x1xxxxxxxxx 0xxxxxxxxxxxxxxx                            /? A6-19 ARM DDI 0406B
226
227 # define MASK_THUMB_INSN_MOV3           0xFF00                  // 11111111xxxxxxxx
228 # define PTRN_THUMB_INSN_MOV3           0x4600                  // 01000110xxxxxxxx     MOV Rd, PC
229
230 # define MASK_THUMB2_INSN_RSBW          0x8000fbe0              // 1xxxxxxxxxxxxxxx 11111x11111xxxxx    // swapped
231 # define PTRN_THUMB2_INSN_RSBW          0x0000f1c0              // 0xxxxxxxxxxxxxxx 11110x01110xxxxx    RSB{S}.W Rd, Rn, #<const> // swapped
232
233 # define MASK_THUMB2_INSN_RORW          0xf0f0ffe0              // 1111xxxx1111xxxx 11111111111xxxxx    // swapped
234 # define PTRN_THUMB2_INSN_RORW          0xf000fa60              // 1111xxxx0000xxxx 11111010011xxxxx    ROR{S}.W Rd, Rn, Rm // swapped
235
236 # define MASK_THUMB2_INSN_ROR           0x0030ffef              // xxxxxxxxxx11xxxx 11111111111x1111    // swapped
237 # define PTRN_THUMB2_INSN_ROR           0x0030ea4f              // xxxxxxxxxx11xxxx 11101010010x1111    ROR{S} Rd, Rm, #<imm> // swapped
238
239 # define MASK_THUMB2_INSN_LSLW1         0xf0f0ffe0              // 1111xxxx1111xxxx 11111111111xxxxx    // swapped
240 # define PTRN_THUMB2_INSN_LSLW1         0xf000fa00              // 1111xxxx0000xxxx 11111010000xxxxx    LSL{S}.W Rd, Rn, Rm // swapped
241
242 # define MASK_THUMB2_INSN_LSLW2         0x0030ffef              // xxxxxxxxxx11xxxx 11111111111x1111    // swapped
243 # define PTRN_THUMB2_INSN_LSLW2         0x0000ea4f              // xxxxxxxxxx00xxxx 11101010010x1111    LSL{S}.W Rd, Rm, #<imm5> // swapped
244
245 # define MASK_THUMB2_INSN_LSRW1         0xf0f0ffe0              // 1111xxxx1111xxxx 11111111111xxxxx    // swapped
246 # define PTRN_THUMB2_INSN_LSRW1         0xf000fa20              // 1111xxxx0000xxxx 11111010001xxxxx    LSR{S}.W Rd, Rn, Rm // swapped
247
248 # define MASK_THUMB2_INSN_LSRW2         0x0030ffef              // xxxxxxxxxx11xxxx 11111111111x1111    // swapped
249 # define PTRN_THUMB2_INSN_LSRW2         0x0010ea4f              // xxxxxxxxxx01xxxx 11101010010x1111    LSR{S}.W Rd, Rm, #<imm5> // swapped
250
251 # define MASK_THUMB2_INSN_TEQ1          0x8f00fbf0              // 1xxx1111xxxxxxxx 11111x111111xxxx    // swapped
252 # define PTRN_THUMB2_INSN_TEQ1          0x0f00f090              // 0xxx1111xxxxxxxx 11110x001001xxxx    TEQ Rn, #<const> // swapped
253
254 # define MASK_THUMB2_INSN_TEQ2          0x0f00fff0              // xxxx1111xxxxxxxx 111111111111xxxx    // swapped
255 # define PTRN_THUMB2_INSN_TEQ2          0x0f00ea90              // xxxx1111xxxxxxxx 111010101001xxxx    TEQ Rn, Rm{,<shift>} // swapped
256
257 # define MASK_THUMB2_INSN_TST1          0x8f00fbf0              // 1xxx1111xxxxxxxx 11111x111111xxxx    // swapped
258 # define PTRN_THUMB2_INSN_TST1          0x0f00f010              // 0xxx1111xxxxxxxx 11110x000001xxxx    TST Rn, #<const> // swapped
259
260 # define MASK_THUMB2_INSN_TST2          0x0f00fff0              // xxxx1111xxxxxxxx 111111111111xxxx    // swapped
261 # define PTRN_THUMB2_INSN_TST2          0x0f00ea10              // xxxx1111xxxxxxxx 111010100001xxxx    TST Rn, Rm{,<shift>} // swapped
262
263
264 // Load immediate offset
265 # define MASK_ARM_INSN_LIO              0x0E100000
266 # define PTRN_ARM_INSN_LIO              0x04100000
267
268 # define MASK_THUMB_INSN_LIO1           0xF800                  // 11111xxxxxxxxxxx
269 # define PTRN_THUMB_INSN_LIO1           0x6800                  // 01101xxxxxxxxxxx     LDR
270
271 # define MASK_THUMB_INSN_LIO2           MASK_THUMB_INSN_LIO1
272 # define PTRN_THUMB_INSN_LIO2           0x7800                  // 01111xxxxxxxxxxx     LDRB
273
274 # define MASK_THUMB_INSN_LIO3           MASK_THUMB_INSN_LIO1
275 # define PTRN_THUMB_INSN_LIO3           0x8800                  // 10001xxxxxxxxxxx     LDRH
276
277 # define MASK_THUMB_INSN_LIO4           MASK_THUMB_INSN_LIO1
278 # define PTRN_THUMB_INSN_LIO4           0x9800                  // 10011xxxxxxxxxxx     LDR SP relative
279
280 # define MASK_THUMB2_INSN_LDRW          0x0000fff0              // xxxxxxxxxxxxxxxx 111111111111xxxx    // swapped
281 # define PTRN_THUMB2_INSN_LDRW          0x0000f850              // xxxxxxxxxxxxxxxx 111110000101xxxx    LDR.W Rt, [Rn, #-<imm12>]// swapped
282
283 # define MASK_THUMB2_INSN_LDRW1         MASK_THUMB2_INSN_LDRW
284 # define PTRN_THUMB2_INSN_LDRW1         0x0000f8d0              // xxxxxxxxxxxxxxxx 111110001101xxxx    LDR.W Rt, [Rn, #<imm12>]// swapped
285
286 # define MASK_THUMB2_INSN_LDRBW         MASK_THUMB2_INSN_LDRW
287 # define PTRN_THUMB2_INSN_LDRBW         0x0000f810              // xxxxxxxxxxxxxxxx 111110000001xxxx    LDRB.W Rt, [Rn, #-<imm8>]// swapped
288
289 # define MASK_THUMB2_INSN_LDRBW1        MASK_THUMB2_INSN_LDRW
290 # define PTRN_THUMB2_INSN_LDRBW1        0x0000f890              // xxxxxxxxxxxxxxxx 111110001001xxxx    LDRB.W Rt, [Rn, #<imm12>]// swapped
291
292 # define MASK_THUMB2_INSN_LDRHW         MASK_THUMB2_INSN_LDRW
293 # define PTRN_THUMB2_INSN_LDRHW         0x0000f830              // xxxxxxxxxxxxxxxx 111110000011xxxx    LDRH.W Rt, [Rn, #-<imm8>]// swapped
294
295 # define MASK_THUMB2_INSN_LDRHW1        MASK_THUMB2_INSN_LDRW
296 # define PTRN_THUMB2_INSN_LDRHW1        0x0000f8b0              // xxxxxxxxxxxxxxxx 111110001011xxxx    LDRH.W Rt, [Rn, #<imm12>]// swapped
297
298 # define MASK_THUMB2_INSN_LDRD          0x0000fed0              // xxxxxxxxxxxxxxxx 1111111x11x1xxxx    // swapped
299 # define PTRN_THUMB2_INSN_LDRD          0x0000e850              // xxxxxxxxxxxxxxxx 1110100x01x1xxxx    LDRD Rt, Rt2, [Rn, #-<imm8>]// swapped
300
301 # define MASK_THUMB2_INSN_LDRD1         MASK_THUMB2_INSN_LDRD
302 # define PTRN_THUMB2_INSN_LDRD1         0x0000e8d0              // xxxxxxxxxxxxxxxx 1110100x11x1xxxx    LDRD Rt, Rt2, [Rn, #<imm8>]// swapped
303
304 # define MASK_THUMB2_INSN_LDRWL         0x0fc0fff0              // xxxx111111xxxxxx 111111111111xxxx    // swapped
305 # define PTRN_THUMB2_INSN_LDRWL         0x0000f850              // xxxxxxxxxxxxxxxx 111110000101xxxx    LDR.W Rt, [Rn, Rm, LSL #<imm2>]// swapped
306
307 # define MASK_THUMB2_INSN_LDREX         0x0f00ffff              // xxxx1111xxxxxxxx 1111111111111111    // swapped
308 # define PTRN_THUMB2_INSN_LDREX         0x0f00e85f              // xxxx1111xxxxxxxx 1110100001011111    LDREX Rt, [PC, #<imm8>]// swapped
309
310 # define MASK_THUMB2_INSN_MUL           0xf0f0fff0              // 1111xxxx1111xxxx 111111111111xxxx    // swapped
311 # define PTRN_THUMB2_INSN_MUL           0xf000fb00              // 1111xxxx0000xxxx 111110110000xxxx    MUL Rd, Rn, Rm// swapped
312
313 # define MASK_THUMB2_INSN_DP            0x0000ff00              // xxxxxxxxxxxxxxxx 11111111xxxxxxxx    // swapped
314 # define PTRN_THUMB2_INSN_DP            0x0000eb00              // xxxxxxxxxxxxxxxx 11101011xxxxxxxx    // swapped      ADD/SUB/SBC/...Rd, Rn, Rm{,<shift>}
315
316
317
318
319 // Store immediate offset
320 # define MASK_ARM_INSN_SIO              MASK_ARM_INSN_LIO
321 # define PTRN_ARM_INSN_SIO              0x04000000
322
323 # define MASK_THUMB_INSN_SIO1           MASK_THUMB_INSN_LIO1
324 # define PTRN_THUMB_INSN_SIO1           0x6000                  // 01100xxxxxxxxxxx     STR
325
326 # define MASK_THUMB_INSN_SIO2           MASK_THUMB_INSN_LIO1
327 # define PTRN_THUMB_INSN_SIO2           0x7000                  // 01110xxxxxxxxxxx     STRB
328
329 # define MASK_THUMB_INSN_SIO3           MASK_THUMB_INSN_LIO1
330 # define PTRN_THUMB_INSN_SIO3           0x8000                  // 10000xxxxxxxxxxx     STRH
331
332 # define MASK_THUMB_INSN_SIO4           MASK_THUMB_INSN_LIO1
333 # define PTRN_THUMB_INSN_SIO4           0x9000                  // 10010xxxxxxxxxxx     STR SP relative
334
335 # define MASK_THUMB2_INSN_STRW          0x0fc0fff0              // xxxx111111xxxxxx 111111111111xxxx    // swapped
336 # define PTRN_THUMB2_INSN_STRW          0x0000f840              // xxxx000000xxxxxx 111110000100xxxx    STR.W Rt, [Rn, Rm, {LSL #<imm2>}]// swapped
337
338 # define MASK_THUMB2_INSN_STRW1         0x0000fff0              // xxxxxxxxxxxxxxxx 111111111111xxxx    // swapped
339 # define PTRN_THUMB2_INSN_STRW1         0x0000f8c0              // xxxxxxxxxxxxxxxx 111110001100xxxx    STR.W Rt, [Rn, #imm12]// swapped                                // STR.W Rt, [PC, #imm12] shall be skipped, because it hangs on Tegra. WTF
340
341 # define MASK_THUMB2_INSN_STRHW         MASK_THUMB2_INSN_STRW
342 # define PTRN_THUMB2_INSN_STRHW         0x0000f820              // xxxx000000xxxxxx 111110000010xxxx    STRH.W Rt, [Rn, Rm, {LSL #<imm2>}]// swapped
343
344 # define MASK_THUMB2_INSN_STRHW1        0x0000fff0              // xxxxxxxxxxxxxxxx 111111111111xxxx    // swapped
345 # define PTRN_THUMB2_INSN_STRHW1        0x0000f8a0              // xxxxxxxxxxxxxxxx 111110001010xxxx    STRH.W Rt, [Rn, #<imm12>]// swapped
346
347 # define MASK_THUMB2_INSN_STRHT         0x0f00fff0              // xxxx1111xxxxxxxx 111111111111xxxx    // swapped                                                      // strht r1, [pc, #imm] illegal instruction on Tegra. WTF
348 # define PTRN_THUMB2_INSN_STRHT         0x0e00f820              // xxxx1110xxxxxxxx 111110000010xxxx    STRHT Rt, [Rn, #<imm8>]// swapped
349
350 # define MASK_THUMB2_INSN_STRT          0x0f00fff0              // xxxx1111xxxxxxxx 111111111111xxxx    // swapped
351 # define PTRN_THUMB2_INSN_STRT          0x0e00f840              // xxxx1110xxxxxxxx 111110000100xxxx    STRT Rt, [Rn, #<imm8>]// swapped
352
353 # define MASK_THUMB2_INSN_STRBW         MASK_THUMB2_INSN_STRW   // xxxx111111xxxxxx 111111111111xxxx    // swapped
354 # define PTRN_THUMB2_INSN_STRBW         0x0000f800              // xxxx000000xxxxxx 111110000100xxxx    STRB.W Rt, [Rn, Rm, {LSL #<imm2>}]// swapped
355
356 # define MASK_THUMB2_INSN_STRBW1        0x0000fff0              // xxxxxxxxxxxxxxxx 111111111111xxxx    // swapped
357 # define PTRN_THUMB2_INSN_STRBW1        0x0000f880              // xxxxxxxxxxxxxxxx 111110001000xxxx    STRB.W Rt, [Rn, #<imm12>]// swapped                             // STRB.W Rt, [PC, #imm12] shall be skipped, because it hangs on Tegra. WTF
358
359 # define MASK_THUMB2_INSN_STRBT         0x0f00fff0              // xxxx1111xxxxxxxx 111111111111xxxx    // swapped
360 # define PTRN_THUMB2_INSN_STRBT         0x0e00f800              // xxxx1110xxxxxxxx 111110000000xxxx    STRBT Rt, [Rn, #<imm8>}]// swapped
361
362 # define MASK_THUMB2_INSN_STRD          0x0000fe50              // xxxxxxxxxxxxxxxx 1111111xx1x1xxxx    // swapped
363 # define PTRN_THUMB2_INSN_STRD          0x0000e840              // xxxxxxxxxxxxxxxx 1110100xx1x0xxxx    STR{D, EX, EXB, EXH, EXD} Rt, Rt2, [Rn, #<imm8>]// swapped
364
365
366 // Load register offset
367 # define MASK_ARM_INSN_LRO              0x0E100010
368 # define PTRN_ARM_INSN_LRO              0x06100000
369
370 # define MASK_THUMB_INSN_LRO1           0xFE00                  // 1111111xxxxxxxxx
371 # define PTRN_THUMB_INSN_LRO1           0x5600                  // 0101011xxxxxxxxx     LDRSB
372
373 # define MASK_THUMB_INSN_LRO2           MASK_THUMB_INSN_LRO1
374 # define PTRN_THUMB_INSN_LRO2           0x5800                  // 0101100xxxxxxxxx     LDR
375
376 # define MASK_THUMB_INSN_LRO3           0xf800                  // 11111xxxxxxxxxxx
377 # define PTRN_THUMB_INSN_LRO3           0x4800                  // 01001xxxxxxxxxxx     LDR Rd, [PC, #<imm8> * 4]
378
379 # define MASK_THUMB_INSN_LRO4           MASK_THUMB_INSN_LRO1
380 # define PTRN_THUMB_INSN_LRO4           0x5A00                  // 0101101xxxxxxxxx     LDRH
381
382 # define MASK_THUMB_INSN_LRO5           MASK_THUMB_INSN_LRO1
383 # define PTRN_THUMB_INSN_LRO5           0x5C00                  // 0101110xxxxxxxxx     LDRB
384
385 # define MASK_THUMB_INSN_LRO6           MASK_THUMB_INSN_LRO1
386 # define PTRN_THUMB_INSN_LRO6           0x5E00                  // 0101111xxxxxxxxx     LDRSH
387
388 # define MASK_THUMB2_INSN_ADR           0x8000fa1f              // 1xxxxxxxxxxxxxxx 11111x1xxxx11111    // swapped
389 # define PTRN_THUMB2_INSN_ADR           0x0000f20f              // 0xxxxxxxxxxxxxxx 11110x1xxxx01111    // swapped
390
391
392
393 // Store register offset
394 # define MASK_ARM_INSN_SRO              MASK_ARM_INSN_LRO
395 # define PTRN_ARM_INSN_SRO              0x06000000
396
397 # define MASK_THUMB_INSN_SRO1           MASK_THUMB_INSN_LRO1
398 # define PTRN_THUMB_INSN_SRO1           0x5000                  // 0101000xxxxxxxxx     STR
399
400 # define MASK_THUMB_INSN_SRO2           MASK_THUMB_INSN_LRO1
401 # define PTRN_THUMB_INSN_SRO2           0x5200                  // 0101001xxxxxxxxx     STRH
402
403 # define MASK_THUMB_INSN_SRO3           MASK_THUMB_INSN_LRO1
404 # define PTRN_THUMB_INSN_SRO3           0x5400                  // 0101010xxxxxxxxx     STRB
405
406 // Load multiple
407 # define MASK_ARM_INSN_LM               0x0E100000
408 # define PTRN_ARM_INSN_LM               0x08100000
409
410 # define MASK_THUMB2_INSN_LDMIA         0x8000ffd0              // 1xxxxxxxxxxxxxxx 1111111111x1xxxx    // swapped
411 # define PTRN_THUMB2_INSN_LDMIA         0x8000e890              // 1xxxxxxxxxxxxxxx 1110100010x1xxxx    LDMIA(.W) Rn(!), {Rx, ..., PC}// swapped
412
413 # define MASK_THUMB2_INSN_LDMDB         0x8000ffd0              // 1xxxxxxxxxxxxxxx 1111111111x1xxxx    // swapped
414 # define PTRN_THUMB2_INSN_LDMDB         0x8000e910              // 1xxxxxxxxxxxxxxx 1110100100x1xxxx    LDMDB(.W) Rn(!), {Rx, ..., PC}// swapped
415
416 // Store multiple
417 # define MASK_ARM_INSN_SM               MASK_ARM_INSN_LM
418 # define PTRN_ARM_INSN_SM               0x08000000
419
420
421 // Coprocessor load/store and double register transfers
422 # define MASK_ARM_INSN_CLS              0x0E000000
423 # define PTRN_ARM_INSN_CLS              0x0C000000
424 // Coprocessor register transfers
425 # define MASK_ARM_INSN_CRT              0x0F000010
426 # define PTRN_ARM_INSN_CRT              0x0E000010
427
428 # define ARM_INSN_MATCH(name, insn)             ((insn & MASK_ARM_INSN_##name) == PTRN_ARM_INSN_##name)
429 # define THUMB_INSN_MATCH(name, insn)           (((insn & 0x0000FFFF) & MASK_THUMB_INSN_##name) == PTRN_THUMB_INSN_##name)
430 # define THUMB2_INSN_MATCH(name, insn)          ((insn & MASK_THUMB2_INSN_##name) == PTRN_THUMB2_INSN_##name)
431
432 # define ARM_INSN_REG_RN(insn)                  ((insn & 0x000F0000)>>16)
433
434 # define ARM_INSN_REG_SET_RN(insn, nreg)        {insn &= ~0x000F0000; insn |= nreg<<16;}
435
436 # define ARM_INSN_REG_RD(insn)                  ((insn & 0x0000F000)>>12)
437
438 # define ARM_INSN_REG_SET_RD(insn, nreg)        {insn &= ~0x0000F000; insn |= nreg<<12;}
439
440 # define ARM_INSN_REG_RS(insn)                  ((insn & 0x00000F00)>>8)
441
442 # define ARM_INSN_REG_SET_RS(insn, nreg)        {insn &= ~0x00000F00; insn |= nreg<<8;}
443
444 # define ARM_INSN_REG_RM(insn)                  (insn & 0x0000000F)
445
446 # define ARM_INSN_REG_SET_RM(insn, nreg)        {insn &= ~0x0000000F; insn |= nreg;}
447
448 # define ARM_INSN_REG_MR(insn, nreg)            (insn & (1 << nreg))
449
450 # define ARM_INSN_REG_SET_MR(insn, nreg)        {insn |= (1 << nreg);}
451
452 # define ARM_INSN_REG_CLEAR_MR(insn, nreg)      {insn &= ~(1 << nreg);}
453
454 # define THUMB2_INSN_REG_RT(insn)               ((insn & 0xf0000000) >> 28)
455 # define THUMB2_INSN_REG_RT2(insn)              ((insn & 0x0f000000) >> 24)
456 # define THUMB2_INSN_REG_RN(insn)               (insn & 0x0000000f)
457 # define THUMB2_INSN_REG_RD(insn)               ((insn & 0x0f000000) >> 24)
458 # define THUMB2_INSN_REG_RM(insn)               ((insn & 0x000f0000) >> 16)
459
460
461 /* per-cpu kprobe control block */
462 struct kprobe_ctlblk {
463         unsigned long kprobe_status;
464         struct prev_kprobe prev_kprobe;
465 };
466
467 /* Architecture specific copy of original instruction */
468 struct arch_specific_insn {
469         /* copy of the original instruction */
470         kprobe_opcode_t *insn;
471         kprobe_opcode_t *insn_arm;
472         kprobe_opcode_t *insn_thumb;
473 };
474
475 typedef kprobe_opcode_t (*entry_point_t) (unsigned long, unsigned long, unsigned long, unsigned long, unsigned long, unsigned long);
476
477 struct undef_hook;
478
479 void swap_register_undef_hook(struct undef_hook *hook);
480 void swap_unregister_undef_hook(struct undef_hook *hook);
481
482 static inline int arch_init_module_deps(void)
483 {
484         return 0;
485 }
486
487 int arch_check_insn_arm(unsigned long insn);
488 int prep_pc_dep_insn_execbuf(kprobe_opcode_t *insns, kprobe_opcode_t insn, int uregs);
489
490 struct slot_manager;
491 struct kretprobe;
492 struct kretprobe_instance;
493 int arch_prepare_kprobe(struct kprobe *p, struct slot_manager *sm);
494 void arch_prepare_kretprobe(struct kretprobe_instance *ri, struct pt_regs *regs);
495
496 void arch_arm_kprobe(struct kprobe *p);
497 void arch_disarm_kprobe(struct kprobe *p);
498
499 int setjmp_pre_handler(struct kprobe *p, struct pt_regs *regs);
500 int longjmp_break_handler(struct kprobe *p, struct pt_regs *regs);
501
502 void save_previous_kprobe(struct kprobe_ctlblk *kcb, struct kprobe *cur_p);
503 void restore_previous_kprobe(struct kprobe_ctlblk *kcb);
504 void set_current_kprobe(struct kprobe *p, struct pt_regs *regs, struct kprobe_ctlblk *kcb);
505
506 void __naked kretprobe_trampoline(void);
507
508 static inline unsigned long swap_get_karg(struct pt_regs *regs, unsigned long n)
509 {
510         switch (n) {
511         case 0:
512                 return regs->ARM_r0;
513         case 1:
514                 return regs->ARM_r1;
515         case 2:
516                 return regs->ARM_r2;
517         case 3:
518                 return regs->ARM_r3;
519         }
520
521         return *((unsigned long *)regs->ARM_sp + n - 4);
522 }
523
524 static inline unsigned long swap_get_sarg(struct pt_regs *regs, unsigned long n)
525 {
526         return swap_get_karg(regs, n);
527 }
528
529 int arch_init_kprobes(void);
530 void arch_exit_kprobes(void);
531
532 //void gen_insn_execbuf (void);
533 //void pc_dep_insn_execbuf (void);
534 //void gen_insn_execbuf_holder (void);
535 //void pc_dep_insn_execbuf_holder (void);
536
537 #endif /* _DBI_ASM_ARM_KPROBES_H */