kprobe/arch/asm-arm/dbi_kprobes.c

   1 /*
   2  *  Dynamic Binary Instrumentation Module based on KProbes
   3  *  modules/kprobe/arch/asm-arm/dbi_kprobes.c
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  18  *
  19  * Copyright (C) Samsung Electronics, 2006-2010
  20  *
  21  * 2006-2007    Ekaterina Gorelkina <e.gorelkina@samsung.com>: initial implementation for ARM/MIPS
  22  * 2008-2009    Alexey Gerenkov <a.gerenkov@samsung.com> User-Space
  23  *              Probes initial implementation; Support x86.
  24  * 2010         Ekaterina Gorelkina <e.gorelkina@samsung.com>: redesign module for separating core and arch parts
  25  * 2010-2011    Alexander Shirshikov <a.shirshikov@samsung.com>: initial implementation for Thumb
  26  * 2012         Stanislav Andreev <s.andreev@samsung.com>: added time debug profiling support; BUG() message fix
  27  * 2012         Stanislav Andreev <s.andreev@samsung.com>: redesign of kprobe functionality -
  28  *              kprobe_handler() now called via undefined instruction hooks
  29  * 2012         Stanislav Andreev <s.andreev@samsung.com>: hash tables search implemented for uprobes
  30  */
  31
  32 #include <linux/module.h>
  33 #include <linux/mm.h>
  34
  35 #include "dbi_kprobes.h"
  36 #include "../dbi_kprobes.h"
  37
  38 #include "../../dbi_kdebug.h"
  39 #include "../../dbi_insn_slots.h"
  40 #include "../../dbi_kprobes_deps.h"
  41 #include "../../dbi_uprobes.h"
  42
  43 #include <asm/cacheflush.h>
  44
  45 #ifdef OVERHEAD_DEBUG
  46 #include <linux/time.h>
  47 #endif
  48
  49 #include <asm/traps.h>
  50 #include <asm/ptrace.h>
  51 #include <linux/list.h>
  52 #include <linux/hash.h>
  53
  54 #define SUPRESS_BUG_MESSAGES
  55
  56 extern unsigned int *sched_addr;
  57 extern unsigned int *fork_addr;
  58
  59 extern struct kprobe * per_cpu__current_kprobe;
  60 extern spinlock_t kretprobe_lock;
  61 extern struct kretprobe *sched_rp;
  62
  63 extern struct hlist_head kprobe_insn_pages;
  64 extern struct hlist_head uprobe_insn_pages;
  65
  66 extern unsigned long (*kallsyms_search) (const char *name);
  67
  68 extern struct kprobe *kprobe_running(void);
  69 extern void reset_current_kprobe(void);
  70 extern struct kprobe_ctlblk *get_kprobe_ctlblk(void);
  71 extern struct kprobe * current_kprobe;
  72
  73 extern struct hlist_head kprobe_table[KPROBE_TABLE_SIZE];
  74
  75 #ifdef OVERHEAD_DEBUG
  76 unsigned long swap_sum_time = 0;
  77 unsigned long swap_sum_hit = 0;
  78 EXPORT_SYMBOL_GPL (swap_sum_time);
  79 EXPORT_SYMBOL_GPL (swap_sum_hit);
  80 #endif
  81
  82 #define sign_extend(x, signbit) ((x) | (0 - ((x) & (1 << (signbit)))))
  83 #define branch_displacement(insn) sign_extend(((insn) & 0xffffff) << 2, 25)
  84
  85 static kprobe_opcode_t get_addr_b(kprobe_opcode_t insn, kprobe_opcode_t addr)
  86 {
  87         // real position less then PC by 8
  88         return (kprobe_opcode_t)((long)addr + 8 + branch_displacement(insn));
  89 }
  90
  91 unsigned int arr_traps_template[] = {
  92                 0xe1a0c00d,    // mov          ip, sp
  93                 0xe92dd800,    // stmdb        sp!, {fp, ip, lr, pc}
  94                 0xe24cb004,    // sub          fp, ip, #4      ; 0x4
  95                 0x00000000,    // b
  96                 0xe3500000,    // cmp          r0, #0  ; 0x0
  97                 0xe89da800,    // ldmia        sp, {fp, sp, pc}
  98                 0x00000000,    // nop
  99                 0xffffffff     // end
 100 };
 101
 102
 103 struct kprobe trampoline_p =
 104 {
 105         .addr = (kprobe_opcode_t *) & kretprobe_trampoline,
 106         .pre_handler = trampoline_probe_handler
 107 };
 108
 109 // is instruction Thumb2 and NOT a branch, etc...
 110 int isThumb2(kprobe_opcode_t insn)
 111 {
 112         if((    (insn & 0xf800) == 0xe800 ||
 113                 (insn & 0xf800) == 0xf000 ||
 114                 (insn & 0xf800) == 0xf800)) return 1;
 115         return 0;
 116 }
 117
 118
 119 int prep_pc_dep_insn_execbuf (kprobe_opcode_t * insns, kprobe_opcode_t insn, int uregs)
 120 {
 121         int i;
 122
 123         if (uregs & 0x10)
 124         {
 125                 int reg_mask = 0x1;
 126                 //search in reg list
 127                 for (i = 0; i < 13; i++, reg_mask <<= 1)
 128                 {
 129                         if (!(insn & reg_mask))
 130                                 break;
 131                 }
 132         }
 133         else
 134         {
 135                 for (i = 0; i < 13; i++)
 136                 {
 137                         if ((uregs & 0x1) && (ARM_INSN_REG_RN (insn) == i))
 138                                 continue;
 139                         if ((uregs & 0x2) && (ARM_INSN_REG_RD (insn) == i))
 140                                 continue;
 141                         if ((uregs & 0x4) && (ARM_INSN_REG_RS (insn) == i))
 142                                 continue;
 143                         if ((uregs & 0x8) && (ARM_INSN_REG_RM (insn) == i))
 144                                 continue;
 145                         break;
 146                 }
 147         }
 148         if (i == 13)
 149         {
 150                 DBPRINTF ("there are no free register %x in insn %lx!", uregs, insn);
 151                 return -EINVAL;
 152         }
 153         DBPRINTF ("prep_pc_dep_insn_execbuf: using R%d, changing regs %x", i, uregs);
 154
 155         // set register to save
 156         ARM_INSN_REG_SET_RD (insns[0], i);
 157         // set register to load address to
 158         ARM_INSN_REG_SET_RD (insns[1], i);
 159         // set instruction to execute and patch it
 160         if (uregs & 0x10)
 161         {
 162                 ARM_INSN_REG_CLEAR_MR (insn, 15);
 163                 ARM_INSN_REG_SET_MR (insn, i);
 164         }
 165         else
 166         {
 167                 if ((uregs & 0x1) && (ARM_INSN_REG_RN (insn) == 15))
 168                         ARM_INSN_REG_SET_RN (insn, i);
 169                 if ((uregs & 0x2) && (ARM_INSN_REG_RD (insn) == 15))
 170                         ARM_INSN_REG_SET_RD (insn, i);
 171                 if ((uregs & 0x4) && (ARM_INSN_REG_RS (insn) == 15))
 172                         ARM_INSN_REG_SET_RS (insn, i);
 173                 if ((uregs & 0x8) && (ARM_INSN_REG_RM (insn) == 15))
 174                         ARM_INSN_REG_SET_RM (insn, i);
 175         }
 176         insns[UPROBES_TRAMP_INSN_IDX] = insn;
 177         // set register to restore
 178         ARM_INSN_REG_SET_RD (insns[3], i);
 179         return 0;
 180 }
 181
 182
 183
 184 int prep_pc_dep_insn_execbuf_thumb (kprobe_opcode_t * insns, kprobe_opcode_t insn, int uregs)
 185 {
 186         unsigned char mreg = 0;
 187         unsigned char reg = 0;
 188
 189
 190         if (THUMB_INSN_MATCH (APC, insn) || THUMB_INSN_MATCH (LRO3, insn))
 191         {
 192                 reg = ((insn & 0xffff) & uregs) >> 8;
 193         }else{
 194                 if (THUMB_INSN_MATCH (MOV3, insn))
 195                 {
 196                         if (((((unsigned char) insn) & 0xff) >> 3) == 15)
 197                                 reg = (insn & 0xffff) & uregs;
 198                         else
 199                                 return 0;
 200                 }else{
 201                         if (THUMB2_INSN_MATCH (ADR, insn))
 202                         {
 203                                 reg = ((insn >> 16) & uregs) >> 8;
 204                                 if (reg == 15) return 0;
 205                         }else{
 206                                 if (THUMB2_INSN_MATCH (LDRW, insn) || THUMB2_INSN_MATCH (LDRW1, insn) ||
 207                                     THUMB2_INSN_MATCH (LDRHW, insn) || THUMB2_INSN_MATCH (LDRHW1, insn) ||
 208                                     THUMB2_INSN_MATCH (LDRWL, insn))
 209                                 {
 210                                         reg = ((insn >> 16) & uregs) >> 12;
 211                                         if (reg == 15) return 0;
 212                                 }else{
 213 // LDRB.W PC, [PC, #immed] => PLD [PC, #immed], so Rt == PC is skipped
 214                                         if (THUMB2_INSN_MATCH (LDRBW, insn) || THUMB2_INSN_MATCH (LDRBW1, insn) || THUMB2_INSN_MATCH (LDREX, insn))
 215                                         {
 216                                                 reg = ((insn >> 16) & uregs) >> 12;
 217                                         }else{
 218                                                 if (THUMB2_INSN_MATCH (DP, insn))
 219                                                 {
 220                                                         reg = ((insn >> 16) & uregs) >> 12;
 221                                                         if (reg == 15) return 0;
 222                                                 }else{
 223                                                         if (THUMB2_INSN_MATCH (RSBW, insn))
 224                                                         {
 225                                                                 reg = ((insn >> 12) & uregs) >> 8;
 226                                                                 if (reg == 15) return 0;
 227                                                         }else{
 228                                                                 if (THUMB2_INSN_MATCH (RORW, insn))
 229                                                                 {
 230                                                                         reg = ((insn >> 12) & uregs) >> 8;
 231                                                                         if (reg == 15) return 0;
 232                                                                 }else{
 233                                                                         if (THUMB2_INSN_MATCH (ROR, insn) || THUMB2_INSN_MATCH (LSLW1, insn) || THUMB2_INSN_MATCH (LSLW2, insn) || THUMB2_INSN_MATCH (LSRW1, insn) || THUMB2_INSN_MATCH (LSRW2, insn))
 234                                                                         {
 235                                                                                 reg = ((insn >> 12) & uregs) >> 8;
 236                                                                                 if (reg == 15) return 0;
 237                                                                         }else{
 238                                                                                 if (THUMB2_INSN_MATCH (TEQ1, insn) || THUMB2_INSN_MATCH (TST1, insn))
 239                                                                                 {
 240                                                                                         reg = 15;
 241                                                                                 }else{
 242                                                                                         if (THUMB2_INSN_MATCH (TEQ2, insn) || THUMB2_INSN_MATCH (TST2, insn))
 243                                                                                         {
 244                                                                                                 reg = THUMB2_INSN_REG_RM(insn);
 245                                                                                         }
 246                                                                                 }
 247                                                                         }
 248                                                                 }
 249                                                         }
 250                                                 }
 251                                         }
 252                                 }
 253                         }
 254                 }
 255         }
 256
 257         if ((   THUMB2_INSN_MATCH (STRW, insn) || THUMB2_INSN_MATCH (STRBW, insn) || THUMB2_INSN_MATCH (STRD, insn) || \
 258                 THUMB2_INSN_MATCH (STRHT, insn) || THUMB2_INSN_MATCH (STRT, insn) || THUMB2_INSN_MATCH (STRHW1, insn) || \
 259                 THUMB2_INSN_MATCH (STRHW, insn)) && THUMB2_INSN_REG_RT(insn) == 15)
 260         {
 261                 reg = THUMB2_INSN_REG_RT(insn);
 262         }
 263
 264         if (reg == 6 || reg == 7)
 265         {
 266                 *((unsigned short*)insns + 0) = (*((unsigned short*)insns + 0) & 0x00ff) | ((1 << mreg) | (1 << (mreg + 1)));
 267                 *((unsigned short*)insns + 1) = (*((unsigned short*)insns + 1) & 0xf8ff) | (mreg << 8);
 268                 *((unsigned short*)insns + 2) = (*((unsigned short*)insns + 2) & 0xfff8) | (mreg + 1);
 269                 *((unsigned short*)insns + 3) = (*((unsigned short*)insns + 3) & 0xffc7) | (mreg << 3);
 270                 *((unsigned short*)insns + 7) = (*((unsigned short*)insns + 7) & 0xf8ff) | (mreg << 8);
 271                 *((unsigned short*)insns + 8) = (*((unsigned short*)insns + 8) & 0xffc7) | (mreg << 3);
 272                 *((unsigned short*)insns + 9) = (*((unsigned short*)insns + 9) & 0xffc7) | ((mreg + 1) << 3);
 273                 *((unsigned short*)insns + 10) = (*((unsigned short*)insns + 10) & 0x00ff) | (( 1 << mreg) | (1 << (mreg + 1)));
 274         }
 275
 276
 277         if (THUMB_INSN_MATCH (APC, insn))
 278         {
 279 //              ADD Rd, PC, #immed_8*4 -> ADD Rd, SP, #immed_8*4
 280                 *((unsigned short*)insns + 4) = ((insn & 0xffff) | 0x800);                              // ADD Rd, SP, #immed_8*4
 281         }else{
 282                 if (THUMB_INSN_MATCH (LRO3, insn))
 283                 {
 284 //                      LDR Rd, [PC, #immed_8*4] -> LDR Rd, [SP, #immed_8*4]
 285                         *((unsigned short*)insns + 4) = ((insn & 0xffff) + 0x5000);                     // LDR Rd, [SP, #immed_8*4]
 286                 }else{
 287                         if (THUMB_INSN_MATCH (MOV3, insn))
 288                         {
 289 //                              MOV Rd, PC -> MOV Rd, SP
 290                                 *((unsigned short*)insns + 4) = ((insn & 0xffff) ^ 0x10);               // MOV Rd, SP
 291                         }else{
 292                                 if (THUMB2_INSN_MATCH (ADR, insn))
 293                                 {
 294 //                                      ADDW Rd, PC, #imm -> ADDW Rd, SP, #imm
 295                                         insns[2] = (insn & 0xfffffff0) | 0x0d;                          // ADDW Rd, SP, #imm
 296                                 }else{
 297                                         if (THUMB2_INSN_MATCH (LDRW, insn) || THUMB2_INSN_MATCH (LDRBW, insn) ||
 298                                             THUMB2_INSN_MATCH (LDRHW, insn))
 299                                         {
 300 //                                              LDR.W Rt, [PC, #-<imm_12>] -> LDR.W Rt, [SP, #-<imm_8>]
 301 //                                              !!!!!!!!!!!!!!!!!!!!!!!!
 302 //                                              !!! imm_12 vs. imm_8 !!!
 303 //                                              !!!!!!!!!!!!!!!!!!!!!!!!
 304                                                 insns[2] = (insn & 0xf0fffff0) | 0x0c00000d;            // LDR.W Rt, [SP, #-<imm_8>]
 305                                         }else{
 306                                                 if (THUMB2_INSN_MATCH (LDRW1, insn) || THUMB2_INSN_MATCH (LDRBW1, insn) ||
 307                                                     THUMB2_INSN_MATCH (LDRHW1, insn) || THUMB2_INSN_MATCH (LDRD, insn) || THUMB2_INSN_MATCH (LDRD1, insn) ||
 308                                                     THUMB2_INSN_MATCH (LDREX, insn))
 309                                                 {
 310 //                                                      LDRx.W Rt, [PC, #+<imm_12>] -> LDRx.W Rt, [SP, #+<imm_12>] (+/-imm_8 for LDRD Rt, Rt2, [PC, #<imm_8>]
 311                                                         insns[2] = (insn & 0xfffffff0) | 0xd;                                                                                                   // LDRx.W Rt, [SP, #+<imm_12>]
 312                                                 }else{
 313                                                         if (THUMB2_INSN_MATCH (MUL, insn))
 314                                                         {
 315                                                                 insns[2] = (insn & 0xfff0ffff) | 0x000d0000;                                                                                    // MUL Rd, Rn, SP
 316                                                         }else{  if (THUMB2_INSN_MATCH (DP, insn))
 317                                                                 {
 318                                                                         if (THUMB2_INSN_REG_RM(insn) == 15) insns[2] = (insn & 0xfff0ffff) | 0x000d0000;                                        // DP Rd, Rn, PC
 319                                                                         else if (THUMB2_INSN_REG_RN(insn) == 15) insns[2] = (insn & 0xfffffff0) | 0xd;                                          // DP Rd, PC, Rm
 320                                                                 }else{  if (THUMB2_INSN_MATCH (LDRWL, insn))
 321                                                                         {
 322 //                                                                              LDRx.W Rt, [PC, #<imm_12>] -> LDRx.W Rt, [SP, #+<imm_12>] (+/-imm_8 for LDRD Rt, Rt2, [PC, #<imm_8>]
 323                                                                                 insns[2] = (insn & 0xfffffff0) | 0xd;                                                                           // LDRx.W Rt, [SP, #+<imm_12>]
 324                                                                         }else{  if (THUMB2_INSN_MATCH (RSBW, insn))
 325                                                                                 {
 326                                                                                         insns[2] = (insn & 0xfffffff0) | 0xd;                                                                   // RSB{S}.W Rd, PC, #<const> -> RSB{S}.W Rd, SP, #<const>
 327                                                                                 }else{  if (THUMB2_INSN_MATCH (RORW, insn) || THUMB2_INSN_MATCH (LSLW1, insn) || THUMB2_INSN_MATCH (LSRW1, insn))
 328                                                                                         {
 329                                                                                                 if ((THUMB2_INSN_REG_RM(insn) == 15) && (THUMB2_INSN_REG_RN(insn) == 15))
 330                                                                                                 {
 331                                                                                                         insns[2] = (insn & 0xfffdfffd);                                                         // ROR.W Rd, PC, PC
 332                                                                                                 }else if (THUMB2_INSN_REG_RM(insn) == 15) insns[2] = (insn & 0xfff0ffff) | 0xd0000;             // ROR.W Rd, Rn, PC
 333                                                                                                         else if (THUMB2_INSN_REG_RN(insn) == 15) insns[2] = (insn & 0xfffffff0) | 0xd;          // ROR.W Rd, PC, Rm
 334                                                                                         }else{  if (THUMB2_INSN_MATCH (ROR, insn) || THUMB2_INSN_MATCH (LSLW2, insn) || THUMB2_INSN_MATCH (LSRW2, insn))
 335                                                                                                 {
 336                                                                                                         insns[2] = (insn & 0xfff0ffff) | 0xd0000;                                               // ROR{S} Rd, PC, #<const> -> ROR{S} Rd, SP, #<const>
 337                                                                                                 }
 338                                                                                         }
 339                                                                                 }
 340                                                                         }
 341                                                                 }
 342                                                         }
 343                                                 }
 344                                         }
 345                                 }
 346                         }
 347                 }
 348         }
 349
 350         if (THUMB2_INSN_MATCH (STRW, insn) || THUMB2_INSN_MATCH (STRBW, insn))
 351         {
 352                 insns[2] = (insn & 0xfff0ffff) | 0x000d0000;                                                            // STRx.W Rt, [Rn, SP]
 353         }else{
 354                 if (THUMB2_INSN_MATCH (STRD, insn) || THUMB2_INSN_MATCH (STRHT, insn) || THUMB2_INSN_MATCH (STRT, insn) || THUMB2_INSN_MATCH (STRHW1, insn))
 355                 {
 356                         if (THUMB2_INSN_REG_RN(insn) == 15)
 357                         {
 358                                 insns[2] = (insn & 0xfffffff0) | 0xd;                                                   // STRD/T/HT{.W} Rt, [SP, ...]
 359                         }else{
 360                                 insns[2] = insn;
 361                         }
 362                 }else{
 363                         if (THUMB2_INSN_MATCH (STRHW, insn) && (THUMB2_INSN_REG_RN(insn) == 15))
 364                         {
 365                                 if (THUMB2_INSN_REG_RN(insn) == 15)
 366                                 {
 367                                         insns[2] = (insn & 0xf0fffff0) | 0x0c00000d;                                    // STRH.W Rt, [SP, #-<imm_8>]
 368                                 }else{
 369                                         insns[2] = insn;
 370                                 }
 371                         }
 372                 }
 373         }
 374
 375 //       STRx PC, xxx
 376         if ((reg == 15) && THUMB2_INSN_MATCH (STRW, insn)   || \
 377                            THUMB2_INSN_MATCH (STRBW, insn)  || \
 378                            THUMB2_INSN_MATCH (STRD, insn)   || \
 379                            THUMB2_INSN_MATCH (STRHT, insn)  || \
 380                            THUMB2_INSN_MATCH (STRT, insn)   || \
 381                            THUMB2_INSN_MATCH (STRHW1, insn) || \
 382                            THUMB2_INSN_MATCH (STRHW, insn) )
 383         {
 384                 insns[2] = (insns[2] & 0x0fffffff) | 0xd0000000;
 385         }
 386
 387
 388
 389         if (THUMB2_INSN_MATCH (TEQ1, insn) || THUMB2_INSN_MATCH (TST1, insn))
 390         {
 391                 insns[2] = (insn & 0xfffffff0) | 0xd;                                                                   // TEQ SP, #<const>
 392         }else{  if (THUMB2_INSN_MATCH (TEQ2, insn) || THUMB2_INSN_MATCH (TST2, insn))
 393                 {
 394                         if ((THUMB2_INSN_REG_RN(insn) == 15) && (THUMB2_INSN_REG_RM(insn) == 15))
 395                         {
 396                                 insns[2] = (insn & 0xfffdfffd);                                                         // TEQ/TST PC, PC
 397                         }else   if (THUMB2_INSN_REG_RM(insn) == 15) insns[2] = (insn & 0xfff0ffff) | 0xd0000;           // TEQ/TST Rn, PC
 398                                 else if (THUMB2_INSN_REG_RN(insn) == 15) insns[2] = (insn & 0xfffffff0) | 0xd;          // TEQ/TST PC, Rm
 399                 }
 400         }
 401
 402         return 0;
 403 }
 404
 405
 406
 407 int arch_check_insn_arm (struct arch_specific_insn *ainsn)
 408 {
 409         int ret = 0;
 410         kprobe_opcode_t *insn;
 411
 412         // check instructions that can change PC by nature
 413         if (
 414 //              ARM_INSN_MATCH (UNDEF, ainsn->insn_arm[0]) ||
 415                 ARM_INSN_MATCH (AUNDEF, ainsn->insn_arm[0]) ||
 416                 ARM_INSN_MATCH (SWI, ainsn->insn_arm[0]) ||
 417                 ARM_INSN_MATCH (BREAK, ainsn->insn_arm[0]) ||
 418                 ARM_INSN_MATCH (BL, ainsn->insn_arm[0]) ||
 419                 ARM_INSN_MATCH (BLX1, ainsn->insn_arm[0]) ||
 420                 ARM_INSN_MATCH (BLX2, ainsn->insn_arm[0]) ||
 421                 ARM_INSN_MATCH (BX, ainsn->insn_arm[0]) ||
 422                 ARM_INSN_MATCH (BXJ, ainsn->insn_arm[0]))
 423         {
 424                 DBPRINTF ("Bad insn arch_check_insn_arm: %lx\n", ainsn->insn_arm[0]);
 425                 ret = -EFAULT;
 426         }
 427 #ifndef CONFIG_CPU_V7
 428         // check instructions that can write result to PC
 429         else if ((ARM_INSN_MATCH (DPIS, ainsn->insn_arm[0]) ||
 430                                 ARM_INSN_MATCH (DPRS, ainsn->insn_arm[0]) ||
 431                                 ARM_INSN_MATCH (DPI, ainsn->insn_arm[0]) ||
 432                                 ARM_INSN_MATCH (LIO, ainsn->insn_arm[0]) ||
 433                                 ARM_INSN_MATCH (LRO, ainsn->insn_arm[0])) &&
 434                         (ARM_INSN_REG_RD (ainsn->insn_arm[0]) == 15))
 435         {
 436                 DBPRINTF ("Bad arch_check_insn_arm: %lx\n", ainsn->insn_arm[0]);
 437                 ret = -EFAULT;
 438         }
 439 #endif // CONFIG_CPU_V7
 440         // check special instruction loads store multiple registers
 441         else if ((ARM_INSN_MATCH (LM, ainsn->insn_arm[0]) || ARM_INSN_MATCH (SM, ainsn->insn_arm[0])) &&
 442                         // store pc or load to pc
 443                         (ARM_INSN_REG_MR (ainsn->insn_arm[0], 15) ||
 444                          // store/load with pc update
 445                          ((ARM_INSN_REG_RN (ainsn->insn_arm[0]) == 15) && (ainsn->insn_arm[0] & 0x200000))))
 446         {
 447                 DBPRINTF ("Bad insn arch_check_insn_arm: %lx\n", ainsn->insn_arm[0]);
 448                 ret = -EFAULT;
 449         }
 450         return ret;
 451 }
 452
 453 int arch_check_insn_thumb (struct arch_specific_insn *ainsn)
 454 {
 455         int ret = 0;
 456
 457         // check instructions that can change PC
 458         if (    THUMB_INSN_MATCH (UNDEF, ainsn->insn_thumb[0]) ||
 459                 THUMB_INSN_MATCH (SWI, ainsn->insn_thumb[0]) ||
 460                 THUMB_INSN_MATCH (BREAK, ainsn->insn_thumb[0]) ||
 461                 THUMB2_INSN_MATCH (BL, ainsn->insn_thumb[0]) ||
 462                 THUMB_INSN_MATCH (B1, ainsn->insn_thumb[0]) ||
 463                 THUMB_INSN_MATCH (B2, ainsn->insn_thumb[0]) ||
 464                 THUMB2_INSN_MATCH (B1, ainsn->insn_thumb[0]) ||
 465                 THUMB2_INSN_MATCH (B2, ainsn->insn_thumb[0]) ||
 466                 THUMB2_INSN_MATCH (BLX1, ainsn->insn_thumb[0]) ||
 467                 THUMB_INSN_MATCH (BLX2, ainsn->insn_thumb[0]) ||
 468                 THUMB_INSN_MATCH (BX, ainsn->insn_thumb[0]) ||
 469                 THUMB2_INSN_MATCH (BXJ, ainsn->insn_thumb[0]) ||
 470                 (THUMB2_INSN_MATCH (ADR, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RD(ainsn->insn_thumb[0]) == 15) ||
 471                 (THUMB2_INSN_MATCH (LDRW, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RT(ainsn->insn_thumb[0]) == 15) ||
 472                 (THUMB2_INSN_MATCH (LDRW1, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RT(ainsn->insn_thumb[0]) == 15) ||
 473                 (THUMB2_INSN_MATCH (LDRHW, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RT(ainsn->insn_thumb[0]) == 15) ||
 474                 (THUMB2_INSN_MATCH (LDRHW1, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RT(ainsn->insn_thumb[0]) == 15) ||
 475                 (THUMB2_INSN_MATCH (LDRWL, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RT(ainsn->insn_thumb[0]) == 15) ||
 476                 THUMB2_INSN_MATCH (LDMIA, ainsn->insn_thumb[0]) ||
 477                 THUMB2_INSN_MATCH (LDMDB, ainsn->insn_thumb[0]) ||
 478                 (THUMB2_INSN_MATCH (DP, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RD(ainsn->insn_thumb[0]) == 15) ||
 479                 (THUMB2_INSN_MATCH (RSBW, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RD(ainsn->insn_thumb[0]) == 15) ||
 480                 (THUMB2_INSN_MATCH (RORW, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RD(ainsn->insn_thumb[0]) == 15) ||
 481                 (THUMB2_INSN_MATCH (ROR, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RD(ainsn->insn_thumb[0]) == 15) ||
 482                 (THUMB2_INSN_MATCH (LSLW1, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RD(ainsn->insn_thumb[0]) == 15) ||
 483                 (THUMB2_INSN_MATCH (LSLW2, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RD(ainsn->insn_thumb[0]) == 15) ||
 484                 (THUMB2_INSN_MATCH (LSRW1, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RD(ainsn->insn_thumb[0]) == 15) ||
 485                 (THUMB2_INSN_MATCH (LSRW2, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RD(ainsn->insn_thumb[0]) == 15) ||
 486 /* skip PC, #-imm12 -> SP, #-imm8 and Tegra-hanging instructions */
 487                 (THUMB2_INSN_MATCH (STRW1, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RN(ainsn->insn_thumb[0]) == 15) ||
 488                 (THUMB2_INSN_MATCH (STRBW1, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RN(ainsn->insn_thumb[0]) == 15) ||
 489                 (THUMB2_INSN_MATCH (STRHW1, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RN(ainsn->insn_thumb[0]) == 15) ||
 490                 (THUMB2_INSN_MATCH (STRW, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RN(ainsn->insn_thumb[0]) == 15) ||
 491                 (THUMB2_INSN_MATCH (STRHW, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RN(ainsn->insn_thumb[0]) == 15) ||
 492                 (THUMB2_INSN_MATCH (LDRW, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RN(ainsn->insn_thumb[0]) == 15) ||
 493                 (THUMB2_INSN_MATCH (LDRBW, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RN(ainsn->insn_thumb[0]) == 15) ||
 494                 (THUMB2_INSN_MATCH (LDRHW, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RN(ainsn->insn_thumb[0]) == 15) ||
 495 /* skip STRDx/LDRDx Rt, Rt2, [Rd, ...] */
 496                 (THUMB2_INSN_MATCH (LDRD, ainsn->insn_thumb[0]) || THUMB2_INSN_MATCH (LDRD1, ainsn->insn_thumb[0]) || THUMB2_INSN_MATCH (STRD, ainsn->insn_thumb[0])) )
 497         {
 498                 DBPRINTF ("Bad insn arch_check_insn_thumb: %lx\n", ainsn->insn_thumb[0]);
 499                 ret = -EFAULT;
 500         }
 501
 502         return ret;
 503 }
 504
 505 int arch_prepare_kretprobe (struct kretprobe *p)
 506 {
 507         DBPRINTF("Warrning: arch_prepare_kretprobe is not implemented\n");
 508         return 0;
 509 }
 510
 511 int arch_prepare_kprobe (struct kprobe *p)
 512 {
 513         kprobe_opcode_t insns[KPROBES_TRAMP_LEN];
 514         int uregs, pc_dep, ret = 0;
 515     kprobe_opcode_t insn[MAX_INSN_SIZE];
 516     struct arch_specific_insn ainsn;
 517
 518     /* insn: must be on special executable page on i386. */
 519     p->ainsn.insn = get_insn_slot (NULL, 0);
 520     if (!p->ainsn.insn)
 521         return -ENOMEM;
 522
 523     memcpy (insn, p->addr, MAX_INSN_SIZE * sizeof (kprobe_opcode_t));
 524     ainsn.insn_arm = ainsn.insn = insn;
 525     ret = arch_check_insn_arm (&ainsn);
 526     if (!ret)
 527     {
 528         p->opcode = *p->addr;
 529         uregs = pc_dep = 0;
 530
 531         // Rn, Rm ,Rd
 532         if(ARM_INSN_MATCH (DPIS, insn[0]) || ARM_INSN_MATCH (LRO, insn[0]) ||
 533            ARM_INSN_MATCH (SRO, insn[0]))
 534         {
 535             uregs = 0xb;
 536             if( (ARM_INSN_REG_RN (insn[0]) == 15) || (ARM_INSN_REG_RM (insn[0]) == 15) ||
 537                 (ARM_INSN_MATCH (SRO, insn[0]) && (ARM_INSN_REG_RD (insn[0]) == 15)) )
 538             {
 539                 DBPRINTF ("Unboostable insn %lx, DPIS/LRO/SRO\n", insn[0]);
 540                 pc_dep = 1;
 541             }
 542         }
 543         // Rn ,Rd
 544         else if(ARM_INSN_MATCH (DPI, insn[0]) || ARM_INSN_MATCH (LIO, insn[0]) ||
 545                 ARM_INSN_MATCH (SIO, insn[0]))
 546         {
 547             uregs = 0x3;
 548             if ((ARM_INSN_REG_RN (insn[0]) == 15) || (ARM_INSN_MATCH (SIO, insn[0]) &&
 549                         (ARM_INSN_REG_RD (insn[0]) == 15)))
 550             {
 551                 pc_dep = 1;
 552                 DBPRINTF ("Unboostable insn %lx/%p, DPI/LIO/SIO\n", insn[0], p);
 553             }
 554         }
 555         // Rn, Rm, Rs
 556         else if(ARM_INSN_MATCH (DPRS, insn[0]))
 557         {
 558             uregs = 0xd;
 559             if ((ARM_INSN_REG_RN (insn[0]) == 15) || (ARM_INSN_REG_RM (insn[0]) == 15) ||
 560                 (ARM_INSN_REG_RS (insn[0]) == 15))
 561             {
 562                 pc_dep = 1;
 563                 DBPRINTF ("Unboostable insn %lx, DPRS\n", insn[0]);
 564             }
 565         }
 566         // register list
 567         else if(ARM_INSN_MATCH (SM, insn[0]))
 568         {
 569             uregs = 0x10;
 570             if (ARM_INSN_REG_MR (insn[0], 15))
 571             {
 572                 DBPRINTF ("Unboostable insn %lx, SM\n", insn[0]);
 573                 pc_dep = 1;
 574             }
 575         }
 576         // check instructions that can write result to SP andu uses PC
 577         if (pc_dep  && (ARM_INSN_REG_RD (ainsn.insn[0]) == 13))
 578         {
 579             free_insn_slot(&kprobe_insn_pages, NULL, p->ainsn.insn);
 580             ret = -EFAULT;
 581         }
 582         else
 583         {
 584             if (uregs && pc_dep)
 585             {
 586                 memcpy (insns, pc_dep_insn_execbuf, sizeof (insns));
 587                 if (prep_pc_dep_insn_execbuf (insns, insn[0], uregs) != 0)
 588                 {
 589                     DBPRINTF ("failed to prepare exec buffer for insn %lx!", insn[0]);
 590                     free_insn_slot(&kprobe_insn_pages, NULL, p->ainsn.insn);
 591                     return -EINVAL;
 592                 }
 593                 insns[6] = (kprobe_opcode_t) (p->addr + 2);
 594             }
 595             else
 596             {
 597                 memcpy (insns, gen_insn_execbuf, sizeof (insns));
 598                 insns[KPROBES_TRAMP_INSN_IDX] = insn[0];
 599             }
 600             insns[7] = (kprobe_opcode_t) (p->addr + 1);
 601             DBPRINTF ("arch_prepare_kprobe: insn %lx", insn[0]);
 602             DBPRINTF ("arch_prepare_kprobe: to %p - %lx %lx %lx %lx %lx %lx %lx %lx %lx",
 603                     p->ainsn.insn, insns[0], insns[1], insns[2], insns[3], insns[4],
 604                     insns[5], insns[6], insns[7], insns[8]);
 605             memcpy (p->ainsn.insn, insns, sizeof(insns));
 606             flush_icache_range(p->ainsn.insn, p->ainsn.insn + sizeof(insns));
 607 #ifdef BOARD_tegra
 608             flush_cache_all();
 609 #endif
 610         }
 611     }
 612     else
 613     {
 614         free_insn_slot(&kprobe_insn_pages, NULL, p->ainsn.insn);
 615         printk("arch_prepare_kprobe: instruction 0x%x not instrumentation, addr=0x%p\n", insn[0], p->addr);
 616     }
 617
 618     return ret;
 619 }
 620
 621 static unsigned int arch_construct_brunch (unsigned int base, unsigned int addr, int link)
 622 {
 623         kprobe_opcode_t insn;
 624         unsigned int bpi = (unsigned int) base - (unsigned int) addr - 8;
 625
 626         insn = bpi >> 2;
 627         DBPRINTF ("base=%x addr=%x base-addr-8=%x\n", base, addr, bpi);
 628         if (abs (insn & 0xffffff) > 0xffffff)
 629         {
 630                 DBPRINTF ("ERROR: kprobe address out of range\n");
 631                 BUG ();
 632         }
 633         insn = insn & 0xffffff;
 634         insn = insn | ((link != 0) ? 0xeb000000 : 0xea000000);
 635         DBPRINTF ("insn=%lX\n", insn);
 636         return (unsigned int) insn;
 637 }
 638
 639
 640 int arch_copy_trampoline_arm_uprobe (struct kprobe *p, struct task_struct *task, int atomic);
 641 int arch_copy_trampoline_thumb_uprobe (struct kprobe *p, struct task_struct *task, int atomic);
 642
 643 int arch_prepare_uprobe (struct kprobe *p, struct task_struct *task, int atomic)
 644 {
 645         int ret = 0;
 646         kprobe_opcode_t insn[MAX_INSN_SIZE];
 647
 648         if ((unsigned long) p->addr & 0x01)
 649         {
 650                 printk("Error in %s at %d: attempt to register kprobe at an unaligned address\n", __FILE__, __LINE__);
 651                 return -EINVAL;
 652         }
 653         if (!read_proc_vm_atomic (task, (unsigned long) p->addr, &insn, MAX_INSN_SIZE * sizeof(kprobe_opcode_t)))
 654                 panic ("Failed to read memory %p!\n", p->addr);
 655         p->opcode = insn[0];
 656         p->ainsn.insn_arm = get_insn_slot(task, atomic);
 657         if (!p->ainsn.insn_arm) {
 658                 printk("Error in %s at %d: kprobe slot allocation error (arm)\n", __FILE__, __LINE__);
 659                 return -ENOMEM;
 660         }
 661         ret = arch_copy_trampoline_arm_uprobe(p, task, 1);
 662         if (ret) {
 663                 free_insn_slot(&uprobe_insn_pages, task, p->ainsn.insn_arm);
 664                 return -EFAULT;
 665         }
 666         p->ainsn.insn_thumb = get_insn_slot(task, atomic);
 667         if (!p->ainsn.insn_thumb) {
 668                 printk("Error in %s at %d: kprobe slot allocation error (thumb)\n", __FILE__, __LINE__);
 669                 return -ENOMEM;
 670         }
 671         ret = arch_copy_trampoline_thumb_uprobe(p, task, 1);
 672         if (ret) {
 673                 free_insn_slot(&uprobe_insn_pages, task, p->ainsn.insn_arm);
 674                 free_insn_slot(&uprobe_insn_pages, task, p->ainsn.insn_thumb);
 675                 return -EFAULT;
 676         }
 677         if ((p->safe_arm == -1) && (p->safe_thumb == -1)) {
 678                 printk("Error in %s at %d: failed arch_copy_trampoline_*_uprobe() (both)\n", __FILE__, __LINE__);
 679                 if (!write_proc_vm_atomic (task, (unsigned long) p->addr, &p->opcode, sizeof (p->opcode)))
 680                         panic ("Failed to write memory %p!\n", p->addr);
 681                 free_insn_slot(&uprobe_insn_pages, task, p->ainsn.insn_arm);
 682                 free_insn_slot(&uprobe_insn_pages, task, p->ainsn.insn_thumb);
 683                 return -EFAULT;
 684         }
 685         return ret;
 686 }
 687
 688 int arch_prepare_uretprobe (struct kretprobe *p, struct task_struct *task)
 689 {
 690         DBPRINTF("Warrning: arch_prepare_uretprobe is not implemented\n");
 691         return 0;
 692 }
 693
 694 void prepare_singlestep (struct kprobe *p, struct pt_regs *regs)
 695 {
 696         if (p->ss_addr) {
 697                 regs->ARM_pc = (unsigned long)p->ss_addr;
 698                 p->ss_addr = NULL;
 699         } else {
 700                 regs->ARM_pc = (unsigned long)p->ainsn.insn;
 701         }
 702 }
 703
 704 void save_previous_kprobe(struct kprobe_ctlblk *kcb, struct kprobe *p_run)
 705 {
 706         if (p_run == NULL) {
 707                 panic("arm_save_previous_kprobe: p_run == NULL\n");
 708         }
 709
 710         if (kcb->prev_kprobe.kp != NULL) {
 711                 DBPRINTF ("no space to save new probe[]: task = %d/%s", current->pid, current->comm);
 712         }
 713
 714         kcb->prev_kprobe.kp = p_run;
 715         kcb->prev_kprobe.status = kcb->kprobe_status;
 716 }
 717
 718 void restore_previous_kprobe(struct kprobe_ctlblk *kcb)
 719 {
 720         set_current_kprobe(kcb->prev_kprobe.kp, NULL, NULL);
 721         kcb->kprobe_status = kcb->prev_kprobe.status;
 722         kcb->prev_kprobe.kp = NULL;
 723         kcb->prev_kprobe.status = 0;
 724 }
 725
 726 void set_current_kprobe(struct kprobe *p, struct pt_regs *regs, struct kprobe_ctlblk *kcb)
 727 {
 728         __get_cpu_var(current_kprobe) = p;
 729         DBPRINTF ("set_current_kprobe: p=%p addr=%p\n", p, p->addr);
 730 }
 731
 732 int arch_copy_trampoline_arm_uprobe (struct kprobe *p, struct task_struct *task, int atomic)
 733 {
 734         kprobe_opcode_t insns[UPROBES_TRAMP_LEN];
 735         int uregs, pc_dep;
 736         kprobe_opcode_t insn[MAX_INSN_SIZE];
 737         struct arch_specific_insn ainsn;
 738
 739         p->safe_arm = -1;
 740         if ((unsigned long) p->addr & 0x01)
 741         {
 742                 printk("Error in %s at %d: attempt to register kprobe at an unaligned address\n", __FILE__, __LINE__);
 743                 return -EINVAL;
 744         }
 745         insn[0] = p->opcode;
 746         ainsn.insn_arm = insn;
 747         if (!arch_check_insn_arm(&ainsn))
 748         {
 749                 p->safe_arm = 0;
 750         }
 751         uregs = pc_dep = 0;
 752         // Rn, Rm ,Rd
 753         if (ARM_INSN_MATCH (DPIS, insn[0]) || ARM_INSN_MATCH (LRO, insn[0]) ||
 754                         ARM_INSN_MATCH (SRO, insn[0]))
 755         {
 756                 uregs = 0xb;
 757                 if ((ARM_INSN_REG_RN (insn[0]) == 15) || (ARM_INSN_REG_RM (insn[0]) == 15) ||
 758                                 (ARM_INSN_MATCH (SRO, insn[0]) && (ARM_INSN_REG_RD (insn[0]) == 15)))
 759                 {
 760                         DBPRINTF ("Unboostable insn %lx, DPIS/LRO/SRO\n", insn[0]);
 761                         pc_dep = 1;
 762                 }
 763         }
 764         // Rn ,Rd
 765         else if (ARM_INSN_MATCH (DPI, insn[0]) || ARM_INSN_MATCH (LIO, insn[0]) ||
 766                         ARM_INSN_MATCH (SIO, insn[0]))
 767         {
 768                 uregs = 0x3;
 769                 if ((ARM_INSN_REG_RN (insn[0]) == 15) || (ARM_INSN_MATCH (SIO, insn[0]) &&
 770                                 (ARM_INSN_REG_RD (insn[0]) == 15)))
 771                 {
 772                         pc_dep = 1;
 773                         DBPRINTF ("Unboostable insn %lx/%p, DPI/LIO/SIO\n", insn[0], p);
 774                 }
 775         }
 776         // Rn, Rm, Rs
 777         else if (ARM_INSN_MATCH (DPRS, insn[0]))
 778         {
 779                 uregs = 0xd;
 780                 if ((ARM_INSN_REG_RN (insn[0]) == 15) || (ARM_INSN_REG_RM (insn[0]) == 15) ||
 781                                 (ARM_INSN_REG_RS (insn[0]) == 15))
 782                 {
 783                         pc_dep = 1;
 784                         DBPRINTF ("Unboostable insn %lx, DPRS\n", insn[0]);
 785                 }
 786         }
 787         // register list
 788         else if (ARM_INSN_MATCH (SM, insn[0]))
 789         {
 790                 uregs = 0x10;
 791                 if (ARM_INSN_REG_MR (insn[0], 15))
 792                 {
 793                         DBPRINTF ("Unboostable insn %lx, SM\n", insn[0]);
 794                         pc_dep = 1;
 795                 }
 796         }
 797         // check instructions that can write result to SP andu uses PC
 798         if (pc_dep  && (ARM_INSN_REG_RD (ainsn.insn_arm[0]) == 13))
 799         {
 800                 printk("Error in %s at %d: instruction check failed (arm)\n", __FILE__, __LINE__);
 801                 p->safe_arm = -1;
 802                 // TODO: move free to later phase
 803                 //free_insn_slot (&uprobe_insn_pages, task, p->ainsn.insn_arm, 0);
 804                 //ret = -EFAULT;
 805         }
 806         if (unlikely(uregs && pc_dep))
 807         {
 808                 memcpy (insns, pc_dep_insn_execbuf, sizeof (insns));
 809                 if (prep_pc_dep_insn_execbuf (insns, insn[0], uregs) != 0)
 810                 {
 811                         printk("Error in %s at %d: failed to prepare exec buffer for insn %lx!",
 812                                 insn[0], __FILE__, __LINE__);
 813                         p->safe_arm = -1;
 814                         // TODO: move free to later phase
 815                         //free_insn_slot (&uprobe_insn_pages, task, p->ainsn.insn_arm, 0);
 816                         //return -EINVAL;
 817                 }
 818                 //insns[UPROBES_TRAMP_SS_BREAK_IDX] = BREAKPOINT_INSTRUCTION;
 819                 insns[6] = (kprobe_opcode_t) (p->addr + 2);
 820         }
 821         else
 822         {
 823                 memcpy (insns, gen_insn_execbuf, sizeof (insns));
 824                 insns[UPROBES_TRAMP_INSN_IDX] = insn[0];
 825         }
 826         insns[UPROBES_TRAMP_RET_BREAK_IDX] = BREAKPOINT_INSTRUCTION;
 827         insns[7] = (kprobe_opcode_t) (p->addr + 1);
 828
 829         // B
 830         if(ARM_INSN_MATCH (B, ainsn.insn_arm[0]))
 831         {
 832                 memcpy (insns, pc_dep_insn_execbuf, sizeof (insns));
 833                 insns[UPROBES_TRAMP_RET_BREAK_IDX] = BREAKPOINT_INSTRUCTION;
 834                 insns[6] = (kprobe_opcode_t) (p->addr + 2);
 835                 insns[7] = get_addr_b(p->opcode, p->addr);
 836         }
 837
 838         DBPRINTF ("arch_prepare_uprobe: to %p - %lx %lx %lx %lx %lx %lx %lx %lx %lx",
 839                         p->ainsn.insn_arm, insns[0], insns[1], insns[2], insns[3], insns[4],
 840                         insns[5], insns[6], insns[7], insns[8]);
 841         if (!write_proc_vm_atomic (task, (unsigned long) p->ainsn.insn_arm, insns, sizeof (insns)))
 842         {
 843                 panic("failed to write memory %p!\n", p->ainsn.insn);
 844                 // Mr_Nobody: we have to panic, really??...
 845                 //free_insn_slot (&uprobe_insn_pages, task, p->ainsn.insn_arm, 0);
 846                 //return -EINVAL;
 847         }
 848         return 0;
 849 }
 850
 851 int arch_copy_trampoline_thumb_uprobe (struct kprobe *p, struct task_struct *task, int atomic)
 852 {
 853         int uregs, pc_dep;
 854         unsigned int addr;
 855         kprobe_opcode_t insn[MAX_INSN_SIZE];
 856         struct arch_specific_insn ainsn;
 857         kprobe_opcode_t insns[UPROBES_TRAMP_LEN * 2];
 858
 859         p->safe_thumb = -1;
 860         if ((unsigned long) p->addr & 0x01)
 861         {
 862                 printk("Error in %s at %d: attempt to register kprobe at an unaligned address\n", __FILE__, __LINE__);
 863                 return -EINVAL;
 864         }
 865         insn[0] = p->opcode;
 866         ainsn.insn_thumb = insn;
 867         if (!arch_check_insn_thumb(&ainsn))
 868         {
 869                 p->safe_thumb = 0;
 870         }
 871         uregs = 0;
 872         pc_dep = 0;
 873         if (THUMB_INSN_MATCH (APC, insn[0]) || THUMB_INSN_MATCH (LRO3, insn[0]))
 874         {
 875                 uregs = 0x0700;         // 8-10
 876                 pc_dep = 1;
 877         }
 878         else if (THUMB_INSN_MATCH (MOV3, insn[0]) && (((((unsigned char) insn[0]) & 0xff) >> 3) == 15))
 879         {
 880                 // MOV Rd, PC
 881                 uregs = 0x07;
 882                 pc_dep = 1;
 883         }
 884         else if THUMB2_INSN_MATCH (ADR, insn[0])
 885         {
 886                 uregs = 0x0f00;         // Rd 8-11
 887                 pc_dep = 1;
 888         }
 889         else if (((THUMB2_INSN_MATCH (LDRW, insn[0]) || THUMB2_INSN_MATCH (LDRW1, insn[0])  ||
 890                         THUMB2_INSN_MATCH (LDRBW, insn[0]) || THUMB2_INSN_MATCH (LDRBW1, insn[0]) ||
 891                         THUMB2_INSN_MATCH (LDRHW, insn[0]) || THUMB2_INSN_MATCH (LDRHW1, insn[0]) ||
 892                         THUMB2_INSN_MATCH (LDRWL, insn[0])) && THUMB2_INSN_REG_RN(insn[0]) == 15) ||
 893                         THUMB2_INSN_MATCH (LDREX, insn[0]) ||
 894                         ((THUMB2_INSN_MATCH (STRW, insn[0]) || THUMB2_INSN_MATCH (STRBW, insn[0]) ||
 895                                 THUMB2_INSN_MATCH (STRHW, insn[0]) || THUMB2_INSN_MATCH (STRHW1, insn[0])) &&
 896                                 (THUMB2_INSN_REG_RN(insn[0]) == 15 || THUMB2_INSN_REG_RT(insn[0]) == 15)) ||
 897                         ((THUMB2_INSN_MATCH (STRT, insn[0]) || THUMB2_INSN_MATCH (STRHT, insn[0])) &&
 898                                 (THUMB2_INSN_REG_RN(insn[0]) == 15 || THUMB2_INSN_REG_RT(insn[0]) == 15)) )
 899         {
 900                 uregs = 0xf000;         // Rt 12-15
 901                 pc_dep = 1;
 902         }
 903         else if ((THUMB2_INSN_MATCH (LDRD, insn[0]) || THUMB2_INSN_MATCH (LDRD1, insn[0])) && (THUMB2_INSN_REG_RN(insn[0]) == 15))
 904         {
 905                 uregs = 0xff00;         // Rt 12-15, Rt2 8-11
 906                 pc_dep = 1;
 907         }
 908         else if (THUMB2_INSN_MATCH (MUL, insn[0]) && THUMB2_INSN_REG_RM(insn[0]) == 15)
 909         {
 910                 uregs = 0xf;
 911                 pc_dep = 1;
 912         }
 913         else if (THUMB2_INSN_MATCH (DP, insn[0]) && (THUMB2_INSN_REG_RN(insn[0]) == 15 || THUMB2_INSN_REG_RM(insn[0]) == 15))
 914         {
 915                 uregs = 0xf000; // Rd 12-15
 916                 pc_dep = 1;
 917         }
 918         else if (THUMB2_INSN_MATCH (STRD, insn[0]) && (THUMB2_INSN_REG_RN(insn[0] == 15) || THUMB2_INSN_REG_RT(insn[0] == 15) || THUMB2_INSN_REG_RT2(insn[0]) == 15))
 919         {
 920                 uregs = 0xff00;         // Rt 12-15, Rt2 8-11
 921                 pc_dep = 1;
 922         }
 923         else if (THUMB2_INSN_MATCH (RSBW, insn[0]) && THUMB2_INSN_REG_RN(insn[0]) == 15)
 924         {
 925                 uregs = 0x0f00; // Rd 8-11
 926                 pc_dep = 1;
 927         }
 928         else if (THUMB2_INSN_MATCH (RORW, insn[0]) && (THUMB2_INSN_REG_RN(insn[0]) == 15 || THUMB2_INSN_REG_RM(insn[0]) == 15))
 929         {
 930                 uregs = 0x0f00;
 931                 pc_dep = 1;
 932         }
 933         else if ((THUMB2_INSN_MATCH (ROR, insn[0]) || THUMB2_INSN_MATCH(LSLW2, insn[0]) || THUMB2_INSN_MATCH(LSRW2, insn[0])) && THUMB2_INSN_REG_RM(insn[0]) == 15)
 934         {
 935                 uregs = 0x0f00; // Rd 8-11
 936                 pc_dep = 1;
 937         }
 938         else if ((THUMB2_INSN_MATCH (LSLW1, insn[0]) || THUMB2_INSN_MATCH (LSRW1, insn[0])) && (THUMB2_INSN_REG_RN(insn[0]) == 15 || THUMB2_INSN_REG_RM(insn[0]) == 15))
 939         {
 940                 uregs = 0x0f00; // Rd 8-11
 941                 pc_dep = 1;
 942         }
 943         else if ((THUMB2_INSN_MATCH (TEQ1, insn[0]) || THUMB2_INSN_MATCH (TST1, insn[0])) && THUMB2_INSN_REG_RN(insn[0]) == 15)
 944         {
 945                 uregs = 0xf0000;        //Rn 0-3 (16-19)
 946                 pc_dep = 1;
 947         }
 948         else if ((THUMB2_INSN_MATCH (TEQ2, insn[0]) || THUMB2_INSN_MATCH (TST2, insn[0])) &&
 949                 (THUMB2_INSN_REG_RN(insn[0]) == 15 || THUMB2_INSN_REG_RM(insn[0]) == 15))
 950         {
 951                 uregs = 0xf0000;        //Rn 0-3 (16-19)
 952                 pc_dep = 1;
 953         }
 954         if (unlikely(uregs && pc_dep))
 955         {
 956                 memcpy (insns, pc_dep_insn_execbuf_thumb, 18 * 2);
 957                 if (prep_pc_dep_insn_execbuf_thumb (insns, insn[0], uregs) != 0)
 958                 {
 959                         printk("Error in %s at %d: failed to prepare exec buffer for insn %lx!",
 960                                 insn[0], __FILE__, __LINE__);
 961                         p->safe_thumb = -1;
 962                         //free_insn_slot (&uprobe_insn_pages, task, p->ainsn.insn_thumb, 0);
 963                         //return -EINVAL;
 964                 }
 965                 addr = ((unsigned int)p->addr) + 4;
 966                 *((unsigned short*)insns + 13) = 0xdeff;
 967                 *((unsigned short*)insns + 14) = addr & 0x0000ffff;
 968                 *((unsigned short*)insns + 15) = addr >> 16;
 969                 if (!isThumb2(insn[0]))
 970                 {
 971                         addr = ((unsigned int)p->addr) + 2;
 972                         *((unsigned short*)insns + 16) = addr & 0x0000ffff | 0x1;
 973                         *((unsigned short*)insns + 17) = addr >> 16;
 974                 }
 975                 else {
 976                         addr = ((unsigned int)p->addr) + 4;
 977                         *((unsigned short*)insns + 16) = addr & 0x0000ffff | 0x1;
 978                         *((unsigned short*)insns + 17) = addr >> 16;
 979                 }
 980         }
 981         else {
 982                 memcpy (insns, gen_insn_execbuf_thumb, 18 * 2);
 983                 *((unsigned short*)insns + 13) = 0xdeff;
 984                 if (!isThumb2(insn[0]))
 985                 {
 986                         addr = ((unsigned int)p->addr) + 2;
 987                         *((unsigned short*)insns + 2) = insn[0];
 988                         *((unsigned short*)insns + 16) = addr & 0x0000ffff | 0x1;
 989                         *((unsigned short*)insns + 17) = addr >> 16;
 990                 }
 991                 else {
 992                         addr = ((unsigned int)p->addr) + 4;
 993                         insns[1] = insn[0];
 994                         *((unsigned short*)insns + 16) = addr & 0x0000ffff | 0x1;
 995                         *((unsigned short*)insns + 17) = addr >> 16;
 996                 }
 997         }
 998         if (!write_proc_vm_atomic (task, (unsigned long) p->ainsn.insn_thumb, insns, 18 * 2))
 999         {
1000                 panic("failed to write memory %p!\n", p->ainsn.insn_thumb);
1001                 // Mr_Nobody: we have to panic, really??...
1002                 //free_insn_slot (&uprobe_insn_pages, task, p->ainsn.insn_thumb, 0);
1003                 //return -EINVAL;
1004         }
1005         return 0;
1006 }
1007
1008 static int check_validity_insn(struct kprobe *p, struct pt_regs *regs, struct task_struct *task)
1009 {
1010         struct kprobe *kp;
1011
1012         if (unlikely(thumb_mode(regs))) {
1013                 if (p->safe_thumb != -1) {
1014                         p->ainsn.insn = p->ainsn.insn_thumb;
1015                         list_for_each_entry_rcu(kp, &p->list, list) {
1016                                 kp->ainsn.insn = p->ainsn.insn_thumb;
1017                         }
1018                 } else {
1019                         printk("Error in %s at %d: we are in thumb mode (!) and check instruction was fail \
1020                                 (%0X instruction at %p address)!\n", __FILE__, __LINE__, p->opcode, p->addr);
1021                         // Test case when we do our actions on already running application
1022                         arch_disarm_uprobe(p, task);
1023                         return -1;
1024                 }
1025         } else {
1026                 if (p->safe_arm != -1) {
1027                         p->ainsn.insn = p->ainsn.insn_arm;
1028                         list_for_each_entry_rcu(kp, &p->list, list) {
1029                                 kp->ainsn.insn = p->ainsn.insn_arm;
1030                         }
1031                 } else {
1032                         printk("Error in %s at %d: we are in arm mode (!) and check instruction was fail \
1033                                 (%0X instruction at %p address)!\n", __FILE__, __LINE__, p->opcode, p->addr );
1034                         // Test case when we do our actions on already running application
1035                         arch_disarm_uprobe(p, task);
1036                         return -1;
1037                 }
1038         }
1039
1040         return 0;
1041 }
1042
1043 int kprobe_handler(struct pt_regs *regs)
1044 {
1045         int err_out = 0;
1046         char *msg_out = NULL;
1047         unsigned long user_m = user_mode(regs);
1048         pid_t tgid = (user_m) ? current->tgid : 0;
1049         kprobe_opcode_t *addr = (kprobe_opcode_t *) (regs->ARM_pc);
1050
1051         struct kprobe *p = NULL, *p_run = NULL;
1052         int ret = 0, retprobe = 0, reenter = 0;
1053         kprobe_opcode_t *ssaddr = 0;
1054         struct kprobe_ctlblk *kcb;
1055         int i = 0;
1056
1057 #ifdef SUPRESS_BUG_MESSAGES
1058         int swap_oops_in_progress;
1059         // oops_in_progress used to avoid BUG() messages that slow down kprobe_handler() execution
1060         swap_oops_in_progress = oops_in_progress;
1061         oops_in_progress = 1;
1062 #endif
1063 #ifdef OVERHEAD_DEBUG
1064         struct timeval swap_tv1;
1065         struct timeval swap_tv2;
1066 #define USEC_IN_SEC_NUM                         1000000
1067         do_gettimeofday(&swap_tv1);
1068 #endif
1069         preempt_disable();
1070
1071         p = get_kprobe(addr, tgid);
1072
1073         if (user_m && p && (check_validity_insn(p, regs, current) != 0)) {
1074                 goto no_kprobe_live;
1075         }
1076
1077         /* We're in an interrupt, but this is clear and BUG()-safe. */
1078         kcb = get_kprobe_ctlblk ();
1079
1080         /* Check we're not actually recursing */
1081         // TODO: event is not saving in trace
1082         p_run = kprobe_running();
1083         if (p_run)
1084         {
1085                 DBPRINTF("lock???");
1086                 if (p)
1087                 {
1088                         if (!tgid && (addr == (kprobe_opcode_t *)kretprobe_trampoline)) {
1089                                 save_previous_kprobe(kcb, p_run);
1090                                 kcb->kprobe_status = KPROBE_REENTER;
1091                                 reenter = 1;
1092                         } else {
1093                                 /* We have reentered the kprobe_handler(), since
1094                                  * another probe was hit while within the handler.
1095                                  * We here save the original kprobes variables and
1096                                  * just single step on the instruction of the new probe
1097                                  * without calling any user handlers.
1098                                  */
1099                                 kprobes_inc_nmissed_count (p);
1100                                 prepare_singlestep (p, regs);
1101
1102                                 err_out = 0;
1103                                 goto out;
1104                         }
1105                 } else {
1106                         if(tgid) { //we can reenter probe upon uretprobe exception
1107                                 DBPRINTF ("check for UNDEF_INSTRUCTION %p\n", addr);
1108                                 // UNDEF_INSTRUCTION from user space
1109
1110                                 p = get_kprobe_by_insn_slot(addr, tgid, regs);
1111                                 if (p) {
1112                                         save_previous_kprobe(kcb, p_run);
1113                                         kcb->kprobe_status = KPROBE_REENTER;
1114                                         reenter = 1;
1115                                         retprobe = 1;
1116                                         DBPRINTF ("uretprobe %p\n", addr);
1117                                 }
1118                         }
1119                         if(!p) {
1120                                 p = p_run;
1121                                 DBPRINTF ("kprobe_running !!! p = 0x%p p->break_handler = 0x%p", p, p->break_handler);
1122                                 /*if (p->break_handler && p->break_handler(p, regs)) {
1123                                   DBPRINTF("kprobe_running !!! goto ss");
1124                                   goto ss_probe;
1125                                   } */
1126                                 DBPRINTF ("unknown uprobe at %p cur at %p/%p\n", addr, p->addr, p->ainsn.insn);
1127                                 if (tgid)
1128                                         ssaddr = p->ainsn.insn + UPROBES_TRAMP_SS_BREAK_IDX;
1129                                 else
1130                                         ssaddr = p->ainsn.insn + KPROBES_TRAMP_SS_BREAK_IDX;
1131                                 if (addr == ssaddr) {
1132                                         regs->ARM_pc = (unsigned long) (p->addr + 1);
1133                                         DBPRINTF ("finish step at %p cur at %p/%p, redirect to %lx\n", addr, p->addr, p->ainsn.insn, regs->ARM_pc);
1134                                         if (kcb->kprobe_status == KPROBE_REENTER) {
1135                                                 restore_previous_kprobe(kcb);
1136                                         } else {
1137                                                 reset_current_kprobe();
1138                                         }
1139                                 }
1140                                 DBPRINTF ("kprobe_running !!! goto no");
1141                                 ret = 1;
1142                                 /* If it's not ours, can't be delete race, (we hold lock). */
1143                                 DBPRINTF ("no_kprobe");
1144                                 goto no_kprobe;
1145                         }
1146                 }
1147         }
1148
1149         if (!p) {
1150                 if (tgid) {
1151                         DBPRINTF ("search UNDEF_INSTRUCTION %p\n", addr);
1152                         // UNDEF_INSTRUCTION from user space
1153
1154                         p = get_kprobe_by_insn_slot(addr, tgid, regs);
1155                         if (!p) {
1156                                 /* Not one of ours: let kernel handle it */
1157                                 DBPRINTF ("no_kprobe");
1158                                 goto no_kprobe;
1159                         }
1160                         retprobe = 1;
1161                         DBPRINTF ("uretprobe %p\n", addr);
1162                 } else {
1163                         /* Not one of ours: let kernel handle it */
1164                         DBPRINTF ("no_kprobe");
1165                         goto no_kprobe;
1166                 }
1167         }
1168         // restore opcode for thumb app
1169         if (user_mode( regs ) && thumb_mode( regs )) {
1170                 if (!isThumb2(p->opcode)) {
1171                         unsigned long tmp = p->opcode >> 16;
1172                         write_proc_vm_atomic(current, (unsigned long)((unsigned short*)p->addr + 1), &tmp, 2);
1173                 } else {
1174                         unsigned long tmp = p->opcode;
1175                         write_proc_vm_atomic(current, (unsigned long)((unsigned short*)p->addr), &tmp, 4);
1176                 }
1177                 flush_icache_range ((unsigned int) p->addr, (unsigned int) (((unsigned int) p->addr) + (sizeof (kprobe_opcode_t) * 2)));
1178         }
1179         set_current_kprobe(p, NULL, NULL);
1180         if(!reenter)
1181                 kcb->kprobe_status = KPROBE_HIT_ACTIVE;
1182         if (retprobe) {         //(einsn == UNDEF_INSTRUCTION)
1183                 ret = trampoline_probe_handler (p, regs);
1184         } else if (p->pre_handler) {
1185                 ret = p->pre_handler (p, regs);
1186                 if(p->pre_handler != trampoline_probe_handler) {
1187                         reset_current_kprobe();
1188                 }
1189         }
1190
1191         if (ret) {
1192                 /* handler has already set things up, so skip ss setup */
1193                 err_out = 0;
1194                 goto out;
1195         }
1196
1197 no_kprobe:
1198         msg_out = "no_kprobe\n";
1199         err_out = 1;            // return with death
1200         goto out;
1201
1202 no_kprobe_live:
1203         msg_out = "no_kprobe live\n";
1204         err_out = 0;            // ok - life is life
1205         goto out;
1206
1207 out:
1208         preempt_enable_no_resched();
1209 #ifdef OVERHEAD_DEBUG
1210         do_gettimeofday(&swap_tv2);
1211         swap_sum_hit++;
1212         swap_sum_time += ((swap_tv2.tv_sec - swap_tv1.tv_sec) *  USEC_IN_SEC_NUM +
1213                 (swap_tv2.tv_usec - swap_tv1.tv_usec));
1214 #endif
1215 #ifdef SUPRESS_BUG_MESSAGES
1216         oops_in_progress = swap_oops_in_progress;
1217 #endif
1218
1219         if(msg_out) {
1220                 printk(msg_out);
1221         }
1222
1223         return err_out;
1224 }
1225
1226 int setjmp_pre_handler (struct kprobe *p, struct pt_regs *regs)
1227 {
1228         struct jprobe *jp = container_of (p, struct jprobe, kp);
1229         kprobe_pre_entry_handler_t pre_entry;
1230         entry_point_t entry;
1231
1232 # ifdef REENTER
1233 //      p = kprobe_running(regs);
1234 # endif
1235
1236         DBPRINTF ("pjp = 0x%p jp->entry = 0x%p", jp, jp->entry);
1237         entry = (entry_point_t) jp->entry;
1238         pre_entry = (kprobe_pre_entry_handler_t) jp->pre_entry;
1239         //if(!entry)
1240         //      DIE("entry NULL", regs)
1241         DBPRINTF ("entry = 0x%p jp->entry = 0x%p", entry, jp->entry);
1242
1243         //call handler for all kernel probes and user space ones which belong to current tgid
1244         if (!p->tgid || (p->tgid == current->tgid))
1245         {
1246                 if(!p->tgid && ((unsigned int)p->addr == sched_addr) && sched_rp) {
1247                     patch_suspended_all_task_ret_addr(sched_rp);
1248                 }
1249                 if (pre_entry)
1250                         p->ss_addr = (void *)pre_entry (jp->priv_arg, regs);
1251                 if (entry){
1252                         entry (regs->ARM_r0, regs->ARM_r1, regs->ARM_r2, regs->ARM_r3, regs->ARM_r4, regs->ARM_r5);
1253                 }
1254                 else {
1255                         if (p->tgid)
1256                                 dbi_arch_uprobe_return ();
1257                         else
1258                                 dbi_jprobe_return ();
1259                 }
1260         }
1261         else if (p->tgid)
1262                 dbi_arch_uprobe_return ();
1263
1264         prepare_singlestep (p, regs);
1265
1266         return 1;
1267 }
1268
1269 void dbi_jprobe_return (void)
1270 {
1271 }
1272
1273 void dbi_arch_uprobe_return (void)
1274 {
1275 }
1276
1277 int longjmp_break_handler (struct kprobe *p, struct pt_regs *regs)
1278 {
1279 # ifndef REENTER
1280         //kprobe_opcode_t insn = BREAKPOINT_INSTRUCTION;
1281         kprobe_opcode_t insns[2];
1282
1283         if (p->pid)
1284         {
1285                 insns[0] = BREAKPOINT_INSTRUCTION;
1286                 insns[1] = p->opcode;
1287                 //p->opcode = *p->addr;
1288                 if (read_proc_vm_atomic (current, (unsigned long) (p->addr), &(p->opcode), sizeof (p->opcode)) < sizeof (p->opcode))
1289                 {
1290                         printk ("ERROR[%lu]: failed to read vm of proc %s/%u addr %p.", nCount, current->comm, current->pid, p->addr);
1291                         return -1;
1292                 }
1293                 //*p->addr = BREAKPOINT_INSTRUCTION;
1294                 //*(p->addr+1) = p->opcode;
1295                 if (write_proc_vm_atomic (current, (unsigned long) (p->addr), insns, sizeof (insns)) < sizeof (insns))
1296                 {
1297                         printk ("ERROR[%lu]: failed to write vm of proc %s/%u addr %p.", nCount, current->comm, current->pid, p->addr);
1298                         return -1;
1299                 }
1300         }
1301         else
1302         {
1303                 DBPRINTF ("p->opcode = 0x%lx *p->addr = 0x%lx p->addr = 0x%p\n", p->opcode, *p->addr, p->addr);
1304                 *(p->addr + 1) = p->opcode;
1305                 p->opcode = *p->addr;
1306                 *p->addr = BREAKPOINT_INSTRUCTION;
1307
1308                 flush_icache_range ((unsigned int) p->addr, (unsigned int) (((unsigned int) p->addr) + (sizeof (kprobe_opcode_t) * 2)));
1309         }
1310
1311         reset_current_kprobe();
1312
1313 #endif //REENTER
1314
1315         return 0;
1316 }
1317
1318
1319 void arch_arm_kprobe (struct kprobe *p)
1320 {
1321         *p->addr = BREAKPOINT_INSTRUCTION;
1322         flush_icache_range ((unsigned long) p->addr, (unsigned long) p->addr + sizeof (kprobe_opcode_t));
1323 }
1324
1325 void arch_disarm_kprobe (struct kprobe *p)
1326 {
1327         *p->addr = p->opcode;
1328         flush_icache_range ((unsigned long) p->addr, (unsigned long) p->addr + sizeof (kprobe_opcode_t));
1329 }
1330
1331
1332 int trampoline_probe_handler (struct kprobe *p, struct pt_regs *regs)
1333 {
1334         struct kretprobe_instance *ri = NULL;
1335         struct hlist_head *head;
1336         struct hlist_node *node, *tmp;
1337         unsigned long flags, orig_ret_address = 0;
1338         unsigned long trampoline_address = (unsigned long) &kretprobe_trampoline;
1339
1340         struct kretprobe *crp = NULL;
1341         struct kprobe_ctlblk *kcb = get_kprobe_ctlblk ();
1342
1343         DBPRINTF ("start");
1344
1345         if (p && p->tgid){
1346                 // in case of user space retprobe trampoline is at the Nth instruction of US tramp
1347                 if (!thumb_mode( regs ))
1348                         trampoline_address = (unsigned long)(p->ainsn.insn + UPROBES_TRAMP_RET_BREAK_IDX);
1349                 else
1350                         trampoline_address = (unsigned long)(p->ainsn.insn) + 0x1b;
1351         }
1352
1353         spin_lock_irqsave (&kretprobe_lock, flags);
1354
1355         /*
1356          * We are using different hash keys (current and mm) for finding kernel
1357          * space and user space probes.  Kernel space probes can change mm field in
1358          * task_struct.  User space probes can be shared between threads of one
1359          * process so they have different current but same mm.
1360          */
1361         if (p && p->tgid) {
1362                 head = kretprobe_inst_table_head(current->mm);
1363         } else {
1364                 head = kretprobe_inst_table_head(current);
1365         }
1366
1367         /*
1368          * It is possible to have multiple instances associated with a given
1369          * task either because an multiple functions in the call path
1370          * have a return probe installed on them, and/or more then one
1371          * return probe was registered for a target function.
1372          *
1373          * We can handle this because:
1374          *     - instances are always inserted at the head of the list
1375          *     - when multiple return probes are registered for the same
1376          *       function, the first instance's ret_addr will point to the
1377          *       real return address, and all the rest will point to
1378          *       kretprobe_trampoline
1379          */
1380         hlist_for_each_entry_safe (ri, node, tmp, head, hlist)
1381         {
1382                 if (ri->task != current)
1383                         /* another task is sharing our hash bucket */
1384                         continue;
1385                 if (ri->rp && ri->rp->handler){
1386                         ri->rp->handler (ri, regs, ri->rp->priv_arg);
1387                 }
1388
1389                 orig_ret_address = (unsigned long) ri->ret_addr;
1390                 recycle_rp_inst (ri);
1391                 if (orig_ret_address != trampoline_address)
1392                         /*
1393                          * This is the real return address. Any other
1394                          * instances associated with this task are for
1395                          * other calls deeper on the call stack
1396                          */
1397                         break;
1398         }
1399         kretprobe_assert (ri, orig_ret_address, trampoline_address);
1400         //BUG_ON(!orig_ret_address || (orig_ret_address == trampoline_address));
1401         //E.G. Check this code in case of __switch_to function instrumentation -- currently this code generates dump in this case
1402         //if (trampoline_address != (unsigned long) &kretprobe_trampoline){
1403         //if (ri->rp2) BUG_ON (ri->rp2->kp.tgid == 0);
1404         //if (ri->rp) BUG_ON (ri->rp->kp.tgid == 0);
1405         //else if (ri->rp2) BUG_ON (ri->rp2->kp.tgid == 0);
1406         //}
1407         if ((ri->rp && ri->rp->kp.tgid) || (ri->rp2 && ri->rp2->kp.tgid))
1408                 BUG_ON (trampoline_address == (unsigned long) &kretprobe_trampoline);
1409
1410         regs->uregs[14] = orig_ret_address;
1411         DBPRINTF ("regs->uregs[14] = 0x%lx\n", regs->uregs[14]);
1412         DBPRINTF ("regs->uregs[15] = 0x%lx\n", regs->uregs[15]);
1413
1414         if (trampoline_address != (unsigned long) &kretprobe_trampoline)
1415         {
1416                 regs->uregs[15] = orig_ret_address;
1417         }else{
1418                 if (!thumb_mode( regs )) regs->uregs[15] += 4;
1419                 else regs->uregs[15] += 2;
1420         }
1421
1422         DBPRINTF ("regs->uregs[15] = 0x%lx\n", regs->uregs[15]);
1423
1424         if(p){ // ARM, MIPS, X86 user space
1425                 if (thumb_mode( regs ) && !(regs->uregs[14] & 0x01))
1426                 {
1427                         regs->ARM_cpsr &= 0xFFFFFFDF;
1428                 }else{
1429                         if (user_mode( regs ) && (regs->uregs[14] & 0x01))
1430                         {
1431                                 regs->ARM_cpsr |= 0x20;
1432                         }
1433                 }
1434
1435                 //TODO: test - enter function, delete us retprobe, exit function
1436                 // for user space retprobes only - deferred deletion
1437
1438                 if (trampoline_address != (unsigned long) &kretprobe_trampoline)
1439                 {
1440                         // if we are not at the end of the list and current retprobe should be disarmed
1441                         if (node && ri->rp2)
1442                         {
1443                                 struct hlist_node *current_node = node;
1444                                 crp = ri->rp2;
1445                                 /*sprintf(die_msg, "deferred disarm p->addr = %p [%lx %lx %lx]\n",
1446                                   crp->kp.addr, *kaddrs[0], *kaddrs[1], *kaddrs[2]);
1447                                   DIE(die_msg, regs); */
1448                                 // look for other instances for the same retprobe
1449                                 hlist_for_each_entry_safe (ri, node, tmp, head, hlist)
1450                                 {
1451                                         /*
1452                                          * Trying to find another retprobe instance associated with
1453                                          * the same retprobe.
1454                                          */
1455                                         if (ri->rp2 == crp && node != current_node)
1456                                                 break;
1457                                 }
1458
1459                                 if (!node)
1460                                 {       // if there are no more instances for this retprobe
1461                                         // delete retprobe
1462                                         DBPRINTF ("defered retprobe deletion p->addr = %p", crp->kp.addr);
1463                                         /*
1464                                           If there is no any retprobe instances of this retprobe
1465                                           we can free the resources related to the probe.
1466                                          */
1467                                         struct kprobe *is_p = &crp->kp;
1468                                         if (!(hlist_unhashed(&is_p->is_hlist_arm))) {
1469                                                 hlist_del_rcu(&is_p->is_hlist_arm);
1470                                         }
1471                                         if (!(hlist_unhashed(&is_p->is_hlist_thumb))) {
1472                                                 hlist_del_rcu(&is_p->is_hlist_thumb);
1473                                         }
1474                                         unregister_uprobe (&crp->kp, current, 1);
1475                                         kfree (crp);
1476                                 }
1477                                 hlist_del(current_node);
1478                         }
1479                 }
1480
1481                 if (kcb->kprobe_status == KPROBE_REENTER) {
1482                         restore_previous_kprobe(kcb);
1483                 } else {
1484                         reset_current_kprobe();
1485                 }
1486         }
1487
1488         spin_unlock_irqrestore (&kretprobe_lock, flags);
1489
1490         /*
1491          * By returning a non-zero value, we are telling
1492          * kprobe_handler() that we don't want the post_handler
1493          * to run (and have re-enabled preemption)
1494          */
1495
1496         return 1;
1497 }
1498
1499 void  __arch_prepare_kretprobe (struct kretprobe *rp, struct pt_regs *regs)
1500 {
1501         struct kretprobe_instance *ri;
1502
1503         DBPRINTF ("start\n");
1504         //TODO: test - remove retprobe after func entry but before its exit
1505         if ((ri = get_free_rp_inst (rp)) != NULL)
1506         {
1507                 ri->rp = rp;
1508                 ri->rp2 = NULL;
1509                 ri->task = current;
1510                 ri->ret_addr = (kprobe_opcode_t *) regs->uregs[14];
1511
1512                 if (rp->kp.tgid)
1513                         if (!thumb_mode( regs ))
1514                                 regs->uregs[14] = (unsigned long) (rp->kp.ainsn.insn + UPROBES_TRAMP_RET_BREAK_IDX);
1515                         else
1516                                 regs->uregs[14] = (unsigned long) (rp->kp.ainsn.insn) + 0x1b;
1517
1518                 else    /* Replace the return addr with trampoline addr */
1519                         regs->uregs[14] = (unsigned long) &kretprobe_trampoline;
1520
1521 //              DBPRINTF ("ret addr set to %p->%lx\n", ri->ret_addr, regs->uregs[14]);
1522                 add_rp_inst (ri);
1523         }
1524         else {
1525                 DBPRINTF ("WARNING: missed retprobe %p\n", rp->kp.addr);
1526                 rp->nmissed++;
1527         }
1528 }
1529
1530
1531 int asm_init_module_dependencies()
1532 {
1533         //No module dependencies
1534         return 0;
1535 }
1536
1537
1538 void (* do_kpro)(struct undef_hook *);
1539 void (* undo_kpro)(struct undef_hook *);
1540
1541 // kernel probes hook
1542 struct undef_hook undef_ho_k = {
1543     .instr_mask = 0xffffffff,
1544     .instr_val  = BREAKPOINT_INSTRUCTION,
1545     .cpsr_mask  = MODE_MASK,
1546     .cpsr_val   = SVC_MODE,
1547     .fn         = kprobe_handler,
1548 };
1549
1550 // userspace probes hook (arm)
1551 struct undef_hook undef_ho_u = {
1552     .instr_mask = 0xffffffff,
1553     .instr_val  = BREAKPOINT_INSTRUCTION,
1554     .cpsr_mask  = MODE_MASK,
1555     .cpsr_val   = USR_MODE,
1556     .fn         = kprobe_handler,
1557 };
1558
1559 // userspace probes hook (thumb)
1560 struct undef_hook undef_ho_u_t = {
1561     .instr_mask = 0xffffffff,
1562     .instr_val  = BREAKPOINT_INSTRUCTION & 0x0000ffff,
1563     .cpsr_mask  = MODE_MASK,
1564     .cpsr_val   = USR_MODE,
1565     .fn         = kprobe_handler,
1566 };
1567
1568 int __init arch_init_kprobes (void)
1569 {
1570         unsigned int do_bp_handler = 0;
1571         int ret = 0;
1572
1573         if (arch_init_module_dependencies())
1574         {
1575                 DBPRINTF ("Unable to init module dependencies\n");
1576                 return -1;
1577         }
1578
1579         do_bp_handler = (unsigned int) kallsyms_search ("do_undefinstr");
1580         if (do_bp_handler == 0) {
1581                 DBPRINTF("no do_undefinstr symbol found!");
1582                 return -1;
1583         }
1584         arr_traps_template[NOTIFIER_CALL_CHAIN_INDEX] = arch_construct_brunch ((unsigned int)kprobe_handler, do_bp_handler + NOTIFIER_CALL_CHAIN_INDEX * 4, 1);
1585         // Register hooks (kprobe_handler)
1586         do_kpro = kallsyms_search ("register_undef_hook");
1587         if (do_kpro == 0) {
1588                 printk("no register_undef_hook symbol found!\n");
1589                 return -1;
1590         }
1591         do_kpro(&undef_ho_k);
1592         do_kpro(&undef_ho_u);
1593         do_kpro(&undef_ho_u_t);
1594         if ((ret = dbi_register_kprobe (&trampoline_p)) != 0) {
1595                 //dbi_unregister_jprobe(&do_exit_p, 0);
1596                 return ret;
1597         }
1598         return ret;
1599 }
1600
1601 void __exit dbi_arch_exit_kprobes (void)
1602 {
1603         // Unregister hooks (kprobe_handler)
1604         undo_kpro = kallsyms_search ("unregister_undef_hook");
1605         if (undo_kpro == 0) {
1606                 printk("no unregister_undef_hook symbol found!\n");
1607                 return -1;
1608         }
1609         undo_kpro(&undef_ho_u_t);
1610         undo_kpro(&undef_ho_u);
1611         undo_kpro(&undef_ho_k);
1612 }
1613
1614 //EXPORT_SYMBOL_GPL (dbi_arch_uprobe_return);
1615 //EXPORT_SYMBOL_GPL (dbi_arch_exit_kprobes);