Merge branch 'dev' into new_dpf
[kernel/swap-modules.git] / kprobe / arch / asm-arm / dbi_kprobes.c
1 /*
2  *  Dynamic Binary Instrumentation Module based on KProbes
3  *  modules/kprobe/arch/asm-arm/dbi_kprobes.c
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation; either version 2 of the License, or
8  * (at your option) any later version.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18  *
19  * Copyright (C) Samsung Electronics, 2006-2010
20  *
21  * 2006-2007    Ekaterina Gorelkina <e.gorelkina@samsung.com>: initial implementation for ARM/MIPS
22  * 2008-2009    Alexey Gerenkov <a.gerenkov@samsung.com> User-Space
23  *              Probes initial implementation; Support x86.
24  * 2010         Ekaterina Gorelkina <e.gorelkina@samsung.com>: redesign module for separating core and arch parts
25  * 2010-2011    Alexander Shirshikov <a.shirshikov@samsung.com>: initial implementation for Thumb
26  * 2012         Stanislav Andreev <s.andreev@samsung.com>: added time debug profiling support; BUG() message fix
27  * 2012         Stanislav Andreev <s.andreev@samsung.com>: redesign of kprobe functionality -
28  *              kprobe_handler() now called via undefined instruction hooks
29  * 2012         Stanislav Andreev <s.andreev@samsung.com>: hash tables search implemented for uprobes
30  */
31
32 #include <linux/module.h>
33 #include <linux/mm.h>
34
35 #include "dbi_kprobes.h"
36 #include "../dbi_kprobes.h"
37
38 #include "../../dbi_kdebug.h"
39 #include "../../dbi_insn_slots.h"
40 #include "../../dbi_kprobes_deps.h"
41 #include "../../dbi_uprobes.h"
42
43 #include <asm/cacheflush.h>
44
45 #ifdef OVERHEAD_DEBUG
46 #include <linux/time.h>
47 #endif
48
49 #include <asm/traps.h>
50 #include <asm/ptrace.h>
51 #include <linux/list.h>
52 #include <linux/hash.h>
53
54 #define SUPRESS_BUG_MESSAGES
55
56 extern unsigned long sched_addr;
57 extern unsigned long fork_addr;
58
59 extern struct kprobe * per_cpu__current_kprobe;
60 extern spinlock_t kretprobe_lock;
61 extern struct kretprobe *sched_rp;
62
63 extern struct hlist_head kprobe_insn_pages;
64 extern struct hlist_head uprobe_insn_pages;
65
66 extern unsigned long (*kallsyms_search) (const char *name);
67
68 extern struct kprobe *kprobe_running(void);
69 extern void reset_current_kprobe(void);
70 extern struct kprobe_ctlblk *get_kprobe_ctlblk(void);
71 extern struct kprobe * current_kprobe;
72
73 extern struct hlist_head kprobe_table[KPROBE_TABLE_SIZE];
74
75 #ifdef OVERHEAD_DEBUG
76 unsigned long swap_sum_time = 0;
77 unsigned long swap_sum_hit = 0;
78 EXPORT_SYMBOL_GPL (swap_sum_time);
79 EXPORT_SYMBOL_GPL (swap_sum_hit);
80 #endif
81
82 #define sign_extend(x, signbit) ((x) | (0 - ((x) & (1 << (signbit)))))
83 #define branch_displacement(insn) sign_extend(((insn) & 0xffffff) << 2, 25)
84
85 static kprobe_opcode_t get_addr_b(kprobe_opcode_t insn, kprobe_opcode_t *addr)
86 {
87         // real position less then PC by 8
88         return (kprobe_opcode_t)((long)addr + 8 + branch_displacement(insn));
89 }
90
91 unsigned int arr_traps_template[] = {
92                 0xe1a0c00d,    // mov          ip, sp
93                 0xe92dd800,    // stmdb        sp!, {fp, ip, lr, pc}
94                 0xe24cb004,    // sub          fp, ip, #4      ; 0x4
95                 0x00000000,    // b
96                 0xe3500000,    // cmp          r0, #0  ; 0x0
97                 0xe89da800,    // ldmia        sp, {fp, sp, pc}
98                 0x00000000,    // nop
99                 0xffffffff     // end
100 };
101
102
103 struct kprobe trampoline_p =
104 {
105         .addr = (kprobe_opcode_t *) & kretprobe_trampoline,
106         .pre_handler = trampoline_probe_handler
107 };
108
109 // is instruction Thumb2 and NOT a branch, etc...
110 int isThumb2(kprobe_opcode_t insn)
111 {
112         if((    (insn & 0xf800) == 0xe800 ||
113                 (insn & 0xf800) == 0xf000 ||
114                 (insn & 0xf800) == 0xf800)) return 1;
115         return 0;
116 }
117
118
119 int prep_pc_dep_insn_execbuf (kprobe_opcode_t * insns, kprobe_opcode_t insn, int uregs)
120 {
121         int i;
122
123         if (uregs & 0x10)
124         {
125                 int reg_mask = 0x1;
126                 //search in reg list
127                 for (i = 0; i < 13; i++, reg_mask <<= 1)
128                 {
129                         if (!(insn & reg_mask))
130                                 break;
131                 }
132         }
133         else
134         {
135                 for (i = 0; i < 13; i++)
136                 {
137                         if ((uregs & 0x1) && (ARM_INSN_REG_RN (insn) == i))
138                                 continue;
139                         if ((uregs & 0x2) && (ARM_INSN_REG_RD (insn) == i))
140                                 continue;
141                         if ((uregs & 0x4) && (ARM_INSN_REG_RS (insn) == i))
142                                 continue;
143                         if ((uregs & 0x8) && (ARM_INSN_REG_RM (insn) == i))
144                                 continue;
145                         break;
146                 }
147         }
148         if (i == 13)
149         {
150                 DBPRINTF ("there are no free register %x in insn %lx!", uregs, insn);
151                 return -EINVAL;
152         }
153         DBPRINTF ("prep_pc_dep_insn_execbuf: using R%d, changing regs %x", i, uregs);
154
155         // set register to save
156         ARM_INSN_REG_SET_RD (insns[0], i);
157         // set register to load address to
158         ARM_INSN_REG_SET_RD (insns[1], i);
159         // set instruction to execute and patch it
160         if (uregs & 0x10)
161         {
162                 ARM_INSN_REG_CLEAR_MR (insn, 15);
163                 ARM_INSN_REG_SET_MR (insn, i);
164         }
165         else
166         {
167                 if ((uregs & 0x1) && (ARM_INSN_REG_RN (insn) == 15))
168                         ARM_INSN_REG_SET_RN (insn, i);
169                 if ((uregs & 0x2) && (ARM_INSN_REG_RD (insn) == 15))
170                         ARM_INSN_REG_SET_RD (insn, i);
171                 if ((uregs & 0x4) && (ARM_INSN_REG_RS (insn) == 15))
172                         ARM_INSN_REG_SET_RS (insn, i);
173                 if ((uregs & 0x8) && (ARM_INSN_REG_RM (insn) == 15))
174                         ARM_INSN_REG_SET_RM (insn, i);
175         }
176         insns[UPROBES_TRAMP_INSN_IDX] = insn;
177         // set register to restore
178         ARM_INSN_REG_SET_RD (insns[3], i);
179         return 0;
180 }
181
182
183
184 int prep_pc_dep_insn_execbuf_thumb (kprobe_opcode_t * insns, kprobe_opcode_t insn, int uregs)
185 {
186         unsigned char mreg = 0;
187         unsigned char reg = 0;
188
189
190         if (THUMB_INSN_MATCH (APC, insn) || THUMB_INSN_MATCH (LRO3, insn))
191         {
192                 reg = ((insn & 0xffff) & uregs) >> 8;
193         }else{
194                 if (THUMB_INSN_MATCH (MOV3, insn))
195                 {
196                         if (((((unsigned char) insn) & 0xff) >> 3) == 15)
197                                 reg = (insn & 0xffff) & uregs;
198                         else
199                                 return 0;
200                 }else{
201                         if (THUMB2_INSN_MATCH (ADR, insn))
202                         {
203                                 reg = ((insn >> 16) & uregs) >> 8;
204                                 if (reg == 15) return 0;
205                         }else{
206                                 if (THUMB2_INSN_MATCH (LDRW, insn) || THUMB2_INSN_MATCH (LDRW1, insn) ||
207                                     THUMB2_INSN_MATCH (LDRHW, insn) || THUMB2_INSN_MATCH (LDRHW1, insn) ||
208                                     THUMB2_INSN_MATCH (LDRWL, insn))
209                                 {
210                                         reg = ((insn >> 16) & uregs) >> 12;
211                                         if (reg == 15) return 0;
212                                 }else{
213 // LDRB.W PC, [PC, #immed] => PLD [PC, #immed], so Rt == PC is skipped
214                                         if (THUMB2_INSN_MATCH (LDRBW, insn) || THUMB2_INSN_MATCH (LDRBW1, insn) || THUMB2_INSN_MATCH (LDREX, insn))
215                                         {
216                                                 reg = ((insn >> 16) & uregs) >> 12;
217                                         }else{
218                                                 if (THUMB2_INSN_MATCH (DP, insn))
219                                                 {
220                                                         reg = ((insn >> 16) & uregs) >> 12;
221                                                         if (reg == 15) return 0;
222                                                 }else{
223                                                         if (THUMB2_INSN_MATCH (RSBW, insn))
224                                                         {
225                                                                 reg = ((insn >> 12) & uregs) >> 8;
226                                                                 if (reg == 15) return 0;
227                                                         }else{
228                                                                 if (THUMB2_INSN_MATCH (RORW, insn))
229                                                                 {
230                                                                         reg = ((insn >> 12) & uregs) >> 8;
231                                                                         if (reg == 15) return 0;
232                                                                 }else{
233                                                                         if (THUMB2_INSN_MATCH (ROR, insn) || THUMB2_INSN_MATCH (LSLW1, insn) || THUMB2_INSN_MATCH (LSLW2, insn) || THUMB2_INSN_MATCH (LSRW1, insn) || THUMB2_INSN_MATCH (LSRW2, insn))
234                                                                         {
235                                                                                 reg = ((insn >> 12) & uregs) >> 8;
236                                                                                 if (reg == 15) return 0;
237                                                                         }else{
238                                                                                 if (THUMB2_INSN_MATCH (TEQ1, insn) || THUMB2_INSN_MATCH (TST1, insn))
239                                                                                 {
240                                                                                         reg = 15;
241                                                                                 }else{
242                                                                                         if (THUMB2_INSN_MATCH (TEQ2, insn) || THUMB2_INSN_MATCH (TST2, insn))
243                                                                                         {
244                                                                                                 reg = THUMB2_INSN_REG_RM(insn);
245                                                                                         }
246                                                                                 }
247                                                                         }
248                                                                 }
249                                                         }
250                                                 }
251                                         }
252                                 }
253                         }
254                 }
255         }
256
257         if ((   THUMB2_INSN_MATCH (STRW, insn) || THUMB2_INSN_MATCH (STRBW, insn) || THUMB2_INSN_MATCH (STRD, insn) || \
258                 THUMB2_INSN_MATCH (STRHT, insn) || THUMB2_INSN_MATCH (STRT, insn) || THUMB2_INSN_MATCH (STRHW1, insn) || \
259                 THUMB2_INSN_MATCH (STRHW, insn)) && THUMB2_INSN_REG_RT(insn) == 15)
260         {
261                 reg = THUMB2_INSN_REG_RT(insn);
262         }
263
264         if (reg == 6 || reg == 7)
265         {
266                 *((unsigned short*)insns + 0) = (*((unsigned short*)insns + 0) & 0x00ff) | ((1 << mreg) | (1 << (mreg + 1)));
267                 *((unsigned short*)insns + 1) = (*((unsigned short*)insns + 1) & 0xf8ff) | (mreg << 8);
268                 *((unsigned short*)insns + 2) = (*((unsigned short*)insns + 2) & 0xfff8) | (mreg + 1);
269                 *((unsigned short*)insns + 3) = (*((unsigned short*)insns + 3) & 0xffc7) | (mreg << 3);
270                 *((unsigned short*)insns + 7) = (*((unsigned short*)insns + 7) & 0xf8ff) | (mreg << 8);
271                 *((unsigned short*)insns + 8) = (*((unsigned short*)insns + 8) & 0xffc7) | (mreg << 3);
272                 *((unsigned short*)insns + 9) = (*((unsigned short*)insns + 9) & 0xffc7) | ((mreg + 1) << 3);
273                 *((unsigned short*)insns + 10) = (*((unsigned short*)insns + 10) & 0x00ff) | (( 1 << mreg) | (1 << (mreg + 1)));
274         }
275
276
277         if (THUMB_INSN_MATCH (APC, insn))
278         {
279 //              ADD Rd, PC, #immed_8*4 -> ADD Rd, SP, #immed_8*4
280                 *((unsigned short*)insns + 4) = ((insn & 0xffff) | 0x800);                              // ADD Rd, SP, #immed_8*4
281         }else{
282                 if (THUMB_INSN_MATCH (LRO3, insn))
283                 {
284 //                      LDR Rd, [PC, #immed_8*4] -> LDR Rd, [SP, #immed_8*4]
285                         *((unsigned short*)insns + 4) = ((insn & 0xffff) + 0x5000);                     // LDR Rd, [SP, #immed_8*4]
286                 }else{
287                         if (THUMB_INSN_MATCH (MOV3, insn))
288                         {
289 //                              MOV Rd, PC -> MOV Rd, SP
290                                 *((unsigned short*)insns + 4) = ((insn & 0xffff) ^ 0x10);               // MOV Rd, SP
291                         }else{
292                                 if (THUMB2_INSN_MATCH (ADR, insn))
293                                 {
294 //                                      ADDW Rd, PC, #imm -> ADDW Rd, SP, #imm
295                                         insns[2] = (insn & 0xfffffff0) | 0x0d;                          // ADDW Rd, SP, #imm
296                                 }else{
297                                         if (THUMB2_INSN_MATCH (LDRW, insn) || THUMB2_INSN_MATCH (LDRBW, insn) ||
298                                             THUMB2_INSN_MATCH (LDRHW, insn))
299                                         {
300 //                                              LDR.W Rt, [PC, #-<imm_12>] -> LDR.W Rt, [SP, #-<imm_8>]
301 //                                              !!!!!!!!!!!!!!!!!!!!!!!!
302 //                                              !!! imm_12 vs. imm_8 !!!
303 //                                              !!!!!!!!!!!!!!!!!!!!!!!!
304                                                 insns[2] = (insn & 0xf0fffff0) | 0x0c00000d;            // LDR.W Rt, [SP, #-<imm_8>]
305                                         }else{
306                                                 if (THUMB2_INSN_MATCH (LDRW1, insn) || THUMB2_INSN_MATCH (LDRBW1, insn) ||
307                                                     THUMB2_INSN_MATCH (LDRHW1, insn) || THUMB2_INSN_MATCH (LDRD, insn) || THUMB2_INSN_MATCH (LDRD1, insn) ||
308                                                     THUMB2_INSN_MATCH (LDREX, insn))
309                                                 {
310 //                                                      LDRx.W Rt, [PC, #+<imm_12>] -> LDRx.W Rt, [SP, #+<imm_12>] (+/-imm_8 for LDRD Rt, Rt2, [PC, #<imm_8>]
311                                                         insns[2] = (insn & 0xfffffff0) | 0xd;                                                                                                   // LDRx.W Rt, [SP, #+<imm_12>]
312                                                 }else{
313                                                         if (THUMB2_INSN_MATCH (MUL, insn))
314                                                         {
315                                                                 insns[2] = (insn & 0xfff0ffff) | 0x000d0000;                                                                                    // MUL Rd, Rn, SP
316                                                         }else{  if (THUMB2_INSN_MATCH (DP, insn))
317                                                                 {
318                                                                         if (THUMB2_INSN_REG_RM(insn) == 15) insns[2] = (insn & 0xfff0ffff) | 0x000d0000;                                        // DP Rd, Rn, PC
319                                                                         else if (THUMB2_INSN_REG_RN(insn) == 15) insns[2] = (insn & 0xfffffff0) | 0xd;                                          // DP Rd, PC, Rm
320                                                                 }else{  if (THUMB2_INSN_MATCH (LDRWL, insn))
321                                                                         {
322 //                                                                              LDRx.W Rt, [PC, #<imm_12>] -> LDRx.W Rt, [SP, #+<imm_12>] (+/-imm_8 for LDRD Rt, Rt2, [PC, #<imm_8>]
323                                                                                 insns[2] = (insn & 0xfffffff0) | 0xd;                                                                           // LDRx.W Rt, [SP, #+<imm_12>]
324                                                                         }else{  if (THUMB2_INSN_MATCH (RSBW, insn))
325                                                                                 {
326                                                                                         insns[2] = (insn & 0xfffffff0) | 0xd;                                                                   // RSB{S}.W Rd, PC, #<const> -> RSB{S}.W Rd, SP, #<const>
327                                                                                 }else{  if (THUMB2_INSN_MATCH (RORW, insn) || THUMB2_INSN_MATCH (LSLW1, insn) || THUMB2_INSN_MATCH (LSRW1, insn))
328                                                                                         {
329                                                                                                 if ((THUMB2_INSN_REG_RM(insn) == 15) && (THUMB2_INSN_REG_RN(insn) == 15))
330                                                                                                 {
331                                                                                                         insns[2] = (insn & 0xfffdfffd);                                                         // ROR.W Rd, PC, PC
332                                                                                                 }else if (THUMB2_INSN_REG_RM(insn) == 15) insns[2] = (insn & 0xfff0ffff) | 0xd0000;             // ROR.W Rd, Rn, PC
333                                                                                                         else if (THUMB2_INSN_REG_RN(insn) == 15) insns[2] = (insn & 0xfffffff0) | 0xd;          // ROR.W Rd, PC, Rm
334                                                                                         }else{  if (THUMB2_INSN_MATCH (ROR, insn) || THUMB2_INSN_MATCH (LSLW2, insn) || THUMB2_INSN_MATCH (LSRW2, insn))
335                                                                                                 {
336                                                                                                         insns[2] = (insn & 0xfff0ffff) | 0xd0000;                                               // ROR{S} Rd, PC, #<const> -> ROR{S} Rd, SP, #<const>
337                                                                                                 }
338                                                                                         }
339                                                                                 }
340                                                                         }
341                                                                 }
342                                                         }
343                                                 }
344                                         }
345                                 }
346                         }
347                 }
348         }
349
350         if (THUMB2_INSN_MATCH (STRW, insn) || THUMB2_INSN_MATCH (STRBW, insn))
351         {
352                 insns[2] = (insn & 0xfff0ffff) | 0x000d0000;                                                            // STRx.W Rt, [Rn, SP]
353         }else{
354                 if (THUMB2_INSN_MATCH (STRD, insn) || THUMB2_INSN_MATCH (STRHT, insn) || THUMB2_INSN_MATCH (STRT, insn) || THUMB2_INSN_MATCH (STRHW1, insn))
355                 {
356                         if (THUMB2_INSN_REG_RN(insn) == 15)
357                         {
358                                 insns[2] = (insn & 0xfffffff0) | 0xd;                                                   // STRD/T/HT{.W} Rt, [SP, ...]
359                         }else{
360                                 insns[2] = insn;
361                         }
362                 }else{
363                         if (THUMB2_INSN_MATCH (STRHW, insn) && (THUMB2_INSN_REG_RN(insn) == 15))
364                         {
365                                 if (THUMB2_INSN_REG_RN(insn) == 15)
366                                 {
367                                         insns[2] = (insn & 0xf0fffff0) | 0x0c00000d;                                    // STRH.W Rt, [SP, #-<imm_8>]
368                                 }else{
369                                         insns[2] = insn;
370                                 }
371                         }
372                 }
373         }
374
375 //       STRx PC, xxx
376         if ((reg == 15) && (THUMB2_INSN_MATCH (STRW, insn)   || \
377                             THUMB2_INSN_MATCH (STRBW, insn)  || \
378                             THUMB2_INSN_MATCH (STRD, insn)   || \
379                             THUMB2_INSN_MATCH (STRHT, insn)  || \
380                             THUMB2_INSN_MATCH (STRT, insn)   || \
381                             THUMB2_INSN_MATCH (STRHW1, insn) || \
382                             THUMB2_INSN_MATCH (STRHW, insn) ))
383         {
384                 insns[2] = (insns[2] & 0x0fffffff) | 0xd0000000;
385         }
386
387
388
389         if (THUMB2_INSN_MATCH (TEQ1, insn) || THUMB2_INSN_MATCH (TST1, insn))
390         {
391                 insns[2] = (insn & 0xfffffff0) | 0xd;                                                                   // TEQ SP, #<const>
392         }else{  if (THUMB2_INSN_MATCH (TEQ2, insn) || THUMB2_INSN_MATCH (TST2, insn))
393                 {
394                         if ((THUMB2_INSN_REG_RN(insn) == 15) && (THUMB2_INSN_REG_RM(insn) == 15))
395                         {
396                                 insns[2] = (insn & 0xfffdfffd);                                                         // TEQ/TST PC, PC
397                         }else   if (THUMB2_INSN_REG_RM(insn) == 15) insns[2] = (insn & 0xfff0ffff) | 0xd0000;           // TEQ/TST Rn, PC
398                                 else if (THUMB2_INSN_REG_RN(insn) == 15) insns[2] = (insn & 0xfffffff0) | 0xd;          // TEQ/TST PC, Rm
399                 }
400         }
401
402         return 0;
403 }
404
405
406
407 int arch_check_insn_arm (struct arch_specific_insn *ainsn)
408 {
409         int ret = 0;
410
411         // check instructions that can change PC by nature
412         if (
413 //              ARM_INSN_MATCH (UNDEF, ainsn->insn_arm[0]) ||
414                 ARM_INSN_MATCH (AUNDEF, ainsn->insn_arm[0]) ||
415                 ARM_INSN_MATCH (SWI, ainsn->insn_arm[0]) ||
416                 ARM_INSN_MATCH (BREAK, ainsn->insn_arm[0]) ||
417                 ARM_INSN_MATCH (BL, ainsn->insn_arm[0]) ||
418                 ARM_INSN_MATCH (BLX1, ainsn->insn_arm[0]) ||
419                 ARM_INSN_MATCH (BLX2, ainsn->insn_arm[0]) ||
420                 ARM_INSN_MATCH (BX, ainsn->insn_arm[0]) ||
421                 ARM_INSN_MATCH (BXJ, ainsn->insn_arm[0]))
422         {
423                 DBPRINTF ("Bad insn arch_check_insn_arm: %lx\n", ainsn->insn_arm[0]);
424                 ret = -EFAULT;
425         }
426 #ifndef CONFIG_CPU_V7
427         // check instructions that can write result to PC
428         else if ((ARM_INSN_MATCH (DPIS, ainsn->insn_arm[0]) ||
429                                 ARM_INSN_MATCH (DPRS, ainsn->insn_arm[0]) ||
430                                 ARM_INSN_MATCH (DPI, ainsn->insn_arm[0]) ||
431                                 ARM_INSN_MATCH (LIO, ainsn->insn_arm[0]) ||
432                                 ARM_INSN_MATCH (LRO, ainsn->insn_arm[0])) &&
433                         (ARM_INSN_REG_RD (ainsn->insn_arm[0]) == 15))
434         {
435                 DBPRINTF ("Bad arch_check_insn_arm: %lx\n", ainsn->insn_arm[0]);
436                 ret = -EFAULT;
437         }
438 #endif // CONFIG_CPU_V7
439         // check special instruction loads store multiple registers
440         else if ((ARM_INSN_MATCH (LM, ainsn->insn_arm[0]) || ARM_INSN_MATCH (SM, ainsn->insn_arm[0])) &&
441                         // store pc or load to pc
442                         (ARM_INSN_REG_MR (ainsn->insn_arm[0], 15) ||
443                          // store/load with pc update
444                          ((ARM_INSN_REG_RN (ainsn->insn_arm[0]) == 15) && (ainsn->insn_arm[0] & 0x200000))))
445         {
446                 DBPRINTF ("Bad insn arch_check_insn_arm: %lx\n", ainsn->insn_arm[0]);
447                 ret = -EFAULT;
448         }
449         return ret;
450 }
451
452 int arch_check_insn_thumb (struct arch_specific_insn *ainsn)
453 {
454         int ret = 0;
455
456         // check instructions that can change PC
457         if (    THUMB_INSN_MATCH (UNDEF, ainsn->insn_thumb[0]) ||
458                 THUMB_INSN_MATCH (SWI, ainsn->insn_thumb[0]) ||
459                 THUMB_INSN_MATCH (BREAK, ainsn->insn_thumb[0]) ||
460                 THUMB2_INSN_MATCH (BL, ainsn->insn_thumb[0]) ||
461                 THUMB_INSN_MATCH (B1, ainsn->insn_thumb[0]) ||
462                 THUMB_INSN_MATCH (B2, ainsn->insn_thumb[0]) ||
463                 THUMB_INSN_MATCH (CBZ, ainsn->insn_thumb[0]) ||
464                 THUMB2_INSN_MATCH (B1, ainsn->insn_thumb[0]) ||
465                 THUMB2_INSN_MATCH (B2, ainsn->insn_thumb[0]) ||
466                 THUMB2_INSN_MATCH (BLX1, ainsn->insn_thumb[0]) ||
467                 THUMB_INSN_MATCH (BLX2, ainsn->insn_thumb[0]) ||
468                 THUMB_INSN_MATCH (BX, ainsn->insn_thumb[0]) ||
469                 THUMB2_INSN_MATCH (BXJ, ainsn->insn_thumb[0]) ||
470                 (THUMB2_INSN_MATCH (ADR, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RD(ainsn->insn_thumb[0]) == 15) ||
471                 (THUMB2_INSN_MATCH (LDRW, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RT(ainsn->insn_thumb[0]) == 15) ||
472                 (THUMB2_INSN_MATCH (LDRW1, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RT(ainsn->insn_thumb[0]) == 15) ||
473                 (THUMB2_INSN_MATCH (LDRHW, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RT(ainsn->insn_thumb[0]) == 15) ||
474                 (THUMB2_INSN_MATCH (LDRHW1, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RT(ainsn->insn_thumb[0]) == 15) ||
475                 (THUMB2_INSN_MATCH (LDRWL, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RT(ainsn->insn_thumb[0]) == 15) ||
476                 THUMB2_INSN_MATCH (LDMIA, ainsn->insn_thumb[0]) ||
477                 THUMB2_INSN_MATCH (LDMDB, ainsn->insn_thumb[0]) ||
478                 (THUMB2_INSN_MATCH (DP, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RD(ainsn->insn_thumb[0]) == 15) ||
479                 (THUMB2_INSN_MATCH (RSBW, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RD(ainsn->insn_thumb[0]) == 15) ||
480                 (THUMB2_INSN_MATCH (RORW, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RD(ainsn->insn_thumb[0]) == 15) ||
481                 (THUMB2_INSN_MATCH (ROR, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RD(ainsn->insn_thumb[0]) == 15) ||
482                 (THUMB2_INSN_MATCH (LSLW1, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RD(ainsn->insn_thumb[0]) == 15) ||
483                 (THUMB2_INSN_MATCH (LSLW2, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RD(ainsn->insn_thumb[0]) == 15) ||
484                 (THUMB2_INSN_MATCH (LSRW1, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RD(ainsn->insn_thumb[0]) == 15) ||
485                 (THUMB2_INSN_MATCH (LSRW2, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RD(ainsn->insn_thumb[0]) == 15) ||
486 /* skip PC, #-imm12 -> SP, #-imm8 and Tegra-hanging instructions */
487                 (THUMB2_INSN_MATCH (STRW1, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RN(ainsn->insn_thumb[0]) == 15) ||
488                 (THUMB2_INSN_MATCH (STRBW1, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RN(ainsn->insn_thumb[0]) == 15) ||
489                 (THUMB2_INSN_MATCH (STRHW1, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RN(ainsn->insn_thumb[0]) == 15) ||
490                 (THUMB2_INSN_MATCH (STRW, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RN(ainsn->insn_thumb[0]) == 15) ||
491                 (THUMB2_INSN_MATCH (STRHW, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RN(ainsn->insn_thumb[0]) == 15) ||
492                 (THUMB2_INSN_MATCH (LDRW, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RN(ainsn->insn_thumb[0]) == 15) ||
493                 (THUMB2_INSN_MATCH (LDRBW, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RN(ainsn->insn_thumb[0]) == 15) ||
494                 (THUMB2_INSN_MATCH (LDRHW, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RN(ainsn->insn_thumb[0]) == 15) ||
495 /* skip STRDx/LDRDx Rt, Rt2, [Rd, ...] */
496                 (THUMB2_INSN_MATCH (LDRD, ainsn->insn_thumb[0]) || THUMB2_INSN_MATCH (LDRD1, ainsn->insn_thumb[0]) || THUMB2_INSN_MATCH (STRD, ainsn->insn_thumb[0])) )
497         {
498                 DBPRINTF ("Bad insn arch_check_insn_thumb: %lx\n", ainsn->insn_thumb[0]);
499                 ret = -EFAULT;
500         }
501
502         return ret;
503 }
504
505 int arch_prepare_kretprobe (struct kretprobe *p)
506 {
507         DBPRINTF("Warrning: arch_prepare_kretprobe is not implemented\n");
508         return 0;
509 }
510
511 int arch_prepare_kprobe (struct kprobe *p)
512 {
513         kprobe_opcode_t insns[KPROBES_TRAMP_LEN];
514         int uregs, pc_dep, ret = 0;
515     kprobe_opcode_t insn[MAX_INSN_SIZE];
516     struct arch_specific_insn ainsn;
517
518     /* insn: must be on special executable page on i386. */
519     p->ainsn.insn = get_insn_slot (NULL, 0);
520     if (!p->ainsn.insn)
521         return -ENOMEM;
522
523     memcpy (insn, p->addr, MAX_INSN_SIZE * sizeof (kprobe_opcode_t));
524     ainsn.insn_arm = ainsn.insn = insn;
525     ret = arch_check_insn_arm (&ainsn);
526     if (!ret)
527     {
528         p->opcode = *p->addr;
529         uregs = pc_dep = 0;
530
531         // Rn, Rm ,Rd
532         if(ARM_INSN_MATCH (DPIS, insn[0]) || ARM_INSN_MATCH (LRO, insn[0]) ||
533            ARM_INSN_MATCH (SRO, insn[0]))
534         {
535             uregs = 0xb;
536             if( (ARM_INSN_REG_RN (insn[0]) == 15) || (ARM_INSN_REG_RM (insn[0]) == 15) ||
537                 (ARM_INSN_MATCH (SRO, insn[0]) && (ARM_INSN_REG_RD (insn[0]) == 15)) )
538             {
539                 DBPRINTF ("Unboostable insn %lx, DPIS/LRO/SRO\n", insn[0]);
540                 pc_dep = 1;
541             }
542         }
543         // Rn ,Rd
544         else if(ARM_INSN_MATCH (DPI, insn[0]) || ARM_INSN_MATCH (LIO, insn[0]) ||
545                 ARM_INSN_MATCH (SIO, insn[0]))
546         {
547             uregs = 0x3;
548             if ((ARM_INSN_REG_RN (insn[0]) == 15) || (ARM_INSN_MATCH (SIO, insn[0]) &&
549                         (ARM_INSN_REG_RD (insn[0]) == 15)))
550             {
551                 pc_dep = 1;
552                 DBPRINTF ("Unboostable insn %lx/%p, DPI/LIO/SIO\n", insn[0], p);
553             }
554         }
555         // Rn, Rm, Rs
556         else if(ARM_INSN_MATCH (DPRS, insn[0]))
557         {
558             uregs = 0xd;
559             if ((ARM_INSN_REG_RN (insn[0]) == 15) || (ARM_INSN_REG_RM (insn[0]) == 15) ||
560                 (ARM_INSN_REG_RS (insn[0]) == 15))
561             {
562                 pc_dep = 1;
563                 DBPRINTF ("Unboostable insn %lx, DPRS\n", insn[0]);
564             }
565         }
566         // register list
567         else if(ARM_INSN_MATCH (SM, insn[0]))
568         {
569             uregs = 0x10;
570             if (ARM_INSN_REG_MR (insn[0], 15))
571             {
572                 DBPRINTF ("Unboostable insn %lx, SM\n", insn[0]);
573                 pc_dep = 1;
574             }
575         }
576         // check instructions that can write result to SP andu uses PC
577         if (pc_dep  && (ARM_INSN_REG_RD (ainsn.insn[0]) == 13))
578         {
579             free_insn_slot(&kprobe_insn_pages, NULL, p->ainsn.insn);
580             ret = -EFAULT;
581         }
582         else
583         {
584             if (uregs && pc_dep)
585             {
586                 memcpy (insns, pc_dep_insn_execbuf, sizeof (insns));
587                 if (prep_pc_dep_insn_execbuf (insns, insn[0], uregs) != 0)
588                 {
589                     DBPRINTF ("failed to prepare exec buffer for insn %lx!", insn[0]);
590                     free_insn_slot(&kprobe_insn_pages, NULL, p->ainsn.insn);
591                     return -EINVAL;
592                 }
593                 insns[6] = (kprobe_opcode_t) (p->addr + 2);
594             }
595             else
596             {
597                 memcpy (insns, gen_insn_execbuf, sizeof (insns));
598                 insns[KPROBES_TRAMP_INSN_IDX] = insn[0];
599             }
600             insns[7] = (kprobe_opcode_t) (p->addr + 1);
601             DBPRINTF ("arch_prepare_kprobe: insn %lx", insn[0]);
602             DBPRINTF ("arch_prepare_kprobe: to %p - %lx %lx %lx %lx %lx %lx %lx %lx %lx",
603                     p->ainsn.insn, insns[0], insns[1], insns[2], insns[3], insns[4],
604                     insns[5], insns[6], insns[7], insns[8]);
605             memcpy (p->ainsn.insn, insns, sizeof(insns));
606             flush_icache_range((long unsigned)p->ainsn.insn, (long unsigned)(p->ainsn.insn) + sizeof(insns));
607 #ifdef BOARD_tegra
608             flush_cache_all();
609 #endif
610         }
611     }
612     else
613     {
614         free_insn_slot(&kprobe_insn_pages, NULL, p->ainsn.insn);
615         printk("arch_prepare_kprobe: instruction 0x%lx not instrumentation, addr=0x%p\n", insn[0], p->addr);
616     }
617
618     return ret;
619 }
620
621 static unsigned int arch_construct_brunch (unsigned int base, unsigned int addr, int link)
622 {
623         kprobe_opcode_t insn;
624         unsigned int bpi = (unsigned int) base - (unsigned int) addr - 8;
625
626         insn = bpi >> 2;
627         DBPRINTF ("base=%x addr=%x base-addr-8=%x\n", base, addr, bpi);
628         if (abs (insn & 0xffffff) > 0xffffff)
629         {
630                 DBPRINTF ("ERROR: kprobe address out of range\n");
631                 BUG ();
632         }
633         insn = insn & 0xffffff;
634         insn = insn | ((link != 0) ? 0xeb000000 : 0xea000000);
635         DBPRINTF ("insn=%lX\n", insn);
636         return (unsigned int) insn;
637 }
638
639
640 int arch_copy_trampoline_arm_uprobe (struct kprobe *p, struct task_struct *task, int atomic);
641 int arch_copy_trampoline_thumb_uprobe (struct kprobe *p, struct task_struct *task, int atomic);
642
643 int arch_prepare_uprobe (struct kprobe *p, struct task_struct *task, int atomic)
644 {
645         int ret = 0;
646         kprobe_opcode_t insn[MAX_INSN_SIZE];
647
648         if ((unsigned long) p->addr & 0x01)
649         {
650                 printk("Error in %s at %d: attempt to register kprobe at an unaligned address\n", __FILE__, __LINE__);
651                 return -EINVAL;
652         }
653         if (!read_proc_vm_atomic (task, (unsigned long) p->addr, &insn, MAX_INSN_SIZE * sizeof(kprobe_opcode_t)))
654                 panic ("Failed to read memory task[tgid=%u, comm=%s] %p!\n", task->tgid, task->comm, p->addr);
655         p->opcode = insn[0];
656         p->ainsn.insn_arm = get_insn_slot(task, atomic);
657         if (!p->ainsn.insn_arm) {
658                 printk("Error in %s at %d: kprobe slot allocation error (arm)\n", __FILE__, __LINE__);
659                 return -ENOMEM;
660         }
661         ret = arch_copy_trampoline_arm_uprobe(p, task, 1);
662         if (ret) {
663                 free_insn_slot(&uprobe_insn_pages, task, p->ainsn.insn_arm);
664                 return -EFAULT;
665         }
666         p->ainsn.insn_thumb = get_insn_slot(task, atomic);
667         if (!p->ainsn.insn_thumb) {
668                 printk("Error in %s at %d: kprobe slot allocation error (thumb)\n", __FILE__, __LINE__);
669                 return -ENOMEM;
670         }
671         ret = arch_copy_trampoline_thumb_uprobe(p, task, 1);
672         if (ret) {
673                 free_insn_slot(&uprobe_insn_pages, task, p->ainsn.insn_arm);
674                 free_insn_slot(&uprobe_insn_pages, task, p->ainsn.insn_thumb);
675                 return -EFAULT;
676         }
677         if ((p->safe_arm == -1) && (p->safe_thumb == -1)) {
678                 printk("Error in %s at %d: failed arch_copy_trampoline_*_uprobe() (both) [tgid=%u, addr=%x, data=%x]\n",
679                                 __FILE__, __LINE__, task->tgid, p->addr, p->opcode);
680                 if (!write_proc_vm_atomic (task, (unsigned long) p->addr, &p->opcode, sizeof (p->opcode)))
681                         panic ("Failed to write memory %p!\n", p->addr);
682                 free_insn_slot(&uprobe_insn_pages, task, p->ainsn.insn_arm);
683                 free_insn_slot(&uprobe_insn_pages, task, p->ainsn.insn_thumb);
684                 return -EFAULT;
685         }
686         return ret;
687 }
688
689 int arch_prepare_uretprobe (struct kretprobe *p, struct task_struct *task)
690 {
691         DBPRINTF("Warrning: arch_prepare_uretprobe is not implemented\n");
692         return 0;
693 }
694
695 void prepare_singlestep (struct kprobe *p, struct pt_regs *regs)
696 {
697         if (p->ss_addr) {
698                 regs->ARM_pc = (unsigned long)p->ss_addr;
699                 p->ss_addr = NULL;
700         } else {
701                 regs->ARM_pc = (unsigned long)p->ainsn.insn;
702         }
703 }
704
705 void save_previous_kprobe(struct kprobe_ctlblk *kcb, struct kprobe *p_run)
706 {
707         if (p_run == NULL) {
708                 panic("arm_save_previous_kprobe: p_run == NULL\n");
709         }
710
711         if (kcb->prev_kprobe.kp != NULL) {
712                 DBPRINTF ("no space to save new probe[]: task = %d/%s", current->pid, current->comm);
713         }
714
715         kcb->prev_kprobe.kp = p_run;
716         kcb->prev_kprobe.status = kcb->kprobe_status;
717 }
718
719 void restore_previous_kprobe(struct kprobe_ctlblk *kcb)
720 {
721         set_current_kprobe(kcb->prev_kprobe.kp, NULL, NULL);
722         kcb->kprobe_status = kcb->prev_kprobe.status;
723         kcb->prev_kprobe.kp = NULL;
724         kcb->prev_kprobe.status = 0;
725 }
726
727 void set_current_kprobe(struct kprobe *p, struct pt_regs *regs, struct kprobe_ctlblk *kcb)
728 {
729         __get_cpu_var(current_kprobe) = p;
730         DBPRINTF ("set_current_kprobe: p=%p addr=%p\n", p, p->addr);
731 }
732
733 int arch_copy_trampoline_arm_uprobe (struct kprobe *p, struct task_struct *task, int atomic)
734 {
735         kprobe_opcode_t insns[UPROBES_TRAMP_LEN];
736         int uregs, pc_dep;
737         kprobe_opcode_t insn[MAX_INSN_SIZE];
738         struct arch_specific_insn ainsn;
739
740         p->safe_arm = -1;
741         if ((unsigned long) p->addr & 0x01)
742         {
743                 printk("Error in %s at %d: attempt to register kprobe at an unaligned address\n", __FILE__, __LINE__);
744                 return -EINVAL;
745         }
746         insn[0] = p->opcode;
747         ainsn.insn_arm = insn;
748         if (!arch_check_insn_arm(&ainsn))
749         {
750                 p->safe_arm = 0;
751         }
752         uregs = pc_dep = 0;
753         // Rn, Rm ,Rd
754         if (ARM_INSN_MATCH (DPIS, insn[0]) || ARM_INSN_MATCH (LRO, insn[0]) ||
755                         ARM_INSN_MATCH (SRO, insn[0]))
756         {
757                 uregs = 0xb;
758                 if ((ARM_INSN_REG_RN (insn[0]) == 15) || (ARM_INSN_REG_RM (insn[0]) == 15) ||
759                                 (ARM_INSN_MATCH (SRO, insn[0]) && (ARM_INSN_REG_RD (insn[0]) == 15)))
760                 {
761                         DBPRINTF ("Unboostable insn %lx, DPIS/LRO/SRO\n", insn[0]);
762                         pc_dep = 1;
763                 }
764         }
765         // Rn ,Rd
766         else if (ARM_INSN_MATCH (DPI, insn[0]) || ARM_INSN_MATCH (LIO, insn[0]) ||
767                         ARM_INSN_MATCH (SIO, insn[0]))
768         {
769                 uregs = 0x3;
770                 if ((ARM_INSN_REG_RN (insn[0]) == 15) || (ARM_INSN_MATCH (SIO, insn[0]) &&
771                                 (ARM_INSN_REG_RD (insn[0]) == 15)))
772                 {
773                         pc_dep = 1;
774                         DBPRINTF ("Unboostable insn %lx/%p, DPI/LIO/SIO\n", insn[0], p);
775                 }
776         }
777         // Rn, Rm, Rs
778         else if (ARM_INSN_MATCH (DPRS, insn[0]))
779         {
780                 uregs = 0xd;
781                 if ((ARM_INSN_REG_RN (insn[0]) == 15) || (ARM_INSN_REG_RM (insn[0]) == 15) ||
782                                 (ARM_INSN_REG_RS (insn[0]) == 15))
783                 {
784                         pc_dep = 1;
785                         DBPRINTF ("Unboostable insn %lx, DPRS\n", insn[0]);
786                 }
787         }
788         // register list
789         else if (ARM_INSN_MATCH (SM, insn[0]))
790         {
791                 uregs = 0x10;
792                 if (ARM_INSN_REG_MR (insn[0], 15))
793                 {
794                         DBPRINTF ("Unboostable insn %lx, SM\n", insn[0]);
795                         pc_dep = 1;
796                 }
797         }
798         // check instructions that can write result to SP andu uses PC
799         if (pc_dep  && (ARM_INSN_REG_RD (ainsn.insn_arm[0]) == 13))
800         {
801                 printk("Error in %s at %d: instruction check failed (arm)\n", __FILE__, __LINE__);
802                 p->safe_arm = -1;
803                 // TODO: move free to later phase
804                 //free_insn_slot (&uprobe_insn_pages, task, p->ainsn.insn_arm, 0);
805                 //ret = -EFAULT;
806         }
807         if (unlikely(uregs && pc_dep))
808         {
809                 memcpy (insns, pc_dep_insn_execbuf, sizeof (insns));
810                 if (prep_pc_dep_insn_execbuf (insns, insn[0], uregs) != 0)
811                 {
812                         printk("Error in %s at %d: failed to prepare exec buffer for insn %lx!",
813                                 __FILE__, __LINE__, insn[0]);
814                         p->safe_arm = -1;
815                         // TODO: move free to later phase
816                         //free_insn_slot (&uprobe_insn_pages, task, p->ainsn.insn_arm, 0);
817                         //return -EINVAL;
818                 }
819                 //insns[UPROBES_TRAMP_SS_BREAK_IDX] = BREAKPOINT_INSTRUCTION;
820                 insns[6] = (kprobe_opcode_t) (p->addr + 2);
821         }
822         else
823         {
824                 memcpy (insns, gen_insn_execbuf, sizeof (insns));
825                 insns[UPROBES_TRAMP_INSN_IDX] = insn[0];
826         }
827         insns[UPROBES_TRAMP_RET_BREAK_IDX] = BREAKPOINT_INSTRUCTION;
828         insns[7] = (kprobe_opcode_t) (p->addr + 1);
829
830         // B
831         if(ARM_INSN_MATCH (B, ainsn.insn_arm[0]))
832         {
833                 memcpy (insns, pc_dep_insn_execbuf, sizeof (insns));
834                 insns[UPROBES_TRAMP_RET_BREAK_IDX] = BREAKPOINT_INSTRUCTION;
835                 insns[6] = (kprobe_opcode_t) (p->addr + 2);
836                 insns[7] = get_addr_b(p->opcode, p->addr);
837         }
838
839         DBPRINTF ("arch_prepare_uprobe: to %p - %lx %lx %lx %lx %lx %lx %lx %lx %lx",
840                         p->ainsn.insn_arm, insns[0], insns[1], insns[2], insns[3], insns[4],
841                         insns[5], insns[6], insns[7], insns[8]);
842         if (!write_proc_vm_atomic (task, (unsigned long) p->ainsn.insn_arm, insns, sizeof (insns)))
843         {
844                 panic("failed to write memory %p!\n", p->ainsn.insn);
845                 // Mr_Nobody: we have to panic, really??...
846                 //free_insn_slot (&uprobe_insn_pages, task, p->ainsn.insn_arm, 0);
847                 //return -EINVAL;
848         }
849         return 0;
850 }
851
852 int arch_copy_trampoline_thumb_uprobe (struct kprobe *p, struct task_struct *task, int atomic)
853 {
854         int uregs, pc_dep;
855         unsigned int addr;
856         kprobe_opcode_t insn[MAX_INSN_SIZE];
857         struct arch_specific_insn ainsn;
858         kprobe_opcode_t insns[UPROBES_TRAMP_LEN * 2];
859
860         p->safe_thumb = -1;
861         if ((unsigned long) p->addr & 0x01)
862         {
863                 printk("Error in %s at %d: attempt to register kprobe at an unaligned address\n", __FILE__, __LINE__);
864                 return -EINVAL;
865         }
866         insn[0] = p->opcode;
867         ainsn.insn_thumb = insn;
868         if (!arch_check_insn_thumb(&ainsn))
869         {
870                 p->safe_thumb = 0;
871         }
872         uregs = 0;
873         pc_dep = 0;
874         if (THUMB_INSN_MATCH (APC, insn[0]) || THUMB_INSN_MATCH (LRO3, insn[0]))
875         {
876                 uregs = 0x0700;         // 8-10
877                 pc_dep = 1;
878         }
879         else if (THUMB_INSN_MATCH (MOV3, insn[0]) && (((((unsigned char) insn[0]) & 0xff) >> 3) == 15))
880         {
881                 // MOV Rd, PC
882                 uregs = 0x07;
883                 pc_dep = 1;
884         }
885         else if THUMB2_INSN_MATCH (ADR, insn[0])
886         {
887                 uregs = 0x0f00;         // Rd 8-11
888                 pc_dep = 1;
889         }
890         else if (((THUMB2_INSN_MATCH (LDRW, insn[0]) || THUMB2_INSN_MATCH (LDRW1, insn[0])  ||
891                         THUMB2_INSN_MATCH (LDRBW, insn[0]) || THUMB2_INSN_MATCH (LDRBW1, insn[0]) ||
892                         THUMB2_INSN_MATCH (LDRHW, insn[0]) || THUMB2_INSN_MATCH (LDRHW1, insn[0]) ||
893                         THUMB2_INSN_MATCH (LDRWL, insn[0])) && THUMB2_INSN_REG_RN(insn[0]) == 15) ||
894                         THUMB2_INSN_MATCH (LDREX, insn[0]) ||
895                         ((THUMB2_INSN_MATCH (STRW, insn[0]) || THUMB2_INSN_MATCH (STRBW, insn[0]) ||
896                                 THUMB2_INSN_MATCH (STRHW, insn[0]) || THUMB2_INSN_MATCH (STRHW1, insn[0])) &&
897                                 (THUMB2_INSN_REG_RN(insn[0]) == 15 || THUMB2_INSN_REG_RT(insn[0]) == 15)) ||
898                         ((THUMB2_INSN_MATCH (STRT, insn[0]) || THUMB2_INSN_MATCH (STRHT, insn[0])) &&
899                                 (THUMB2_INSN_REG_RN(insn[0]) == 15 || THUMB2_INSN_REG_RT(insn[0]) == 15)) )
900         {
901                 uregs = 0xf000;         // Rt 12-15
902                 pc_dep = 1;
903         }
904         else if ((THUMB2_INSN_MATCH (LDRD, insn[0]) || THUMB2_INSN_MATCH (LDRD1, insn[0])) && (THUMB2_INSN_REG_RN(insn[0]) == 15))
905         {
906                 uregs = 0xff00;         // Rt 12-15, Rt2 8-11
907                 pc_dep = 1;
908         }
909         else if (THUMB2_INSN_MATCH (MUL, insn[0]) && THUMB2_INSN_REG_RM(insn[0]) == 15)
910         {
911                 uregs = 0xf;
912                 pc_dep = 1;
913         }
914         else if (THUMB2_INSN_MATCH (DP, insn[0]) && (THUMB2_INSN_REG_RN(insn[0]) == 15 || THUMB2_INSN_REG_RM(insn[0]) == 15))
915         {
916                 uregs = 0xf000; // Rd 12-15
917                 pc_dep = 1;
918         }
919         else if (THUMB2_INSN_MATCH(STRD, insn[0]) && ((THUMB2_INSN_REG_RN(insn[0]) == 15) || (THUMB2_INSN_REG_RT(insn[0]) == 15) || THUMB2_INSN_REG_RT2(insn[0]) == 15))
920         {
921                 uregs = 0xff00;         // Rt 12-15, Rt2 8-11
922                 pc_dep = 1;
923         }
924         else if (THUMB2_INSN_MATCH (RSBW, insn[0]) && THUMB2_INSN_REG_RN(insn[0]) == 15)
925         {
926                 uregs = 0x0f00; // Rd 8-11
927                 pc_dep = 1;
928         }
929         else if (THUMB2_INSN_MATCH (RORW, insn[0]) && (THUMB2_INSN_REG_RN(insn[0]) == 15 || THUMB2_INSN_REG_RM(insn[0]) == 15))
930         {
931                 uregs = 0x0f00;
932                 pc_dep = 1;
933         }
934         else if ((THUMB2_INSN_MATCH (ROR, insn[0]) || THUMB2_INSN_MATCH(LSLW2, insn[0]) || THUMB2_INSN_MATCH(LSRW2, insn[0])) && THUMB2_INSN_REG_RM(insn[0]) == 15)
935         {
936                 uregs = 0x0f00; // Rd 8-11
937                 pc_dep = 1;
938         }
939         else if ((THUMB2_INSN_MATCH (LSLW1, insn[0]) || THUMB2_INSN_MATCH (LSRW1, insn[0])) && (THUMB2_INSN_REG_RN(insn[0]) == 15 || THUMB2_INSN_REG_RM(insn[0]) == 15))
940         {
941                 uregs = 0x0f00; // Rd 8-11
942                 pc_dep = 1;
943         }
944         else if ((THUMB2_INSN_MATCH (TEQ1, insn[0]) || THUMB2_INSN_MATCH (TST1, insn[0])) && THUMB2_INSN_REG_RN(insn[0]) == 15)
945         {
946                 uregs = 0xf0000;        //Rn 0-3 (16-19)
947                 pc_dep = 1;
948         }
949         else if ((THUMB2_INSN_MATCH (TEQ2, insn[0]) || THUMB2_INSN_MATCH (TST2, insn[0])) &&
950                 (THUMB2_INSN_REG_RN(insn[0]) == 15 || THUMB2_INSN_REG_RM(insn[0]) == 15))
951         {
952                 uregs = 0xf0000;        //Rn 0-3 (16-19)
953                 pc_dep = 1;
954         }
955         if (unlikely(uregs && pc_dep))
956         {
957                 memcpy (insns, pc_dep_insn_execbuf_thumb, 18 * 2);
958                 if (prep_pc_dep_insn_execbuf_thumb (insns, insn[0], uregs) != 0)
959                 {
960                         printk("Error in %s at %d: failed to prepare exec buffer for insn %lx!",
961                                 __FILE__, __LINE__, insn[0]);
962                         p->safe_thumb = -1;
963                         //free_insn_slot (&uprobe_insn_pages, task, p->ainsn.insn_thumb, 0);
964                         //return -EINVAL;
965                 }
966                 addr = ((unsigned int)p->addr) + 4;
967                 *((unsigned short*)insns + 13) = 0xdeff;
968                 *((unsigned short*)insns + 14) = addr & 0x0000ffff;
969                 *((unsigned short*)insns + 15) = addr >> 16;
970                 if (!isThumb2(insn[0]))
971                 {
972                         addr = ((unsigned int)p->addr) + 2;
973                         *((unsigned short*)insns + 16) = (addr & 0x0000ffff) | 0x1;
974                         *((unsigned short*)insns + 17) = addr >> 16;
975                 }
976                 else {
977                         addr = ((unsigned int)p->addr) + 4;
978                         *((unsigned short*)insns + 16) = (addr & 0x0000ffff) | 0x1;
979                         *((unsigned short*)insns + 17) = addr >> 16;
980                 }
981         }
982         else {
983                 memcpy (insns, gen_insn_execbuf_thumb, 18 * 2);
984                 *((unsigned short*)insns + 13) = 0xdeff;
985                 if (!isThumb2(insn[0]))
986                 {
987                         addr = ((unsigned int)p->addr) + 2;
988                         *((unsigned short*)insns + 2) = insn[0];
989                         *((unsigned short*)insns + 16) = (addr & 0x0000ffff) | 0x1;
990                         *((unsigned short*)insns + 17) = addr >> 16;
991                 }
992                 else {
993                         addr = ((unsigned int)p->addr) + 4;
994                         insns[1] = insn[0];
995                         *((unsigned short*)insns + 16) = (addr & 0x0000ffff) | 0x1;
996                         *((unsigned short*)insns + 17) = addr >> 16;
997                 }
998         }
999         if (!write_proc_vm_atomic (task, (unsigned long) p->ainsn.insn_thumb, insns, 18 * 2))
1000         {
1001                 panic("failed to write memory %p!\n", p->ainsn.insn_thumb);
1002                 // Mr_Nobody: we have to panic, really??...
1003                 //free_insn_slot (&uprobe_insn_pages, task, p->ainsn.insn_thumb, 0);
1004                 //return -EINVAL;
1005         }
1006         return 0;
1007 }
1008
1009 static int check_validity_insn(struct kprobe *p, struct pt_regs *regs, struct task_struct *task)
1010 {
1011         struct kprobe *kp;
1012
1013         if (unlikely(thumb_mode(regs))) {
1014                 if (p->safe_thumb != -1) {
1015                         p->ainsn.insn = p->ainsn.insn_thumb;
1016                         list_for_each_entry_rcu(kp, &p->list, list) {
1017                                 kp->ainsn.insn = p->ainsn.insn_thumb;
1018                         }
1019                 } else {
1020                         printk("Error in %s at %d: we are in thumb mode (!) and check instruction was fail \
1021                                 (%0lX instruction at %p address)!\n", __FILE__, __LINE__, p->opcode, p->addr);
1022                         // Test case when we do our actions on already running application
1023                         arch_disarm_uprobe(p, task);
1024                         return -1;
1025                 }
1026         } else {
1027                 if (p->safe_arm != -1) {
1028                         p->ainsn.insn = p->ainsn.insn_arm;
1029                         list_for_each_entry_rcu(kp, &p->list, list) {
1030                                 kp->ainsn.insn = p->ainsn.insn_arm;
1031                         }
1032                 } else {
1033                         printk("Error in %s at %d: we are in arm mode (!) and check instruction was fail \
1034                                 (%0lX instruction at %p address)!\n", __FILE__, __LINE__, p->opcode, p->addr);
1035                         // Test case when we do our actions on already running application
1036                         arch_disarm_uprobe(p, task);
1037                         return -1;
1038                 }
1039         }
1040
1041         return 0;
1042 }
1043
1044 static int kprobe_trap_handler(struct pt_regs *regs, unsigned int instr)
1045 {
1046         int ret;
1047         unsigned long flags;
1048         local_irq_save(flags);
1049         ret = kprobe_handler(regs);
1050         local_irq_restore(flags);
1051         return ret;
1052 }
1053
1054 int kprobe_handler(struct pt_regs *regs)
1055 {
1056         int err_out = 0;
1057         char *msg_out = NULL;
1058         unsigned long user_m = user_mode(regs);
1059         pid_t tgid = (user_m) ? current->tgid : 0;
1060         kprobe_opcode_t *addr = (kprobe_opcode_t *) (regs->ARM_pc);
1061
1062         struct kprobe *p = NULL, *p_run = NULL;
1063         int ret = 0, retprobe = 0, reenter = 0;
1064         kprobe_opcode_t *ssaddr = 0;
1065         struct kprobe_ctlblk *kcb;
1066
1067 #ifdef SUPRESS_BUG_MESSAGES
1068         int swap_oops_in_progress;
1069         // oops_in_progress used to avoid BUG() messages that slow down kprobe_handler() execution
1070         swap_oops_in_progress = oops_in_progress;
1071         oops_in_progress = 1;
1072 #endif
1073 #ifdef OVERHEAD_DEBUG
1074         struct timeval swap_tv1;
1075         struct timeval swap_tv2;
1076 #define USEC_IN_SEC_NUM                         1000000
1077         do_gettimeofday(&swap_tv1);
1078 #endif
1079         preempt_disable();
1080
1081 //      printk("### kprobe_handler: task[tgid=%u (%s)] addr=%p\n", tgid, current->comm, addr);
1082         p = get_kprobe(addr, tgid);
1083
1084         if (user_m && p && (check_validity_insn(p, regs, current) != 0)) {
1085                 goto no_kprobe_live;
1086         }
1087
1088         /* We're in an interrupt, but this is clear and BUG()-safe. */
1089         kcb = get_kprobe_ctlblk ();
1090
1091         /* Check we're not actually recursing */
1092         // TODO: event is not saving in trace
1093         p_run = kprobe_running();
1094         if (p_run)
1095         {
1096                 DBPRINTF("lock???");
1097                 if (p)
1098                 {
1099                         if (!tgid && (addr == (kprobe_opcode_t *)kretprobe_trampoline)) {
1100                                 save_previous_kprobe(kcb, p_run);
1101                                 kcb->kprobe_status = KPROBE_REENTER;
1102                                 reenter = 1;
1103                         } else {
1104                                 /* We have reentered the kprobe_handler(), since
1105                                  * another probe was hit while within the handler.
1106                                  * We here save the original kprobes variables and
1107                                  * just single step on the instruction of the new probe
1108                                  * without calling any user handlers.
1109                                  */
1110                                 kprobes_inc_nmissed_count (p);
1111                                 prepare_singlestep (p, regs);
1112
1113                                 err_out = 0;
1114                                 goto out;
1115                         }
1116                 } else {
1117                         if(tgid) { //we can reenter probe upon uretprobe exception
1118                                 DBPRINTF ("check for UNDEF_INSTRUCTION %p\n", addr);
1119                                 // UNDEF_INSTRUCTION from user space
1120
1121                                 p = get_kprobe_by_insn_slot(addr, tgid, regs);
1122                                 if (p) {
1123                                         save_previous_kprobe(kcb, p_run);
1124                                         kcb->kprobe_status = KPROBE_REENTER;
1125                                         reenter = 1;
1126                                         retprobe = 1;
1127                                         DBPRINTF ("uretprobe %p\n", addr);
1128                                 }
1129                         }
1130                         if(!p) {
1131                                 p = p_run;
1132                                 DBPRINTF ("kprobe_running !!! p = 0x%p p->break_handler = 0x%p", p, p->break_handler);
1133                                 /*if (p->break_handler && p->break_handler(p, regs)) {
1134                                   DBPRINTF("kprobe_running !!! goto ss");
1135                                   goto ss_probe;
1136                                   } */
1137                                 DBPRINTF ("unknown uprobe at %p cur at %p/%p\n", addr, p->addr, p->ainsn.insn);
1138                                 if (tgid)
1139                                         ssaddr = p->ainsn.insn + UPROBES_TRAMP_SS_BREAK_IDX;
1140                                 else
1141                                         ssaddr = p->ainsn.insn + KPROBES_TRAMP_SS_BREAK_IDX;
1142                                 if (addr == ssaddr) {
1143                                         regs->ARM_pc = (unsigned long) (p->addr + 1);
1144                                         DBPRINTF ("finish step at %p cur at %p/%p, redirect to %lx\n", addr, p->addr, p->ainsn.insn, regs->ARM_pc);
1145                                         if (kcb->kprobe_status == KPROBE_REENTER) {
1146                                                 restore_previous_kprobe(kcb);
1147                                         } else {
1148                                                 reset_current_kprobe();
1149                                         }
1150                                 }
1151                                 DBPRINTF ("kprobe_running !!! goto no");
1152                                 ret = 1;
1153                                 /* If it's not ours, can't be delete race, (we hold lock). */
1154                                 DBPRINTF ("no_kprobe");
1155                                 goto no_kprobe;
1156                         }
1157                 }
1158         }
1159
1160         if (!p) {
1161                 if (tgid) {
1162                         DBPRINTF ("search UNDEF_INSTRUCTION %p\n", addr);
1163                         // UNDEF_INSTRUCTION from user space
1164
1165                         p = get_kprobe_by_insn_slot(addr, tgid, regs);
1166                         if (!p) {
1167                                 /* Not one of ours: let kernel handle it */
1168                                 DBPRINTF ("no_kprobe");
1169                                 goto no_kprobe;
1170                         }
1171                         retprobe = 1;
1172                         DBPRINTF ("uretprobe %p\n", addr);
1173                 } else {
1174                         /* Not one of ours: let kernel handle it */
1175                         DBPRINTF ("no_kprobe");
1176                         goto no_kprobe;
1177                 }
1178         }
1179         // restore opcode for thumb app
1180         if (user_mode( regs ) && thumb_mode( regs )) {
1181                 if (!isThumb2(p->opcode)) {
1182                         unsigned long tmp = p->opcode >> 16;
1183                         write_proc_vm_atomic(current, (unsigned long)((unsigned short*)p->addr + 1), &tmp, 2);
1184
1185                         // "2*sizeof(kprobe_opcode_t)" - strange. Should be "sizeof(kprobe_opcode_t)", need to test
1186                         flush_icache_range((unsigned int) p->addr, ((unsigned int)p->addr) + (2 * sizeof(kprobe_opcode_t)));
1187                 }
1188         }
1189         set_current_kprobe(p, NULL, NULL);
1190         if(!reenter)
1191                 kcb->kprobe_status = KPROBE_HIT_ACTIVE;
1192         if (retprobe) {         //(einsn == UNDEF_INSTRUCTION)
1193                 ret = trampoline_probe_handler (p, regs);
1194         } else if (p->pre_handler) {
1195                 ret = p->pre_handler (p, regs);
1196                 if(p->pre_handler != trampoline_probe_handler) {
1197                         reset_current_kprobe();
1198                 }
1199         }
1200
1201         if (ret) {
1202                 /* handler has already set things up, so skip ss setup */
1203                 err_out = 0;
1204                 goto out;
1205         }
1206
1207 no_kprobe:
1208         msg_out = "no_kprobe\n";
1209         err_out = 1;            // return with death
1210         goto out;
1211
1212 no_kprobe_live:
1213         msg_out = "no_kprobe live\n";
1214         err_out = 0;            // ok - life is life
1215         goto out;
1216
1217 out:
1218         preempt_enable_no_resched();
1219 #ifdef OVERHEAD_DEBUG
1220         do_gettimeofday(&swap_tv2);
1221         swap_sum_hit++;
1222         swap_sum_time += ((swap_tv2.tv_sec - swap_tv1.tv_sec) *  USEC_IN_SEC_NUM +
1223                 (swap_tv2.tv_usec - swap_tv1.tv_usec));
1224 #endif
1225 #ifdef SUPRESS_BUG_MESSAGES
1226         oops_in_progress = swap_oops_in_progress;
1227 #endif
1228
1229         if(msg_out) {
1230                 printk(msg_out);
1231         }
1232
1233         return err_out;
1234 }
1235
1236 int setjmp_pre_handler (struct kprobe *p, struct pt_regs *regs)
1237 {
1238         struct jprobe *jp = container_of (p, struct jprobe, kp);
1239         kprobe_pre_entry_handler_t pre_entry;
1240         entry_point_t entry;
1241
1242 # ifdef REENTER
1243 //      p = kprobe_running(regs);
1244 # endif
1245
1246         DBPRINTF ("pjp = 0x%p jp->entry = 0x%p", jp, jp->entry);
1247         entry = (entry_point_t) jp->entry;
1248         pre_entry = (kprobe_pre_entry_handler_t) jp->pre_entry;
1249         //if(!entry)
1250         //      DIE("entry NULL", regs)
1251         DBPRINTF ("entry = 0x%p jp->entry = 0x%p", entry, jp->entry);
1252
1253         //call handler for all kernel probes and user space ones which belong to current tgid
1254         if (!p->tgid || (p->tgid == current->tgid))
1255         {
1256                 if(!p->tgid && ((unsigned int)p->addr == sched_addr) && sched_rp) {
1257                     patch_suspended_all_task_ret_addr(sched_rp);
1258                 }
1259                 if (pre_entry)
1260                         p->ss_addr = (void *)pre_entry (jp->priv_arg, regs);
1261                 if (entry){
1262                         entry (regs->ARM_r0, regs->ARM_r1, regs->ARM_r2, regs->ARM_r3, regs->ARM_r4, regs->ARM_r5);
1263                 }
1264                 else {
1265                         if (p->tgid)
1266                                 dbi_arch_uprobe_return ();
1267                         else
1268                                 dbi_jprobe_return ();
1269                 }
1270         }
1271         else if (p->tgid)
1272                 dbi_arch_uprobe_return ();
1273
1274         prepare_singlestep (p, regs);
1275
1276         return 1;
1277 }
1278
1279 void dbi_jprobe_return (void)
1280 {
1281 }
1282
1283 void dbi_arch_uprobe_return (void)
1284 {
1285 }
1286
1287 int longjmp_break_handler (struct kprobe *p, struct pt_regs *regs)
1288 {
1289 # ifndef REENTER
1290         //kprobe_opcode_t insn = BREAKPOINT_INSTRUCTION;
1291         kprobe_opcode_t insns[2];
1292
1293         if (p->pid)
1294         {
1295                 insns[0] = BREAKPOINT_INSTRUCTION;
1296                 insns[1] = p->opcode;
1297                 //p->opcode = *p->addr;
1298                 if (read_proc_vm_atomic (current, (unsigned long) (p->addr), &(p->opcode), sizeof (p->opcode)) < sizeof (p->opcode))
1299                 {
1300                         printk ("ERROR[%lu]: failed to read vm of proc %s/%u addr %p.", nCount, current->comm, current->pid, p->addr);
1301                         return -1;
1302                 }
1303                 //*p->addr = BREAKPOINT_INSTRUCTION;
1304                 //*(p->addr+1) = p->opcode;
1305                 if (write_proc_vm_atomic (current, (unsigned long) (p->addr), insns, sizeof (insns)) < sizeof (insns))
1306                 {
1307                         printk ("ERROR[%lu]: failed to write vm of proc %s/%u addr %p.", nCount, current->comm, current->pid, p->addr);
1308                         return -1;
1309                 }
1310         }
1311         else
1312         {
1313                 DBPRINTF ("p->opcode = 0x%lx *p->addr = 0x%lx p->addr = 0x%p\n", p->opcode, *p->addr, p->addr);
1314                 *(p->addr + 1) = p->opcode;
1315                 p->opcode = *p->addr;
1316                 *p->addr = BREAKPOINT_INSTRUCTION;
1317
1318                 flush_icache_range ((unsigned int) p->addr, (unsigned int) (((unsigned int) p->addr) + (sizeof (kprobe_opcode_t) * 2)));
1319         }
1320
1321         reset_current_kprobe();
1322
1323 #endif //REENTER
1324
1325         return 0;
1326 }
1327
1328
1329 void arch_arm_kprobe (struct kprobe *p)
1330 {
1331         *p->addr = BREAKPOINT_INSTRUCTION;
1332         flush_icache_range ((unsigned long) p->addr, (unsigned long) p->addr + sizeof (kprobe_opcode_t));
1333 }
1334
1335 void arch_disarm_kprobe (struct kprobe *p)
1336 {
1337         *p->addr = p->opcode;
1338         flush_icache_range ((unsigned long) p->addr, (unsigned long) p->addr + sizeof (kprobe_opcode_t));
1339 }
1340
1341
1342 int trampoline_probe_handler (struct kprobe *p, struct pt_regs *regs)
1343 {
1344         struct kretprobe_instance *ri = NULL;
1345         struct hlist_head *head;
1346         struct hlist_node *node, *tmp;
1347         unsigned long flags, orig_ret_address = 0;
1348         unsigned long trampoline_address = (unsigned long) &kretprobe_trampoline;
1349
1350         struct kretprobe *crp = NULL;
1351         struct kprobe_ctlblk *kcb = get_kprobe_ctlblk ();
1352
1353         DBPRINTF ("start");
1354
1355         if (p && p->tgid){
1356                 // in case of user space retprobe trampoline is at the Nth instruction of US tramp
1357                 if (!thumb_mode( regs ))
1358                         trampoline_address = (unsigned long)(p->ainsn.insn + UPROBES_TRAMP_RET_BREAK_IDX);
1359                 else
1360                         trampoline_address = (unsigned long)(p->ainsn.insn) + 0x1b;
1361         }
1362
1363         spin_lock_irqsave (&kretprobe_lock, flags);
1364
1365         /*
1366          * We are using different hash keys (current and mm) for finding kernel
1367          * space and user space probes.  Kernel space probes can change mm field in
1368          * task_struct.  User space probes can be shared between threads of one
1369          * process so they have different current but same mm.
1370          */
1371         if (p && p->tgid) {
1372                 head = kretprobe_inst_table_head(current->mm);
1373         } else {
1374                 head = kretprobe_inst_table_head(current);
1375         }
1376
1377         /*
1378          * It is possible to have multiple instances associated with a given
1379          * task either because an multiple functions in the call path
1380          * have a return probe installed on them, and/or more then one
1381          * return probe was registered for a target function.
1382          *
1383          * We can handle this because:
1384          *     - instances are always inserted at the head of the list
1385          *     - when multiple return probes are registered for the same
1386          *       function, the first instance's ret_addr will point to the
1387          *       real return address, and all the rest will point to
1388          *       kretprobe_trampoline
1389          */
1390         hlist_for_each_entry_safe (ri, node, tmp, head, hlist)
1391         {
1392                 if (ri->task != current)
1393                         /* another task is sharing our hash bucket */
1394                         continue;
1395                 if (ri->rp && ri->rp->handler){
1396                         ri->rp->handler (ri, regs, ri->rp->priv_arg);
1397                 }
1398
1399                 orig_ret_address = (unsigned long) ri->ret_addr;
1400                 recycle_rp_inst (ri);
1401                 if (orig_ret_address != trampoline_address)
1402                         /*
1403                          * This is the real return address. Any other
1404                          * instances associated with this task are for
1405                          * other calls deeper on the call stack
1406                          */
1407                         break;
1408         }
1409         kretprobe_assert (ri, orig_ret_address, trampoline_address);
1410         //BUG_ON(!orig_ret_address || (orig_ret_address == trampoline_address));
1411         //E.G. Check this code in case of __switch_to function instrumentation -- currently this code generates dump in this case
1412         //if (trampoline_address != (unsigned long) &kretprobe_trampoline){
1413         //if (ri->rp2) BUG_ON (ri->rp2->kp.tgid == 0);
1414         //if (ri->rp) BUG_ON (ri->rp->kp.tgid == 0);
1415         //else if (ri->rp2) BUG_ON (ri->rp2->kp.tgid == 0);
1416         //}
1417         if ((ri->rp && ri->rp->kp.tgid) || (ri->rp2 && ri->rp2->kp.tgid))
1418                 BUG_ON (trampoline_address == (unsigned long) &kretprobe_trampoline);
1419
1420         regs->uregs[14] = orig_ret_address;
1421         DBPRINTF ("regs->uregs[14] = 0x%lx\n", regs->uregs[14]);
1422         DBPRINTF ("regs->uregs[15] = 0x%lx\n", regs->uregs[15]);
1423
1424         if (trampoline_address != (unsigned long) &kretprobe_trampoline)
1425         {
1426                 regs->uregs[15] = orig_ret_address;
1427         }else{
1428                 if (!thumb_mode( regs )) regs->uregs[15] += 4;
1429                 else regs->uregs[15] += 2;
1430         }
1431
1432         DBPRINTF ("regs->uregs[15] = 0x%lx\n", regs->uregs[15]);
1433
1434         if(p){ // ARM, MIPS, X86 user space
1435                 if (thumb_mode( regs ) && !(regs->uregs[14] & 0x01))
1436                 {
1437                         regs->ARM_cpsr &= 0xFFFFFFDF;
1438                 }else{
1439                         if (user_mode( regs ) && (regs->uregs[14] & 0x01))
1440                         {
1441                                 regs->ARM_cpsr |= 0x20;
1442                         }
1443                 }
1444
1445                 //TODO: test - enter function, delete us retprobe, exit function
1446                 // for user space retprobes only - deferred deletion
1447
1448                 if (trampoline_address != (unsigned long) &kretprobe_trampoline)
1449                 {
1450                         // if we are not at the end of the list and current retprobe should be disarmed
1451                         if (node && ri->rp2)
1452                         {
1453                                 struct hlist_node *current_node = node;
1454                                 crp = ri->rp2;
1455                                 /*sprintf(die_msg, "deferred disarm p->addr = %p [%lx %lx %lx]\n",
1456                                   crp->kp.addr, *kaddrs[0], *kaddrs[1], *kaddrs[2]);
1457                                   DIE(die_msg, regs); */
1458                                 // look for other instances for the same retprobe
1459                                 hlist_for_each_entry_safe (ri, node, tmp, head, hlist)
1460                                 {
1461                                         /*
1462                                          * Trying to find another retprobe instance associated with
1463                                          * the same retprobe.
1464                                          */
1465                                         if (ri->rp2 == crp && node != current_node)
1466                                                 break;
1467                                 }
1468
1469                                 if (!node)
1470                                 {
1471                                         // if there are no more instances for this retprobe
1472                                         // delete retprobe
1473                                         struct kprobe *is_p = &crp->kp;
1474                                         DBPRINTF ("defered retprobe deletion p->addr = %p", crp->kp.addr);
1475                                         /*
1476                                           If there is no any retprobe instances of this retprobe
1477                                           we can free the resources related to the probe.
1478                                          */
1479                                         if (!(hlist_unhashed(&is_p->is_hlist_arm))) {
1480                                                 hlist_del_rcu(&is_p->is_hlist_arm);
1481                                         }
1482                                         if (!(hlist_unhashed(&is_p->is_hlist_thumb))) {
1483                                                 hlist_del_rcu(&is_p->is_hlist_thumb);
1484                                         }
1485                                         unregister_uprobe (&crp->kp, current, 1);
1486                                         kfree (crp);
1487                                 }
1488                                 hlist_del(current_node);
1489                         }
1490                 }
1491
1492                 if (kcb->kprobe_status == KPROBE_REENTER) {
1493                         restore_previous_kprobe(kcb);
1494                 } else {
1495                         reset_current_kprobe();
1496                 }
1497         }
1498
1499         spin_unlock_irqrestore (&kretprobe_lock, flags);
1500
1501         /*
1502          * By returning a non-zero value, we are telling
1503          * kprobe_handler() that we don't want the post_handler
1504          * to run (and have re-enabled preemption)
1505          */
1506
1507         return 1;
1508 }
1509
1510 void  __arch_prepare_kretprobe (struct kretprobe *rp, struct pt_regs *regs)
1511 {
1512         struct kretprobe_instance *ri;
1513
1514         DBPRINTF ("start\n");
1515         //TODO: test - remove retprobe after func entry but before its exit
1516         if ((ri = get_free_rp_inst (rp)) != NULL)
1517         {
1518                 ri->rp = rp;
1519                 ri->rp2 = NULL;
1520                 ri->task = current;
1521                 ri->ret_addr = (kprobe_opcode_t *) regs->uregs[14];
1522
1523                 if (rp->kp.tgid)
1524                         if (!thumb_mode( regs ))
1525                                 regs->uregs[14] = (unsigned long) (rp->kp.ainsn.insn + UPROBES_TRAMP_RET_BREAK_IDX);
1526                         else
1527                                 regs->uregs[14] = (unsigned long) (rp->kp.ainsn.insn) + 0x1b;
1528
1529                 else    /* Replace the return addr with trampoline addr */
1530                         regs->uregs[14] = (unsigned long) &kretprobe_trampoline;
1531
1532 //              DBPRINTF ("ret addr set to %p->%lx\n", ri->ret_addr, regs->uregs[14]);
1533                 add_rp_inst (ri);
1534         }
1535         else {
1536                 DBPRINTF ("WARNING: missed retprobe %p\n", rp->kp.addr);
1537                 rp->nmissed++;
1538         }
1539 }
1540
1541
1542 int asm_init_module_dependencies()
1543 {
1544         //No module dependencies
1545         return 0;
1546 }
1547
1548
1549 void (* do_kpro)(struct undef_hook *);
1550 void (* undo_kpro)(struct undef_hook *);
1551
1552 // kernel probes hook
1553 struct undef_hook undef_ho_k = {
1554     .instr_mask = 0xffffffff,
1555     .instr_val  = BREAKPOINT_INSTRUCTION,
1556     .cpsr_mask  = MODE_MASK,
1557     .cpsr_val   = SVC_MODE,
1558     .fn         = kprobe_trap_handler
1559 };
1560
1561 // userspace probes hook (arm)
1562 struct undef_hook undef_ho_u = {
1563     .instr_mask = 0xffffffff,
1564     .instr_val  = BREAKPOINT_INSTRUCTION,
1565     .cpsr_mask  = MODE_MASK,
1566     .cpsr_val   = USR_MODE,
1567     .fn         = kprobe_trap_handler
1568 };
1569
1570 // userspace probes hook (thumb)
1571 struct undef_hook undef_ho_u_t = {
1572     .instr_mask = 0xffffffff,
1573     .instr_val  = BREAKPOINT_INSTRUCTION & 0x0000ffff,
1574     .cpsr_mask  = MODE_MASK,
1575     .cpsr_val   = USR_MODE,
1576     .fn         = kprobe_trap_handler
1577 };
1578
1579 int __init arch_init_kprobes (void)
1580 {
1581         unsigned int do_bp_handler = 0;
1582         int ret = 0;
1583
1584         if (arch_init_module_dependencies())
1585         {
1586                 DBPRINTF ("Unable to init module dependencies\n");
1587                 return -1;
1588         }
1589
1590         do_bp_handler = (unsigned int) kallsyms_search ("do_undefinstr");
1591         if (do_bp_handler == 0) {
1592                 DBPRINTF("no do_undefinstr symbol found!");
1593                 return -1;
1594         }
1595         arr_traps_template[NOTIFIER_CALL_CHAIN_INDEX] = arch_construct_brunch ((unsigned int)kprobe_handler, do_bp_handler + NOTIFIER_CALL_CHAIN_INDEX * 4, 1);
1596         // Register hooks (kprobe_handler)
1597         do_kpro = (void *)kallsyms_search ("register_undef_hook");
1598         if (do_kpro == 0) {
1599                 printk("no register_undef_hook symbol found!\n");
1600                 return -1;
1601         }
1602
1603         // Unregister hooks (kprobe_handler)
1604         undo_kpro = (void *)kallsyms_search ("unregister_undef_hook");
1605         if (undo_kpro == 0) {
1606                 printk("no unregister_undef_hook symbol found!\n");
1607                 return -1;
1608         }
1609
1610         do_kpro(&undef_ho_k);
1611         do_kpro(&undef_ho_u);
1612         do_kpro(&undef_ho_u_t);
1613         if ((ret = dbi_register_kprobe (&trampoline_p)) != 0) {
1614                 //dbi_unregister_jprobe(&do_exit_p, 0);
1615                 return ret;
1616         }
1617         return ret;
1618 }
1619
1620 void __exit dbi_arch_exit_kprobes (void)
1621 {
1622         undo_kpro(&undef_ho_u_t);
1623         undo_kpro(&undef_ho_u);
1624         undo_kpro(&undef_ho_k);
1625 }
1626
1627 //EXPORT_SYMBOL_GPL (dbi_arch_uprobe_return);
1628 //EXPORT_SYMBOL_GPL (dbi_arch_exit_kprobes);