kprobe/arch/asm-arm/dbi_kprobes.c

   1 /*
   2  *  Dynamic Binary Instrumentation Module based on KProbes
   3  *  modules/kprobe/arch/asm-arm/dbi_kprobes.c
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  18  *
  19  * Copyright (C) Samsung Electronics, 2006-2010
  20  *
  21  * 2006-2007    Ekaterina Gorelkina <e.gorelkina@samsung.com>: initial implementation for ARM/MIPS
  22  * 2008-2009    Alexey Gerenkov <a.gerenkov@samsung.com> User-Space
  23  *              Probes initial implementation; Support x86.
  24  * 2010         Ekaterina Gorelkina <e.gorelkina@samsung.com>: redesign module for separating core and arch parts
  25  *
  26  * 2010-2011    Alexander Shirshikov <a.shirshikov@samsung.com>: initial implementation for Thumb
  27  * 2012         Stanislav Andreev <s.andreev@samsung.com>: added time debug profiling support; BUG() message fix
  28  */
  29
  30 #include <linux/module.h>
  31 #include <linux/mm.h>
  32
  33 #include "dbi_kprobes.h"
  34 #include "../dbi_kprobes.h"
  35
  36 #include "../../dbi_kdebug.h"
  37 #include "../../dbi_insn_slots.h"
  38 #include "../../dbi_kprobes_deps.h"
  39 #include "../../dbi_uprobes.h"
  40
  41 #include <asm/cacheflush.h>
  42
  43 #ifdef OVERHEAD_DEBUG
  44 #include <linux/time.h>
  45 #endif
  46
  47 #define SUPRESS_BUG_MESSAGES
  48
  49 unsigned int *arr_traps_original;
  50
  51 extern unsigned int *sched_addr;
  52 extern unsigned int *fork_addr;
  53
  54 extern struct kprobe * per_cpu__current_kprobe;
  55 extern spinlock_t kretprobe_lock;
  56 extern struct kretprobe *sched_rp;
  57
  58 extern struct hlist_head kprobe_insn_pages;
  59 extern struct hlist_head uprobe_insn_pages;
  60
  61 extern unsigned long (*kallsyms_search) (const char *name);
  62
  63 extern struct kprobe *kprobe_running (void);
  64 extern struct kprobe_ctlblk *get_kprobe_ctlblk (void);
  65 extern void reset_current_kprobe (void);
  66 extern struct kprobe * current_kprobe;
  67
  68 #ifdef OVERHEAD_DEBUG
  69 unsigned long swap_sum_time = 0;
  70 unsigned long swap_sum_hit = 0;
  71 EXPORT_SYMBOL_GPL (swap_sum_time);
  72 EXPORT_SYMBOL_GPL (swap_sum_hit);
  73 #endif
  74
  75 unsigned int arr_traps_template[] = {
  76                 0xe1a0c00d,    // mov          ip, sp
  77                 0xe92dd800,    // stmdb        sp!, {fp, ip, lr, pc}
  78                 0xe24cb004,    // sub          fp, ip, #4      ; 0x4
  79                 0x00000000,    // b
  80                 0xe3500000,    // cmp          r0, #0  ; 0x0
  81                 0xe89da800,    // ldmia        sp, {fp, sp, pc}
  82                 0x00000000,    // nop
  83                 0xffffffff     // end
  84 };
  85
  86
  87 struct kprobe trampoline_p =
  88 {
  89         .addr = (kprobe_opcode_t *) & kretprobe_trampoline,
  90         .pre_handler = trampoline_probe_handler
  91 };
  92
  93
  94 static struct kprobe *my_p[0xffff];
  95 static struct task_struct *my_task[0xffff];
  96 static int my_atomic[0xffff];
  97 static int my_probe = 0;
  98
  99
 100 void arch_arm_reinit()
 101 {
 102         my_probe = 0;
 103 }
 104
 105
 106 // is instruction Thumb2 and NOT a branch, etc...
 107 int isThumb2(kprobe_opcode_t insn)
 108 {
 109         if((    (insn & 0xf800) == 0xe800 ||
 110                 (insn & 0xf800) == 0xf000 ||
 111                 (insn & 0xf800) == 0xf800)) return 1;
 112         return 0;
 113 }
 114
 115
 116 int prep_pc_dep_insn_execbuf (kprobe_opcode_t * insns, kprobe_opcode_t insn, int uregs)
 117 {
 118         int i;
 119
 120         if (uregs & 0x10)
 121         {
 122                 int reg_mask = 0x1;
 123                 //search in reg list
 124                 for (i = 0; i < 13; i++, reg_mask <<= 1)
 125                 {
 126                         if (!(insn & reg_mask))
 127                                 break;
 128                 }
 129         }
 130         else
 131         {
 132                 for (i = 0; i < 13; i++)
 133                 {
 134                         //              DBPRINTF("prep_pc_dep_insn_execbuf: check R%d/%d, changing regs %x in %x",
 135                         //                              i, ARM_INSN_REG_RN(insn), uregs, insn);
 136                         if ((uregs & 0x1) && (ARM_INSN_REG_RN (insn) == i))
 137                                 continue;
 138                         if ((uregs & 0x2) && (ARM_INSN_REG_RD (insn) == i))
 139                                 continue;
 140                         if ((uregs & 0x4) && (ARM_INSN_REG_RS (insn) == i))
 141                                 continue;
 142                         if ((uregs & 0x8) && (ARM_INSN_REG_RM (insn) == i))
 143                                 continue;
 144                         break;
 145                 }
 146         }
 147         if (i == 13)
 148         {
 149                 DBPRINTF ("there are no free register %x in insn %lx!", uregs, insn);
 150                 return -EINVAL;
 151         }
 152         DBPRINTF ("prep_pc_dep_insn_execbuf: using R%d, changing regs %x", i, uregs);
 153
 154         // set register to save
 155         ARM_INSN_REG_SET_RD (insns[0], i);
 156         // set register to load address to
 157         ARM_INSN_REG_SET_RD (insns[1], i);
 158         // set instruction to execute and patch it
 159         if (uregs & 0x10)
 160         {
 161                 ARM_INSN_REG_CLEAR_MR (insn, 15);
 162                 ARM_INSN_REG_SET_MR (insn, i);
 163         }
 164         else
 165         {
 166                 if ((uregs & 0x1) && (ARM_INSN_REG_RN (insn) == 15))
 167                         ARM_INSN_REG_SET_RN (insn, i);
 168                 if ((uregs & 0x2) && (ARM_INSN_REG_RD (insn) == 15))
 169                         ARM_INSN_REG_SET_RD (insn, i);
 170                 if ((uregs & 0x4) && (ARM_INSN_REG_RS (insn) == 15))
 171                         ARM_INSN_REG_SET_RS (insn, i);
 172                 if ((uregs & 0x8) && (ARM_INSN_REG_RM (insn) == 15))
 173                         ARM_INSN_REG_SET_RM (insn, i);
 174         }
 175         insns[UPROBES_TRAMP_INSN_IDX] = insn;
 176         // set register to restore
 177         ARM_INSN_REG_SET_RD (insns[3], i);
 178         return 0;
 179 }
 180
 181
 182
 183 int prep_pc_dep_insn_execbuf_thumb (kprobe_opcode_t * insns, kprobe_opcode_t insn, int uregs)
 184 {
 185         unsigned char mreg = 0;
 186         unsigned char reg = 0;
 187
 188
 189         if (THUMB_INSN_MATCH (APC, insn) || THUMB_INSN_MATCH (LRO3, insn))
 190         {
 191                 reg = ((insn & 0xffff) & uregs) >> 8;
 192         }else{
 193                 if (THUMB_INSN_MATCH (MOV3, insn))
 194                 {
 195                         if (((((unsigned char) insn) & 0xff) >> 3) == 15)
 196                                 reg = (insn & 0xffff) & uregs;
 197                         else
 198                                 return 0;
 199                 }else{
 200                         if (THUMB2_INSN_MATCH (ADR, insn))
 201                         {
 202                                 reg = ((insn >> 16) & uregs) >> 8;
 203                                 if (reg == 15) return 0;
 204                         }else{
 205                                 if (THUMB2_INSN_MATCH (LDRW, insn) || THUMB2_INSN_MATCH (LDRW1, insn) ||
 206                                     THUMB2_INSN_MATCH (LDRHW, insn) || THUMB2_INSN_MATCH (LDRHW1, insn) ||
 207                                     THUMB2_INSN_MATCH (LDRWL, insn))
 208                                 {
 209                                         reg = ((insn >> 16) & uregs) >> 12;
 210                                         if (reg == 15) return 0;
 211                                 }else{
 212 // LDRB.W PC, [PC, #immed] => PLD [PC, #immed], so Rt == PC is skipped
 213                                         if (THUMB2_INSN_MATCH (LDRBW, insn) || THUMB2_INSN_MATCH (LDRBW1, insn) || THUMB2_INSN_MATCH (LDREX, insn))
 214                                         {
 215                                                 reg = ((insn >> 16) & uregs) >> 12;
 216                                         }else{
 217                                                 if (THUMB2_INSN_MATCH (DP, insn))
 218                                                 {
 219                                                         reg = ((insn >> 16) & uregs) >> 12;
 220                                                         if (reg == 15) return 0;
 221                                                 }else{
 222                                                         if (THUMB2_INSN_MATCH (RSBW, insn))
 223                                                         {
 224                                                                 reg = ((insn >> 12) & uregs) >> 8;
 225                                                                 if (reg == 15) return 0;
 226                                                         }else{
 227                                                                 if (THUMB2_INSN_MATCH (RORW, insn))
 228                                                                 {
 229                                                                         reg = ((insn >> 12) & uregs) >> 8;
 230                                                                         if (reg == 15) return 0;
 231                                                                 }else{
 232                                                                         if (THUMB2_INSN_MATCH (ROR, insn) || THUMB2_INSN_MATCH (LSLW1, insn) || THUMB2_INSN_MATCH (LSLW2, insn) || THUMB2_INSN_MATCH (LSRW1, insn) || THUMB2_INSN_MATCH (LSRW2, insn))
 233                                                                         {
 234                                                                                 reg = ((insn >> 12) & uregs) >> 8;
 235                                                                                 if (reg == 15) return 0;
 236                                                                         }else{
 237                                                                                 if (THUMB2_INSN_MATCH (TEQ1, insn) || THUMB2_INSN_MATCH (TST1, insn))
 238                                                                                 {
 239                                                                                         reg = 15;
 240                                                                                 }else{
 241                                                                                         if (THUMB2_INSN_MATCH (TEQ2, insn) || THUMB2_INSN_MATCH (TST2, insn))
 242                                                                                         {
 243                                                                                                 reg = THUMB2_INSN_REG_RM(insn);
 244                                                                                         }
 245                                                                                 }
 246                                                                         }
 247                                                                 }
 248                                                         }
 249                                                 }
 250                                         }
 251                                 }
 252                         }
 253                 }
 254         }
 255
 256         if ((   THUMB2_INSN_MATCH (STRW, insn) || THUMB2_INSN_MATCH (STRBW, insn) || THUMB2_INSN_MATCH (STRD, insn) || \
 257                 THUMB2_INSN_MATCH (STRHT, insn) || THUMB2_INSN_MATCH (STRT, insn) || THUMB2_INSN_MATCH (STRHW1, insn) || \
 258                 THUMB2_INSN_MATCH (STRHW, insn)) && THUMB2_INSN_REG_RT(insn) == 15)
 259         {
 260                 reg = THUMB2_INSN_REG_RT(insn);
 261         }
 262
 263         if (reg == 6 || reg == 7)
 264         {
 265                 *((unsigned short*)insns + 0) = (*((unsigned short*)insns + 0) & 0x00ff) | ((1 << mreg) | (1 << (mreg + 1)));
 266                 *((unsigned short*)insns + 1) = (*((unsigned short*)insns + 1) & 0xf8ff) | (mreg << 8);
 267                 *((unsigned short*)insns + 2) = (*((unsigned short*)insns + 2) & 0xfff8) | (mreg + 1);
 268                 *((unsigned short*)insns + 3) = (*((unsigned short*)insns + 3) & 0xffc7) | (mreg << 3);
 269                 *((unsigned short*)insns + 7) = (*((unsigned short*)insns + 7) & 0xf8ff) | (mreg << 8);
 270                 *((unsigned short*)insns + 8) = (*((unsigned short*)insns + 8) & 0xffc7) | (mreg << 3);
 271                 *((unsigned short*)insns + 9) = (*((unsigned short*)insns + 9) & 0xffc7) | ((mreg + 1) << 3);
 272                 *((unsigned short*)insns + 10) = (*((unsigned short*)insns + 10) & 0x00ff) | (( 1 << mreg) | (1 << (mreg + 1)));
 273         }
 274
 275
 276         if (THUMB_INSN_MATCH (APC, insn))
 277         {
 278 //              ADD Rd, PC, #immed_8*4 -> ADD Rd, SP, #immed_8*4
 279                 *((unsigned short*)insns + 4) = ((insn & 0xffff) | 0x800);                              // ADD Rd, SP, #immed_8*4
 280         }else{
 281                 if (THUMB_INSN_MATCH (LRO3, insn))
 282                 {
 283 //                      LDR Rd, [PC, #immed_8*4] -> LDR Rd, [SP, #immed_8*4]
 284                         *((unsigned short*)insns + 4) = ((insn & 0xffff) + 0x5000);                     // LDR Rd, [SP, #immed_8*4]
 285                 }else{
 286                         if (THUMB_INSN_MATCH (MOV3, insn))
 287                         {
 288 //                              MOV Rd, PC -> MOV Rd, SP
 289                                 *((unsigned short*)insns + 4) = ((insn & 0xffff) ^ 0x10);               // MOV Rd, SP
 290                         }else{
 291                                 if (THUMB2_INSN_MATCH (ADR, insn))
 292                                 {
 293 //                                      ADDW Rd, PC, #imm -> ADDW Rd, SP, #imm
 294                                         insns[2] = (insn & 0xfffffff0) | 0x0d;                          // ADDW Rd, SP, #imm
 295                                 }else{
 296                                         if (THUMB2_INSN_MATCH (LDRW, insn) || THUMB2_INSN_MATCH (LDRBW, insn) ||
 297                                             THUMB2_INSN_MATCH (LDRHW, insn))
 298                                         {
 299 //                                              LDR.W Rt, [PC, #-<imm_12>] -> LDR.W Rt, [SP, #-<imm_8>]
 300 //                                              !!!!!!!!!!!!!!!!!!!!!!!!
 301 //                                              !!! imm_12 vs. imm_8 !!!
 302 //                                              !!!!!!!!!!!!!!!!!!!!!!!!
 303                                                 insns[2] = (insn & 0xf0fffff0) | 0x0c00000d;            // LDR.W Rt, [SP, #-<imm_8>]
 304                                         }else{
 305                                                 if (THUMB2_INSN_MATCH (LDRW1, insn) || THUMB2_INSN_MATCH (LDRBW1, insn) ||
 306                                                     THUMB2_INSN_MATCH (LDRHW1, insn) || THUMB2_INSN_MATCH (LDRD, insn) || THUMB2_INSN_MATCH (LDRD1, insn) ||
 307                                                     THUMB2_INSN_MATCH (LDREX, insn))
 308                                                 {
 309 //                                                      LDRx.W Rt, [PC, #+<imm_12>] -> LDRx.W Rt, [SP, #+<imm_12>] (+/-imm_8 for LDRD Rt, Rt2, [PC, #<imm_8>]
 310                                                         insns[2] = (insn & 0xfffffff0) | 0xd;                                                                                                   // LDRx.W Rt, [SP, #+<imm_12>]
 311                                                 }else{
 312                                                         if (THUMB2_INSN_MATCH (MUL, insn))
 313                                                         {
 314                                                                 insns[2] = (insn & 0xfff0ffff) | 0x000d0000;                                                                                    // MUL Rd, Rn, SP
 315                                                         }else{  if (THUMB2_INSN_MATCH (DP, insn))
 316                                                                 {
 317                                                                         if (THUMB2_INSN_REG_RM(insn) == 15) insns[2] = (insn & 0xfff0ffff) | 0x000d0000;                                        // DP Rd, Rn, PC
 318                                                                         else if (THUMB2_INSN_REG_RN(insn) == 15) insns[2] = (insn & 0xfffffff0) | 0xd;                                          // DP Rd, PC, Rm
 319                                                                 }else{  if (THUMB2_INSN_MATCH (LDRWL, insn))
 320                                                                         {
 321 //                                                                              LDRx.W Rt, [PC, #<imm_12>] -> LDRx.W Rt, [SP, #+<imm_12>] (+/-imm_8 for LDRD Rt, Rt2, [PC, #<imm_8>]
 322                                                                                 insns[2] = (insn & 0xfffffff0) | 0xd;                                                                           // LDRx.W Rt, [SP, #+<imm_12>]
 323                                                                         }else{  if (THUMB2_INSN_MATCH (RSBW, insn))
 324                                                                                 {
 325                                                                                         insns[2] = (insn & 0xfffffff0) | 0xd;                                                                   // RSB{S}.W Rd, PC, #<const> -> RSB{S}.W Rd, SP, #<const>
 326                                                                                 }else{  if (THUMB2_INSN_MATCH (RORW, insn) || THUMB2_INSN_MATCH (LSLW1, insn) || THUMB2_INSN_MATCH (LSRW1, insn))
 327                                                                                         {
 328                                                                                                 if ((THUMB2_INSN_REG_RM(insn) == 15) && (THUMB2_INSN_REG_RN(insn) == 15))
 329                                                                                                 {
 330                                                                                                         insns[2] = (insn & 0xfffdfffd);                                                         // ROR.W Rd, PC, PC
 331                                                                                                 }else if (THUMB2_INSN_REG_RM(insn) == 15) insns[2] = (insn & 0xfff0ffff) | 0xd0000;             // ROR.W Rd, Rn, PC
 332                                                                                                         else if (THUMB2_INSN_REG_RN(insn) == 15) insns[2] = (insn & 0xfffffff0) | 0xd;          // ROR.W Rd, PC, Rm
 333                                                                                         }else{  if (THUMB2_INSN_MATCH (ROR, insn) || THUMB2_INSN_MATCH (LSLW2, insn) || THUMB2_INSN_MATCH (LSRW2, insn))
 334                                                                                                 {
 335                                                                                                         insns[2] = (insn & 0xfff0ffff) | 0xd0000;                                               // ROR{S} Rd, PC, #<const> -> ROR{S} Rd, SP, #<const>
 336                                                                                                 }
 337                                                                                         }
 338                                                                                 }
 339                                                                         }
 340                                                                 }
 341                                                         }
 342                                                 }
 343                                         }
 344                                 }
 345                         }
 346                 }
 347         }
 348
 349         if (THUMB2_INSN_MATCH (STRW, insn) || THUMB2_INSN_MATCH (STRBW, insn))
 350         {
 351                 insns[2] = (insn & 0xfff0ffff) | 0x000d0000;                                                            // STRx.W Rt, [Rn, SP]
 352         }else{
 353                 if (THUMB2_INSN_MATCH (STRD, insn) || THUMB2_INSN_MATCH (STRHT, insn) || THUMB2_INSN_MATCH (STRT, insn) || THUMB2_INSN_MATCH (STRHW1, insn))
 354                 {
 355                         if (THUMB2_INSN_REG_RN(insn) == 15)
 356                         {
 357                                 insns[2] = (insn & 0xfffffff0) | 0xd;                                                   // STRD/T/HT{.W} Rt, [SP, ...]
 358                         }else{
 359                                 insns[2] = insn;
 360                         }
 361                 }else{
 362                         if (THUMB2_INSN_MATCH (STRHW, insn) && (THUMB2_INSN_REG_RN(insn) == 15))
 363                         {
 364                                 if (THUMB2_INSN_REG_RN(insn) == 15)
 365                                 {
 366                                         insns[2] = (insn & 0xf0fffff0) | 0x0c00000d;                                    // STRH.W Rt, [SP, #-<imm_8>]
 367                                 }else{
 368                                         insns[2] = insn;
 369                                 }
 370                         }
 371                 }
 372         }
 373
 374 //       STRx PC, xxx
 375         if ((reg == 15) && THUMB2_INSN_MATCH (STRW, insn)   || \
 376                            THUMB2_INSN_MATCH (STRBW, insn)  || \
 377                            THUMB2_INSN_MATCH (STRD, insn)   || \
 378                            THUMB2_INSN_MATCH (STRHT, insn)  || \
 379                            THUMB2_INSN_MATCH (STRT, insn)   || \
 380                            THUMB2_INSN_MATCH (STRHW1, insn) || \
 381                            THUMB2_INSN_MATCH (STRHW, insn) )
 382         {
 383                 insns[2] = (insns[2] & 0x0fffffff) | 0xd0000000;
 384         }
 385
 386
 387
 388         if (THUMB2_INSN_MATCH (TEQ1, insn) || THUMB2_INSN_MATCH (TST1, insn))
 389         {
 390                 insns[2] = (insn & 0xfffffff0) | 0xd;                                                                   // TEQ SP, #<const>
 391         }else{  if (THUMB2_INSN_MATCH (TEQ2, insn) || THUMB2_INSN_MATCH (TST2, insn))
 392                 {
 393                         if ((THUMB2_INSN_REG_RN(insn) == 15) && (THUMB2_INSN_REG_RM(insn) == 15))
 394                         {
 395                                 insns[2] = (insn & 0xfffdfffd);                                                         // TEQ/TST PC, PC
 396                         }else   if (THUMB2_INSN_REG_RM(insn) == 15) insns[2] = (insn & 0xfff0ffff) | 0xd0000;           // TEQ/TST Rn, PC
 397                                 else if (THUMB2_INSN_REG_RN(insn) == 15) insns[2] = (insn & 0xfffffff0) | 0xd;          // TEQ/TST PC, Rm
 398                 }
 399         }
 400
 401         return 0;
 402 }
 403
 404
 405
 406 int arch_check_insn_arm (struct arch_specific_insn *ainsn)
 407 {
 408         int ret = 0;
 409         kprobe_opcode_t *insn;
 410
 411         // check instructions that can change PC by nature
 412         if (    ARM_INSN_MATCH (UNDEF, ainsn->insn_arm[0]) ||
 413                 ARM_INSN_MATCH (AUNDEF, ainsn->insn_arm[0]) ||
 414                 ARM_INSN_MATCH (SWI, ainsn->insn_arm[0]) ||
 415                 ARM_INSN_MATCH (BREAK, ainsn->insn_arm[0]) ||
 416                 ARM_INSN_MATCH (B, ainsn->insn_arm[0]) ||
 417                 ARM_INSN_MATCH (BL, ainsn->insn_arm[0]) ||
 418                 ARM_INSN_MATCH (BLX1, ainsn->insn_arm[0]) ||
 419                 ARM_INSN_MATCH (BLX2, ainsn->insn_arm[0]) ||
 420                 ARM_INSN_MATCH (BX, ainsn->insn_arm[0]) ||
 421                 ARM_INSN_MATCH (BXJ, ainsn->insn_arm[0]))
 422         {
 423                 DBPRINTF ("Bad insn arch_check_insn_arm: %lx\n", ainsn->insn_arm[0]);
 424                 ret = -EFAULT;
 425         }
 426 #ifndef CONFIG_CPU_V7
 427         // check instructions that can write result to PC
 428         else if ((ARM_INSN_MATCH (DPIS, ainsn->insn_arm[0]) ||
 429                                 ARM_INSN_MATCH (DPRS, ainsn->insn_arm[0]) ||
 430                                 ARM_INSN_MATCH (DPI, ainsn->insn_arm[0]) ||
 431                                 ARM_INSN_MATCH (LIO, ainsn->insn_arm[0]) ||
 432                                 ARM_INSN_MATCH (LRO, ainsn->insn_arm[0])) &&
 433                         (ARM_INSN_REG_RD (ainsn->insn_arm[0]) == 15))
 434         {
 435                 DBPRINTF ("Bad arch_check_insn_arm: %lx\n", ainsn->insn_arm[0]);
 436                 ret = -EFAULT;
 437         }
 438 #endif // CONFIG_CPU_V7
 439         // check special instruction loads store multiple registers
 440         else if ((ARM_INSN_MATCH (LM, ainsn->insn_arm[0]) || ARM_INSN_MATCH (SM, ainsn->insn_arm[0])) &&
 441                         // store pc or load to pc
 442                         (ARM_INSN_REG_MR (ainsn->insn_arm[0], 15) ||
 443                          // store/load with pc update
 444                          ((ARM_INSN_REG_RN (ainsn->insn_arm[0]) == 15) && (ainsn->insn_arm[0] & 0x200000))))
 445         {
 446                 DBPRINTF ("Bad insn arch_check_insn_arm: %lx\n", ainsn->insn_arm[0]);
 447                 ret = -EFAULT;
 448         }
 449         return ret;
 450 }
 451
 452 int arch_check_insn_thumb (struct arch_specific_insn *ainsn)
 453 {
 454         int ret = 0;
 455
 456         // check instructions that can change PC
 457         if (    THUMB_INSN_MATCH (UNDEF, ainsn->insn_thumb[0]) ||
 458                 THUMB_INSN_MATCH (SWI, ainsn->insn_thumb[0]) ||
 459                 THUMB_INSN_MATCH (BREAK, ainsn->insn_thumb[0]) ||
 460                 THUMB2_INSN_MATCH (BL, ainsn->insn_thumb[0]) ||
 461                 THUMB_INSN_MATCH (B1, ainsn->insn_thumb[0]) ||
 462                 THUMB_INSN_MATCH (B2, ainsn->insn_thumb[0]) ||
 463                 THUMB2_INSN_MATCH (B1, ainsn->insn_thumb[0]) ||
 464                 THUMB2_INSN_MATCH (B2, ainsn->insn_thumb[0]) ||
 465                 THUMB2_INSN_MATCH (BLX1, ainsn->insn_thumb[0]) ||
 466                 THUMB_INSN_MATCH (BLX2, ainsn->insn_thumb[0]) ||
 467                 THUMB_INSN_MATCH (BX, ainsn->insn_thumb[0]) ||
 468                 THUMB2_INSN_MATCH (BXJ, ainsn->insn_thumb[0]) ||
 469                 (THUMB2_INSN_MATCH (ADR, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RD(ainsn->insn_thumb[0]) == 15) ||
 470                 (THUMB2_INSN_MATCH (LDRW, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RT(ainsn->insn_thumb[0]) == 15) ||
 471                 (THUMB2_INSN_MATCH (LDRW1, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RT(ainsn->insn_thumb[0]) == 15) ||
 472                 (THUMB2_INSN_MATCH (LDRHW, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RT(ainsn->insn_thumb[0]) == 15) ||
 473                 (THUMB2_INSN_MATCH (LDRHW1, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RT(ainsn->insn_thumb[0]) == 15) ||
 474                 (THUMB2_INSN_MATCH (LDRWL, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RT(ainsn->insn_thumb[0]) == 15) ||
 475                 THUMB2_INSN_MATCH (LDMIA, ainsn->insn_thumb[0]) ||
 476                 THUMB2_INSN_MATCH (LDMDB, ainsn->insn_thumb[0]) ||
 477                 (THUMB2_INSN_MATCH (DP, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RD(ainsn->insn_thumb[0]) == 15) ||
 478                 (THUMB2_INSN_MATCH (RSBW, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RD(ainsn->insn_thumb[0]) == 15) ||
 479                 (THUMB2_INSN_MATCH (RORW, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RD(ainsn->insn_thumb[0]) == 15) ||
 480                 (THUMB2_INSN_MATCH (ROR, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RD(ainsn->insn_thumb[0]) == 15) ||
 481                 (THUMB2_INSN_MATCH (LSLW1, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RD(ainsn->insn_thumb[0]) == 15) ||
 482                 (THUMB2_INSN_MATCH (LSLW2, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RD(ainsn->insn_thumb[0]) == 15) ||
 483                 (THUMB2_INSN_MATCH (LSRW1, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RD(ainsn->insn_thumb[0]) == 15) ||
 484                 (THUMB2_INSN_MATCH (LSRW2, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RD(ainsn->insn_thumb[0]) == 15) ||
 485 /* skip PC, #-imm12 -> SP, #-imm8 and Tegra-hanging instructions */
 486                 (THUMB2_INSN_MATCH (STRW1, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RN(ainsn->insn_thumb[0]) == 15) ||
 487                 (THUMB2_INSN_MATCH (STRBW1, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RN(ainsn->insn_thumb[0]) == 15) ||
 488                 (THUMB2_INSN_MATCH (STRHW1, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RN(ainsn->insn_thumb[0]) == 15) ||
 489                 (THUMB2_INSN_MATCH (STRW, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RN(ainsn->insn_thumb[0]) == 15) ||
 490                 (THUMB2_INSN_MATCH (STRHW, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RN(ainsn->insn_thumb[0]) == 15) ||
 491                 (THUMB2_INSN_MATCH (LDRW, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RN(ainsn->insn_thumb[0]) == 15) ||
 492                 (THUMB2_INSN_MATCH (LDRBW, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RN(ainsn->insn_thumb[0]) == 15) ||
 493                 (THUMB2_INSN_MATCH (LDRHW, ainsn->insn_thumb[0]) && THUMB2_INSN_REG_RN(ainsn->insn_thumb[0]) == 15) ||
 494 /* skip STRDx/LDRDx Rt, Rt2, [Rd, ...] */
 495                 (THUMB2_INSN_MATCH (LDRD, ainsn->insn_thumb[0]) || THUMB2_INSN_MATCH (LDRD1, ainsn->insn_thumb[0]) || THUMB2_INSN_MATCH (STRD, ainsn->insn_thumb[0])) )
 496         {
 497                 DBPRINTF ("Bad insn arch_check_insn_thumb: %lx\n", ainsn->insn_thumb[0]);
 498                 ret = -EFAULT;
 499         }
 500
 501         return ret;
 502 }
 503
 504 int arch_prepare_kretprobe (struct kretprobe *p)
 505 {
 506         DBPRINTF("Warrning: arch_prepare_kretprobe is not implemented\n");
 507         return 0;
 508 }
 509
 510 int arch_prepare_kprobe (struct kprobe *p)
 511 {
 512         kprobe_opcode_t insns[KPROBES_TRAMP_LEN];
 513         int uregs, pc_dep;
 514         int ret = 0;
 515
 516         if (!ret)
 517         {
 518                 kprobe_opcode_t insn[MAX_INSN_SIZE];
 519                 struct arch_specific_insn ainsn;
 520                 /* insn: must be on special executable page on i386. */
 521                 p->ainsn.insn = get_insn_slot (NULL, 0);
 522                 if (!p->ainsn.insn)
 523                         return -ENOMEM;
 524                 memcpy (insn, p->addr, MAX_INSN_SIZE * sizeof (kprobe_opcode_t));
 525                 ainsn.insn_arm = ainsn.insn = insn;
 526                 ret = arch_check_insn_arm (&ainsn);
 527                 if (!ret)
 528                 {
 529                         p->opcode = *p->addr;
 530
 531                         p->ainsn.boostable = 1;
 532                         uregs = pc_dep = 0;
 533                         // Rn, Rm ,Rd
 534                         if (ARM_INSN_MATCH (DPIS, insn[0]) || ARM_INSN_MATCH (LRO, insn[0]) ||
 535                                         ARM_INSN_MATCH (SRO, insn[0]))
 536                         {
 537
 538                                 uregs = 0xb;
 539                                 if ((ARM_INSN_REG_RN (insn[0]) == 15) || (ARM_INSN_REG_RM (insn[0]) == 15) ||
 540                                                 (ARM_INSN_MATCH (SRO, insn[0]) && (ARM_INSN_REG_RD (insn[0]) == 15)))
 541                                 {
 542
 543                                         DBPRINTF ("Unboostable insn %lx, DPIS/LRO/SRO\n", insn[0]);
 544                                         pc_dep = 1;
 545                                 }
 546                         }
 547                         // Rn ,Rd
 548                         else if (ARM_INSN_MATCH (DPI, insn[0]) || ARM_INSN_MATCH (LIO, insn[0]) ||
 549                                         ARM_INSN_MATCH (SIO, insn[0]))
 550                         {
 551
 552                                 uregs = 0x3;
 553                                 if ((ARM_INSN_REG_RN (insn[0]) == 15) || (ARM_INSN_MATCH (SIO, insn[0]) &&
 554                                                         (ARM_INSN_REG_RD (insn[0]) == 15)))
 555                                 {
 556
 557                                         pc_dep = 1;
 558                                         DBPRINTF ("Unboostable insn %lx/%p/%d, DPI/LIO/SIO\n", insn[0], p, p->ainsn.boostable);
 559                                 }
 560                         }
 561                         // Rn, Rm, Rs
 562                         else if (ARM_INSN_MATCH (DPRS, insn[0]))
 563                         {
 564
 565                                 uregs = 0xd;
 566                                 if ((ARM_INSN_REG_RN (insn[0]) == 15) || (ARM_INSN_REG_RM (insn[0]) == 15) ||
 567                                                 (ARM_INSN_REG_RS (insn[0]) == 15))
 568                                 {
 569
 570                                         pc_dep = 1;
 571                                         DBPRINTF ("Unboostable insn %lx, DPRS\n", insn[0]);
 572                                 }
 573                         }
 574                         // register list
 575                         else if (ARM_INSN_MATCH (SM, insn[0]))
 576                         {
 577
 578                                 uregs = 0x10;
 579                                 if (ARM_INSN_REG_MR (insn[0], 15))
 580                                 {
 581
 582                                         DBPRINTF ("Unboostable insn %lx, SM\n", insn[0]);
 583                                         pc_dep = 1;
 584                                 }
 585                         }
 586                         // check instructions that can write result to SP andu uses PC
 587                         if (pc_dep  && (ARM_INSN_REG_RD (ainsn.insn[0]) == 13))
 588                         {
 589                                 static int count;
 590                                 count++;
 591                                 //printk ("insn writes result to SP and uses PC: %lx/%d\n", ainsn.insn[0], count);
 592                                 free_insn_slot (&kprobe_insn_pages, NULL, p->ainsn.insn, 0);
 593                                 ret = -EFAULT;
 594                         }
 595                         else {
 596                                 if (uregs && pc_dep)
 597                                 {
 598                                         memcpy (insns, pc_dep_insn_execbuf, sizeof (insns));
 599                                         if (prep_pc_dep_insn_execbuf (insns, insn[0], uregs) != 0)
 600                                         {
 601                                                 DBPRINTF ("failed to prepare exec buffer for insn %lx!", insn[0]);
 602                                                 free_insn_slot (&kprobe_insn_pages, NULL, p->ainsn.insn, 0);
 603                                                 return -EINVAL;
 604                                         }
 605                                         //insns[KPROBES_TRAMP_SS_BREAK_IDX] = BREAKPOINT_INSTRUCTION;
 606                                         insns[6] = (kprobe_opcode_t) (p->addr + 2);
 607                                 }
 608                                 else
 609                                 {
 610                                         memcpy (insns, gen_insn_execbuf, sizeof (insns));
 611                                         insns[KPROBES_TRAMP_INSN_IDX] = insn[0];
 612                                 }
 613                                 //insns[KPROBES_TRAMP_RET_BREAK_IDX] = UNDEF_INSTRUCTION;
 614                                 insns[7] = (kprobe_opcode_t) (p->addr + 1);
 615                                 DBPRINTF ("arch_prepare_kprobe: insn %lx", insn[0]);
 616                                 DBPRINTF ("arch_prepare_kprobe: to %p - %lx %lx %lx %lx %lx %lx %lx %lx %lx",
 617                                                 p->ainsn.insn, insns[0], insns[1], insns[2], insns[3], insns[4],
 618                                                 insns[5], insns[6], insns[7], insns[8]);
 619                                 memcpy (p->ainsn.insn, insns, sizeof(insns));
 620                                 flush_icache_range(p->ainsn.insn, p->ainsn.insn + sizeof(insns));
 621 #ifdef BOARD_tegra
 622                                 flush_cache_all();
 623 #endif
 624                         }
 625                 }
 626                 else
 627                 {
 628                         free_insn_slot (&kprobe_insn_pages, NULL, p->ainsn.insn, 0);
 629                 }
 630         }
 631         return ret;
 632 }
 633
 634 static unsigned int arch_construct_brunch (unsigned int base, unsigned int addr, int link)
 635 {
 636         kprobe_opcode_t insn;
 637         unsigned int bpi = (unsigned int) base - (unsigned int) addr - 8;
 638
 639         insn = bpi >> 2;
 640         DBPRINTF ("base=%x addr=%x base-addr-8=%x\n", base, addr, bpi);
 641         if (abs (insn & 0xffffff) > 0xffffff)
 642         {
 643                 DBPRINTF ("ERROR: kprobe address out of range\n");
 644                 BUG ();
 645         }
 646         insn = insn & 0xffffff;
 647         insn = insn | ((link != 0) ? 0xeb000000 : 0xea000000);
 648         DBPRINTF ("insn=%lX\n", insn);
 649         return (unsigned int) insn;
 650 }
 651
 652
 653 int arch_copy_trampoline_arm_uprobe (struct kprobe *p, struct task_struct *task, int atomic);
 654 int arch_copy_trampoline_thumb_uprobe (struct kprobe *p, struct task_struct *task, int atomic);
 655
 656 int arch_prepare_uprobe (struct kprobe *p, struct task_struct *task, int atomic)
 657 {
 658         int ret = 0;
 659
 660         if ((unsigned long) p->addr & 0x01)
 661         {
 662                 DBPRINTF ("Attempt to register kprobe at an unaligned address");
 663                 ret = -EINVAL;
 664         }
 665         if (!ret)
 666         {
 667                 kprobe_opcode_t insn[MAX_INSN_SIZE];
 668
 669                 if (!read_proc_vm_atomic (task, (unsigned long) p->addr, &insn, MAX_INSN_SIZE * sizeof(kprobe_opcode_t))) panic ("failed to read memory %p!\n", p->addr);
 670
 671                 p->opcode = insn[0];
 672                 p->ainsn.insn_arm = get_insn_slot(task, atomic);
 673                 if (!p->ainsn.insn_arm) {
 674                         return -ENOMEM;
 675                 }
 676
 677                 ret = arch_copy_trampoline_arm_uprobe(p, task, 1);
 678                 if (ret) {
 679                         return -EFAULT;
 680                 }
 681
 682                 p->ainsn.insn_thumb = get_insn_slot(task, atomic);
 683                 if (!p->ainsn.insn_thumb) {
 684                         return -ENOMEM;
 685                 }
 686
 687                 ret = arch_copy_trampoline_thumb_uprobe(p, task, 1);
 688                 if (ret) {
 689                         return -EFAULT;
 690                 }
 691
 692                 p->ainsn.boostable = 1;
 693
 694                 my_p[my_probe] = p;
 695                 my_task[my_probe] = task;
 696                 my_atomic[my_probe] = atomic;
 697
 698                 my_probe++;
 699
 700         }
 701         return ret;
 702 }
 703
 704 int arch_prepare_uretprobe (struct kretprobe *p, struct task_struct *task)
 705 {
 706         DBPRINTF("Warrning: arch_prepare_uretprobe is not implemented\n");
 707         return 0;
 708 }
 709
 710 void prepare_singlestep (struct kprobe *p, struct pt_regs *regs)
 711 {
 712         if(p->ss_addr)
 713         {
 714                 regs->uregs[15] = (unsigned long) p->ss_addr;
 715                 p->ss_addr = NULL;
 716         }
 717         else
 718                 regs->uregs[15] = (unsigned long) p->ainsn.insn;
 719 }
 720
 721 void save_previous_kprobe (struct kprobe_ctlblk *kcb, struct kprobe *cur_p)
 722 {
 723         if (kcb->prev_kprobe.kp != NULL)
 724         {
 725                 DBPRINTF ("no space to save new probe[]: task = %d/%s", current->pid, current->comm);
 726         }
 727
 728         kcb->prev_kprobe.kp = kprobe_running ();
 729         kcb->prev_kprobe.status = kcb->kprobe_status;
 730 }
 731
 732 void restore_previous_kprobe (struct kprobe_ctlblk *kcb)
 733 {
 734         __get_cpu_var (current_kprobe) = kcb->prev_kprobe.kp;
 735         kcb->kprobe_status = kcb->prev_kprobe.status;
 736         kcb->prev_kprobe.kp = NULL;
 737         kcb->prev_kprobe.status = 0;
 738 }
 739
 740 void set_current_kprobe (struct kprobe *p, struct pt_regs *regs, struct kprobe_ctlblk *kcb)
 741 {
 742         __get_cpu_var (current_kprobe) = p;
 743         DBPRINTF ("set_current_kprobe: p=%p addr=%p\n", p, p->addr);
 744 }
 745
 746 int arch_copy_trampoline_arm_uprobe (struct kprobe *p, struct task_struct *task, int atomic)
 747 {
 748         int ret = 0;
 749         kprobe_opcode_t insns[UPROBES_TRAMP_LEN];
 750         int uregs, pc_dep;
 751
 752         if ((unsigned long) p->addr & 0x01)
 753         {
 754                 DBPRINTF ("Attempt to register kprobe at an unaligned address");
 755                 ret = -EINVAL;
 756         }
 757
 758         if (!ret)
 759         {
 760                 kprobe_opcode_t insn[MAX_INSN_SIZE];
 761                 struct arch_specific_insn ainsn;
 762
 763 //              *p->addr = p->opcode;
 764 //              flush_icache_range ((unsigned long) p->addr, (unsigned long) p->addr + sizeof (kprobe_opcode_t));
 765
 766 //              if (!read_proc_vm_atomic (task, (unsigned long) p->addr, &insn, MAX_INSN_SIZE * sizeof(kprobe_opcode_t)))
 767 //                      panic ("failed to read memory %p!\n", p->addr);
 768
 769                 insn[0] = p->opcode;
 770
 771                 ainsn.insn_arm = insn;
 772
 773                 ret = arch_check_insn_arm (&ainsn);
 774                 if (!ret)
 775                 {
 776 //                      p->opcode = insn[0];
 777 //                      p->ainsn.insn = get_insn_slot(task, atomic);
 778
 779 //                      if (!p->ainsn.insn)
 780 //                              return -ENOMEM;
 781
 782 //                      p->ainsn.boostable = 1;
 783
 784                         uregs = pc_dep = 0;
 785
 786                         // Rn, Rm ,Rd
 787                         if (ARM_INSN_MATCH (DPIS, insn[0]) || ARM_INSN_MATCH (LRO, insn[0]) ||
 788                                         ARM_INSN_MATCH (SRO, insn[0]))
 789                         {
 790                                 uregs = 0xb;
 791                                 if ((ARM_INSN_REG_RN (insn[0]) == 15) || (ARM_INSN_REG_RM (insn[0]) == 15) ||
 792                                                 (ARM_INSN_MATCH (SRO, insn[0]) && (ARM_INSN_REG_RD (insn[0]) == 15)))
 793                                 {
 794                                         DBPRINTF ("Unboostable insn %lx, DPIS/LRO/SRO\n", insn[0]);
 795                                         pc_dep = 1;
 796                                 }
 797                         }
 798                         // Rn ,Rd
 799                         else if (ARM_INSN_MATCH (DPI, insn[0]) || ARM_INSN_MATCH (LIO, insn[0]) ||
 800                                         ARM_INSN_MATCH (SIO, insn[0]))
 801                         {
 802                                 uregs = 0x3;
 803                                 if ((ARM_INSN_REG_RN (insn[0]) == 15) || (ARM_INSN_MATCH (SIO, insn[0]) &&
 804                                                         (ARM_INSN_REG_RD (insn[0]) == 15)))
 805                                 {
 806                                         pc_dep = 1;
 807                                         DBPRINTF ("Unboostable insn %lx/%p/%d, DPI/LIO/SIO\n", insn[0], p, p->ainsn.boostable);
 808                                 }
 809                         }
 810                         // Rn, Rm, Rs
 811                         else if (ARM_INSN_MATCH (DPRS, insn[0]))
 812                         {
 813                                 uregs = 0xd;
 814                                 if ((ARM_INSN_REG_RN (insn[0]) == 15) || (ARM_INSN_REG_RM (insn[0]) == 15) ||
 815                                                 (ARM_INSN_REG_RS (insn[0]) == 15))
 816                                 {
 817                                         pc_dep = 1;
 818                                         DBPRINTF ("Unboostable insn %lx, DPRS\n", insn[0]);
 819                                 }
 820                         }
 821                         // register list
 822                         else if (ARM_INSN_MATCH (SM, insn[0]))
 823                         {
 824                                 uregs = 0x10;
 825                                 if (ARM_INSN_REG_MR (insn[0], 15))
 826                                 {
 827                                         DBPRINTF ("Unboostable insn %lx, SM\n", insn[0]);
 828                                         pc_dep = 1;
 829                                 }
 830                         }
 831                         // check instructions that can write result to SP andu uses PC
 832                         if (pc_dep  && (ARM_INSN_REG_RD (ainsn.insn_arm[0]) == 13))
 833                         {
 834                                 static int count;
 835                                 count++;
 836                                 //printk ("insn writes result to SP and uses PC: %lx/%d\n", ainsn.insn_arm[0], count);
 837                                 free_insn_slot (&uprobe_insn_pages, task, p->ainsn.insn_arm, 0);
 838                                 ret = -EFAULT;
 839                         }
 840                         else {
 841                                 if (uregs && pc_dep)
 842                                 {
 843                                         memcpy (insns, pc_dep_insn_execbuf, sizeof (insns));
 844                                         if (prep_pc_dep_insn_execbuf (insns, insn[0], uregs) != 0)
 845                                         {
 846                                                 DBPRINTF ("failed to prepare exec buffer for insn %lx!", insn[0]);
 847                                                 free_insn_slot (&uprobe_insn_pages, task, p->ainsn.insn_arm, 0);
 848                                                 return -EINVAL;
 849                                         }
 850                                         //insns[UPROBES_TRAMP_SS_BREAK_IDX] = BREAKPOINT_INSTRUCTION;
 851                                         insns[6] = (kprobe_opcode_t) (p->addr + 2);
 852                                 }
 853                                 else
 854                                 {
 855                                         memcpy (insns, gen_insn_execbuf, sizeof (insns));
 856                                         insns[UPROBES_TRAMP_INSN_IDX] = insn[0];
 857                                 }
 858                                 insns[UPROBES_TRAMP_RET_BREAK_IDX] = BREAKPOINT_INSTRUCTION;
 859                                 insns[7] = (kprobe_opcode_t) (p->addr + 1);
 860                                 DBPRINTF ("arch_prepare_uprobe: to %p - %lx %lx %lx %lx %lx %lx %lx %lx %lx",
 861                                                 p->ainsn.insn_arm, insns[0], insns[1], insns[2], insns[3], insns[4],
 862                                                 insns[5], insns[6], insns[7], insns[8]);
 863                         }
 864
 865                         if (!write_proc_vm_atomic (task, (unsigned long) p->ainsn.insn_arm, insns, sizeof (insns)))
 866                         {
 867                                 panic("failed to write memory %p!\n", p->ainsn.insn);
 868                                 DBPRINTF ("failed to write insn slot to process memory: insn %p, addr %p, probe %p!", insn, p->ainsn.insn, p->addr);
 869                                 //printk ("failed to write insn slot to process memory: %p/%d insn %lx, addr %p, probe %p!\n", task, task->pid, insn, p->ainsn.insn, p->addr);
 870                                 free_insn_slot (&uprobe_insn_pages, task, p->ainsn.insn_arm, 0);
 871                                 return -EINVAL;
 872                         }
 873                 }
 874         }
 875         return ret;
 876 }
 877
 878
 879
 880 int arch_copy_trampoline_thumb_uprobe (struct kprobe *p, struct task_struct *task, int atomic)
 881 {
 882         int ret = 0;
 883         int uregs, pc_dep;
 884         unsigned int addr;
 885
 886         kprobe_opcode_t insns[UPROBES_TRAMP_LEN * 2];
 887
 888         if ((unsigned long) p->addr & 0x01)
 889         {
 890                 DBPRINTF ("Attempt to register kprobe at an unaligned address");
 891                 ret = -EINVAL;
 892         }
 893         if (!ret)
 894         {
 895                 kprobe_opcode_t insn[MAX_INSN_SIZE];
 896                 struct arch_specific_insn ainsn;
 897
 898 //              *p->addr = p->opcode;
 899 //              flush_icache_range ((unsigned long) p->addr, (unsigned long) p->addr + sizeof (kprobe_opcode_t));
 900
 901 //              if (!read_proc_vm_atomic (task, (unsigned long) p->addr, &insn, MAX_INSN_SIZE * sizeof(kprobe_opcode_t)))
 902 //                      panic ("failed to read memory %p!\n", p->addr);
 903
 904                 insn[0] = p->opcode;
 905
 906                 ainsn.insn_thumb = insn;
 907
 908                 ret = arch_check_insn_thumb (&ainsn);
 909                 if (!ret)
 910                 {
 911 //                      p->opcode = insn[0];
 912 //                      p->ainsn.insn_thumb = get_insn_slot(task, atomic);
 913
 914 //                      if (!p->ainsn.insn_thumb)
 915 //                              return -ENOMEM;
 916
 917 //                      p->ainsn.boostable = 1;
 918
 919                         uregs = 0;
 920                         pc_dep = 0;
 921
 922
 923                         if (THUMB_INSN_MATCH (APC, insn[0]) || THUMB_INSN_MATCH (LRO3, insn[0]))
 924                         {
 925                                 uregs = 0x0700;         // 8-10
 926                                 pc_dep = 1;
 927                         }else   if (THUMB_INSN_MATCH (MOV3, insn[0]) && (((((unsigned char) insn[0]) & 0xff) >> 3) == 15))
 928                                 {
 929                                         // MOV Rd, PC
 930                                         uregs = 0x07;
 931                                         pc_dep = 1;
 932                                 }else   if THUMB2_INSN_MATCH (ADR, insn[0])
 933                                         {
 934                                         uregs = 0x0f00;         // Rd 8-11
 935                                         pc_dep = 1;
 936                                         }else   if(     ((THUMB2_INSN_MATCH (LDRW, insn[0]) || THUMB2_INSN_MATCH (LDRW1, insn[0])  ||
 937                                                         THUMB2_INSN_MATCH (LDRBW, insn[0]) || THUMB2_INSN_MATCH (LDRBW1, insn[0]) ||
 938                                                         THUMB2_INSN_MATCH (LDRHW, insn[0]) || THUMB2_INSN_MATCH (LDRHW1, insn[0]) ||
 939                                                         THUMB2_INSN_MATCH (LDRWL, insn[0])) && THUMB2_INSN_REG_RN(insn[0]) == 15) ||
 940                                                         THUMB2_INSN_MATCH (LDREX, insn[0]) ||
 941                                                         ((THUMB2_INSN_MATCH (STRW, insn[0]) || THUMB2_INSN_MATCH (STRBW, insn[0]) || \
 942                                                                 THUMB2_INSN_MATCH (STRHW, insn[0]) || THUMB2_INSN_MATCH (STRHW1, insn[0])) && (THUMB2_INSN_REG_RN(insn[0]) == 15 || THUMB2_INSN_REG_RT(insn[0]) == 15)) ||
 943                                                         ((THUMB2_INSN_MATCH (STRT, insn[0]) || THUMB2_INSN_MATCH (STRHT, insn[0])) && (THUMB2_INSN_REG_RN(insn[0]) == 15 || THUMB2_INSN_REG_RT(insn[0]) == 15)) )
 944                                                 {
 945                                                         uregs = 0xf000;         // Rt 12-15
 946                                                         pc_dep = 1;
 947                                                 }else   if ((THUMB2_INSN_MATCH (LDRD, insn[0]) || THUMB2_INSN_MATCH (LDRD1, insn[0])) && (THUMB2_INSN_REG_RN(insn[0]) == 15))
 948                                                         {
 949                                                                 uregs = 0xff00;         // Rt 12-15, Rt2 8-11
 950                                                                 pc_dep = 1;
 951                                                         }else   if (THUMB2_INSN_MATCH (MUL, insn[0]) && THUMB2_INSN_REG_RM(insn[0]) == 15)
 952                                                                 {
 953                                                                         uregs = 0xf;
 954                                                                         pc_dep = 1;
 955                                                                 }else   if (THUMB2_INSN_MATCH (DP, insn[0]) && (THUMB2_INSN_REG_RN(insn[0]) == 15 || THUMB2_INSN_REG_RM(insn[0]) == 15))
 956                                                                         {
 957                                                                                 uregs = 0xf000; // Rd 12-15
 958                                                                                 pc_dep = 1;
 959                                                                         }else   if (THUMB2_INSN_MATCH (STRD, insn[0]) && (THUMB2_INSN_REG_RN(insn[0] == 15) || THUMB2_INSN_REG_RT(insn[0] == 15) || THUMB2_INSN_REG_RT2(insn[0]) == 15))
 960                                                                                 {
 961                                                                                         uregs = 0xff00;         // Rt 12-15, Rt2 8-11
 962                                                                                         pc_dep = 1;
 963                                                                                 }else   if (THUMB2_INSN_MATCH (RSBW, insn[0]) && THUMB2_INSN_REG_RN(insn[0]) == 15)
 964                                                                                         {
 965                                                                                                 uregs = 0x0f00; // Rd 8-11
 966                                                                                                 pc_dep = 1;
 967                                                                                         }else   if (THUMB2_INSN_MATCH (RORW, insn[0]) && (THUMB2_INSN_REG_RN(insn[0]) == 15 || THUMB2_INSN_REG_RM(insn[0]) == 15))
 968                                                                                                 {
 969                                                                                                         uregs = 0x0f00;
 970                                                                                                         pc_dep = 1;
 971                                                                                                 }else   if ((THUMB2_INSN_MATCH (ROR, insn[0]) || THUMB2_INSN_MATCH(LSLW2, insn[0]) || THUMB2_INSN_MATCH(LSRW2, insn[0])) && THUMB2_INSN_REG_RM(insn[0]) == 15)
 972                                                                                                         {
 973                                                                                                                 uregs = 0x0f00; // Rd 8-11
 974                                                                                                                 pc_dep = 1;
 975                                                                                                         }else   if ((THUMB2_INSN_MATCH (LSLW1, insn[0]) || THUMB2_INSN_MATCH (LSRW1, insn[0])) && (THUMB2_INSN_REG_RN(insn[0]) == 15 || THUMB2_INSN_REG_RM(insn[0]) == 15))
 976                                                                                                                 {
 977                                                                                                                         uregs = 0x0f00; // Rd 8-11
 978                                                                                                                         pc_dep = 1;
 979                                                                                                                 }else   if ((THUMB2_INSN_MATCH (TEQ1, insn[0]) || THUMB2_INSN_MATCH (TST1, insn[0])) && THUMB2_INSN_REG_RN(insn[0]) == 15)
 980                                                                                                                         {
 981                                                                                                                                 uregs = 0xf0000;        //Rn 0-3 (16-19)
 982                                                                                                                                 pc_dep = 1;
 983                                                                                                                         }else   if ((THUMB2_INSN_MATCH (TEQ2, insn[0]) || THUMB2_INSN_MATCH (TST2, insn[0])) && \
 984                                                                                                                                         (THUMB2_INSN_REG_RN(insn[0]) == 15 || THUMB2_INSN_REG_RM(insn[0]) == 15))
 985                                                                                                                                 {
 986                                                                                                                                         uregs = 0xf0000;        //Rn 0-3 (16-19)
 987                                                                                                                                         pc_dep = 1;
 988                                                                                                                                 }
 989
 990                         if (uregs && pc_dep)
 991                         {
 992                                 memcpy (insns, pc_dep_insn_execbuf_thumb, 18 * 2);
 993                                 if (prep_pc_dep_insn_execbuf_thumb (insns, insn[0], uregs) != 0)
 994                                 {
 995                                         DBPRINTF ("failed to prepare exec buffer for insn %lx!", insn[0]);
 996                                         free_insn_slot (&uprobe_insn_pages, task, p->ainsn.insn_thumb, 0);
 997                                         return -EINVAL;
 998                                 }
 999                                 addr = ((unsigned int)p->addr) + 4;
1000
1001                                 *((unsigned short*)insns + 13) = 0xdeff;
1002                                 *((unsigned short*)insns + 14) = addr & 0x0000ffff;
1003                                 *((unsigned short*)insns + 15) = addr >> 16;
1004
1005                                 if (!isThumb2(insn[0]))
1006                                 {
1007                                         addr = ((unsigned int)p->addr) + 2;
1008
1009                                         *((unsigned short*)insns + 16) = addr & 0x0000ffff | 0x1;
1010                                         *((unsigned short*)insns + 17) = addr >> 16;
1011                                 }else{
1012                                         addr = ((unsigned int)p->addr) + 4;
1013
1014                                         *((unsigned short*)insns + 16) = addr & 0x0000ffff | 0x1;
1015                                         *((unsigned short*)insns + 17) = addr >> 16;
1016                                 }
1017                         }else{
1018                                 memcpy (insns, gen_insn_execbuf_thumb, 18 * 2);
1019
1020                                 *((unsigned short*)insns + 13) = 0xdeff;
1021
1022                                 if (!isThumb2(insn[0]))
1023                                 {
1024                                         addr = ((unsigned int)p->addr) + 2;
1025
1026                                         *((unsigned short*)insns + 2) = insn[0];
1027                                         *((unsigned short*)insns + 16) = addr & 0x0000ffff | 0x1;
1028                                         *((unsigned short*)insns + 17) = addr >> 16;
1029                                 }else{
1030                                         addr = ((unsigned int)p->addr) + 4;
1031                                         insns[1] = insn[0];
1032                                         *((unsigned short*)insns + 16) = addr & 0x0000ffff | 0x1;
1033                                         *((unsigned short*)insns + 17) = addr >> 16;
1034                                 }
1035                         }
1036                 }
1037                 if (!write_proc_vm_atomic (task, (unsigned long) p->ainsn.insn_thumb, insns, 18 * 2))
1038                 {
1039                         panic("failed to write memory %p!\n", p->ainsn.insn_thumb);
1040                         DBPRINTF ("failed to write insn slot to process memory: insn %p, addr %p, probe %p!", insn, p->ainsn.insn_thumb, p->addr);
1041                         //printk ("failed to write insn slot to process memory: %p/%d insn %lx, addr %p, probe %p!\n", task, task->pid, insn, p->ainsn.insn_thumb, p->addr);
1042                         free_insn_slot (&uprobe_insn_pages, task, p->ainsn.insn_thumb, 0);
1043                         return -EINVAL;
1044                 }
1045         }
1046
1047         return ret;
1048 }
1049
1050
1051 int kprobe_handler (struct pt_regs *regs)
1052 {
1053         struct kprobe *p = 0;
1054         int ret = 0, pid = 0, retprobe = 0, reenter = 0;
1055         kprobe_opcode_t *addr = NULL, *ssaddr = 0;
1056         struct kprobe_ctlblk *kcb;
1057         int i = 0;
1058 #ifdef OVERHEAD_DEBUG
1059         struct timeval swap_tv1;
1060         struct timeval swap_tv2;
1061 #endif
1062 #ifdef SUPRESS_BUG_MESSAGES
1063         int swap_oops_in_progress;
1064 #endif
1065
1066 #ifdef SUPRESS_BUG_MESSAGES
1067         // oops_in_progress used to avoid BUG() messages that slow down kprobe_handler() execution
1068         swap_oops_in_progress = oops_in_progress;
1069         oops_in_progress = 1;
1070 #endif
1071 #ifdef OVERHEAD_DEBUG
1072 #define USEC_IN_SEC_NUM                         1000000
1073         do_gettimeofday(&swap_tv1);
1074 #endif
1075         preempt_disable ();
1076
1077         if (user_mode(regs))
1078         {
1079                 if (!thumb_mode ( regs )) addr = (kprobe_opcode_t *) (regs->uregs[15] - 4);
1080                 else addr = (kprobe_opcode_t *) (regs->uregs[15] - 2);
1081
1082                 for(i = 0; i < my_probe; i++)
1083                 {
1084                         if (my_p[i] != -1)
1085                         {
1086                                 /*
1087                                  * Searching occurred probe by
1088                                  * instruction address and task_struct
1089                                  */
1090                                 if (my_p[i]->addr == addr &&
1091                                     my_task[i]->tgid == current->tgid)
1092                                 {
1093                                         if (thumb_mode(regs))
1094                                         {
1095                                                 my_p[i]->ainsn.insn = my_p[i]->ainsn.insn_thumb;
1096                                                 struct kprobe *kp;
1097                                                 list_for_each_entry_rcu (kp, &my_p[i]->list, list)
1098                                                 {
1099                                                         kp->ainsn.insn = my_p[i]->ainsn.insn_thumb;
1100                                                 }
1101                                                 my_p[i]->ainsn.insn = my_p[i]->ainsn.insn_thumb;
1102                                         }else{
1103                                                 my_p[i]->ainsn.insn = my_p[i]->ainsn.insn_arm;
1104                                                 struct kprobe *kp;
1105                                                 list_for_each_entry_rcu (kp, &my_p[i]->list, list)
1106                                                 {
1107                                                         kp->ainsn.insn = my_p[i]->ainsn.insn_arm;
1108                                                 }
1109                                                 my_p[i]->ainsn.insn = my_p[i]->ainsn.insn_arm;
1110                                         }
1111
1112                                         break;
1113                                 }
1114                         }
1115                 }
1116         }
1117
1118         /* We're in an interrupt, but this is clear and BUG()-safe. */
1119
1120         if (!thumb_mode ( regs )) regs->uregs[15] -= 4;
1121         else regs->uregs[15] -= 2;
1122
1123         addr = (kprobe_opcode_t *) regs->uregs[15];
1124
1125 //      DBPRINTF ("KPROBE: regs->uregs[15] = 0x%lx addr = 0x%p\n", regs->uregs[15], addr);
1126         //DBPRINTF("regs->uregs[14] = 0x%lx\n", regs->uregs[14]);
1127
1128 //      preempt_disable ();
1129
1130         kcb = get_kprobe_ctlblk ();
1131
1132         if (user_mode (regs))
1133         {
1134                 //DBPRINTF("exception[%lu] from user mode %s/%u addr %p (%lx).", nCount, current->comm, current->pid, addr, regs->uregs[14]);
1135                 pid = current->tgid;
1136         }
1137
1138         /* Check we're not actually recursing */
1139         if (kprobe_running ())
1140         {
1141                 DBPRINTF ("lock???");
1142                 p = get_kprobe (addr, pid, current);
1143                 if (p)
1144                 {
1145                         if(!pid && (addr == (kprobe_opcode_t *)kretprobe_trampoline)){
1146                                 save_previous_kprobe (kcb, p);
1147                                 kcb->kprobe_status = KPROBE_REENTER;
1148                                 reenter = 1;
1149                         }
1150                         else {
1151                                 /* We have reentered the kprobe_handler(), since
1152                                  * another probe was hit while within the handler.
1153                                  * We here save the original kprobes variables and
1154                                  * just single step on the instruction of the new probe
1155                                  * without calling any user handlers.
1156                                  */
1157                                 if(!p->ainsn.boostable){
1158                                         save_previous_kprobe (kcb, p);
1159                                         set_current_kprobe (p, regs, kcb);
1160                                 }
1161                                 kprobes_inc_nmissed_count (p);
1162                                 prepare_singlestep (p, regs);
1163                                 if(!p->ainsn.boostable)
1164                                         kcb->kprobe_status = KPROBE_REENTER;
1165                                 preempt_enable_no_resched ();
1166 #ifdef OVERHEAD_DEBUG
1167                                 do_gettimeofday(&swap_tv2);
1168                                 swap_sum_hit++;
1169                                 swap_sum_time += ((swap_tv2.tv_sec - swap_tv1.tv_sec) * USEC_IN_SEC_NUM +
1170                                         (swap_tv2.tv_usec - swap_tv1.tv_usec));
1171 #endif
1172 #ifdef SUPRESS_BUG_MESSAGES
1173                                 oops_in_progress = swap_oops_in_progress;
1174 #endif
1175                                 return 1;
1176                         }
1177                 }
1178                 else
1179                 {
1180                         if(pid) { //we can reenter probe upon uretprobe exception
1181                                 DBPRINTF ("check for UNDEF_INSTRUCTION %p\n", addr);
1182                                 // UNDEF_INSTRUCTION from user space
1183
1184                                 if (!thumb_mode ( regs ))
1185                                         p = get_kprobe_by_insn_slot_arm (addr-UPROBES_TRAMP_RET_BREAK_IDX, pid, current);
1186                                 else
1187                                         p = get_kprobe_by_insn_slot_thumb ((unsigned long)addr - 0x1a, pid, current);
1188
1189                                 if (p) {
1190                                         save_previous_kprobe (kcb, p);
1191                                         kcb->kprobe_status = KPROBE_REENTER;
1192                                         reenter = 1;
1193                                         retprobe = 1;
1194                                         DBPRINTF ("uretprobe %p\n", addr);
1195                                 }
1196                         }
1197                         if(!p) {
1198                                 p = __get_cpu_var (current_kprobe);
1199                                 DBPRINTF ("kprobe_running !!! p = 0x%p p->break_handler = 0x%p", p, p->break_handler);
1200                                 /*if (p->break_handler && p->break_handler(p, regs)) {
1201                                   DBPRINTF("kprobe_running !!! goto ss");
1202                                   goto ss_probe;
1203                                   } */
1204                                 DBPRINTF ("unknown uprobe at %p cur at %p/%p\n", addr, p->addr, p->ainsn.insn);
1205                                 if(pid)
1206                                         ssaddr = p->ainsn.insn + UPROBES_TRAMP_SS_BREAK_IDX;
1207                                 else
1208                                         ssaddr = p->ainsn.insn + KPROBES_TRAMP_SS_BREAK_IDX;
1209                                 if (addr == ssaddr)
1210                                 {
1211                                         regs->uregs[15] = (unsigned long) (p->addr + 1);
1212                                         DBPRINTF ("finish step at %p cur at %p/%p, redirect to %lx\n", addr, p->addr, p->ainsn.insn, regs->uregs[15]);
1213                                         if (kcb->kprobe_status == KPROBE_REENTER) {
1214                                                 restore_previous_kprobe (kcb);
1215                                         }
1216                                         else {
1217                                                 reset_current_kprobe ();
1218                                         }
1219                                 }
1220                                 DBPRINTF ("kprobe_running !!! goto no");
1221                                 ret = 1;
1222                                 /* If it's not ours, can't be delete race, (we hold lock). */
1223                                 DBPRINTF ("no_kprobe");
1224                                 goto no_kprobe;
1225                         }
1226                 }
1227         }
1228         //if(einsn != UNDEF_INSTRUCTION) {
1229 //      DBPRINTF ("get_kprobe %p-%d", addr, pid);
1230
1231         if (!p)
1232         {
1233                 p = get_kprobe (addr, pid, current);
1234         }
1235         if (!p)
1236         {
1237                 if(pid) {
1238                         DBPRINTF ("search UNDEF_INSTRUCTION %p\n", addr);
1239                         // UNDEF_INSTRUCTION from user space
1240
1241                         if (!thumb_mode ( regs ))
1242                                 p = get_kprobe_by_insn_slot_arm (addr-UPROBES_TRAMP_RET_BREAK_IDX, pid, current);
1243                         else
1244                                 p = get_kprobe_by_insn_slot_thumb ((unsigned long)addr - 0x1a, pid, current);
1245
1246                         if (!p) {
1247                                 /* Not one of ours: let kernel handle it */
1248                                 DBPRINTF ("no_kprobe");
1249                                 goto no_kprobe;
1250                         }
1251                         retprobe = 1;
1252                         DBPRINTF ("uretprobe %p\n", addr);
1253                 }
1254                 else {
1255                         /* Not one of ours: let kernel handle it */
1256                         DBPRINTF ("no_kprobe");
1257                         goto no_kprobe;
1258                 }
1259         }
1260
1261         // restore opcode for thumb app
1262         if (user_mode( regs ) && thumb_mode( regs ))
1263         {
1264                 if (!isThumb2(p->opcode))
1265                 {
1266                         unsigned long tmp = p->opcode >> 16;
1267                         write_proc_vm_atomic(current, (unsigned long)((unsigned short*)p->addr + 1), &tmp, 2);
1268                 }else{
1269                         unsigned long tmp = p->opcode;
1270                         write_proc_vm_atomic(current, (unsigned long)((unsigned short*)p->addr), &tmp, 4);
1271                 }
1272                 flush_icache_range ((unsigned int) p->addr, (unsigned int) (((unsigned int) p->addr) + (sizeof (kprobe_opcode_t) * 2)));
1273         }
1274
1275         set_current_kprobe (p, regs, kcb);
1276
1277         if(!reenter)
1278                 kcb->kprobe_status = KPROBE_HIT_ACTIVE;
1279
1280         if (retprobe)           //(einsn == UNDEF_INSTRUCTION)
1281                 ret = trampoline_probe_handler (p, regs);
1282         else if (p->pre_handler)
1283         {
1284                 ret = p->pre_handler (p, regs);
1285                 if(!p->ainsn.boostable)
1286                         kcb->kprobe_status = KPROBE_HIT_SS;
1287                 else if(p->pre_handler != trampoline_probe_handler) {
1288 #ifdef SUPRESS_BUG_MESSAGES
1289                         preempt_disable();
1290 #endif
1291                         reset_current_kprobe();
1292 #ifdef SUPRESS_BUG_MESSAGES
1293                         preempt_enable_no_resched();
1294 #endif
1295                 }
1296         }
1297         if (ret)
1298         {
1299                 DBPRINTF ("p->pre_handler 1");
1300                 /* handler has already set things up, so skip ss setup */
1301 #ifdef OVERHEAD_DEBUG
1302                 do_gettimeofday(&swap_tv2);
1303                 swap_sum_hit++;
1304                 swap_sum_time += ((swap_tv2.tv_sec - swap_tv1.tv_sec) * USEC_IN_SEC_NUM +
1305                         (swap_tv2.tv_usec - swap_tv1.tv_usec));
1306 #endif
1307 #ifdef SUPRESS_BUG_MESSAGES
1308                 oops_in_progress = swap_oops_in_progress;
1309 #endif
1310                 return 1;
1311         }
1312         DBPRINTF ("p->pre_handler 0");
1313
1314 no_kprobe:
1315         preempt_enable_no_resched ();
1316 #ifdef OVERHEAD_DEBUG
1317         do_gettimeofday(&swap_tv2);
1318         swap_sum_hit++;
1319         swap_sum_time += ((swap_tv2.tv_sec - swap_tv1.tv_sec) *  USEC_IN_SEC_NUM +
1320                 (swap_tv2.tv_usec - swap_tv1.tv_usec));
1321 #endif
1322 #ifdef SUPRESS_BUG_MESSAGES
1323         oops_in_progress = swap_oops_in_progress;
1324 #endif
1325         return ret;
1326 }
1327
1328
1329 void patch_suspended_task_ret_addr(struct task_struct *p, struct kretprobe *rp)
1330 {
1331         struct kretprobe_instance *ri = NULL;
1332         struct hlist_node *node, *tmp;
1333         struct hlist_head *head;
1334         unsigned long flags;
1335         int found = 0;
1336
1337         spin_lock_irqsave (&kretprobe_lock, flags);
1338         head = kretprobe_inst_table_head (p);
1339         hlist_for_each_entry_safe (ri, node, tmp, head, hlist){
1340                 if ((ri->rp == rp) && (p == ri->task)){
1341                         found = 1;
1342                         break;
1343                 }
1344         }
1345         spin_unlock_irqrestore (&kretprobe_lock, flags);
1346
1347 #ifndef task_thread_info
1348 #define task_thread_info(task) (task)->thread_info
1349 #endif // task_thread_info
1350
1351         if (found){
1352                 // update PC
1353                 if(thread_saved_pc(p) != (unsigned long)&kretprobe_trampoline){
1354                         ri->ret_addr = (kprobe_opcode_t *)thread_saved_pc(p);
1355                         task_thread_info(p)->cpu_context.pc = (unsigned long) &kretprobe_trampoline;
1356                 }
1357                 return;
1358         }
1359
1360         spin_lock_irqsave (&kretprobe_lock, flags);
1361         if ((ri = get_free_rp_inst(rp)) != NULL)
1362         {
1363                 ri->rp = rp;
1364                 ri->rp2 = NULL;
1365                 ri->task = p;
1366                 ri->ret_addr = (kprobe_opcode_t *)thread_saved_pc(p);
1367                 task_thread_info(p)->cpu_context.pc = (unsigned long) &kretprobe_trampoline;
1368                 add_rp_inst (ri);
1369                 //              printk("change2 saved pc %p->%p for %d/%d/%p\n", ri->ret_addr, &kretprobe_trampoline, p->tgid, p->pid, p);
1370         }
1371         else{
1372                 printk("no ri for %d\n", p->pid);
1373                 BUG();
1374         }
1375         spin_unlock_irqrestore (&kretprobe_lock, flags);
1376 }
1377
1378 int setjmp_pre_handler (struct kprobe *p, struct pt_regs *regs)
1379 {
1380         struct jprobe *jp = container_of (p, struct jprobe, kp);
1381         kprobe_pre_entry_handler_t pre_entry;
1382         entry_point_t entry;
1383
1384 # ifdef REENTER
1385         p = __get_cpu_var (current_kprobe);
1386 # endif
1387
1388         DBPRINTF ("pjp = 0x%p jp->entry = 0x%p", jp, jp->entry);
1389         entry = (entry_point_t) jp->entry;
1390         pre_entry = (kprobe_pre_entry_handler_t) jp->pre_entry;
1391         //if(!entry)
1392         //      DIE("entry NULL", regs)
1393         DBPRINTF ("entry = 0x%p jp->entry = 0x%p", entry, jp->entry);
1394
1395         //call handler for all kernel probes and user space ones which belong to current tgid
1396         if (!p->tgid || (p->tgid == current->tgid))
1397         {
1398                 if(!p->tgid && ((unsigned int)p->addr == sched_addr) && sched_rp){
1399                         struct task_struct *p, *g;
1400                         rcu_read_lock();
1401                         //swapper task
1402                         if(current != &init_task)
1403                                 patch_suspended_task_ret_addr(&init_task, sched_rp);
1404                         // other tasks
1405                         do_each_thread(g, p){
1406                                 if(p == current)
1407                                         continue;
1408                                 patch_suspended_task_ret_addr(p, sched_rp);
1409                         } while_each_thread(g, p);
1410                         rcu_read_unlock();
1411                 }
1412                 if (pre_entry)
1413                         p->ss_addr = (void *)pre_entry (jp->priv_arg, regs);
1414                 if (entry){
1415                         entry (regs->ARM_r0, regs->ARM_r1, regs->ARM_r2, regs->ARM_r3, regs->ARM_r4, regs->ARM_r5);
1416                 }
1417                 else {
1418                         if (p->tgid)
1419                                 dbi_arch_uprobe_return ();
1420                         else
1421                                 dbi_jprobe_return ();
1422                 }
1423         }
1424         else if (p->tgid)
1425                 dbi_arch_uprobe_return ();
1426
1427         prepare_singlestep (p, regs);
1428
1429         return 1;
1430 }
1431
1432 void dbi_jprobe_return (void)
1433 {
1434         preempt_enable_no_resched();
1435 }
1436
1437 void dbi_arch_uprobe_return (void)
1438 {
1439         preempt_enable_no_resched();
1440 }
1441
1442 int longjmp_break_handler (struct kprobe *p, struct pt_regs *regs)
1443 {
1444 # ifndef REENTER
1445         //kprobe_opcode_t insn = BREAKPOINT_INSTRUCTION;
1446         kprobe_opcode_t insns[2];
1447
1448         if (p->pid)
1449         {
1450                 insns[0] = BREAKPOINT_INSTRUCTION;
1451                 insns[1] = p->opcode;
1452                 //p->opcode = *p->addr;
1453                 if (read_proc_vm_atomic (current, (unsigned long) (p->addr), &(p->opcode), sizeof (p->opcode)) < sizeof (p->opcode))
1454                 {
1455                         printk ("ERROR[%lu]: failed to read vm of proc %s/%u addr %p.", nCount, current->comm, current->pid, p->addr);
1456                         return -1;
1457                 }
1458                 //*p->addr = BREAKPOINT_INSTRUCTION;
1459                 //*(p->addr+1) = p->opcode;
1460                 if (write_proc_vm_atomic (current, (unsigned long) (p->addr), insns, sizeof (insns)) < sizeof (insns))
1461                 {
1462                         printk ("ERROR[%lu]: failed to write vm of proc %s/%u addr %p.", nCount, current->comm, current->pid, p->addr);
1463                         return -1;
1464                 }
1465         }
1466         else
1467         {
1468                 DBPRINTF ("p->opcode = 0x%lx *p->addr = 0x%lx p->addr = 0x%p\n", p->opcode, *p->addr, p->addr);
1469                 *(p->addr + 1) = p->opcode;
1470                 p->opcode = *p->addr;
1471                 *p->addr = BREAKPOINT_INSTRUCTION;
1472
1473                 flush_icache_range ((unsigned int) p->addr, (unsigned int) (((unsigned int) p->addr) + (sizeof (kprobe_opcode_t) * 2)));
1474         }
1475
1476         reset_current_kprobe ();
1477
1478 #endif //REENTER
1479
1480         return 0;
1481 }
1482
1483
1484 void arch_arm_kprobe (struct kprobe *p)
1485 {
1486         *p->addr = BREAKPOINT_INSTRUCTION;
1487         flush_icache_range ((unsigned long) p->addr, (unsigned long) p->addr + sizeof (kprobe_opcode_t));
1488 }
1489
1490 void arch_disarm_kprobe (struct kprobe *p)
1491 {
1492         *p->addr = p->opcode;
1493         flush_icache_range ((unsigned long) p->addr, (unsigned long) p->addr + sizeof (kprobe_opcode_t));
1494 }
1495
1496
1497 int trampoline_probe_handler (struct kprobe *p, struct pt_regs *regs)
1498 {
1499         struct kretprobe_instance *ri = NULL;
1500         struct hlist_head *head, empty_rp;
1501         struct hlist_node *node, *tmp;
1502         unsigned long flags, orig_ret_address = 0;
1503         unsigned long trampoline_address = (unsigned long) &kretprobe_trampoline;
1504
1505         struct kretprobe *crp = NULL;
1506         struct kprobe_ctlblk *kcb = get_kprobe_ctlblk ();
1507
1508         DBPRINTF ("start");
1509
1510         if (p && p->tgid){
1511                 // in case of user space retprobe trampoline is at the Nth instruction of US tramp
1512                 if (!thumb_mode( regs ))
1513                         trampoline_address = (unsigned long)(p->ainsn.insn + UPROBES_TRAMP_RET_BREAK_IDX);
1514                 else
1515                         trampoline_address = (unsigned long)(p->ainsn.insn) + 0x1b;
1516         }
1517
1518         INIT_HLIST_HEAD (&empty_rp);
1519         spin_lock_irqsave (&kretprobe_lock, flags);
1520
1521         /*
1522          * We are using different hash keys (current and mm) for finding kernel
1523          * space and user space probes.  Kernel space probes can change mm field in
1524          * task_struct.  User space probes can be shared between threads of one
1525          * process so they have different current but same mm.
1526          */
1527         if (p && p->tgid) {
1528                 head = kretprobe_inst_table_head(current->mm);
1529         } else {
1530                 head = kretprobe_inst_table_head(current);
1531         }
1532
1533         /*
1534          * It is possible to have multiple instances associated with a given
1535          * task either because an multiple functions in the call path
1536          * have a return probe installed on them, and/or more then one
1537          * return probe was registered for a target function.
1538          *
1539          * We can handle this because:
1540          *     - instances are always inserted at the head of the list
1541          *     - when multiple return probes are registered for the same
1542          *       function, the first instance's ret_addr will point to the
1543          *       real return address, and all the rest will point to
1544          *       kretprobe_trampoline
1545          */
1546         hlist_for_each_entry_safe (ri, node, tmp, head, hlist)
1547         {
1548                 if (ri->task != current)
1549                         /* another task is sharing our hash bucket */
1550                         continue;
1551                 if (ri->rp && ri->rp->handler){
1552                         ri->rp->handler (ri, regs, ri->rp->priv_arg);
1553                 }
1554
1555                 orig_ret_address = (unsigned long) ri->ret_addr;
1556                 recycle_rp_inst (ri, &empty_rp);
1557                 if (orig_ret_address != trampoline_address)
1558                         /*
1559                          * This is the real return address. Any other
1560                          * instances associated with this task are for
1561                          * other calls deeper on the call stack
1562                          */
1563                         break;
1564         }
1565         kretprobe_assert (ri, orig_ret_address, trampoline_address);
1566         //BUG_ON(!orig_ret_address || (orig_ret_address == trampoline_address));
1567         //E.G. Check this code in case of __switch_to function instrumentation -- currently this code generates dump in this case
1568         //if (trampoline_address != (unsigned long) &kretprobe_trampoline){
1569         //if (ri->rp2) BUG_ON (ri->rp2->kp.tgid == 0);
1570         //if (ri->rp) BUG_ON (ri->rp->kp.tgid == 0);
1571         //else if (ri->rp2) BUG_ON (ri->rp2->kp.tgid == 0);
1572         //}
1573         if ((ri->rp && ri->rp->kp.tgid) || (ri->rp2 && ri->rp2->kp.tgid))
1574                 BUG_ON (trampoline_address == (unsigned long) &kretprobe_trampoline);
1575
1576         regs->uregs[14] = orig_ret_address;
1577         DBPRINTF ("regs->uregs[14] = 0x%lx\n", regs->uregs[14]);
1578         DBPRINTF ("regs->uregs[15] = 0x%lx\n", regs->uregs[15]);
1579
1580         if (trampoline_address != (unsigned long) &kretprobe_trampoline)
1581         {
1582                 regs->uregs[15] = orig_ret_address;
1583         }else{
1584                 if (!thumb_mode( regs )) regs->uregs[15] += 4;
1585                 else regs->uregs[15] += 2;
1586         }
1587
1588         DBPRINTF ("regs->uregs[15] = 0x%lx\n", regs->uregs[15]);
1589
1590         if(p){ // ARM, MIPS, X86 user space
1591                 if (kcb->kprobe_status == KPROBE_REENTER)
1592                         restore_previous_kprobe (kcb);
1593                 else
1594                         reset_current_kprobe ();
1595
1596                 if (thumb_mode( regs ) && !(regs->uregs[14] & 0x01))
1597                 {
1598                         regs->ARM_cpsr &= 0xFFFFFFDF;
1599                 }else{
1600                         if (user_mode( regs ) && (regs->uregs[14] & 0x01))
1601                         {
1602                                 regs->ARM_cpsr |= 0x20;
1603                         }
1604                 }
1605
1606                 //TODO: test - enter function, delete us retprobe, exit function
1607                 // for user space retprobes only - deferred deletion
1608
1609                 if (trampoline_address != (unsigned long) &kretprobe_trampoline)
1610                 {
1611                         // if we are not at the end of the list and current retprobe should be disarmed
1612                         if (node && ri->rp2)
1613                         {
1614                                 struct hlist_node *current_node = node;
1615                                 crp = ri->rp2;
1616                                 /*sprintf(die_msg, "deferred disarm p->addr = %p [%lx %lx %lx]\n",
1617                                   crp->kp.addr, *kaddrs[0], *kaddrs[1], *kaddrs[2]);
1618                                   DIE(die_msg, regs); */
1619                                 // look for other instances for the same retprobe
1620                                 hlist_for_each_entry_safe (ri, node, tmp, head, hlist)
1621                                 {
1622                                         /*
1623                                          * Trying to find another retprobe instance associated with
1624                                          * the same retprobe.
1625                                          */
1626                                         if (ri->rp2 == crp && node != current_node)
1627                                                 break;
1628                                 }
1629
1630                                 if (!node)
1631                                 {       // if there are no more instances for this retprobe
1632                                         // delete retprobe
1633                                         DBPRINTF ("defered retprobe deletion p->addr = %p", crp->kp.addr);
1634                                         /*
1635                                           If there is no any retprobe instances of this retprobe
1636                                           we can free the resources related to the probe.
1637                                          */
1638                                         struct kprobe *is_p = &crp->kp;
1639                                         if (!(hlist_unhashed(&is_p->is_hlist_arm))) {
1640                                                 hlist_del_rcu(&is_p->is_hlist_arm);
1641                                         }
1642                                         if (!(hlist_unhashed(&is_p->is_hlist_thumb))) {
1643                                                 hlist_del_rcu(&is_p->is_hlist_thumb);
1644                                         }
1645                                         unregister_uprobe (&crp->kp, current, 1);
1646                                         kfree (crp);
1647                                 }
1648                                 hlist_del(current_node);
1649                         }
1650                 }
1651         }
1652
1653         hlist_for_each_entry_safe (ri, node, tmp, &empty_rp, hlist)
1654         {
1655                 hlist_del (&ri->hlist);
1656                 kfree (ri);
1657         }
1658         spin_unlock_irqrestore (&kretprobe_lock, flags);
1659
1660         preempt_enable_no_resched ();
1661         /*
1662          * By returning a non-zero value, we are telling
1663          * kprobe_handler() that we don't want the post_handler
1664          * to run (and have re-enabled preemption)
1665          */
1666
1667         return 1;
1668 }
1669
1670 void  __arch_prepare_kretprobe (struct kretprobe *rp, struct pt_regs *regs)
1671 {
1672         struct kretprobe_instance *ri;
1673
1674         DBPRINTF ("start\n");
1675         //TODO: test - remove retprobe after func entry but before its exit
1676         if ((ri = get_free_rp_inst (rp)) != NULL)
1677         {
1678                 ri->rp = rp;
1679                 ri->rp2 = NULL;
1680                 ri->task = current;
1681                 ri->ret_addr = (kprobe_opcode_t *) regs->uregs[14];
1682
1683                 if (rp->kp.tgid)
1684                         if (!thumb_mode( regs ))
1685                                 regs->uregs[14] = (unsigned long) (rp->kp.ainsn.insn + UPROBES_TRAMP_RET_BREAK_IDX);
1686                         else
1687                                 regs->uregs[14] = (unsigned long) (rp->kp.ainsn.insn) + 0x1b;
1688
1689                 else    /* Replace the return addr with trampoline addr */
1690                         regs->uregs[14] = (unsigned long) &kretprobe_trampoline;
1691
1692 //              DBPRINTF ("ret addr set to %p->%lx\n", ri->ret_addr, regs->uregs[14]);
1693                 add_rp_inst (ri);
1694         }
1695         else {
1696                 DBPRINTF ("WARNING: missed retprobe %p\n", rp->kp.addr);
1697                 rp->nmissed++;
1698         }
1699 }
1700
1701
1702 int asm_init_module_dependencies()
1703 {
1704         //No module dependencies
1705         return 0;
1706 }
1707
1708 #if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 38)
1709 typedef unsigned long (* in_gate_area_fp_t)(unsigned long);
1710 in_gate_area_fp_t in_gate_area_fp;
1711 #endif /* LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 38) */
1712
1713 int __init arch_init_kprobes (void)
1714 {
1715         unsigned int do_bp_handler;
1716         unsigned int kprobe_handler_addr;
1717
1718         unsigned int insns_num = 0;
1719         unsigned int code_size = 0;
1720
1721         int ret = 0;
1722
1723         if (arch_init_module_dependencies())
1724         {
1725                 DBPRINTF ("Unable to init module dependencies\n");
1726                 return -1;
1727         }
1728
1729 #if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 38)
1730         in_gate_area_fp = (in_gate_area_fp_t)kallsyms_search("in_gate_area_no_mm");
1731         if (!in_gate_area_fp) {
1732                 DBPRINTF("no in_gate_area symbol found!");
1733                 return -1;
1734         }
1735 #endif /* LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 38) */
1736
1737         do_bp_handler = (unsigned int) kallsyms_search ("do_undefinstr");
1738
1739         kprobe_handler_addr = (unsigned int) &kprobe_handler;
1740         insns_num = sizeof (arr_traps_template) / sizeof (arr_traps_template[0]);
1741         code_size = insns_num * sizeof (unsigned int);
1742         DBPRINTF ("insns_num = %d\n", insns_num);
1743         // Save original code
1744         arr_traps_original = kmalloc (code_size, GFP_KERNEL);
1745         if (!arr_traps_original)
1746         {
1747                 DBPRINTF ("Unable to allocate space for original code of <do_bp>!\n");
1748                 return -1;
1749         }
1750         memcpy (arr_traps_original, (void *) do_bp_handler, code_size);
1751
1752         arr_traps_template[NOTIFIER_CALL_CHAIN_INDEX] = arch_construct_brunch ((unsigned int)kprobe_handler, do_bp_handler + NOTIFIER_CALL_CHAIN_INDEX * 4, 1);
1753
1754         // Insert new code
1755         memcpy ((void *) do_bp_handler, arr_traps_template, code_size);
1756         flush_icache_range (do_bp_handler, do_bp_handler + code_size);
1757         if((ret = dbi_register_kprobe (&trampoline_p, 0)) != 0){
1758                 //dbi_unregister_jprobe(&do_exit_p, 0);
1759                 return ret;
1760         }
1761
1762         return ret;
1763 }
1764
1765 void __exit dbi_arch_exit_kprobes (void)
1766 {
1767         unsigned int do_bp_handler;
1768
1769         unsigned int insns_num = 0;
1770         unsigned int code_size = 0;
1771
1772         // Get instruction address
1773         do_bp_handler = (unsigned int) kallsyms_search ("do_undefinstr");
1774
1775         //dbi_unregister_jprobe(&do_exit_p, 0);
1776
1777         // Replace back the original code
1778
1779         insns_num = sizeof (arr_traps_template) / sizeof (arr_traps_template[0]);
1780         code_size = insns_num * sizeof (unsigned int);
1781         memcpy ((void *) do_bp_handler, arr_traps_original, code_size);
1782         flush_icache_range (do_bp_handler, do_bp_handler + code_size);
1783         kfree (arr_traps_original);
1784         arr_traps_original = NULL;
1785 }
1786
1787
1788 //EXPORT_SYMBOL_GPL (dbi_arch_uprobe_return);
1789 //EXPORT_SYMBOL_GPL (dbi_arch_exit_kprobes);