1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2010-2017 Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
5 * membarrier system call
10 * For documentation purposes, here are some membarrier ordering
11 * scenarios to keep in mind:
13 * A) Userspace thread execution after IPI vs membarrier's memory
14 * barrier before sending the IPI
16 * Userspace variables:
20 * The memory barrier at the start of membarrier() on CPU0 is necessary in
21 * order to enforce the guarantee that any writes occurring on CPU0 before
22 * the membarrier() is executed will be visible to any code executing on
23 * CPU1 after the IPI-induced memory barrier:
30 * b: send IPI IPI-induced mb
37 * BUG_ON(r1 == 0 && r2 == 0)
39 * The write to y and load from x by CPU1 are unordered by the hardware,
40 * so it's possible to have "r1 = x" reordered before "y = 1" at any
41 * point after (b). If the memory barrier at (a) is omitted, then "x = 1"
42 * can be reordered after (a) (although not after (c)), so we get r1 == 0
43 * and r2 == 0. This violates the guarantee that membarrier() is
44 * supposed by provide.
46 * The timing of the memory barrier at (a) has to ensure that it executes
47 * before the IPI-induced memory barrier on CPU1.
49 * B) Userspace thread execution before IPI vs membarrier's memory
50 * barrier after completing the IPI
52 * Userspace variables:
56 * The memory barrier at the end of membarrier() on CPU0 is necessary in
57 * order to enforce the guarantee that any writes occurring on CPU1 before
58 * the membarrier() is executed will be visible to any code executing on
59 * CPU0 after the membarrier():
69 * b: send IPI IPI-induced mb
72 * BUG_ON(r1 == 0 && r2 == 1)
74 * The writes to x and y are unordered by the hardware, so it's possible to
75 * have "r2 = 1" even though the write to x doesn't execute until (b). If
76 * the memory barrier at (c) is omitted then "r1 = x" can be reordered
77 * before (b) (although not before (a)), so we get "r1 = 0". This violates
78 * the guarantee that membarrier() is supposed to provide.
80 * The timing of the memory barrier at (c) has to ensure that it executes
81 * after the IPI-induced memory barrier on CPU1.
83 * C) Scheduling userspace thread -> kthread -> userspace thread vs membarrier
89 * d: switch to kthread (includes mb)
90 * b: read rq->curr->mm == NULL
91 * e: switch to user (includes mb)
94 * Using the scenario from (A), we can show that (a) needs to be paired
95 * with (e). Using the scenario from (B), we can show that (c) needs to
98 * D) exit_mm vs membarrier
100 * Two thread groups are created, A and B. Thread group B is created by
101 * issuing clone from group A with flag CLONE_VM set, but not CLONE_THREAD.
102 * Let's assume we have a single thread within each thread group (Thread A
103 * and Thread B). Thread A runs on CPU0, Thread B runs on CPU1.
111 * e: current->mm = NULL
112 * b: read rq->curr->mm == NULL
115 * Using scenario (B), we can show that (c) needs to be paired with (d).
117 * E) kthread_{use,unuse}_mm vs membarrier
125 * e: current->mm = NULL
126 * b: read rq->curr->mm == NULL
128 * f: current->mm = mm
132 * Using the scenario from (A), we can show that (a) needs to be paired
133 * with (g). Using the scenario from (B), we can show that (c) needs to
134 * be paired with (d).
138 * Bitmask made from a "or" of all commands within enum membarrier_cmd,
139 * except MEMBARRIER_CMD_QUERY.
141 #ifdef CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE
142 #define MEMBARRIER_PRIVATE_EXPEDITED_SYNC_CORE_BITMASK \
143 (MEMBARRIER_CMD_PRIVATE_EXPEDITED_SYNC_CORE \
144 | MEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED_SYNC_CORE)
146 #define MEMBARRIER_PRIVATE_EXPEDITED_SYNC_CORE_BITMASK 0
150 #define MEMBARRIER_PRIVATE_EXPEDITED_RSEQ_BITMASK \
151 (MEMBARRIER_CMD_PRIVATE_EXPEDITED_RSEQ \
152 | MEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED_RSEQ)
154 #define MEMBARRIER_PRIVATE_EXPEDITED_RSEQ_BITMASK 0
157 #define MEMBARRIER_CMD_BITMASK \
158 (MEMBARRIER_CMD_GLOBAL | MEMBARRIER_CMD_GLOBAL_EXPEDITED \
159 | MEMBARRIER_CMD_REGISTER_GLOBAL_EXPEDITED \
160 | MEMBARRIER_CMD_PRIVATE_EXPEDITED \
161 | MEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED \
162 | MEMBARRIER_PRIVATE_EXPEDITED_SYNC_CORE_BITMASK \
163 | MEMBARRIER_PRIVATE_EXPEDITED_RSEQ_BITMASK)
165 static void ipi_mb(void *info)
167 smp_mb(); /* IPIs should be serializing but paranoid. */
170 static void ipi_sync_core(void *info)
173 * The smp_mb() in membarrier after all the IPIs is supposed to
174 * ensure that memory on remote CPUs that occur before the IPI
175 * become visible to membarrier()'s caller -- see scenario B in
176 * the big comment at the top of this file.
178 * A sync_core() would provide this guarantee, but
179 * sync_core_before_usermode() might end up being deferred until
180 * after membarrier()'s smp_mb().
182 smp_mb(); /* IPIs should be serializing but paranoid. */
184 sync_core_before_usermode();
187 static void ipi_rseq(void *info)
190 * Ensure that all stores done by the calling thread are visible
191 * to the current task before the current task resumes. We could
192 * probably optimize this away on most architectures, but by the
193 * time we've already sent an IPI, the cost of the extra smp_mb()
197 rseq_preempt(current);
200 static void ipi_sync_rq_state(void *info)
202 struct mm_struct *mm = (struct mm_struct *) info;
204 if (current->mm != mm)
206 this_cpu_write(runqueues.membarrier_state,
207 atomic_read(&mm->membarrier_state));
209 * Issue a memory barrier after setting
210 * MEMBARRIER_STATE_GLOBAL_EXPEDITED in the current runqueue to
211 * guarantee that no memory access following registration is reordered
212 * before registration.
217 void membarrier_exec_mmap(struct mm_struct *mm)
220 * Issue a memory barrier before clearing membarrier_state to
221 * guarantee that no memory access prior to exec is reordered after
222 * clearing this state.
225 atomic_set(&mm->membarrier_state, 0);
227 * Keep the runqueue membarrier_state in sync with this mm
230 this_cpu_write(runqueues.membarrier_state, 0);
233 void membarrier_update_current_mm(struct mm_struct *next_mm)
235 struct rq *rq = this_rq();
236 int membarrier_state = 0;
239 membarrier_state = atomic_read(&next_mm->membarrier_state);
240 if (READ_ONCE(rq->membarrier_state) == membarrier_state)
242 WRITE_ONCE(rq->membarrier_state, membarrier_state);
245 static int membarrier_global_expedited(void)
248 cpumask_var_t tmpmask;
250 if (num_online_cpus() == 1)
254 * Matches memory barriers around rq->curr modification in
257 smp_mb(); /* system call entry is not a mb. */
259 if (!zalloc_cpumask_var(&tmpmask, GFP_KERNEL))
264 for_each_online_cpu(cpu) {
265 struct task_struct *p;
268 * Skipping the current CPU is OK even through we can be
269 * migrated at any point. The current CPU, at the point
270 * where we read raw_smp_processor_id(), is ensured to
271 * be in program order with respect to the caller
272 * thread. Therefore, we can skip this CPU from the
275 if (cpu == raw_smp_processor_id())
278 if (!(READ_ONCE(cpu_rq(cpu)->membarrier_state) &
279 MEMBARRIER_STATE_GLOBAL_EXPEDITED))
283 * Skip the CPU if it runs a kernel thread which is not using
286 p = rcu_dereference(cpu_rq(cpu)->curr);
290 __cpumask_set_cpu(cpu, tmpmask);
295 smp_call_function_many(tmpmask, ipi_mb, NULL, 1);
298 free_cpumask_var(tmpmask);
302 * Memory barrier on the caller thread _after_ we finished
303 * waiting for the last IPI. Matches memory barriers around
304 * rq->curr modification in scheduler.
306 smp_mb(); /* exit from system call is not a mb */
310 static int membarrier_private_expedited(int flags, int cpu_id)
312 cpumask_var_t tmpmask;
313 struct mm_struct *mm = current->mm;
314 smp_call_func_t ipi_func = ipi_mb;
316 if (flags == MEMBARRIER_FLAG_SYNC_CORE) {
317 if (!IS_ENABLED(CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE))
319 if (!(atomic_read(&mm->membarrier_state) &
320 MEMBARRIER_STATE_PRIVATE_EXPEDITED_SYNC_CORE_READY))
322 ipi_func = ipi_sync_core;
323 } else if (flags == MEMBARRIER_FLAG_RSEQ) {
324 if (!IS_ENABLED(CONFIG_RSEQ))
326 if (!(atomic_read(&mm->membarrier_state) &
327 MEMBARRIER_STATE_PRIVATE_EXPEDITED_RSEQ_READY))
332 if (!(atomic_read(&mm->membarrier_state) &
333 MEMBARRIER_STATE_PRIVATE_EXPEDITED_READY))
337 if (flags != MEMBARRIER_FLAG_SYNC_CORE &&
338 (atomic_read(&mm->mm_users) == 1 || num_online_cpus() == 1))
342 * Matches memory barriers around rq->curr modification in
345 smp_mb(); /* system call entry is not a mb. */
347 if (cpu_id < 0 && !zalloc_cpumask_var(&tmpmask, GFP_KERNEL))
353 struct task_struct *p;
355 if (cpu_id >= nr_cpu_ids || !cpu_online(cpu_id))
358 p = rcu_dereference(cpu_rq(cpu_id)->curr);
359 if (!p || p->mm != mm) {
368 for_each_online_cpu(cpu) {
369 struct task_struct *p;
371 p = rcu_dereference(cpu_rq(cpu)->curr);
372 if (p && p->mm == mm)
373 __cpumask_set_cpu(cpu, tmpmask);
380 * smp_call_function_single() will call ipi_func() if cpu_id
381 * is the calling CPU.
383 smp_call_function_single(cpu_id, ipi_func, NULL, 1);
386 * For regular membarrier, we can save a few cycles by
387 * skipping the current cpu -- we're about to do smp_mb()
388 * below, and if we migrate to a different cpu, this cpu
389 * and the new cpu will execute a full barrier in the
392 * For SYNC_CORE, we do need a barrier on the current cpu --
393 * otherwise, if we are migrated and replaced by a different
394 * task in the same mm just before, during, or after
395 * membarrier, we will end up with some thread in the mm
396 * running without a core sync.
398 * For RSEQ, don't rseq_preempt() the caller. User code
399 * is not supposed to issue syscalls at all from inside an
400 * rseq critical section.
402 if (flags != MEMBARRIER_FLAG_SYNC_CORE) {
404 smp_call_function_many(tmpmask, ipi_func, NULL, true);
407 on_each_cpu_mask(tmpmask, ipi_func, NULL, true);
413 free_cpumask_var(tmpmask);
417 * Memory barrier on the caller thread _after_ we finished
418 * waiting for the last IPI. Matches memory barriers around
419 * rq->curr modification in scheduler.
421 smp_mb(); /* exit from system call is not a mb */
426 static int sync_runqueues_membarrier_state(struct mm_struct *mm)
428 int membarrier_state = atomic_read(&mm->membarrier_state);
429 cpumask_var_t tmpmask;
432 if (atomic_read(&mm->mm_users) == 1 || num_online_cpus() == 1) {
433 this_cpu_write(runqueues.membarrier_state, membarrier_state);
436 * For single mm user, we can simply issue a memory barrier
437 * after setting MEMBARRIER_STATE_GLOBAL_EXPEDITED in the
438 * mm and in the current runqueue to guarantee that no memory
439 * access following registration is reordered before
446 if (!zalloc_cpumask_var(&tmpmask, GFP_KERNEL))
450 * For mm with multiple users, we need to ensure all future
451 * scheduler executions will observe @mm's new membarrier
457 * For each cpu runqueue, if the task's mm match @mm, ensure that all
458 * @mm's membarrier state set bits are also set in the runqueue's
459 * membarrier state. This ensures that a runqueue scheduling
460 * between threads which are users of @mm has its membarrier state
465 for_each_online_cpu(cpu) {
466 struct rq *rq = cpu_rq(cpu);
467 struct task_struct *p;
469 p = rcu_dereference(rq->curr);
470 if (p && p->mm == mm)
471 __cpumask_set_cpu(cpu, tmpmask);
475 on_each_cpu_mask(tmpmask, ipi_sync_rq_state, mm, true);
477 free_cpumask_var(tmpmask);
483 static int membarrier_register_global_expedited(void)
485 struct task_struct *p = current;
486 struct mm_struct *mm = p->mm;
489 if (atomic_read(&mm->membarrier_state) &
490 MEMBARRIER_STATE_GLOBAL_EXPEDITED_READY)
492 atomic_or(MEMBARRIER_STATE_GLOBAL_EXPEDITED, &mm->membarrier_state);
493 ret = sync_runqueues_membarrier_state(mm);
496 atomic_or(MEMBARRIER_STATE_GLOBAL_EXPEDITED_READY,
497 &mm->membarrier_state);
502 static int membarrier_register_private_expedited(int flags)
504 struct task_struct *p = current;
505 struct mm_struct *mm = p->mm;
506 int ready_state = MEMBARRIER_STATE_PRIVATE_EXPEDITED_READY,
507 set_state = MEMBARRIER_STATE_PRIVATE_EXPEDITED,
510 if (flags == MEMBARRIER_FLAG_SYNC_CORE) {
511 if (!IS_ENABLED(CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE))
514 MEMBARRIER_STATE_PRIVATE_EXPEDITED_SYNC_CORE_READY;
515 } else if (flags == MEMBARRIER_FLAG_RSEQ) {
516 if (!IS_ENABLED(CONFIG_RSEQ))
519 MEMBARRIER_STATE_PRIVATE_EXPEDITED_RSEQ_READY;
525 * We need to consider threads belonging to different thread
526 * groups, which use the same mm. (CLONE_VM but not
529 if ((atomic_read(&mm->membarrier_state) & ready_state) == ready_state)
531 if (flags & MEMBARRIER_FLAG_SYNC_CORE)
532 set_state |= MEMBARRIER_STATE_PRIVATE_EXPEDITED_SYNC_CORE;
533 if (flags & MEMBARRIER_FLAG_RSEQ)
534 set_state |= MEMBARRIER_STATE_PRIVATE_EXPEDITED_RSEQ;
535 atomic_or(set_state, &mm->membarrier_state);
536 ret = sync_runqueues_membarrier_state(mm);
539 atomic_or(ready_state, &mm->membarrier_state);
545 * sys_membarrier - issue memory barriers on a set of threads
546 * @cmd: Takes command values defined in enum membarrier_cmd.
547 * @flags: Currently needs to be 0 for all commands other than
548 * MEMBARRIER_CMD_PRIVATE_EXPEDITED_RSEQ: in the latter
549 * case it can be MEMBARRIER_CMD_FLAG_CPU, indicating that @cpu_id
550 * contains the CPU on which to interrupt (= restart)
551 * the RSEQ critical section.
552 * @cpu_id: if @flags == MEMBARRIER_CMD_FLAG_CPU, indicates the cpu on which
553 * RSEQ CS should be interrupted (@cmd must be
554 * MEMBARRIER_CMD_PRIVATE_EXPEDITED_RSEQ).
556 * If this system call is not implemented, -ENOSYS is returned. If the
557 * command specified does not exist, not available on the running
558 * kernel, or if the command argument is invalid, this system call
559 * returns -EINVAL. For a given command, with flags argument set to 0,
560 * if this system call returns -ENOSYS or -EINVAL, it is guaranteed to
561 * always return the same value until reboot. In addition, it can return
562 * -ENOMEM if there is not enough memory available to perform the system
565 * All memory accesses performed in program order from each targeted thread
566 * is guaranteed to be ordered with respect to sys_membarrier(). If we use
567 * the semantic "barrier()" to represent a compiler barrier forcing memory
568 * accesses to be performed in program order across the barrier, and
569 * smp_mb() to represent explicit memory barriers forcing full memory
570 * ordering across the barrier, we have the following ordering table for
571 * each pair of barrier(), sys_membarrier() and smp_mb():
573 * The pair ordering is detailed as (O: ordered, X: not ordered):
575 * barrier() smp_mb() sys_membarrier()
578 * sys_membarrier() O O O
580 SYSCALL_DEFINE3(membarrier, int, cmd, unsigned int, flags, int, cpu_id)
583 case MEMBARRIER_CMD_PRIVATE_EXPEDITED_RSEQ:
584 if (unlikely(flags && flags != MEMBARRIER_CMD_FLAG_CPU))
592 if (!(flags & MEMBARRIER_CMD_FLAG_CPU))
596 case MEMBARRIER_CMD_QUERY:
598 int cmd_mask = MEMBARRIER_CMD_BITMASK;
600 if (tick_nohz_full_enabled())
601 cmd_mask &= ~MEMBARRIER_CMD_GLOBAL;
604 case MEMBARRIER_CMD_GLOBAL:
605 /* MEMBARRIER_CMD_GLOBAL is not compatible with nohz_full. */
606 if (tick_nohz_full_enabled())
608 if (num_online_cpus() > 1)
611 case MEMBARRIER_CMD_GLOBAL_EXPEDITED:
612 return membarrier_global_expedited();
613 case MEMBARRIER_CMD_REGISTER_GLOBAL_EXPEDITED:
614 return membarrier_register_global_expedited();
615 case MEMBARRIER_CMD_PRIVATE_EXPEDITED:
616 return membarrier_private_expedited(0, cpu_id);
617 case MEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED:
618 return membarrier_register_private_expedited(0);
619 case MEMBARRIER_CMD_PRIVATE_EXPEDITED_SYNC_CORE:
620 return membarrier_private_expedited(MEMBARRIER_FLAG_SYNC_CORE, cpu_id);
621 case MEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED_SYNC_CORE:
622 return membarrier_register_private_expedited(MEMBARRIER_FLAG_SYNC_CORE);
623 case MEMBARRIER_CMD_PRIVATE_EXPEDITED_RSEQ:
624 return membarrier_private_expedited(MEMBARRIER_FLAG_RSEQ, cpu_id);
625 case MEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED_RSEQ:
626 return membarrier_register_private_expedited(MEMBARRIER_FLAG_RSEQ);