1 // SPDX-License-Identifier: GPL-2.0
3 * Library implementing the most common irq chip callback functions
5 * Copyright (C) 2011, Thomas Gleixner
9 #include <linux/slab.h>
10 #include <linux/export.h>
11 #include <linux/irqdomain.h>
12 #include <linux/interrupt.h>
13 #include <linux/kernel_stat.h>
14 #include <linux/syscore_ops.h>
16 #include "internals.h"
18 static LIST_HEAD(gc_list);
19 static DEFINE_RAW_SPINLOCK(gc_lock);
22 * irq_gc_noop - NOOP function
25 void irq_gc_noop(struct irq_data *d)
30 * irq_gc_mask_disable_reg - Mask chip via disable register
33 * Chip has separate enable/disable registers instead of a single mask
36 void irq_gc_mask_disable_reg(struct irq_data *d)
38 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
39 struct irq_chip_type *ct = irq_data_get_chip_type(d);
43 irq_reg_writel(gc, mask, ct->regs.disable);
44 *ct->mask_cache &= ~mask;
49 * irq_gc_mask_set_bit - Mask chip via setting bit in mask register
52 * Chip has a single mask register. Values of this register are cached
53 * and protected by gc->lock
55 void irq_gc_mask_set_bit(struct irq_data *d)
57 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
58 struct irq_chip_type *ct = irq_data_get_chip_type(d);
62 *ct->mask_cache |= mask;
63 irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);
66 EXPORT_SYMBOL_GPL(irq_gc_mask_set_bit);
69 * irq_gc_mask_clr_bit - Mask chip via clearing bit in mask register
72 * Chip has a single mask register. Values of this register are cached
73 * and protected by gc->lock
75 void irq_gc_mask_clr_bit(struct irq_data *d)
77 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
78 struct irq_chip_type *ct = irq_data_get_chip_type(d);
82 *ct->mask_cache &= ~mask;
83 irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);
86 EXPORT_SYMBOL_GPL(irq_gc_mask_clr_bit);
89 * irq_gc_unmask_enable_reg - Unmask chip via enable register
92 * Chip has separate enable/disable registers instead of a single mask
95 void irq_gc_unmask_enable_reg(struct irq_data *d)
97 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
98 struct irq_chip_type *ct = irq_data_get_chip_type(d);
102 irq_reg_writel(gc, mask, ct->regs.enable);
103 *ct->mask_cache |= mask;
108 * irq_gc_ack_set_bit - Ack pending interrupt via setting bit
111 void irq_gc_ack_set_bit(struct irq_data *d)
113 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
114 struct irq_chip_type *ct = irq_data_get_chip_type(d);
118 irq_reg_writel(gc, mask, ct->regs.ack);
121 EXPORT_SYMBOL_GPL(irq_gc_ack_set_bit);
124 * irq_gc_ack_clr_bit - Ack pending interrupt via clearing bit
127 void irq_gc_ack_clr_bit(struct irq_data *d)
129 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
130 struct irq_chip_type *ct = irq_data_get_chip_type(d);
134 irq_reg_writel(gc, mask, ct->regs.ack);
139 * irq_gc_mask_disable_and_ack_set - Mask and ack pending interrupt
142 * This generic implementation of the irq_mask_ack method is for chips
143 * with separate enable/disable registers instead of a single mask
144 * register and where a pending interrupt is acknowledged by setting a
147 * Note: This is the only permutation currently used. Similar generic
148 * functions should be added here if other permutations are required.
150 void irq_gc_mask_disable_and_ack_set(struct irq_data *d)
152 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
153 struct irq_chip_type *ct = irq_data_get_chip_type(d);
157 irq_reg_writel(gc, mask, ct->regs.disable);
158 *ct->mask_cache &= ~mask;
159 irq_reg_writel(gc, mask, ct->regs.ack);
164 * irq_gc_eoi - EOI interrupt
167 void irq_gc_eoi(struct irq_data *d)
169 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
170 struct irq_chip_type *ct = irq_data_get_chip_type(d);
174 irq_reg_writel(gc, mask, ct->regs.eoi);
179 * irq_gc_set_wake - Set/clr wake bit for an interrupt
181 * @on: Indicates whether the wake bit should be set or cleared
183 * For chips where the wake from suspend functionality is not
184 * configured in a separate register and the wakeup active state is
185 * just stored in a bitmask.
187 int irq_gc_set_wake(struct irq_data *d, unsigned int on)
189 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
192 if (!(mask & gc->wake_enabled))
197 gc->wake_active |= mask;
199 gc->wake_active &= ~mask;
203 EXPORT_SYMBOL_GPL(irq_gc_set_wake);
205 static u32 irq_readl_be(void __iomem *addr)
207 return ioread32be(addr);
210 static void irq_writel_be(u32 val, void __iomem *addr)
212 iowrite32be(val, addr);
215 void irq_init_generic_chip(struct irq_chip_generic *gc, const char *name,
216 int num_ct, unsigned int irq_base,
217 void __iomem *reg_base, irq_flow_handler_t handler)
219 raw_spin_lock_init(&gc->lock);
221 gc->irq_base = irq_base;
222 gc->reg_base = reg_base;
223 gc->chip_types->chip.name = name;
224 gc->chip_types->handler = handler;
228 * irq_alloc_generic_chip - Allocate a generic chip and initialize it
229 * @name: Name of the irq chip
230 * @num_ct: Number of irq_chip_type instances associated with this
231 * @irq_base: Interrupt base nr for this chip
232 * @reg_base: Register base address (virtual)
233 * @handler: Default flow handler associated with this chip
235 * Returns an initialized irq_chip_generic structure. The chip defaults
236 * to the primary (index 0) irq_chip_type and @handler
238 struct irq_chip_generic *
239 irq_alloc_generic_chip(const char *name, int num_ct, unsigned int irq_base,
240 void __iomem *reg_base, irq_flow_handler_t handler)
242 struct irq_chip_generic *gc;
244 gc = kzalloc(struct_size(gc, chip_types, num_ct), GFP_KERNEL);
246 irq_init_generic_chip(gc, name, num_ct, irq_base, reg_base,
251 EXPORT_SYMBOL_GPL(irq_alloc_generic_chip);
254 irq_gc_init_mask_cache(struct irq_chip_generic *gc, enum irq_gc_flags flags)
256 struct irq_chip_type *ct = gc->chip_types;
257 u32 *mskptr = &gc->mask_cache, mskreg = ct->regs.mask;
260 for (i = 0; i < gc->num_ct; i++) {
261 if (flags & IRQ_GC_MASK_CACHE_PER_TYPE) {
262 mskptr = &ct[i].mask_cache_priv;
263 mskreg = ct[i].regs.mask;
265 ct[i].mask_cache = mskptr;
266 if (flags & IRQ_GC_INIT_MASK_CACHE)
267 *mskptr = irq_reg_readl(gc, mskreg);
272 * __irq_alloc_domain_generic_chips - Allocate generic chips for an irq domain
273 * @d: irq domain for which to allocate chips
274 * @irqs_per_chip: Number of interrupts each chip handles (max 32)
275 * @num_ct: Number of irq_chip_type instances associated with this
276 * @name: Name of the irq chip
277 * @handler: Default flow handler associated with these chips
278 * @clr: IRQ_* bits to clear in the mapping function
279 * @set: IRQ_* bits to set in the mapping function
280 * @gcflags: Generic chip specific setup flags
282 int __irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
283 int num_ct, const char *name,
284 irq_flow_handler_t handler,
285 unsigned int clr, unsigned int set,
286 enum irq_gc_flags gcflags)
288 struct irq_domain_chip_generic *dgc;
289 struct irq_chip_generic *gc;
300 numchips = DIV_ROUND_UP(d->revmap_size, irqs_per_chip);
304 /* Allocate a pointer, generic chip and chiptypes for each chip */
305 gc_sz = struct_size(gc, chip_types, num_ct);
306 dgc_sz = struct_size(dgc, gc, numchips);
307 sz = dgc_sz + numchips * gc_sz;
309 tmp = dgc = kzalloc(sz, GFP_KERNEL);
312 dgc->irqs_per_chip = irqs_per_chip;
313 dgc->num_chips = numchips;
314 dgc->irq_flags_to_set = set;
315 dgc->irq_flags_to_clear = clr;
316 dgc->gc_flags = gcflags;
319 /* Calc pointer to the first generic chip */
321 for (i = 0; i < numchips; i++) {
322 /* Store the pointer to the generic chip */
323 dgc->gc[i] = gc = tmp;
324 irq_init_generic_chip(gc, name, num_ct, i * irqs_per_chip,
328 if (gcflags & IRQ_GC_BE_IO) {
329 gc->reg_readl = &irq_readl_be;
330 gc->reg_writel = &irq_writel_be;
333 raw_spin_lock_irqsave(&gc_lock, flags);
334 list_add_tail(&gc->list, &gc_list);
335 raw_spin_unlock_irqrestore(&gc_lock, flags);
336 /* Calc pointer to the next generic chip */
341 EXPORT_SYMBOL_GPL(__irq_alloc_domain_generic_chips);
343 static struct irq_chip_generic *
344 __irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq)
346 struct irq_domain_chip_generic *dgc = d->gc;
350 return ERR_PTR(-ENODEV);
351 idx = hw_irq / dgc->irqs_per_chip;
352 if (idx >= dgc->num_chips)
353 return ERR_PTR(-EINVAL);
358 * irq_get_domain_generic_chip - Get a pointer to the generic chip of a hw_irq
359 * @d: irq domain pointer
360 * @hw_irq: Hardware interrupt number
362 struct irq_chip_generic *
363 irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq)
365 struct irq_chip_generic *gc = __irq_get_domain_generic_chip(d, hw_irq);
367 return !IS_ERR(gc) ? gc : NULL;
369 EXPORT_SYMBOL_GPL(irq_get_domain_generic_chip);
372 * Separate lockdep classes for interrupt chip which can nest irq_desc
373 * lock and request mutex.
375 static struct lock_class_key irq_nested_lock_class;
376 static struct lock_class_key irq_nested_request_class;
379 * irq_map_generic_chip - Map a generic chip for an irq domain
381 int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
382 irq_hw_number_t hw_irq)
384 struct irq_data *data = irq_domain_get_irq_data(d, virq);
385 struct irq_domain_chip_generic *dgc = d->gc;
386 struct irq_chip_generic *gc;
387 struct irq_chip_type *ct;
388 struct irq_chip *chip;
392 gc = __irq_get_domain_generic_chip(d, hw_irq);
396 idx = hw_irq % dgc->irqs_per_chip;
398 if (test_bit(idx, &gc->unused))
401 if (test_bit(idx, &gc->installed))
407 /* We only init the cache for the first mapping of a generic chip */
408 if (!gc->installed) {
409 raw_spin_lock_irqsave(&gc->lock, flags);
410 irq_gc_init_mask_cache(gc, dgc->gc_flags);
411 raw_spin_unlock_irqrestore(&gc->lock, flags);
414 /* Mark the interrupt as installed */
415 set_bit(idx, &gc->installed);
417 if (dgc->gc_flags & IRQ_GC_INIT_NESTED_LOCK)
418 irq_set_lockdep_class(virq, &irq_nested_lock_class,
419 &irq_nested_request_class);
421 if (chip->irq_calc_mask)
422 chip->irq_calc_mask(data);
424 data->mask = 1 << idx;
426 irq_domain_set_info(d, virq, hw_irq, chip, gc, ct->handler, NULL, NULL);
427 irq_modify_status(virq, dgc->irq_flags_to_clear, dgc->irq_flags_to_set);
431 static void irq_unmap_generic_chip(struct irq_domain *d, unsigned int virq)
433 struct irq_data *data = irq_domain_get_irq_data(d, virq);
434 struct irq_domain_chip_generic *dgc = d->gc;
435 unsigned int hw_irq = data->hwirq;
436 struct irq_chip_generic *gc;
439 gc = irq_get_domain_generic_chip(d, hw_irq);
443 irq_idx = hw_irq % dgc->irqs_per_chip;
445 clear_bit(irq_idx, &gc->installed);
446 irq_domain_set_info(d, virq, hw_irq, &no_irq_chip, NULL, NULL, NULL,
451 struct irq_domain_ops irq_generic_chip_ops = {
452 .map = irq_map_generic_chip,
453 .unmap = irq_unmap_generic_chip,
454 .xlate = irq_domain_xlate_onetwocell,
456 EXPORT_SYMBOL_GPL(irq_generic_chip_ops);
459 * irq_setup_generic_chip - Setup a range of interrupts with a generic chip
460 * @gc: Generic irq chip holding all data
461 * @msk: Bitmask holding the irqs to initialize relative to gc->irq_base
462 * @flags: Flags for initialization
463 * @clr: IRQ_* bits to clear
464 * @set: IRQ_* bits to set
466 * Set up max. 32 interrupts starting from gc->irq_base. Note, this
467 * initializes all interrupts to the primary irq_chip_type and its
468 * associated handler.
470 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
471 enum irq_gc_flags flags, unsigned int clr,
474 struct irq_chip_type *ct = gc->chip_types;
475 struct irq_chip *chip = &ct->chip;
478 raw_spin_lock(&gc_lock);
479 list_add_tail(&gc->list, &gc_list);
480 raw_spin_unlock(&gc_lock);
482 irq_gc_init_mask_cache(gc, flags);
484 for (i = gc->irq_base; msk; msk >>= 1, i++) {
488 if (flags & IRQ_GC_INIT_NESTED_LOCK)
489 irq_set_lockdep_class(i, &irq_nested_lock_class,
490 &irq_nested_request_class);
492 if (!(flags & IRQ_GC_NO_MASK)) {
493 struct irq_data *d = irq_get_irq_data(i);
495 if (chip->irq_calc_mask)
496 chip->irq_calc_mask(d);
498 d->mask = 1 << (i - gc->irq_base);
500 irq_set_chip_and_handler(i, chip, ct->handler);
501 irq_set_chip_data(i, gc);
502 irq_modify_status(i, clr, set);
504 gc->irq_cnt = i - gc->irq_base;
506 EXPORT_SYMBOL_GPL(irq_setup_generic_chip);
509 * irq_setup_alt_chip - Switch to alternative chip
510 * @d: irq_data for this interrupt
511 * @type: Flow type to be initialized
513 * Only to be called from chip->irq_set_type() callbacks.
515 int irq_setup_alt_chip(struct irq_data *d, unsigned int type)
517 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
518 struct irq_chip_type *ct = gc->chip_types;
521 for (i = 0; i < gc->num_ct; i++, ct++) {
522 if (ct->type & type) {
524 irq_data_to_desc(d)->handle_irq = ct->handler;
530 EXPORT_SYMBOL_GPL(irq_setup_alt_chip);
533 * irq_remove_generic_chip - Remove a chip
534 * @gc: Generic irq chip holding all data
535 * @msk: Bitmask holding the irqs to initialize relative to gc->irq_base
536 * @clr: IRQ_* bits to clear
537 * @set: IRQ_* bits to set
539 * Remove up to 32 interrupts starting from gc->irq_base.
541 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
542 unsigned int clr, unsigned int set)
544 unsigned int i = gc->irq_base;
546 raw_spin_lock(&gc_lock);
548 raw_spin_unlock(&gc_lock);
550 for (; msk; msk >>= 1, i++) {
554 /* Remove handler first. That will mask the irq line */
555 irq_set_handler(i, NULL);
556 irq_set_chip(i, &no_irq_chip);
557 irq_set_chip_data(i, NULL);
558 irq_modify_status(i, clr, set);
561 EXPORT_SYMBOL_GPL(irq_remove_generic_chip);
563 static struct irq_data *irq_gc_get_irq_data(struct irq_chip_generic *gc)
568 return irq_get_irq_data(gc->irq_base);
571 * We don't know which of the irqs has been actually
572 * installed. Use the first one.
577 virq = irq_find_mapping(gc->domain, gc->irq_base + __ffs(gc->installed));
578 return virq ? irq_get_irq_data(virq) : NULL;
582 static int irq_gc_suspend(void)
584 struct irq_chip_generic *gc;
586 list_for_each_entry(gc, &gc_list, list) {
587 struct irq_chip_type *ct = gc->chip_types;
589 if (ct->chip.irq_suspend) {
590 struct irq_data *data = irq_gc_get_irq_data(gc);
593 ct->chip.irq_suspend(data);
602 static void irq_gc_resume(void)
604 struct irq_chip_generic *gc;
606 list_for_each_entry(gc, &gc_list, list) {
607 struct irq_chip_type *ct = gc->chip_types;
612 if (ct->chip.irq_resume) {
613 struct irq_data *data = irq_gc_get_irq_data(gc);
616 ct->chip.irq_resume(data);
621 #define irq_gc_suspend NULL
622 #define irq_gc_resume NULL
625 static void irq_gc_shutdown(void)
627 struct irq_chip_generic *gc;
629 list_for_each_entry(gc, &gc_list, list) {
630 struct irq_chip_type *ct = gc->chip_types;
632 if (ct->chip.irq_pm_shutdown) {
633 struct irq_data *data = irq_gc_get_irq_data(gc);
636 ct->chip.irq_pm_shutdown(data);
641 static struct syscore_ops irq_gc_syscore_ops = {
642 .suspend = irq_gc_suspend,
643 .resume = irq_gc_resume,
644 .shutdown = irq_gc_shutdown,
647 static int __init irq_gc_init_ops(void)
649 register_syscore_ops(&irq_gc_syscore_ops);
652 device_initcall(irq_gc_init_ops);