3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #ifndef _INTEL_CHIPSET_H
29 #define _INTEL_CHIPSET_H
31 #define PCI_CHIP_I810 0x7121
32 #define PCI_CHIP_I810_DC100 0x7123
33 #define PCI_CHIP_I810_E 0x7125
34 #define PCI_CHIP_I815 0x1132
36 #define PCI_CHIP_I830_M 0x3577
37 #define PCI_CHIP_845_G 0x2562
38 #define PCI_CHIP_I855_GM 0x3582
39 #define PCI_CHIP_I865_G 0x2572
41 #define PCI_CHIP_I915_G 0x2582
42 #define PCI_CHIP_E7221_G 0x258A
43 #define PCI_CHIP_I915_GM 0x2592
44 #define PCI_CHIP_I945_G 0x2772
45 #define PCI_CHIP_I945_GM 0x27A2
46 #define PCI_CHIP_I945_GME 0x27AE
48 #define PCI_CHIP_Q35_G 0x29B2
49 #define PCI_CHIP_G33_G 0x29C2
50 #define PCI_CHIP_Q33_G 0x29D2
52 #define PCI_CHIP_IGD_GM 0xA011
53 #define PCI_CHIP_IGD_G 0xA001
55 #define IS_IGDGM(devid) ((devid) == PCI_CHIP_IGD_GM)
56 #define IS_IGDG(devid) ((devid) == PCI_CHIP_IGD_G)
57 #define IS_IGD(devid) (IS_IGDG(devid) || IS_IGDGM(devid))
59 #define PCI_CHIP_I965_G 0x29A2
60 #define PCI_CHIP_I965_Q 0x2992
61 #define PCI_CHIP_I965_G_1 0x2982
62 #define PCI_CHIP_I946_GZ 0x2972
63 #define PCI_CHIP_I965_GM 0x2A02
64 #define PCI_CHIP_I965_GME 0x2A12
66 #define PCI_CHIP_GM45_GM 0x2A42
68 #define PCI_CHIP_IGD_E_G 0x2E02
69 #define PCI_CHIP_Q45_G 0x2E12
70 #define PCI_CHIP_G45_G 0x2E22
71 #define PCI_CHIP_G41_G 0x2E32
73 #define PCI_CHIP_ILD_G 0x0042
74 #define PCI_CHIP_ILM_G 0x0046
76 #define PCI_CHIP_SANDYBRIDGE_GT1 0x0102 /* desktop */
77 #define PCI_CHIP_SANDYBRIDGE_GT2 0x0112
78 #define PCI_CHIP_SANDYBRIDGE_GT2_PLUS 0x0122
79 #define PCI_CHIP_SANDYBRIDGE_M_GT1 0x0106 /* mobile */
80 #define PCI_CHIP_SANDYBRIDGE_M_GT2 0x0116
81 #define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS 0x0126
82 #define PCI_CHIP_SANDYBRIDGE_S 0x010A /* server */
84 #define PCI_CHIP_IVYBRIDGE_GT1 0x0152 /* desktop */
85 #define PCI_CHIP_IVYBRIDGE_GT2 0x0162
86 #define PCI_CHIP_IVYBRIDGE_M_GT1 0x0156 /* mobile */
87 #define PCI_CHIP_IVYBRIDGE_M_GT2 0x0166
88 #define PCI_CHIP_IVYBRIDGE_S 0x015a /* server */
89 #define PCI_CHIP_IVYBRIDGE_S_GT2 0x016a /* server */
91 #define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */
92 #define PCI_CHIP_HASWELL_GT2 0x0412
93 #define PCI_CHIP_HASWELL_GT2_PLUS 0x0422
94 #define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */
95 #define PCI_CHIP_HASWELL_M_GT2 0x0416
96 #define PCI_CHIP_HASWELL_M_GT2_PLUS 0x0426
97 #define PCI_CHIP_HASWELL_S_GT1 0x040A /* Server */
98 #define PCI_CHIP_HASWELL_S_GT2 0x041A
99 #define PCI_CHIP_HASWELL_S_GT2_PLUS 0x042A
100 #define PCI_CHIP_HASWELL_SDV_GT1 0x0C02 /* Desktop */
101 #define PCI_CHIP_HASWELL_SDV_GT2 0x0C12
102 #define PCI_CHIP_HASWELL_SDV_GT2_PLUS 0x0C22
103 #define PCI_CHIP_HASWELL_SDV_M_GT1 0x0C06 /* Mobile */
104 #define PCI_CHIP_HASWELL_SDV_M_GT2 0x0C16
105 #define PCI_CHIP_HASWELL_SDV_M_GT2_PLUS 0x0C26
106 #define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A /* Server */
107 #define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A
108 #define PCI_CHIP_HASWELL_SDV_S_GT2_PLUS 0x0C2A
109 #define PCI_CHIP_HASWELL_ULT_GT1 0x0A02 /* Desktop */
110 #define PCI_CHIP_HASWELL_ULT_GT2 0x0A12
111 #define PCI_CHIP_HASWELL_ULT_GT2_PLUS 0x0A22
112 #define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 /* Mobile */
113 #define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16
114 #define PCI_CHIP_HASWELL_ULT_M_GT2_PLUS 0x0A26
115 #define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */
116 #define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A
117 #define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A
118 #define PCI_CHIP_HASWELL_CRW_GT1 0x0D02 /* Desktop */
119 #define PCI_CHIP_HASWELL_CRW_GT2 0x0D12
120 #define PCI_CHIP_HASWELL_CRW_GT2_PLUS 0x0D22
121 #define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D06 /* Mobile */
122 #define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D16
123 #define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D26
124 #define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A /* Server */
125 #define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A
126 #define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D2A
128 #define PCI_CHIP_VALLEYVIEW_PO 0x0f30 /* VLV PO board */
129 #define PCI_CHIP_VALLEYVIEW_1 0x0f31
130 #define PCI_CHIP_VALLEYVIEW_2 0x0f32
131 #define PCI_CHIP_VALLEYVIEW_3 0x0f33
133 #define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \
134 (devid) == PCI_CHIP_I915_GM || \
135 (devid) == PCI_CHIP_I945_GM || \
136 (devid) == PCI_CHIP_I945_GME || \
137 (devid) == PCI_CHIP_I965_GM || \
138 (devid) == PCI_CHIP_I965_GME || \
139 (devid) == PCI_CHIP_GM45_GM || IS_IGD(devid) || \
140 (devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \
141 (devid) == PCI_CHIP_IVYBRIDGE_M_GT2)
143 #define IS_G45(devid) ((devid) == PCI_CHIP_IGD_E_G || \
144 (devid) == PCI_CHIP_Q45_G || \
145 (devid) == PCI_CHIP_G45_G || \
146 (devid) == PCI_CHIP_G41_G)
147 #define IS_GM45(devid) ((devid) == PCI_CHIP_GM45_GM)
148 #define IS_G4X(devid) (IS_G45(devid) || IS_GM45(devid))
150 #define IS_ILD(devid) ((devid) == PCI_CHIP_ILD_G)
151 #define IS_ILM(devid) ((devid) == PCI_CHIP_ILM_G)
153 #define IS_915(devid) ((devid) == PCI_CHIP_I915_G || \
154 (devid) == PCI_CHIP_E7221_G || \
155 (devid) == PCI_CHIP_I915_GM)
157 #define IS_945GM(devid) ((devid) == PCI_CHIP_I945_GM || \
158 (devid) == PCI_CHIP_I945_GME)
160 #define IS_945(devid) ((devid) == PCI_CHIP_I945_G || \
161 (devid) == PCI_CHIP_I945_GM || \
162 (devid) == PCI_CHIP_I945_GME || \
165 #define IS_G33(devid) ((devid) == PCI_CHIP_G33_G || \
166 (devid) == PCI_CHIP_Q33_G || \
167 (devid) == PCI_CHIP_Q35_G || IS_IGD(devid))
169 #define IS_GEN2(devid) ((devid) == PCI_CHIP_I830_M || \
170 (devid) == PCI_CHIP_845_G || \
171 (devid) == PCI_CHIP_I855_GM || \
172 (devid) == PCI_CHIP_I865_G)
174 #define IS_GEN3(devid) (IS_945(devid) || IS_915(devid))
176 #define IS_GEN4(devid) ((devid) == PCI_CHIP_I965_G || \
177 (devid) == PCI_CHIP_I965_Q || \
178 (devid) == PCI_CHIP_I965_G_1 || \
179 (devid) == PCI_CHIP_I965_GM || \
180 (devid) == PCI_CHIP_I965_GME || \
181 (devid) == PCI_CHIP_I946_GZ || \
184 #define IS_GEN5(devid) (IS_ILD(devid) || IS_ILM(devid))
186 #define IS_GEN6(devid) ((devid) == PCI_CHIP_SANDYBRIDGE_GT1 || \
187 (devid) == PCI_CHIP_SANDYBRIDGE_GT2 || \
188 (devid) == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
189 (devid) == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
190 (devid) == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
191 (devid) == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \
192 (devid) == PCI_CHIP_SANDYBRIDGE_S)
194 #define IS_GEN7(devid) (IS_IVYBRIDGE(devid) || \
195 IS_HASWELL(devid) || \
196 IS_VALLEYVIEW(devid))
198 #define IS_IVYBRIDGE(devid) ((devid) == PCI_CHIP_IVYBRIDGE_GT1 || \
199 (devid) == PCI_CHIP_IVYBRIDGE_GT2 || \
200 (devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \
201 (devid) == PCI_CHIP_IVYBRIDGE_M_GT2 || \
202 (devid) == PCI_CHIP_IVYBRIDGE_S || \
203 (devid) == PCI_CHIP_IVYBRIDGE_S_GT2)
205 #define IS_VALLEYVIEW(devid) ((devid) == PCI_CHIP_VALLEYVIEW_PO || \
206 (devid) == PCI_CHIP_VALLEYVIEW_1 || \
207 (devid) == PCI_CHIP_VALLEYVIEW_2 || \
208 (devid) == PCI_CHIP_VALLEYVIEW_3)
210 #define IS_HSW_GT1(devid) ((devid) == PCI_CHIP_HASWELL_GT1 || \
211 (devid) == PCI_CHIP_HASWELL_M_GT1 || \
212 (devid) == PCI_CHIP_HASWELL_S_GT1 || \
213 (devid) == PCI_CHIP_HASWELL_SDV_GT1 || \
214 (devid) == PCI_CHIP_HASWELL_SDV_M_GT1 || \
215 (devid) == PCI_CHIP_HASWELL_SDV_S_GT1 || \
216 (devid) == PCI_CHIP_HASWELL_ULT_GT1 || \
217 (devid) == PCI_CHIP_HASWELL_ULT_M_GT1 || \
218 (devid) == PCI_CHIP_HASWELL_ULT_S_GT1 || \
219 (devid) == PCI_CHIP_HASWELL_CRW_GT1 || \
220 (devid) == PCI_CHIP_HASWELL_CRW_M_GT1 || \
221 (devid) == PCI_CHIP_HASWELL_CRW_S_GT1)
222 #define IS_HSW_GT2(devid) ((devid) == PCI_CHIP_HASWELL_GT2 || \
223 (devid) == PCI_CHIP_HASWELL_M_GT2 || \
224 (devid) == PCI_CHIP_HASWELL_S_GT2 || \
225 (devid) == PCI_CHIP_HASWELL_SDV_GT2 || \
226 (devid) == PCI_CHIP_HASWELL_SDV_M_GT2 || \
227 (devid) == PCI_CHIP_HASWELL_SDV_S_GT2 || \
228 (devid) == PCI_CHIP_HASWELL_ULT_GT2 || \
229 (devid) == PCI_CHIP_HASWELL_ULT_M_GT2 || \
230 (devid) == PCI_CHIP_HASWELL_ULT_S_GT2 || \
231 (devid) == PCI_CHIP_HASWELL_CRW_GT2 || \
232 (devid) == PCI_CHIP_HASWELL_CRW_M_GT2 || \
233 (devid) == PCI_CHIP_HASWELL_CRW_S_GT2 || \
234 (devid) == PCI_CHIP_HASWELL_GT2_PLUS || \
235 (devid) == PCI_CHIP_HASWELL_M_GT2_PLUS || \
236 (devid) == PCI_CHIP_HASWELL_S_GT2_PLUS || \
237 (devid) == PCI_CHIP_HASWELL_SDV_GT2_PLUS || \
238 (devid) == PCI_CHIP_HASWELL_SDV_M_GT2_PLUS || \
239 (devid) == PCI_CHIP_HASWELL_SDV_S_GT2_PLUS || \
240 (devid) == PCI_CHIP_HASWELL_ULT_GT2_PLUS || \
241 (devid) == PCI_CHIP_HASWELL_ULT_M_GT2_PLUS || \
242 (devid) == PCI_CHIP_HASWELL_ULT_S_GT2_PLUS || \
243 (devid) == PCI_CHIP_HASWELL_CRW_GT2_PLUS || \
244 (devid) == PCI_CHIP_HASWELL_CRW_M_GT2_PLUS || \
245 (devid) == PCI_CHIP_HASWELL_CRW_S_GT2_PLUS)
247 #define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \
250 #define IS_9XX(dev) (IS_GEN3(dev) || \
256 #endif /* _INTEL_CHIPSET_H */