3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #ifndef _INTEL_CHIPSET_H
29 #define _INTEL_CHIPSET_H
31 #define PCI_CHIP_ILD_G 0x0042
32 #define PCI_CHIP_ILM_G 0x0046
34 #define PCI_CHIP_SANDYBRIDGE_GT1 0x0102 /* desktop */
35 #define PCI_CHIP_SANDYBRIDGE_GT2 0x0112
36 #define PCI_CHIP_SANDYBRIDGE_GT2_PLUS 0x0122
37 #define PCI_CHIP_SANDYBRIDGE_M_GT1 0x0106 /* mobile */
38 #define PCI_CHIP_SANDYBRIDGE_M_GT2 0x0116
39 #define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS 0x0126
40 #define PCI_CHIP_SANDYBRIDGE_S 0x010A /* server */
42 #define PCI_CHIP_IVYBRIDGE_GT1 0x0152 /* desktop */
43 #define PCI_CHIP_IVYBRIDGE_GT2 0x0162
44 #define PCI_CHIP_IVYBRIDGE_M_GT1 0x0156 /* mobile */
45 #define PCI_CHIP_IVYBRIDGE_M_GT2 0x0166
46 #define PCI_CHIP_IVYBRIDGE_S 0x015a /* server */
47 #define PCI_CHIP_IVYBRIDGE_S_GT2 0x016a /* server */
49 #define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */
50 #define PCI_CHIP_HASWELL_GT2 0x0412
51 #define PCI_CHIP_HASWELL_GT2_PLUS 0x0422
52 #define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */
53 #define PCI_CHIP_HASWELL_M_GT2 0x0416
54 #define PCI_CHIP_HASWELL_M_GT2_PLUS 0x0426
55 #define PCI_CHIP_HASWELL_S_GT1 0x040A /* Server */
56 #define PCI_CHIP_HASWELL_S_GT2 0x041A
57 #define PCI_CHIP_HASWELL_S_GT2_PLUS 0x042A
58 #define PCI_CHIP_HASWELL_SDV_GT1 0x0C02 /* Desktop */
59 #define PCI_CHIP_HASWELL_SDV_GT2 0x0C12
60 #define PCI_CHIP_HASWELL_SDV_GT2_PLUS 0x0C22
61 #define PCI_CHIP_HASWELL_SDV_M_GT1 0x0C06 /* Mobile */
62 #define PCI_CHIP_HASWELL_SDV_M_GT2 0x0C16
63 #define PCI_CHIP_HASWELL_SDV_M_GT2_PLUS 0x0C26
64 #define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A /* Server */
65 #define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A
66 #define PCI_CHIP_HASWELL_SDV_S_GT2_PLUS 0x0C2A
67 #define PCI_CHIP_HASWELL_ULT_GT1 0x0A02 /* Desktop */
68 #define PCI_CHIP_HASWELL_ULT_GT2 0x0A12
69 #define PCI_CHIP_HASWELL_ULT_GT2_PLUS 0x0A22
70 #define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 /* Mobile */
71 #define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16
72 #define PCI_CHIP_HASWELL_ULT_M_GT2_PLUS 0x0A26
73 #define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */
74 #define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A
75 #define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A
76 #define PCI_CHIP_HASWELL_CRW_GT1 0x0D12 /* Desktop */
77 #define PCI_CHIP_HASWELL_CRW_GT2 0x0D22
78 #define PCI_CHIP_HASWELL_CRW_GT2_PLUS 0x0D32
79 #define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D16 /* Mobile */
80 #define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D26
81 #define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D36
82 #define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D1A /* Server */
83 #define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D2A
84 #define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D3A
86 #define PCI_CHIP_VALLEYVIEW_PO 0x0f30 /* power on board */
87 #define PCI_CHIP_VALLEYVIEW_1 0x0f31
88 #define PCI_CHIP_VALLEYVIEW_2 0x0f32
89 #define PCI_CHIP_VALLEYVIEW_3 0x0f33
91 #define IS_830(dev) (dev == 0x3577)
92 #define IS_845(dev) (dev == 0x2562)
93 #define IS_85X(dev) (dev == 0x3582)
94 #define IS_865(dev) (dev == 0x2572)
96 #define IS_GEN2(dev) (IS_830(dev) || \
101 #define IS_915G(dev) (dev == 0x2582 || \
103 #define IS_915GM(dev) (dev == 0x2592)
104 #define IS_945G(dev) (dev == 0x2772)
105 #define IS_945GM(dev) (dev == 0x27A2 || \
108 #define IS_915(dev) (IS_915G(dev) || \
111 #define IS_945(dev) (IS_945G(dev) || \
116 #define IS_G33(dev) (dev == 0x29C2 || \
120 #define IS_PINEVIEW(dev) (dev == 0xa001 || \
123 #define IS_GEN3(dev) (IS_915(dev) || \
128 #define IS_I965GM(dev) (dev == 0x2A02)
130 #define IS_VALLEYVIEW(dev) (((dev) == PCI_CHIP_VALLEYVIEW_PO) || \
131 ((dev) == PCI_CHIP_VALLEYVIEW_1) || \
132 ((dev) == PCI_CHIP_VALLEYVIEW_2) || \
133 ((dev) == PCI_CHIP_VALLEYVIEW_3))
135 #define IS_GEN4(dev) (dev == 0x2972 || \
152 #define IS_GM45(dev) (dev == 0x2A42)
155 #define IS_GEN5(dev) (dev == PCI_CHIP_ILD_G || \
156 dev == PCI_CHIP_ILM_G)
158 #define IS_GEN6(dev) (dev == PCI_CHIP_SANDYBRIDGE_GT1 || \
159 dev == PCI_CHIP_SANDYBRIDGE_GT2 || \
160 dev == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
161 dev == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
162 dev == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
163 dev == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \
164 dev == PCI_CHIP_SANDYBRIDGE_S)
166 #define IS_GEN7(devid) (IS_IVYBRIDGE(devid) || \
167 IS_HASWELL(devid) || \
168 IS_VALLEYVIEW(devid))
170 #define IS_IVYBRIDGE(dev) (dev == PCI_CHIP_IVYBRIDGE_GT1 || \
171 dev == PCI_CHIP_IVYBRIDGE_GT2 || \
172 dev == PCI_CHIP_IVYBRIDGE_M_GT1 || \
173 dev == PCI_CHIP_IVYBRIDGE_M_GT2 || \
174 dev == PCI_CHIP_IVYBRIDGE_S || \
175 dev == PCI_CHIP_IVYBRIDGE_S_GT2)
177 #define IS_HSW_GT1(devid) (devid == PCI_CHIP_HASWELL_GT1 || \
178 devid == PCI_CHIP_HASWELL_M_GT1 || \
179 devid == PCI_CHIP_HASWELL_S_GT1 || \
180 devid == PCI_CHIP_HASWELL_SDV_GT1 || \
181 devid == PCI_CHIP_HASWELL_SDV_M_GT1 || \
182 devid == PCI_CHIP_HASWELL_SDV_S_GT1 || \
183 devid == PCI_CHIP_HASWELL_ULT_GT1 || \
184 devid == PCI_CHIP_HASWELL_ULT_M_GT1 || \
185 devid == PCI_CHIP_HASWELL_ULT_S_GT1 || \
186 devid == PCI_CHIP_HASWELL_CRW_GT1 || \
187 devid == PCI_CHIP_HASWELL_CRW_M_GT1 || \
188 devid == PCI_CHIP_HASWELL_CRW_S_GT1)
189 #define IS_HSW_GT2(devid) (devid == PCI_CHIP_HASWELL_GT2 || \
190 devid == PCI_CHIP_HASWELL_M_GT2 || \
191 devid == PCI_CHIP_HASWELL_S_GT2 || \
192 devid == PCI_CHIP_HASWELL_SDV_GT2 || \
193 devid == PCI_CHIP_HASWELL_SDV_M_GT2 || \
194 devid == PCI_CHIP_HASWELL_SDV_S_GT2 || \
195 devid == PCI_CHIP_HASWELL_ULT_GT2 || \
196 devid == PCI_CHIP_HASWELL_ULT_M_GT2 || \
197 devid == PCI_CHIP_HASWELL_ULT_S_GT2 || \
198 devid == PCI_CHIP_HASWELL_CRW_GT2 || \
199 devid == PCI_CHIP_HASWELL_CRW_M_GT2 || \
200 devid == PCI_CHIP_HASWELL_CRW_S_GT2 || \
201 devid == PCI_CHIP_HASWELL_GT2_PLUS || \
202 devid == PCI_CHIP_HASWELL_M_GT2_PLUS || \
203 devid == PCI_CHIP_HASWELL_S_GT2_PLUS || \
204 devid == PCI_CHIP_HASWELL_SDV_GT2_PLUS || \
205 devid == PCI_CHIP_HASWELL_SDV_M_GT2_PLUS || \
206 devid == PCI_CHIP_HASWELL_SDV_S_GT2_PLUS || \
207 devid == PCI_CHIP_HASWELL_ULT_GT2_PLUS || \
208 devid == PCI_CHIP_HASWELL_ULT_M_GT2_PLUS || \
209 devid == PCI_CHIP_HASWELL_ULT_S_GT2_PLUS || \
210 devid == PCI_CHIP_HASWELL_CRW_GT2_PLUS || \
211 devid == PCI_CHIP_HASWELL_CRW_M_GT2_PLUS || \
212 devid == PCI_CHIP_HASWELL_CRW_S_GT2_PLUS)
214 #define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \
217 #define IS_G4X(dev) (dev == 0x2E02 || \
224 #define IS_9XX(dev) (IS_GEN3(dev) || \
230 #endif /* _INTEL_CHIPSET_H */