1 /**************************************************************************
3 * Copyright © 2007 Red Hat Inc.
4 * Copyright © 2007-2012 Intel Corporation
5 * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
29 **************************************************************************/
31 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
32 * Keith Whitwell <keithw-at-tungstengraphics-dot-com>
33 * Eric Anholt <eric@anholt.net>
34 * Dave Airlie <airlied@linux.ie>
42 #include <xf86atomic.h>
50 #include <sys/ioctl.h>
53 #include <sys/types.h>
58 #define ETIME ETIMEDOUT
60 #include "libdrm_lists.h"
61 #include "intel_bufmgr.h"
62 #include "intel_bufmgr_priv.h"
63 #include "intel_chipset.h"
64 #include "intel_aub.h"
77 #define VG_CLEAR(s) VG(memset(&s, 0, sizeof(s)))
79 #define DBG(...) do { \
80 if (bufmgr_gem->bufmgr.debug) \
81 fprintf(stderr, __VA_ARGS__); \
84 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
86 typedef struct _drm_intel_bo_gem drm_intel_bo_gem;
88 struct drm_intel_gem_bo_bucket {
93 typedef struct _drm_intel_bufmgr_gem {
94 drm_intel_bufmgr bufmgr;
100 pthread_mutex_t lock;
102 struct drm_i915_gem_exec_object *exec_objects;
103 struct drm_i915_gem_exec_object2 *exec2_objects;
104 drm_intel_bo **exec_bos;
108 /** Array of lists of cached gem objects of power-of-two sizes */
109 struct drm_intel_gem_bo_bucket cache_bucket[14 * 4];
114 drmMMListHead vma_cache;
115 int vma_count, vma_open, vma_max;
118 int available_fences;
121 unsigned int has_bsd : 1;
122 unsigned int has_blt : 1;
123 unsigned int has_relaxed_fencing : 1;
124 unsigned int has_llc : 1;
125 unsigned int has_wait_timeout : 1;
126 unsigned int bo_reuse : 1;
127 unsigned int no_exec : 1;
128 unsigned int has_vebox : 1;
134 } drm_intel_bufmgr_gem;
136 #define DRM_INTEL_RELOC_FENCE (1<<0)
138 typedef struct _drm_intel_reloc_target_info {
141 } drm_intel_reloc_target;
143 struct _drm_intel_bo_gem {
151 * Kenel-assigned global name for this object
153 unsigned int global_name;
154 drmMMListHead name_list;
157 * Index of the buffer within the validation list while preparing a
158 * batchbuffer execution.
163 * Current tiling mode
165 uint32_t tiling_mode;
166 uint32_t swizzle_mode;
167 unsigned long stride;
171 /** Array passed to the DRM containing relocation information. */
172 struct drm_i915_gem_relocation_entry *relocs;
174 * Array of info structs corresponding to relocs[i].target_handle etc
176 drm_intel_reloc_target *reloc_target_info;
177 /** Number of entries in relocs */
179 /** Mapped address for the buffer, saved across map/unmap cycles */
181 /** GTT virtual address for the buffer, saved across map/unmap cycles */
184 drmMMListHead vma_list;
190 * Boolean of whether this BO and its children have been included in
191 * the current drm_intel_bufmgr_check_aperture_space() total.
193 bool included_in_check_aperture;
196 * Boolean of whether this buffer has been used as a relocation
197 * target and had its size accounted for, and thus can't have any
198 * further relocations added to it.
200 bool used_as_reloc_target;
203 * Boolean of whether we have encountered an error whilst building the relocation tree.
208 * Boolean of whether this buffer can be re-used
213 * Size in bytes of this buffer and its relocation descendents.
215 * Used to avoid costly tree walking in
216 * drm_intel_bufmgr_check_aperture in the common case.
221 * Number of potential fence registers required by this buffer and its
224 int reloc_tree_fences;
226 /** Flags that we may need to do the SW_FINSIH ioctl on unmap. */
227 bool mapped_cpu_write;
231 drm_intel_aub_annotation *aub_annotations;
232 unsigned aub_annotation_count;
236 drm_intel_gem_estimate_batch_space(drm_intel_bo ** bo_array, int count);
239 drm_intel_gem_compute_batch_space(drm_intel_bo ** bo_array, int count);
242 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
243 uint32_t * swizzle_mode);
246 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
247 uint32_t tiling_mode,
250 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
253 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo);
255 static void drm_intel_gem_bo_free(drm_intel_bo *bo);
258 drm_intel_gem_bo_tile_size(drm_intel_bufmgr_gem *bufmgr_gem, unsigned long size,
259 uint32_t *tiling_mode)
261 unsigned long min_size, max_size;
264 if (*tiling_mode == I915_TILING_NONE)
267 /* 965+ just need multiples of page size for tiling */
268 if (bufmgr_gem->gen >= 4)
269 return ROUND_UP_TO(size, 4096);
271 /* Older chips need powers of two, of at least 512k or 1M */
272 if (bufmgr_gem->gen == 3) {
273 min_size = 1024*1024;
274 max_size = 128*1024*1024;
277 max_size = 64*1024*1024;
280 if (size > max_size) {
281 *tiling_mode = I915_TILING_NONE;
285 /* Do we need to allocate every page for the fence? */
286 if (bufmgr_gem->has_relaxed_fencing)
287 return ROUND_UP_TO(size, 4096);
289 for (i = min_size; i < size; i <<= 1)
296 * Round a given pitch up to the minimum required for X tiling on a
297 * given chip. We use 512 as the minimum to allow for a later tiling
301 drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem,
302 unsigned long pitch, uint32_t *tiling_mode)
304 unsigned long tile_width;
307 /* If untiled, then just align it so that we can do rendering
308 * to it with the 3D engine.
310 if (*tiling_mode == I915_TILING_NONE)
311 return ALIGN(pitch, 64);
313 if (*tiling_mode == I915_TILING_X
314 || (IS_915(bufmgr_gem->pci_device)
315 && *tiling_mode == I915_TILING_Y))
320 /* 965 is flexible */
321 if (bufmgr_gem->gen >= 4)
322 return ROUND_UP_TO(pitch, tile_width);
324 /* The older hardware has a maximum pitch of 8192 with tiled
325 * surfaces, so fallback to untiled if it's too large.
328 *tiling_mode = I915_TILING_NONE;
329 return ALIGN(pitch, 64);
332 /* Pre-965 needs power of two tile width */
333 for (i = tile_width; i < pitch; i <<= 1)
339 static struct drm_intel_gem_bo_bucket *
340 drm_intel_gem_bo_bucket_for_size(drm_intel_bufmgr_gem *bufmgr_gem,
345 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
346 struct drm_intel_gem_bo_bucket *bucket =
347 &bufmgr_gem->cache_bucket[i];
348 if (bucket->size >= size) {
357 drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem *bufmgr_gem)
361 for (i = 0; i < bufmgr_gem->exec_count; i++) {
362 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
363 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
365 if (bo_gem->relocs == NULL) {
366 DBG("%2d: %d (%s)\n", i, bo_gem->gem_handle,
371 for (j = 0; j < bo_gem->reloc_count; j++) {
372 drm_intel_bo *target_bo = bo_gem->reloc_target_info[j].bo;
373 drm_intel_bo_gem *target_gem =
374 (drm_intel_bo_gem *) target_bo;
376 DBG("%2d: %d (%s)@0x%08llx -> "
377 "%d (%s)@0x%08lx + 0x%08x\n",
379 bo_gem->gem_handle, bo_gem->name,
380 (unsigned long long)bo_gem->relocs[j].offset,
381 target_gem->gem_handle,
384 bo_gem->relocs[j].delta);
390 drm_intel_gem_bo_reference(drm_intel_bo *bo)
392 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
394 atomic_inc(&bo_gem->refcount);
398 * Adds the given buffer to the list of buffers to be validated (moved into the
399 * appropriate memory type) with the next batch submission.
401 * If a buffer is validated multiple times in a batch submission, it ends up
402 * with the intersection of the memory type flags and the union of the
406 drm_intel_add_validate_buffer(drm_intel_bo *bo)
408 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
409 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
412 if (bo_gem->validate_index != -1)
415 /* Extend the array of validation entries as necessary. */
416 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
417 int new_size = bufmgr_gem->exec_size * 2;
422 bufmgr_gem->exec_objects =
423 realloc(bufmgr_gem->exec_objects,
424 sizeof(*bufmgr_gem->exec_objects) * new_size);
425 bufmgr_gem->exec_bos =
426 realloc(bufmgr_gem->exec_bos,
427 sizeof(*bufmgr_gem->exec_bos) * new_size);
428 bufmgr_gem->exec_size = new_size;
431 index = bufmgr_gem->exec_count;
432 bo_gem->validate_index = index;
433 /* Fill in array entry */
434 bufmgr_gem->exec_objects[index].handle = bo_gem->gem_handle;
435 bufmgr_gem->exec_objects[index].relocation_count = bo_gem->reloc_count;
436 bufmgr_gem->exec_objects[index].relocs_ptr = (uintptr_t) bo_gem->relocs;
437 bufmgr_gem->exec_objects[index].alignment = 0;
438 bufmgr_gem->exec_objects[index].offset = 0;
439 bufmgr_gem->exec_bos[index] = bo;
440 bufmgr_gem->exec_count++;
444 drm_intel_add_validate_buffer2(drm_intel_bo *bo, int need_fence)
446 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
447 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
450 if (bo_gem->validate_index != -1) {
452 bufmgr_gem->exec2_objects[bo_gem->validate_index].flags |=
453 EXEC_OBJECT_NEEDS_FENCE;
457 /* Extend the array of validation entries as necessary. */
458 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
459 int new_size = bufmgr_gem->exec_size * 2;
464 bufmgr_gem->exec2_objects =
465 realloc(bufmgr_gem->exec2_objects,
466 sizeof(*bufmgr_gem->exec2_objects) * new_size);
467 bufmgr_gem->exec_bos =
468 realloc(bufmgr_gem->exec_bos,
469 sizeof(*bufmgr_gem->exec_bos) * new_size);
470 bufmgr_gem->exec_size = new_size;
473 index = bufmgr_gem->exec_count;
474 bo_gem->validate_index = index;
475 /* Fill in array entry */
476 bufmgr_gem->exec2_objects[index].handle = bo_gem->gem_handle;
477 bufmgr_gem->exec2_objects[index].relocation_count = bo_gem->reloc_count;
478 bufmgr_gem->exec2_objects[index].relocs_ptr = (uintptr_t)bo_gem->relocs;
479 bufmgr_gem->exec2_objects[index].alignment = 0;
480 bufmgr_gem->exec2_objects[index].offset = 0;
481 bufmgr_gem->exec_bos[index] = bo;
482 bufmgr_gem->exec2_objects[index].flags = 0;
483 bufmgr_gem->exec2_objects[index].rsvd1 = 0;
484 bufmgr_gem->exec2_objects[index].rsvd2 = 0;
486 bufmgr_gem->exec2_objects[index].flags |=
487 EXEC_OBJECT_NEEDS_FENCE;
489 bufmgr_gem->exec_count++;
492 #define RELOC_BUF_SIZE(x) ((I915_RELOC_HEADER + x * I915_RELOC0_STRIDE) * \
496 drm_intel_bo_gem_set_in_aperture_size(drm_intel_bufmgr_gem *bufmgr_gem,
497 drm_intel_bo_gem *bo_gem)
501 assert(!bo_gem->used_as_reloc_target);
503 /* The older chipsets are far-less flexible in terms of tiling,
504 * and require tiled buffer to be size aligned in the aperture.
505 * This means that in the worst possible case we will need a hole
506 * twice as large as the object in order for it to fit into the
507 * aperture. Optimal packing is for wimps.
509 size = bo_gem->bo.size;
510 if (bufmgr_gem->gen < 4 && bo_gem->tiling_mode != I915_TILING_NONE) {
513 if (bufmgr_gem->has_relaxed_fencing) {
514 if (bufmgr_gem->gen == 3)
515 min_size = 1024*1024;
519 while (min_size < size)
524 /* Account for worst-case alignment. */
528 bo_gem->reloc_tree_size = size;
532 drm_intel_setup_reloc_list(drm_intel_bo *bo)
534 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
535 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
536 unsigned int max_relocs = bufmgr_gem->max_relocs;
538 if (bo->size / 4 < max_relocs)
539 max_relocs = bo->size / 4;
541 bo_gem->relocs = malloc(max_relocs *
542 sizeof(struct drm_i915_gem_relocation_entry));
543 bo_gem->reloc_target_info = malloc(max_relocs *
544 sizeof(drm_intel_reloc_target));
545 if (bo_gem->relocs == NULL || bo_gem->reloc_target_info == NULL) {
546 bo_gem->has_error = true;
548 free (bo_gem->relocs);
549 bo_gem->relocs = NULL;
551 free (bo_gem->reloc_target_info);
552 bo_gem->reloc_target_info = NULL;
561 drm_intel_gem_bo_busy(drm_intel_bo *bo)
563 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
564 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
565 struct drm_i915_gem_busy busy;
569 busy.handle = bo_gem->gem_handle;
571 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_BUSY, &busy);
573 return (ret == 0 && busy.busy);
577 drm_intel_gem_bo_madvise_internal(drm_intel_bufmgr_gem *bufmgr_gem,
578 drm_intel_bo_gem *bo_gem, int state)
580 struct drm_i915_gem_madvise madv;
583 madv.handle = bo_gem->gem_handle;
586 drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MADVISE, &madv);
588 return madv.retained;
592 drm_intel_gem_bo_madvise(drm_intel_bo *bo, int madv)
594 return drm_intel_gem_bo_madvise_internal
595 ((drm_intel_bufmgr_gem *) bo->bufmgr,
596 (drm_intel_bo_gem *) bo,
600 /* drop the oldest entries that have been purged by the kernel */
602 drm_intel_gem_bo_cache_purge_bucket(drm_intel_bufmgr_gem *bufmgr_gem,
603 struct drm_intel_gem_bo_bucket *bucket)
605 while (!DRMLISTEMPTY(&bucket->head)) {
606 drm_intel_bo_gem *bo_gem;
608 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
609 bucket->head.next, head);
610 if (drm_intel_gem_bo_madvise_internal
611 (bufmgr_gem, bo_gem, I915_MADV_DONTNEED))
614 DRMLISTDEL(&bo_gem->head);
615 drm_intel_gem_bo_free(&bo_gem->bo);
619 static drm_intel_bo *
620 drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr,
624 uint32_t tiling_mode,
625 unsigned long stride)
627 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
628 drm_intel_bo_gem *bo_gem;
629 unsigned int page_size = getpagesize();
631 struct drm_intel_gem_bo_bucket *bucket;
632 bool alloc_from_cache;
633 unsigned long bo_size;
634 bool for_render = false;
636 if (flags & BO_ALLOC_FOR_RENDER)
639 /* Round the allocated size up to a power of two number of pages. */
640 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, size);
642 /* If we don't have caching at this size, don't actually round the
645 if (bucket == NULL) {
647 if (bo_size < page_size)
650 bo_size = bucket->size;
653 pthread_mutex_lock(&bufmgr_gem->lock);
654 /* Get a buffer out of the cache if available */
656 alloc_from_cache = false;
657 if (bucket != NULL && !DRMLISTEMPTY(&bucket->head)) {
659 /* Allocate new render-target BOs from the tail (MRU)
660 * of the list, as it will likely be hot in the GPU
661 * cache and in the aperture for us.
663 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
664 bucket->head.prev, head);
665 DRMLISTDEL(&bo_gem->head);
666 alloc_from_cache = true;
668 /* For non-render-target BOs (where we're probably
669 * going to map it first thing in order to fill it
670 * with data), check if the last BO in the cache is
671 * unbusy, and only reuse in that case. Otherwise,
672 * allocating a new buffer is probably faster than
673 * waiting for the GPU to finish.
675 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
676 bucket->head.next, head);
677 if (!drm_intel_gem_bo_busy(&bo_gem->bo)) {
678 alloc_from_cache = true;
679 DRMLISTDEL(&bo_gem->head);
683 if (alloc_from_cache) {
684 if (!drm_intel_gem_bo_madvise_internal
685 (bufmgr_gem, bo_gem, I915_MADV_WILLNEED)) {
686 drm_intel_gem_bo_free(&bo_gem->bo);
687 drm_intel_gem_bo_cache_purge_bucket(bufmgr_gem,
692 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
695 drm_intel_gem_bo_free(&bo_gem->bo);
700 pthread_mutex_unlock(&bufmgr_gem->lock);
702 if (!alloc_from_cache) {
703 struct drm_i915_gem_create create;
705 bo_gem = calloc(1, sizeof(*bo_gem));
709 bo_gem->bo.size = bo_size;
712 create.size = bo_size;
714 ret = drmIoctl(bufmgr_gem->fd,
715 DRM_IOCTL_I915_GEM_CREATE,
717 bo_gem->gem_handle = create.handle;
718 bo_gem->bo.handle = bo_gem->gem_handle;
723 bo_gem->bo.bufmgr = bufmgr;
725 bo_gem->tiling_mode = I915_TILING_NONE;
726 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
729 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
732 drm_intel_gem_bo_free(&bo_gem->bo);
736 DRMINITLISTHEAD(&bo_gem->name_list);
737 DRMINITLISTHEAD(&bo_gem->vma_list);
741 atomic_set(&bo_gem->refcount, 1);
742 bo_gem->validate_index = -1;
743 bo_gem->reloc_tree_fences = 0;
744 bo_gem->used_as_reloc_target = false;
745 bo_gem->has_error = false;
746 bo_gem->reusable = true;
747 bo_gem->aub_annotations = NULL;
748 bo_gem->aub_annotation_count = 0;
750 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
752 DBG("bo_create: buf %d (%s) %ldb\n",
753 bo_gem->gem_handle, bo_gem->name, size);
758 static drm_intel_bo *
759 drm_intel_gem_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
762 unsigned int alignment)
764 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size,
766 I915_TILING_NONE, 0);
769 static drm_intel_bo *
770 drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr,
773 unsigned int alignment)
775 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, 0,
776 I915_TILING_NONE, 0);
779 static drm_intel_bo *
780 drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
781 int x, int y, int cpp, uint32_t *tiling_mode,
782 unsigned long *pitch, unsigned long flags)
784 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
785 unsigned long size, stride;
789 unsigned long aligned_y, height_alignment;
791 tiling = *tiling_mode;
793 /* If we're tiled, our allocations are in 8 or 32-row blocks,
794 * so failure to align our height means that we won't allocate
797 * If we're untiled, we still have to align to 2 rows high
798 * because the data port accesses 2x2 blocks even if the
799 * bottom row isn't to be rendered, so failure to align means
800 * we could walk off the end of the GTT and fault. This is
801 * documented on 965, and may be the case on older chipsets
802 * too so we try to be careful.
805 height_alignment = 2;
807 if ((bufmgr_gem->gen == 2) && tiling != I915_TILING_NONE)
808 height_alignment = 16;
809 else if (tiling == I915_TILING_X
810 || (IS_915(bufmgr_gem->pci_device)
811 && tiling == I915_TILING_Y))
812 height_alignment = 8;
813 else if (tiling == I915_TILING_Y)
814 height_alignment = 32;
815 aligned_y = ALIGN(y, height_alignment);
818 stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, tiling_mode);
819 size = stride * aligned_y;
820 size = drm_intel_gem_bo_tile_size(bufmgr_gem, size, tiling_mode);
821 } while (*tiling_mode != tiling);
824 if (tiling == I915_TILING_NONE)
827 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, flags,
832 * Returns a drm_intel_bo wrapping the given buffer object handle.
834 * This can be used when one application needs to pass a buffer object
838 drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
842 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
843 drm_intel_bo_gem *bo_gem;
845 struct drm_gem_open open_arg;
846 struct drm_i915_gem_get_tiling get_tiling;
849 /* At the moment most applications only have a few named bo.
850 * For instance, in a DRI client only the render buffers passed
851 * between X and the client are named. And since X returns the
852 * alternating names for the front/back buffer a linear search
853 * provides a sufficiently fast match.
855 for (list = bufmgr_gem->named.next;
856 list != &bufmgr_gem->named;
858 bo_gem = DRMLISTENTRY(drm_intel_bo_gem, list, name_list);
859 if (bo_gem->global_name == handle) {
860 drm_intel_gem_bo_reference(&bo_gem->bo);
865 bo_gem = calloc(1, sizeof(*bo_gem));
870 open_arg.name = handle;
871 ret = drmIoctl(bufmgr_gem->fd,
875 DBG("Couldn't reference %s handle 0x%08x: %s\n",
876 name, handle, strerror(errno));
880 bo_gem->bo.size = open_arg.size;
881 bo_gem->bo.offset = 0;
882 bo_gem->bo.virtual = NULL;
883 bo_gem->bo.bufmgr = bufmgr;
885 atomic_set(&bo_gem->refcount, 1);
886 bo_gem->validate_index = -1;
887 bo_gem->gem_handle = open_arg.handle;
888 bo_gem->bo.handle = open_arg.handle;
889 bo_gem->global_name = handle;
890 bo_gem->reusable = false;
892 VG_CLEAR(get_tiling);
893 get_tiling.handle = bo_gem->gem_handle;
894 ret = drmIoctl(bufmgr_gem->fd,
895 DRM_IOCTL_I915_GEM_GET_TILING,
898 drm_intel_gem_bo_unreference(&bo_gem->bo);
901 bo_gem->tiling_mode = get_tiling.tiling_mode;
902 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
903 /* XXX stride is unknown */
904 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
906 DRMINITLISTHEAD(&bo_gem->vma_list);
907 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
908 DBG("bo_create_from_handle: %d (%s)\n", handle, bo_gem->name);
914 drm_intel_gem_bo_free(drm_intel_bo *bo)
916 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
917 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
918 struct drm_gem_close close;
921 DRMLISTDEL(&bo_gem->vma_list);
922 if (bo_gem->mem_virtual) {
923 VG(VALGRIND_FREELIKE_BLOCK(bo_gem->mem_virtual, 0));
924 munmap(bo_gem->mem_virtual, bo_gem->bo.size);
925 bufmgr_gem->vma_count--;
927 if (bo_gem->gtt_virtual) {
928 munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
929 bufmgr_gem->vma_count--;
932 /* Close this object */
934 close.handle = bo_gem->gem_handle;
935 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close);
937 DBG("DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
938 bo_gem->gem_handle, bo_gem->name, strerror(errno));
940 free(bo_gem->aub_annotations);
945 drm_intel_gem_bo_mark_mmaps_incoherent(drm_intel_bo *bo)
948 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
950 if (bo_gem->mem_virtual)
951 VALGRIND_MAKE_MEM_NOACCESS(bo_gem->mem_virtual, bo->size);
953 if (bo_gem->gtt_virtual)
954 VALGRIND_MAKE_MEM_NOACCESS(bo_gem->gtt_virtual, bo->size);
958 /** Frees all cached buffers significantly older than @time. */
960 drm_intel_gem_cleanup_bo_cache(drm_intel_bufmgr_gem *bufmgr_gem, time_t time)
964 if (bufmgr_gem->time == time)
967 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
968 struct drm_intel_gem_bo_bucket *bucket =
969 &bufmgr_gem->cache_bucket[i];
971 while (!DRMLISTEMPTY(&bucket->head)) {
972 drm_intel_bo_gem *bo_gem;
974 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
975 bucket->head.next, head);
976 if (time - bo_gem->free_time <= 1)
979 DRMLISTDEL(&bo_gem->head);
981 drm_intel_gem_bo_free(&bo_gem->bo);
985 bufmgr_gem->time = time;
988 static void drm_intel_gem_bo_purge_vma_cache(drm_intel_bufmgr_gem *bufmgr_gem)
992 DBG("%s: cached=%d, open=%d, limit=%d\n", __FUNCTION__,
993 bufmgr_gem->vma_count, bufmgr_gem->vma_open, bufmgr_gem->vma_max);
995 if (bufmgr_gem->vma_max < 0)
998 /* We may need to evict a few entries in order to create new mmaps */
999 limit = bufmgr_gem->vma_max - 2*bufmgr_gem->vma_open;
1003 while (bufmgr_gem->vma_count > limit) {
1004 drm_intel_bo_gem *bo_gem;
1006 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1007 bufmgr_gem->vma_cache.next,
1009 assert(bo_gem->map_count == 0);
1010 DRMLISTDELINIT(&bo_gem->vma_list);
1012 if (bo_gem->mem_virtual) {
1013 munmap(bo_gem->mem_virtual, bo_gem->bo.size);
1014 bo_gem->mem_virtual = NULL;
1015 bufmgr_gem->vma_count--;
1017 if (bo_gem->gtt_virtual) {
1018 munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
1019 bo_gem->gtt_virtual = NULL;
1020 bufmgr_gem->vma_count--;
1025 static void drm_intel_gem_bo_close_vma(drm_intel_bufmgr_gem *bufmgr_gem,
1026 drm_intel_bo_gem *bo_gem)
1028 bufmgr_gem->vma_open--;
1029 DRMLISTADDTAIL(&bo_gem->vma_list, &bufmgr_gem->vma_cache);
1030 if (bo_gem->mem_virtual)
1031 bufmgr_gem->vma_count++;
1032 if (bo_gem->gtt_virtual)
1033 bufmgr_gem->vma_count++;
1034 drm_intel_gem_bo_purge_vma_cache(bufmgr_gem);
1037 static void drm_intel_gem_bo_open_vma(drm_intel_bufmgr_gem *bufmgr_gem,
1038 drm_intel_bo_gem *bo_gem)
1040 bufmgr_gem->vma_open++;
1041 DRMLISTDEL(&bo_gem->vma_list);
1042 if (bo_gem->mem_virtual)
1043 bufmgr_gem->vma_count--;
1044 if (bo_gem->gtt_virtual)
1045 bufmgr_gem->vma_count--;
1046 drm_intel_gem_bo_purge_vma_cache(bufmgr_gem);
1050 drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time)
1052 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1053 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1054 struct drm_intel_gem_bo_bucket *bucket;
1057 /* Unreference all the target buffers */
1058 for (i = 0; i < bo_gem->reloc_count; i++) {
1059 if (bo_gem->reloc_target_info[i].bo != bo) {
1060 drm_intel_gem_bo_unreference_locked_timed(bo_gem->
1061 reloc_target_info[i].bo,
1065 bo_gem->reloc_count = 0;
1066 bo_gem->used_as_reloc_target = false;
1068 DBG("bo_unreference final: %d (%s)\n",
1069 bo_gem->gem_handle, bo_gem->name);
1071 /* release memory associated with this object */
1072 if (bo_gem->reloc_target_info) {
1073 free(bo_gem->reloc_target_info);
1074 bo_gem->reloc_target_info = NULL;
1076 if (bo_gem->relocs) {
1077 free(bo_gem->relocs);
1078 bo_gem->relocs = NULL;
1081 /* Clear any left-over mappings */
1082 if (bo_gem->map_count) {
1083 DBG("bo freed with non-zero map-count %d\n", bo_gem->map_count);
1084 bo_gem->map_count = 0;
1085 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1086 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1089 DRMLISTDEL(&bo_gem->name_list);
1091 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, bo->size);
1092 /* Put the buffer into our internal cache for reuse if we can. */
1093 if (bufmgr_gem->bo_reuse && bo_gem->reusable && bucket != NULL &&
1094 drm_intel_gem_bo_madvise_internal(bufmgr_gem, bo_gem,
1095 I915_MADV_DONTNEED)) {
1096 bo_gem->free_time = time;
1098 bo_gem->name = NULL;
1099 bo_gem->validate_index = -1;
1101 DRMLISTADDTAIL(&bo_gem->head, &bucket->head);
1103 drm_intel_gem_bo_free(bo);
1107 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
1110 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1112 assert(atomic_read(&bo_gem->refcount) > 0);
1113 if (atomic_dec_and_test(&bo_gem->refcount))
1114 drm_intel_gem_bo_unreference_final(bo, time);
1117 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo)
1119 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1121 assert(atomic_read(&bo_gem->refcount) > 0);
1122 if (atomic_dec_and_test(&bo_gem->refcount)) {
1123 drm_intel_bufmgr_gem *bufmgr_gem =
1124 (drm_intel_bufmgr_gem *) bo->bufmgr;
1125 struct timespec time;
1127 clock_gettime(CLOCK_MONOTONIC, &time);
1129 pthread_mutex_lock(&bufmgr_gem->lock);
1130 drm_intel_gem_bo_unreference_final(bo, time.tv_sec);
1131 drm_intel_gem_cleanup_bo_cache(bufmgr_gem, time.tv_sec);
1132 pthread_mutex_unlock(&bufmgr_gem->lock);
1136 static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable)
1138 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1139 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1140 struct drm_i915_gem_set_domain set_domain;
1143 pthread_mutex_lock(&bufmgr_gem->lock);
1145 if (bo_gem->map_count++ == 0)
1146 drm_intel_gem_bo_open_vma(bufmgr_gem, bo_gem);
1148 if (!bo_gem->mem_virtual) {
1149 struct drm_i915_gem_mmap mmap_arg;
1151 DBG("bo_map: %d (%s), map_count=%d\n",
1152 bo_gem->gem_handle, bo_gem->name, bo_gem->map_count);
1155 mmap_arg.handle = bo_gem->gem_handle;
1156 mmap_arg.offset = 0;
1157 mmap_arg.size = bo->size;
1158 ret = drmIoctl(bufmgr_gem->fd,
1159 DRM_IOCTL_I915_GEM_MMAP,
1163 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1164 __FILE__, __LINE__, bo_gem->gem_handle,
1165 bo_gem->name, strerror(errno));
1166 if (--bo_gem->map_count == 0)
1167 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1168 pthread_mutex_unlock(&bufmgr_gem->lock);
1171 VG(VALGRIND_MALLOCLIKE_BLOCK(mmap_arg.addr_ptr, mmap_arg.size, 0, 1));
1172 bo_gem->mem_virtual = (void *)(uintptr_t) mmap_arg.addr_ptr;
1174 DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1175 bo_gem->mem_virtual);
1176 bo->virtual = bo_gem->mem_virtual;
1178 VG_CLEAR(set_domain);
1179 set_domain.handle = bo_gem->gem_handle;
1180 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
1182 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
1184 set_domain.write_domain = 0;
1185 ret = drmIoctl(bufmgr_gem->fd,
1186 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1189 DBG("%s:%d: Error setting to CPU domain %d: %s\n",
1190 __FILE__, __LINE__, bo_gem->gem_handle,
1195 bo_gem->mapped_cpu_write = true;
1197 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1198 VG(VALGRIND_MAKE_MEM_DEFINED(bo_gem->mem_virtual, bo->size));
1199 pthread_mutex_unlock(&bufmgr_gem->lock);
1205 map_gtt(drm_intel_bo *bo)
1207 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1208 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1211 if (bo_gem->map_count++ == 0)
1212 drm_intel_gem_bo_open_vma(bufmgr_gem, bo_gem);
1214 /* Get a mapping of the buffer if we haven't before. */
1215 if (bo_gem->gtt_virtual == NULL) {
1216 struct drm_i915_gem_mmap_gtt mmap_arg;
1218 DBG("bo_map_gtt: mmap %d (%s), map_count=%d\n",
1219 bo_gem->gem_handle, bo_gem->name, bo_gem->map_count);
1222 mmap_arg.handle = bo_gem->gem_handle;
1224 /* Get the fake offset back... */
1225 ret = drmIoctl(bufmgr_gem->fd,
1226 DRM_IOCTL_I915_GEM_MMAP_GTT,
1230 DBG("%s:%d: Error preparing buffer map %d (%s): %s .\n",
1232 bo_gem->gem_handle, bo_gem->name,
1234 if (--bo_gem->map_count == 0)
1235 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1240 bo_gem->gtt_virtual = mmap(0, bo->size, PROT_READ | PROT_WRITE,
1241 MAP_SHARED, bufmgr_gem->fd,
1243 if (bo_gem->gtt_virtual == MAP_FAILED) {
1244 bo_gem->gtt_virtual = NULL;
1246 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1248 bo_gem->gem_handle, bo_gem->name,
1250 if (--bo_gem->map_count == 0)
1251 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1256 bo->virtual = bo_gem->gtt_virtual;
1258 DBG("bo_map_gtt: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1259 bo_gem->gtt_virtual);
1264 int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
1266 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1267 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1268 struct drm_i915_gem_set_domain set_domain;
1271 pthread_mutex_lock(&bufmgr_gem->lock);
1275 pthread_mutex_unlock(&bufmgr_gem->lock);
1279 /* Now move it to the GTT domain so that the GPU and CPU
1280 * caches are flushed and the GPU isn't actively using the
1283 * The pagefault handler does this domain change for us when
1284 * it has unbound the BO from the GTT, but it's up to us to
1285 * tell it when we're about to use things if we had done
1286 * rendering and it still happens to be bound to the GTT.
1288 VG_CLEAR(set_domain);
1289 set_domain.handle = bo_gem->gem_handle;
1290 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1291 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
1292 ret = drmIoctl(bufmgr_gem->fd,
1293 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1296 DBG("%s:%d: Error setting domain %d: %s\n",
1297 __FILE__, __LINE__, bo_gem->gem_handle,
1301 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1302 VG(VALGRIND_MAKE_MEM_DEFINED(bo_gem->gtt_virtual, bo->size));
1303 pthread_mutex_unlock(&bufmgr_gem->lock);
1309 * Performs a mapping of the buffer object like the normal GTT
1310 * mapping, but avoids waiting for the GPU to be done reading from or
1311 * rendering to the buffer.
1313 * This is used in the implementation of GL_ARB_map_buffer_range: The
1314 * user asks to create a buffer, then does a mapping, fills some
1315 * space, runs a drawing command, then asks to map it again without
1316 * synchronizing because it guarantees that it won't write over the
1317 * data that the GPU is busy using (or, more specifically, that if it
1318 * does write over the data, it acknowledges that rendering is
1322 int drm_intel_gem_bo_map_unsynchronized(drm_intel_bo *bo)
1324 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1327 /* If the CPU cache isn't coherent with the GTT, then use a
1328 * regular synchronized mapping. The problem is that we don't
1329 * track where the buffer was last used on the CPU side in
1330 * terms of drm_intel_bo_map vs drm_intel_gem_bo_map_gtt, so
1331 * we would potentially corrupt the buffer even when the user
1332 * does reasonable things.
1334 if (!bufmgr_gem->has_llc)
1335 return drm_intel_gem_bo_map_gtt(bo);
1337 pthread_mutex_lock(&bufmgr_gem->lock);
1339 pthread_mutex_unlock(&bufmgr_gem->lock);
1344 static int drm_intel_gem_bo_unmap(drm_intel_bo *bo)
1346 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1347 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1353 pthread_mutex_lock(&bufmgr_gem->lock);
1355 if (bo_gem->map_count <= 0) {
1356 DBG("attempted to unmap an unmapped bo\n");
1357 pthread_mutex_unlock(&bufmgr_gem->lock);
1358 /* Preserve the old behaviour of just treating this as a
1359 * no-op rather than reporting the error.
1364 if (bo_gem->mapped_cpu_write) {
1365 struct drm_i915_gem_sw_finish sw_finish;
1367 /* Cause a flush to happen if the buffer's pinned for
1368 * scanout, so the results show up in a timely manner.
1369 * Unlike GTT set domains, this only does work if the
1370 * buffer should be scanout-related.
1372 VG_CLEAR(sw_finish);
1373 sw_finish.handle = bo_gem->gem_handle;
1374 ret = drmIoctl(bufmgr_gem->fd,
1375 DRM_IOCTL_I915_GEM_SW_FINISH,
1377 ret = ret == -1 ? -errno : 0;
1379 bo_gem->mapped_cpu_write = false;
1382 /* We need to unmap after every innovation as we cannot track
1383 * an open vma for every bo as that will exhaasut the system
1384 * limits and cause later failures.
1386 if (--bo_gem->map_count == 0) {
1387 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1388 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1391 pthread_mutex_unlock(&bufmgr_gem->lock);
1396 int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo)
1398 return drm_intel_gem_bo_unmap(bo);
1402 drm_intel_gem_bo_subdata(drm_intel_bo *bo, unsigned long offset,
1403 unsigned long size, const void *data)
1405 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1406 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1407 struct drm_i915_gem_pwrite pwrite;
1411 pwrite.handle = bo_gem->gem_handle;
1412 pwrite.offset = offset;
1414 pwrite.data_ptr = (uint64_t) (uintptr_t) data;
1415 ret = drmIoctl(bufmgr_gem->fd,
1416 DRM_IOCTL_I915_GEM_PWRITE,
1420 DBG("%s:%d: Error writing data to buffer %d: (%d %d) %s .\n",
1421 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1422 (int)size, strerror(errno));
1429 drm_intel_gem_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id)
1431 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1432 struct drm_i915_get_pipe_from_crtc_id get_pipe_from_crtc_id;
1435 VG_CLEAR(get_pipe_from_crtc_id);
1436 get_pipe_from_crtc_id.crtc_id = crtc_id;
1437 ret = drmIoctl(bufmgr_gem->fd,
1438 DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID,
1439 &get_pipe_from_crtc_id);
1441 /* We return -1 here to signal that we don't
1442 * know which pipe is associated with this crtc.
1443 * This lets the caller know that this information
1444 * isn't available; using the wrong pipe for
1445 * vblank waiting can cause the chipset to lock up
1450 return get_pipe_from_crtc_id.pipe;
1454 drm_intel_gem_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
1455 unsigned long size, void *data)
1457 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1458 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1459 struct drm_i915_gem_pread pread;
1463 pread.handle = bo_gem->gem_handle;
1464 pread.offset = offset;
1466 pread.data_ptr = (uint64_t) (uintptr_t) data;
1467 ret = drmIoctl(bufmgr_gem->fd,
1468 DRM_IOCTL_I915_GEM_PREAD,
1472 DBG("%s:%d: Error reading data from buffer %d: (%d %d) %s .\n",
1473 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1474 (int)size, strerror(errno));
1480 /** Waits for all GPU rendering with the object to have completed. */
1482 drm_intel_gem_bo_wait_rendering(drm_intel_bo *bo)
1484 drm_intel_gem_bo_start_gtt_access(bo, 1);
1488 * Waits on a BO for the given amount of time.
1490 * @bo: buffer object to wait for
1491 * @timeout_ns: amount of time to wait in nanoseconds.
1492 * If value is less than 0, an infinite wait will occur.
1494 * Returns 0 if the wait was successful ie. the last batch referencing the
1495 * object has completed within the allotted time. Otherwise some negative return
1496 * value describes the error. Of particular interest is -ETIME when the wait has
1497 * failed to yield the desired result.
1499 * Similar to drm_intel_gem_bo_wait_rendering except a timeout parameter allows
1500 * the operation to give up after a certain amount of time. Another subtle
1501 * difference is the internal locking semantics are different (this variant does
1502 * not hold the lock for the duration of the wait). This makes the wait subject
1503 * to a larger userspace race window.
1505 * The implementation shall wait until the object is no longer actively
1506 * referenced within a batch buffer at the time of the call. The wait will
1507 * not guarantee that the buffer is re-issued via another thread, or an flinked
1508 * handle. Userspace must make sure this race does not occur if such precision
1511 int drm_intel_gem_bo_wait(drm_intel_bo *bo, int64_t timeout_ns)
1513 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1514 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1515 struct drm_i915_gem_wait wait;
1518 if (!bufmgr_gem->has_wait_timeout) {
1519 DBG("%s:%d: Timed wait is not supported. Falling back to "
1520 "infinite wait\n", __FILE__, __LINE__);
1522 drm_intel_gem_bo_wait_rendering(bo);
1525 return drm_intel_gem_bo_busy(bo) ? -ETIME : 0;
1529 wait.bo_handle = bo_gem->gem_handle;
1530 wait.timeout_ns = timeout_ns;
1532 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_WAIT, &wait);
1540 * Sets the object to the GTT read and possibly write domain, used by the X
1541 * 2D driver in the absence of kernel support to do drm_intel_gem_bo_map_gtt().
1543 * In combination with drm_intel_gem_bo_pin() and manual fence management, we
1544 * can do tiled pixmaps this way.
1547 drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable)
1549 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1550 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1551 struct drm_i915_gem_set_domain set_domain;
1554 VG_CLEAR(set_domain);
1555 set_domain.handle = bo_gem->gem_handle;
1556 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1557 set_domain.write_domain = write_enable ? I915_GEM_DOMAIN_GTT : 0;
1558 ret = drmIoctl(bufmgr_gem->fd,
1559 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1562 DBG("%s:%d: Error setting memory domains %d (%08x %08x): %s .\n",
1563 __FILE__, __LINE__, bo_gem->gem_handle,
1564 set_domain.read_domains, set_domain.write_domain,
1570 drm_intel_bufmgr_gem_destroy(drm_intel_bufmgr *bufmgr)
1572 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1575 free(bufmgr_gem->exec2_objects);
1576 free(bufmgr_gem->exec_objects);
1577 free(bufmgr_gem->exec_bos);
1578 free(bufmgr_gem->aub_filename);
1580 pthread_mutex_destroy(&bufmgr_gem->lock);
1582 /* Free any cached buffer objects we were going to reuse */
1583 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
1584 struct drm_intel_gem_bo_bucket *bucket =
1585 &bufmgr_gem->cache_bucket[i];
1586 drm_intel_bo_gem *bo_gem;
1588 while (!DRMLISTEMPTY(&bucket->head)) {
1589 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1590 bucket->head.next, head);
1591 DRMLISTDEL(&bo_gem->head);
1593 drm_intel_gem_bo_free(&bo_gem->bo);
1601 * Adds the target buffer to the validation list and adds the relocation
1602 * to the reloc_buffer's relocation list.
1604 * The relocation entry at the given offset must already contain the
1605 * precomputed relocation value, because the kernel will optimize out
1606 * the relocation entry write when the buffer hasn't moved from the
1607 * last known offset in target_bo.
1610 do_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1611 drm_intel_bo *target_bo, uint32_t target_offset,
1612 uint32_t read_domains, uint32_t write_domain,
1615 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1616 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1617 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
1618 bool fenced_command;
1620 if (bo_gem->has_error)
1623 if (target_bo_gem->has_error) {
1624 bo_gem->has_error = true;
1628 /* We never use HW fences for rendering on 965+ */
1629 if (bufmgr_gem->gen >= 4)
1632 fenced_command = need_fence;
1633 if (target_bo_gem->tiling_mode == I915_TILING_NONE)
1636 /* Create a new relocation list if needed */
1637 if (bo_gem->relocs == NULL && drm_intel_setup_reloc_list(bo))
1640 /* Check overflow */
1641 assert(bo_gem->reloc_count < bufmgr_gem->max_relocs);
1644 assert(offset <= bo->size - 4);
1645 assert((write_domain & (write_domain - 1)) == 0);
1647 /* Make sure that we're not adding a reloc to something whose size has
1648 * already been accounted for.
1650 assert(!bo_gem->used_as_reloc_target);
1651 if (target_bo_gem != bo_gem) {
1652 target_bo_gem->used_as_reloc_target = true;
1653 bo_gem->reloc_tree_size += target_bo_gem->reloc_tree_size;
1655 /* An object needing a fence is a tiled buffer, so it won't have
1656 * relocs to other buffers.
1659 target_bo_gem->reloc_tree_fences = 1;
1660 bo_gem->reloc_tree_fences += target_bo_gem->reloc_tree_fences;
1662 bo_gem->relocs[bo_gem->reloc_count].offset = offset;
1663 bo_gem->relocs[bo_gem->reloc_count].delta = target_offset;
1664 bo_gem->relocs[bo_gem->reloc_count].target_handle =
1665 target_bo_gem->gem_handle;
1666 bo_gem->relocs[bo_gem->reloc_count].read_domains = read_domains;
1667 bo_gem->relocs[bo_gem->reloc_count].write_domain = write_domain;
1668 bo_gem->relocs[bo_gem->reloc_count].presumed_offset = target_bo->offset;
1670 bo_gem->reloc_target_info[bo_gem->reloc_count].bo = target_bo;
1671 if (target_bo != bo)
1672 drm_intel_gem_bo_reference(target_bo);
1674 bo_gem->reloc_target_info[bo_gem->reloc_count].flags =
1675 DRM_INTEL_RELOC_FENCE;
1677 bo_gem->reloc_target_info[bo_gem->reloc_count].flags = 0;
1679 bo_gem->reloc_count++;
1685 drm_intel_gem_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1686 drm_intel_bo *target_bo, uint32_t target_offset,
1687 uint32_t read_domains, uint32_t write_domain)
1689 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1691 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1692 read_domains, write_domain,
1693 !bufmgr_gem->fenced_relocs);
1697 drm_intel_gem_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
1698 drm_intel_bo *target_bo,
1699 uint32_t target_offset,
1700 uint32_t read_domains, uint32_t write_domain)
1702 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1703 read_domains, write_domain, true);
1707 drm_intel_gem_bo_get_reloc_count(drm_intel_bo *bo)
1709 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1711 return bo_gem->reloc_count;
1715 * Removes existing relocation entries in the BO after "start".
1717 * This allows a user to avoid a two-step process for state setup with
1718 * counting up all the buffer objects and doing a
1719 * drm_intel_bufmgr_check_aperture_space() before emitting any of the
1720 * relocations for the state setup. Instead, save the state of the
1721 * batchbuffer including drm_intel_gem_get_reloc_count(), emit all the
1722 * state, and then check if it still fits in the aperture.
1724 * Any further drm_intel_bufmgr_check_aperture_space() queries
1725 * involving this buffer in the tree are undefined after this call.
1728 drm_intel_gem_bo_clear_relocs(drm_intel_bo *bo, int start)
1730 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1732 struct timespec time;
1734 clock_gettime(CLOCK_MONOTONIC, &time);
1736 assert(bo_gem->reloc_count >= start);
1737 /* Unreference the cleared target buffers */
1738 for (i = start; i < bo_gem->reloc_count; i++) {
1739 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) bo_gem->reloc_target_info[i].bo;
1740 if (&target_bo_gem->bo != bo) {
1741 bo_gem->reloc_tree_fences -= target_bo_gem->reloc_tree_fences;
1742 drm_intel_gem_bo_unreference_locked_timed(&target_bo_gem->bo,
1746 bo_gem->reloc_count = start;
1750 * Walk the tree of relocations rooted at BO and accumulate the list of
1751 * validations to be performed and update the relocation buffers with
1752 * index values into the validation list.
1755 drm_intel_gem_bo_process_reloc(drm_intel_bo *bo)
1757 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1760 if (bo_gem->relocs == NULL)
1763 for (i = 0; i < bo_gem->reloc_count; i++) {
1764 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1766 if (target_bo == bo)
1769 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1771 /* Continue walking the tree depth-first. */
1772 drm_intel_gem_bo_process_reloc(target_bo);
1774 /* Add the target to the validate list */
1775 drm_intel_add_validate_buffer(target_bo);
1780 drm_intel_gem_bo_process_reloc2(drm_intel_bo *bo)
1782 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1785 if (bo_gem->relocs == NULL)
1788 for (i = 0; i < bo_gem->reloc_count; i++) {
1789 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1792 if (target_bo == bo)
1795 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1797 /* Continue walking the tree depth-first. */
1798 drm_intel_gem_bo_process_reloc2(target_bo);
1800 need_fence = (bo_gem->reloc_target_info[i].flags &
1801 DRM_INTEL_RELOC_FENCE);
1803 /* Add the target to the validate list */
1804 drm_intel_add_validate_buffer2(target_bo, need_fence);
1810 drm_intel_update_buffer_offsets(drm_intel_bufmgr_gem *bufmgr_gem)
1814 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1815 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1816 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1818 /* Update the buffer offset */
1819 if (bufmgr_gem->exec_objects[i].offset != bo->offset) {
1820 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1821 bo_gem->gem_handle, bo_gem->name, bo->offset,
1822 (unsigned long long)bufmgr_gem->exec_objects[i].
1824 bo->offset = bufmgr_gem->exec_objects[i].offset;
1830 drm_intel_update_buffer_offsets2 (drm_intel_bufmgr_gem *bufmgr_gem)
1834 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1835 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1836 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1838 /* Update the buffer offset */
1839 if (bufmgr_gem->exec2_objects[i].offset != bo->offset) {
1840 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1841 bo_gem->gem_handle, bo_gem->name, bo->offset,
1842 (unsigned long long)bufmgr_gem->exec2_objects[i].offset);
1843 bo->offset = bufmgr_gem->exec2_objects[i].offset;
1849 aub_out(drm_intel_bufmgr_gem *bufmgr_gem, uint32_t data)
1851 fwrite(&data, 1, 4, bufmgr_gem->aub_file);
1855 aub_out_data(drm_intel_bufmgr_gem *bufmgr_gem, void *data, size_t size)
1857 fwrite(data, 1, size, bufmgr_gem->aub_file);
1861 aub_write_bo_data(drm_intel_bo *bo, uint32_t offset, uint32_t size)
1863 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1864 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1868 data = malloc(bo->size);
1869 drm_intel_bo_get_subdata(bo, offset, size, data);
1871 /* Easy mode: write out bo with no relocations */
1872 if (!bo_gem->reloc_count) {
1873 aub_out_data(bufmgr_gem, data, size);
1878 /* Otherwise, handle the relocations while writing. */
1879 for (i = 0; i < size / 4; i++) {
1881 for (r = 0; r < bo_gem->reloc_count; r++) {
1882 struct drm_i915_gem_relocation_entry *reloc;
1883 drm_intel_reloc_target *info;
1885 reloc = &bo_gem->relocs[r];
1886 info = &bo_gem->reloc_target_info[r];
1888 if (reloc->offset == offset + i * 4) {
1889 drm_intel_bo_gem *target_gem;
1892 target_gem = (drm_intel_bo_gem *)info->bo;
1895 val += target_gem->aub_offset;
1897 aub_out(bufmgr_gem, val);
1902 if (r == bo_gem->reloc_count) {
1903 /* no relocation, just the data */
1904 aub_out(bufmgr_gem, data[i]);
1912 aub_bo_get_address(drm_intel_bo *bo)
1914 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1915 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1917 /* Give the object a graphics address in the AUB file. We
1918 * don't just use the GEM object address because we do AUB
1919 * dumping before execution -- we want to successfully log
1920 * when the hardware might hang, and we might even want to aub
1921 * capture for a driver trying to execute on a different
1922 * generation of hardware by disabling the actual kernel exec
1925 bo_gem->aub_offset = bufmgr_gem->aub_offset;
1926 bufmgr_gem->aub_offset += bo->size;
1927 /* XXX: Handle aperture overflow. */
1928 assert(bufmgr_gem->aub_offset < 256 * 1024 * 1024);
1932 aub_write_trace_block(drm_intel_bo *bo, uint32_t type, uint32_t subtype,
1933 uint32_t offset, uint32_t size)
1935 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1936 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1939 CMD_AUB_TRACE_HEADER_BLOCK |
1942 AUB_TRACE_MEMTYPE_GTT | type | AUB_TRACE_OP_DATA_WRITE);
1943 aub_out(bufmgr_gem, subtype);
1944 aub_out(bufmgr_gem, bo_gem->aub_offset + offset);
1945 aub_out(bufmgr_gem, size);
1946 aub_write_bo_data(bo, offset, size);
1950 * Break up large objects into multiple writes. Otherwise a 128kb VBO
1951 * would overflow the 16 bits of size field in the packet header and
1952 * everything goes badly after that.
1955 aub_write_large_trace_block(drm_intel_bo *bo, uint32_t type, uint32_t subtype,
1956 uint32_t offset, uint32_t size)
1958 uint32_t block_size;
1959 uint32_t sub_offset;
1961 for (sub_offset = 0; sub_offset < size; sub_offset += block_size) {
1962 block_size = size - sub_offset;
1964 if (block_size > 8 * 4096)
1965 block_size = 8 * 4096;
1967 aub_write_trace_block(bo, type, subtype, offset + sub_offset,
1973 aub_write_bo(drm_intel_bo *bo)
1975 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1976 uint32_t offset = 0;
1979 aub_bo_get_address(bo);
1981 /* Write out each annotated section separately. */
1982 for (i = 0; i < bo_gem->aub_annotation_count; ++i) {
1983 drm_intel_aub_annotation *annotation =
1984 &bo_gem->aub_annotations[i];
1985 uint32_t ending_offset = annotation->ending_offset;
1986 if (ending_offset > bo->size)
1987 ending_offset = bo->size;
1988 if (ending_offset > offset) {
1989 aub_write_large_trace_block(bo, annotation->type,
1990 annotation->subtype,
1992 ending_offset - offset);
1993 offset = ending_offset;
1997 /* Write out any remaining unannotated data */
1998 if (offset < bo->size) {
1999 aub_write_large_trace_block(bo, AUB_TRACE_TYPE_NOTYPE, 0,
2000 offset, bo->size - offset);
2005 * Make a ringbuffer on fly and dump it
2008 aub_build_dump_ringbuffer(drm_intel_bufmgr_gem *bufmgr_gem,
2009 uint32_t batch_buffer, int ring_flag)
2011 uint32_t ringbuffer[4096];
2012 int ring = AUB_TRACE_TYPE_RING_PRB0; /* The default ring */
2015 if (ring_flag == I915_EXEC_BSD)
2016 ring = AUB_TRACE_TYPE_RING_PRB1;
2017 else if (ring_flag == I915_EXEC_BLT)
2018 ring = AUB_TRACE_TYPE_RING_PRB2;
2020 /* Make a ring buffer to execute our batchbuffer. */
2021 memset(ringbuffer, 0, sizeof(ringbuffer));
2022 ringbuffer[ring_count++] = AUB_MI_BATCH_BUFFER_START;
2023 ringbuffer[ring_count++] = batch_buffer;
2025 /* Write out the ring. This appears to trigger execution of
2026 * the ring in the simulator.
2029 CMD_AUB_TRACE_HEADER_BLOCK |
2032 AUB_TRACE_MEMTYPE_GTT | ring | AUB_TRACE_OP_COMMAND_WRITE);
2033 aub_out(bufmgr_gem, 0); /* general/surface subtype */
2034 aub_out(bufmgr_gem, bufmgr_gem->aub_offset);
2035 aub_out(bufmgr_gem, ring_count * 4);
2037 /* FIXME: Need some flush operations here? */
2038 aub_out_data(bufmgr_gem, ringbuffer, ring_count * 4);
2040 /* Update offset pointer */
2041 bufmgr_gem->aub_offset += 4096;
2045 drm_intel_gem_bo_aub_dump_bmp(drm_intel_bo *bo,
2046 int x1, int y1, int width, int height,
2047 enum aub_dump_bmp_format format,
2048 int pitch, int offset)
2050 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2051 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
2055 case AUB_DUMP_BMP_FORMAT_8BIT:
2058 case AUB_DUMP_BMP_FORMAT_ARGB_4444:
2061 case AUB_DUMP_BMP_FORMAT_ARGB_0888:
2062 case AUB_DUMP_BMP_FORMAT_ARGB_8888:
2066 printf("Unknown AUB dump format %d\n", format);
2070 if (!bufmgr_gem->aub_file)
2073 aub_out(bufmgr_gem, CMD_AUB_DUMP_BMP | 4);
2074 aub_out(bufmgr_gem, (y1 << 16) | x1);
2079 aub_out(bufmgr_gem, (height << 16) | width);
2080 aub_out(bufmgr_gem, bo_gem->aub_offset + offset);
2082 ((bo_gem->tiling_mode != I915_TILING_NONE) ? (1 << 2) : 0) |
2083 ((bo_gem->tiling_mode == I915_TILING_Y) ? (1 << 3) : 0));
2087 aub_exec(drm_intel_bo *bo, int ring_flag, int used)
2089 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2090 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2092 bool batch_buffer_needs_annotations;
2094 if (!bufmgr_gem->aub_file)
2097 /* If batch buffer is not annotated, annotate it the best we
2100 batch_buffer_needs_annotations = bo_gem->aub_annotation_count == 0;
2101 if (batch_buffer_needs_annotations) {
2102 drm_intel_aub_annotation annotations[2] = {
2103 { AUB_TRACE_TYPE_BATCH, 0, used },
2104 { AUB_TRACE_TYPE_NOTYPE, 0, bo->size }
2106 drm_intel_bufmgr_gem_set_aub_annotations(bo, annotations, 2);
2109 /* Write out all buffers to AUB memory */
2110 for (i = 0; i < bufmgr_gem->exec_count; i++) {
2111 aub_write_bo(bufmgr_gem->exec_bos[i]);
2114 /* Remove any annotations we added */
2115 if (batch_buffer_needs_annotations)
2116 drm_intel_bufmgr_gem_set_aub_annotations(bo, NULL, 0);
2118 /* Dump ring buffer */
2119 aub_build_dump_ringbuffer(bufmgr_gem, bo_gem->aub_offset, ring_flag);
2121 fflush(bufmgr_gem->aub_file);
2124 * One frame has been dumped. So reset the aub_offset for the next frame.
2126 * FIXME: Can we do this?
2128 bufmgr_gem->aub_offset = 0x10000;
2132 drm_intel_gem_bo_exec(drm_intel_bo *bo, int used,
2133 drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
2135 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2136 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2137 struct drm_i915_gem_execbuffer execbuf;
2140 if (bo_gem->has_error)
2143 pthread_mutex_lock(&bufmgr_gem->lock);
2144 /* Update indices and set up the validate list. */
2145 drm_intel_gem_bo_process_reloc(bo);
2147 /* Add the batch buffer to the validation list. There are no
2148 * relocations pointing to it.
2150 drm_intel_add_validate_buffer(bo);
2153 execbuf.buffers_ptr = (uintptr_t) bufmgr_gem->exec_objects;
2154 execbuf.buffer_count = bufmgr_gem->exec_count;
2155 execbuf.batch_start_offset = 0;
2156 execbuf.batch_len = used;
2157 execbuf.cliprects_ptr = (uintptr_t) cliprects;
2158 execbuf.num_cliprects = num_cliprects;
2162 ret = drmIoctl(bufmgr_gem->fd,
2163 DRM_IOCTL_I915_GEM_EXECBUFFER,
2167 if (errno == ENOSPC) {
2168 DBG("Execbuffer fails to pin. "
2169 "Estimate: %u. Actual: %u. Available: %u\n",
2170 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
2173 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
2176 (unsigned int)bufmgr_gem->gtt_size);
2179 drm_intel_update_buffer_offsets(bufmgr_gem);
2181 if (bufmgr_gem->bufmgr.debug)
2182 drm_intel_gem_dump_validation_list(bufmgr_gem);
2184 for (i = 0; i < bufmgr_gem->exec_count; i++) {
2185 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
2186 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2188 /* Disconnect the buffer from the validate list */
2189 bo_gem->validate_index = -1;
2190 bufmgr_gem->exec_bos[i] = NULL;
2192 bufmgr_gem->exec_count = 0;
2193 pthread_mutex_unlock(&bufmgr_gem->lock);
2199 do_exec2(drm_intel_bo *bo, int used, drm_intel_context *ctx,
2200 drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
2203 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
2204 struct drm_i915_gem_execbuffer2 execbuf;
2208 switch (flags & 0x7) {
2212 if (!bufmgr_gem->has_blt)
2216 if (!bufmgr_gem->has_bsd)
2219 case I915_EXEC_VEBOX:
2220 if (!bufmgr_gem->has_vebox)
2223 case I915_EXEC_RENDER:
2224 case I915_EXEC_DEFAULT:
2228 pthread_mutex_lock(&bufmgr_gem->lock);
2229 /* Update indices and set up the validate list. */
2230 drm_intel_gem_bo_process_reloc2(bo);
2232 /* Add the batch buffer to the validation list. There are no relocations
2235 drm_intel_add_validate_buffer2(bo, 0);
2238 execbuf.buffers_ptr = (uintptr_t)bufmgr_gem->exec2_objects;
2239 execbuf.buffer_count = bufmgr_gem->exec_count;
2240 execbuf.batch_start_offset = 0;
2241 execbuf.batch_len = used;
2242 execbuf.cliprects_ptr = (uintptr_t)cliprects;
2243 execbuf.num_cliprects = num_cliprects;
2246 execbuf.flags = flags;
2248 i915_execbuffer2_set_context_id(execbuf, 0);
2250 i915_execbuffer2_set_context_id(execbuf, ctx->ctx_id);
2253 aub_exec(bo, flags, used);
2255 if (bufmgr_gem->no_exec)
2256 goto skip_execution;
2258 ret = drmIoctl(bufmgr_gem->fd,
2259 DRM_IOCTL_I915_GEM_EXECBUFFER2,
2263 if (ret == -ENOSPC) {
2264 DBG("Execbuffer fails to pin. "
2265 "Estimate: %u. Actual: %u. Available: %u\n",
2266 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
2267 bufmgr_gem->exec_count),
2268 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
2269 bufmgr_gem->exec_count),
2270 (unsigned int) bufmgr_gem->gtt_size);
2273 drm_intel_update_buffer_offsets2(bufmgr_gem);
2276 if (bufmgr_gem->bufmgr.debug)
2277 drm_intel_gem_dump_validation_list(bufmgr_gem);
2279 for (i = 0; i < bufmgr_gem->exec_count; i++) {
2280 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
2281 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
2283 /* Disconnect the buffer from the validate list */
2284 bo_gem->validate_index = -1;
2285 bufmgr_gem->exec_bos[i] = NULL;
2287 bufmgr_gem->exec_count = 0;
2288 pthread_mutex_unlock(&bufmgr_gem->lock);
2294 drm_intel_gem_bo_exec2(drm_intel_bo *bo, int used,
2295 drm_clip_rect_t *cliprects, int num_cliprects,
2298 return do_exec2(bo, used, NULL, cliprects, num_cliprects, DR4,
2303 drm_intel_gem_bo_mrb_exec2(drm_intel_bo *bo, int used,
2304 drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
2307 return do_exec2(bo, used, NULL, cliprects, num_cliprects, DR4,
2312 drm_intel_gem_bo_context_exec(drm_intel_bo *bo, drm_intel_context *ctx,
2313 int used, unsigned int flags)
2315 return do_exec2(bo, used, ctx, NULL, 0, 0, flags);
2319 drm_intel_gem_bo_pin(drm_intel_bo *bo, uint32_t alignment)
2321 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2322 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2323 struct drm_i915_gem_pin pin;
2327 pin.handle = bo_gem->gem_handle;
2328 pin.alignment = alignment;
2330 ret = drmIoctl(bufmgr_gem->fd,
2331 DRM_IOCTL_I915_GEM_PIN,
2336 bo->offset = pin.offset;
2341 drm_intel_gem_bo_unpin(drm_intel_bo *bo)
2343 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2344 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2345 struct drm_i915_gem_unpin unpin;
2349 unpin.handle = bo_gem->gem_handle;
2351 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_UNPIN, &unpin);
2359 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
2360 uint32_t tiling_mode,
2363 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2364 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2365 struct drm_i915_gem_set_tiling set_tiling;
2368 if (bo_gem->global_name == 0 &&
2369 tiling_mode == bo_gem->tiling_mode &&
2370 stride == bo_gem->stride)
2373 memset(&set_tiling, 0, sizeof(set_tiling));
2375 /* set_tiling is slightly broken and overwrites the
2376 * input on the error path, so we have to open code
2379 set_tiling.handle = bo_gem->gem_handle;
2380 set_tiling.tiling_mode = tiling_mode;
2381 set_tiling.stride = stride;
2383 ret = ioctl(bufmgr_gem->fd,
2384 DRM_IOCTL_I915_GEM_SET_TILING,
2386 } while (ret == -1 && (errno == EINTR || errno == EAGAIN));
2390 bo_gem->tiling_mode = set_tiling.tiling_mode;
2391 bo_gem->swizzle_mode = set_tiling.swizzle_mode;
2392 bo_gem->stride = set_tiling.stride;
2397 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
2400 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2401 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2404 /* Linear buffers have no stride. By ensuring that we only ever use
2405 * stride 0 with linear buffers, we simplify our code.
2407 if (*tiling_mode == I915_TILING_NONE)
2410 ret = drm_intel_gem_bo_set_tiling_internal(bo, *tiling_mode, stride);
2412 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
2414 *tiling_mode = bo_gem->tiling_mode;
2419 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
2420 uint32_t * swizzle_mode)
2422 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2424 *tiling_mode = bo_gem->tiling_mode;
2425 *swizzle_mode = bo_gem->swizzle_mode;
2430 drm_intel_bo_gem_create_from_prime(drm_intel_bufmgr *bufmgr, int prime_fd, int size)
2432 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
2435 drm_intel_bo_gem *bo_gem;
2436 struct drm_i915_gem_get_tiling get_tiling;
2438 ret = drmPrimeFDToHandle(bufmgr_gem->fd, prime_fd, &handle);
2440 fprintf(stderr,"ret is %d %d\n", ret, errno);
2444 bo_gem = calloc(1, sizeof(*bo_gem));
2448 bo_gem->bo.size = size;
2449 bo_gem->bo.handle = handle;
2450 bo_gem->bo.bufmgr = bufmgr;
2452 bo_gem->gem_handle = handle;
2454 atomic_set(&bo_gem->refcount, 1);
2456 bo_gem->name = "prime";
2457 bo_gem->validate_index = -1;
2458 bo_gem->reloc_tree_fences = 0;
2459 bo_gem->used_as_reloc_target = false;
2460 bo_gem->has_error = false;
2461 bo_gem->reusable = false;
2463 DRMINITLISTHEAD(&bo_gem->name_list);
2464 DRMINITLISTHEAD(&bo_gem->vma_list);
2466 VG_CLEAR(get_tiling);
2467 get_tiling.handle = bo_gem->gem_handle;
2468 ret = drmIoctl(bufmgr_gem->fd,
2469 DRM_IOCTL_I915_GEM_GET_TILING,
2472 drm_intel_gem_bo_unreference(&bo_gem->bo);
2475 bo_gem->tiling_mode = get_tiling.tiling_mode;
2476 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
2477 /* XXX stride is unknown */
2478 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
2484 drm_intel_bo_gem_export_to_prime(drm_intel_bo *bo, int *prime_fd)
2486 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2487 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2489 if (drmPrimeHandleToFD(bufmgr_gem->fd, bo_gem->gem_handle,
2490 DRM_CLOEXEC, prime_fd) != 0)
2493 bo_gem->reusable = false;
2499 drm_intel_gem_bo_flink(drm_intel_bo *bo, uint32_t * name)
2501 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2502 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2505 if (!bo_gem->global_name) {
2506 struct drm_gem_flink flink;
2509 flink.handle = bo_gem->gem_handle;
2511 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_FLINK, &flink);
2515 bo_gem->global_name = flink.name;
2516 bo_gem->reusable = false;
2518 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
2521 *name = bo_gem->global_name;
2526 * Enables unlimited caching of buffer objects for reuse.
2528 * This is potentially very memory expensive, as the cache at each bucket
2529 * size is only bounded by how many buffers of that size we've managed to have
2530 * in flight at once.
2533 drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr)
2535 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
2537 bufmgr_gem->bo_reuse = true;
2541 * Enable use of fenced reloc type.
2543 * New code should enable this to avoid unnecessary fence register
2544 * allocation. If this option is not enabled, all relocs will have fence
2545 * register allocated.
2548 drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr)
2550 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
2552 if (bufmgr_gem->bufmgr.bo_exec == drm_intel_gem_bo_exec2)
2553 bufmgr_gem->fenced_relocs = true;
2557 * Return the additional aperture space required by the tree of buffer objects
2561 drm_intel_gem_bo_get_aperture_space(drm_intel_bo *bo)
2563 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2567 if (bo == NULL || bo_gem->included_in_check_aperture)
2571 bo_gem->included_in_check_aperture = true;
2573 for (i = 0; i < bo_gem->reloc_count; i++)
2575 drm_intel_gem_bo_get_aperture_space(bo_gem->
2576 reloc_target_info[i].bo);
2582 * Count the number of buffers in this list that need a fence reg
2584 * If the count is greater than the number of available regs, we'll have
2585 * to ask the caller to resubmit a batch with fewer tiled buffers.
2587 * This function over-counts if the same buffer is used multiple times.
2590 drm_intel_gem_total_fences(drm_intel_bo ** bo_array, int count)
2593 unsigned int total = 0;
2595 for (i = 0; i < count; i++) {
2596 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
2601 total += bo_gem->reloc_tree_fences;
2607 * Clear the flag set by drm_intel_gem_bo_get_aperture_space() so we're ready
2608 * for the next drm_intel_bufmgr_check_aperture_space() call.
2611 drm_intel_gem_bo_clear_aperture_space_flag(drm_intel_bo *bo)
2613 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2616 if (bo == NULL || !bo_gem->included_in_check_aperture)
2619 bo_gem->included_in_check_aperture = false;
2621 for (i = 0; i < bo_gem->reloc_count; i++)
2622 drm_intel_gem_bo_clear_aperture_space_flag(bo_gem->
2623 reloc_target_info[i].bo);
2627 * Return a conservative estimate for the amount of aperture required
2628 * for a collection of buffers. This may double-count some buffers.
2631 drm_intel_gem_estimate_batch_space(drm_intel_bo **bo_array, int count)
2634 unsigned int total = 0;
2636 for (i = 0; i < count; i++) {
2637 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
2639 total += bo_gem->reloc_tree_size;
2645 * Return the amount of aperture needed for a collection of buffers.
2646 * This avoids double counting any buffers, at the cost of looking
2647 * at every buffer in the set.
2650 drm_intel_gem_compute_batch_space(drm_intel_bo **bo_array, int count)
2653 unsigned int total = 0;
2655 for (i = 0; i < count; i++) {
2656 total += drm_intel_gem_bo_get_aperture_space(bo_array[i]);
2657 /* For the first buffer object in the array, we get an
2658 * accurate count back for its reloc_tree size (since nothing
2659 * had been flagged as being counted yet). We can save that
2660 * value out as a more conservative reloc_tree_size that
2661 * avoids double-counting target buffers. Since the first
2662 * buffer happens to usually be the batch buffer in our
2663 * callers, this can pull us back from doing the tree
2664 * walk on every new batch emit.
2667 drm_intel_bo_gem *bo_gem =
2668 (drm_intel_bo_gem *) bo_array[i];
2669 bo_gem->reloc_tree_size = total;
2673 for (i = 0; i < count; i++)
2674 drm_intel_gem_bo_clear_aperture_space_flag(bo_array[i]);
2679 * Return -1 if the batchbuffer should be flushed before attempting to
2680 * emit rendering referencing the buffers pointed to by bo_array.
2682 * This is required because if we try to emit a batchbuffer with relocations
2683 * to a tree of buffers that won't simultaneously fit in the aperture,
2684 * the rendering will return an error at a point where the software is not
2685 * prepared to recover from it.
2687 * However, we also want to emit the batchbuffer significantly before we reach
2688 * the limit, as a series of batchbuffers each of which references buffers
2689 * covering almost all of the aperture means that at each emit we end up
2690 * waiting to evict a buffer from the last rendering, and we get synchronous
2691 * performance. By emitting smaller batchbuffers, we eat some CPU overhead to
2692 * get better parallelism.
2695 drm_intel_gem_check_aperture_space(drm_intel_bo **bo_array, int count)
2697 drm_intel_bufmgr_gem *bufmgr_gem =
2698 (drm_intel_bufmgr_gem *) bo_array[0]->bufmgr;
2699 unsigned int total = 0;
2700 unsigned int threshold = bufmgr_gem->gtt_size * 3 / 4;
2703 /* Check for fence reg constraints if necessary */
2704 if (bufmgr_gem->available_fences) {
2705 total_fences = drm_intel_gem_total_fences(bo_array, count);
2706 if (total_fences > bufmgr_gem->available_fences)
2710 total = drm_intel_gem_estimate_batch_space(bo_array, count);
2712 if (total > threshold)
2713 total = drm_intel_gem_compute_batch_space(bo_array, count);
2715 if (total > threshold) {
2716 DBG("check_space: overflowed available aperture, "
2718 total / 1024, (int)bufmgr_gem->gtt_size / 1024);
2721 DBG("drm_check_space: total %dkb vs bufgr %dkb\n", total / 1024,
2722 (int)bufmgr_gem->gtt_size / 1024);
2728 * Disable buffer reuse for objects which are shared with the kernel
2729 * as scanout buffers
2732 drm_intel_gem_bo_disable_reuse(drm_intel_bo *bo)
2734 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2736 bo_gem->reusable = false;
2741 drm_intel_gem_bo_is_reusable(drm_intel_bo *bo)
2743 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2745 return bo_gem->reusable;
2749 _drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
2751 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2754 for (i = 0; i < bo_gem->reloc_count; i++) {
2755 if (bo_gem->reloc_target_info[i].bo == target_bo)
2757 if (bo == bo_gem->reloc_target_info[i].bo)
2759 if (_drm_intel_gem_bo_references(bo_gem->reloc_target_info[i].bo,
2767 /** Return true if target_bo is referenced by bo's relocation tree. */
2769 drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
2771 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
2773 if (bo == NULL || target_bo == NULL)
2775 if (target_bo_gem->used_as_reloc_target)
2776 return _drm_intel_gem_bo_references(bo, target_bo);
2781 add_bucket(drm_intel_bufmgr_gem *bufmgr_gem, int size)
2783 unsigned int i = bufmgr_gem->num_buckets;
2785 assert(i < ARRAY_SIZE(bufmgr_gem->cache_bucket));
2787 DRMINITLISTHEAD(&bufmgr_gem->cache_bucket[i].head);
2788 bufmgr_gem->cache_bucket[i].size = size;
2789 bufmgr_gem->num_buckets++;
2793 init_cache_buckets(drm_intel_bufmgr_gem *bufmgr_gem)
2795 unsigned long size, cache_max_size = 64 * 1024 * 1024;
2797 /* OK, so power of two buckets was too wasteful of memory.
2798 * Give 3 other sizes between each power of two, to hopefully
2799 * cover things accurately enough. (The alternative is
2800 * probably to just go for exact matching of sizes, and assume
2801 * that for things like composited window resize the tiled
2802 * width/height alignment and rounding of sizes to pages will
2803 * get us useful cache hit rates anyway)
2805 add_bucket(bufmgr_gem, 4096);
2806 add_bucket(bufmgr_gem, 4096 * 2);
2807 add_bucket(bufmgr_gem, 4096 * 3);
2809 /* Initialize the linked lists for BO reuse cache. */
2810 for (size = 4 * 4096; size <= cache_max_size; size *= 2) {
2811 add_bucket(bufmgr_gem, size);
2813 add_bucket(bufmgr_gem, size + size * 1 / 4);
2814 add_bucket(bufmgr_gem, size + size * 2 / 4);
2815 add_bucket(bufmgr_gem, size + size * 3 / 4);
2820 drm_intel_bufmgr_gem_set_vma_cache_size(drm_intel_bufmgr *bufmgr, int limit)
2822 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
2824 bufmgr_gem->vma_max = limit;
2826 drm_intel_gem_bo_purge_vma_cache(bufmgr_gem);
2830 * Get the PCI ID for the device. This can be overridden by setting the
2831 * INTEL_DEVID_OVERRIDE environment variable to the desired ID.
2834 get_pci_device_id(drm_intel_bufmgr_gem *bufmgr_gem)
2836 char *devid_override;
2839 drm_i915_getparam_t gp;
2841 if (geteuid() == getuid()) {
2842 devid_override = getenv("INTEL_DEVID_OVERRIDE");
2843 if (devid_override) {
2844 bufmgr_gem->no_exec = true;
2845 return strtod(devid_override, NULL);
2851 gp.param = I915_PARAM_CHIPSET_ID;
2853 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2855 fprintf(stderr, "get chip id failed: %d [%d]\n", ret, errno);
2856 fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value);
2862 drm_intel_bufmgr_gem_get_devid(drm_intel_bufmgr *bufmgr)
2864 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
2866 return bufmgr_gem->pci_device;
2870 * Sets the AUB filename.
2872 * This function has to be called before drm_intel_bufmgr_gem_set_aub_dump()
2873 * for it to have any effect.
2876 drm_intel_bufmgr_gem_set_aub_filename(drm_intel_bufmgr *bufmgr,
2877 const char *filename)
2879 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
2881 free(bufmgr_gem->aub_filename);
2883 bufmgr_gem->aub_filename = strdup(filename);
2887 * Sets up AUB dumping.
2889 * This is a trace file format that can be used with the simulator.
2890 * Packets are emitted in a format somewhat like GPU command packets.
2891 * You can set up a GTT and upload your objects into the referenced
2892 * space, then send off batchbuffers and get BMPs out the other end.
2895 drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable)
2897 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
2898 int entry = 0x200003;
2900 int gtt_size = 0x10000;
2901 const char *filename;
2904 if (bufmgr_gem->aub_file) {
2905 fclose(bufmgr_gem->aub_file);
2906 bufmgr_gem->aub_file = NULL;
2911 if (geteuid() != getuid())
2914 if (bufmgr_gem->aub_filename)
2915 filename = bufmgr_gem->aub_filename;
2917 filename = "intel.aub";
2918 bufmgr_gem->aub_file = fopen(filename, "w+");
2919 if (!bufmgr_gem->aub_file)
2922 /* Start allocating objects from just after the GTT. */
2923 bufmgr_gem->aub_offset = gtt_size;
2925 /* Start with a (required) version packet. */
2926 aub_out(bufmgr_gem, CMD_AUB_HEADER | (13 - 2));
2928 (4 << AUB_HEADER_MAJOR_SHIFT) |
2929 (0 << AUB_HEADER_MINOR_SHIFT));
2930 for (i = 0; i < 8; i++) {
2931 aub_out(bufmgr_gem, 0); /* app name */
2933 aub_out(bufmgr_gem, 0); /* timestamp */
2934 aub_out(bufmgr_gem, 0); /* timestamp */
2935 aub_out(bufmgr_gem, 0); /* comment len */
2937 /* Set up the GTT. The max we can handle is 256M */
2938 aub_out(bufmgr_gem, CMD_AUB_TRACE_HEADER_BLOCK | (5 - 2));
2939 aub_out(bufmgr_gem, AUB_TRACE_MEMTYPE_NONLOCAL | 0 | AUB_TRACE_OP_DATA_WRITE);
2940 aub_out(bufmgr_gem, 0); /* subtype */
2941 aub_out(bufmgr_gem, 0); /* offset */
2942 aub_out(bufmgr_gem, gtt_size); /* size */
2943 for (i = 0x000; i < gtt_size; i += 4, entry += 0x1000) {
2944 aub_out(bufmgr_gem, entry);
2949 drm_intel_gem_context_create(drm_intel_bufmgr *bufmgr)
2951 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
2952 struct drm_i915_gem_context_create create;
2953 drm_intel_context *context = NULL;
2957 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_CONTEXT_CREATE, &create);
2959 DBG("DRM_IOCTL_I915_GEM_CONTEXT_CREATE failed: %s\n",
2964 context = calloc(1, sizeof(*context));
2965 context->ctx_id = create.ctx_id;
2966 context->bufmgr = bufmgr;
2972 drm_intel_gem_context_destroy(drm_intel_context *ctx)
2974 drm_intel_bufmgr_gem *bufmgr_gem;
2975 struct drm_i915_gem_context_destroy destroy;
2983 bufmgr_gem = (drm_intel_bufmgr_gem *)ctx->bufmgr;
2984 destroy.ctx_id = ctx->ctx_id;
2985 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_CONTEXT_DESTROY,
2988 fprintf(stderr, "DRM_IOCTL_I915_GEM_CONTEXT_DESTROY failed: %s\n",
2995 drm_intel_reg_read(drm_intel_bufmgr *bufmgr,
2999 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
3000 struct drm_i915_reg_read reg_read;
3004 reg_read.offset = offset;
3006 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_REG_READ, ®_read);
3008 *result = reg_read.val;
3014 * Annotate the given bo for use in aub dumping.
3016 * \param annotations is an array of drm_intel_aub_annotation objects
3017 * describing the type of data in various sections of the bo. Each
3018 * element of the array specifies the type and subtype of a section of
3019 * the bo, and the past-the-end offset of that section. The elements
3020 * of \c annotations must be sorted so that ending_offset is
3023 * \param count is the number of elements in the \c annotations array.
3024 * If \c count is zero, then \c annotations will not be dereferenced.
3026 * Annotations are copied into a private data structure, so caller may
3027 * re-use the memory pointed to by \c annotations after the call
3030 * Annotations are stored for the lifetime of the bo; to reset to the
3031 * default state (no annotations), call this function with a \c count
3035 drm_intel_bufmgr_gem_set_aub_annotations(drm_intel_bo *bo,
3036 drm_intel_aub_annotation *annotations,
3039 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
3040 unsigned size = sizeof(*annotations) * count;
3041 drm_intel_aub_annotation *new_annotations =
3042 count > 0 ? realloc(bo_gem->aub_annotations, size) : NULL;
3043 if (new_annotations == NULL) {
3044 free(bo_gem->aub_annotations);
3045 bo_gem->aub_annotations = NULL;
3046 bo_gem->aub_annotation_count = 0;
3049 memcpy(new_annotations, annotations, size);
3050 bo_gem->aub_annotations = new_annotations;
3051 bo_gem->aub_annotation_count = count;
3055 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
3056 * and manage map buffer objections.
3058 * \param fd File descriptor of the opened DRM device.
3061 drm_intel_bufmgr_gem_init(int fd, int batch_size)
3063 drm_intel_bufmgr_gem *bufmgr_gem;
3064 struct drm_i915_gem_get_aperture aperture;
3065 drm_i915_getparam_t gp;
3069 bufmgr_gem = calloc(1, sizeof(*bufmgr_gem));
3070 if (bufmgr_gem == NULL)
3073 bufmgr_gem->fd = fd;
3075 if (pthread_mutex_init(&bufmgr_gem->lock, NULL) != 0) {
3080 ret = drmIoctl(bufmgr_gem->fd,
3081 DRM_IOCTL_I915_GEM_GET_APERTURE,
3085 bufmgr_gem->gtt_size = aperture.aper_available_size;
3087 fprintf(stderr, "DRM_IOCTL_I915_GEM_APERTURE failed: %s\n",
3089 bufmgr_gem->gtt_size = 128 * 1024 * 1024;
3090 fprintf(stderr, "Assuming %dkB available aperture size.\n"
3091 "May lead to reduced performance or incorrect "
3093 (int)bufmgr_gem->gtt_size / 1024);
3096 bufmgr_gem->pci_device = get_pci_device_id(bufmgr_gem);
3098 if (IS_GEN2(bufmgr_gem->pci_device))
3099 bufmgr_gem->gen = 2;
3100 else if (IS_GEN3(bufmgr_gem->pci_device))
3101 bufmgr_gem->gen = 3;
3102 else if (IS_GEN4(bufmgr_gem->pci_device))
3103 bufmgr_gem->gen = 4;
3104 else if (IS_GEN5(bufmgr_gem->pci_device))
3105 bufmgr_gem->gen = 5;
3106 else if (IS_GEN6(bufmgr_gem->pci_device))
3107 bufmgr_gem->gen = 6;
3108 else if (IS_GEN7(bufmgr_gem->pci_device))
3109 bufmgr_gem->gen = 7;
3115 if (IS_GEN3(bufmgr_gem->pci_device) &&
3116 bufmgr_gem->gtt_size > 256*1024*1024) {
3117 /* The unmappable part of gtt on gen 3 (i.e. above 256MB) can't
3118 * be used for tiled blits. To simplify the accounting, just
3119 * substract the unmappable part (fixed to 256MB on all known
3120 * gen3 devices) if the kernel advertises it. */
3121 bufmgr_gem->gtt_size -= 256*1024*1024;
3127 gp.param = I915_PARAM_HAS_EXECBUF2;
3128 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3132 gp.param = I915_PARAM_HAS_BSD;
3133 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3134 bufmgr_gem->has_bsd = ret == 0;
3136 gp.param = I915_PARAM_HAS_BLT;
3137 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3138 bufmgr_gem->has_blt = ret == 0;
3140 gp.param = I915_PARAM_HAS_RELAXED_FENCING;
3141 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3142 bufmgr_gem->has_relaxed_fencing = ret == 0;
3144 gp.param = I915_PARAM_HAS_WAIT_TIMEOUT;
3145 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3146 bufmgr_gem->has_wait_timeout = ret == 0;
3148 gp.param = I915_PARAM_HAS_LLC;
3149 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3151 /* Kernel does not supports HAS_LLC query, fallback to GPU
3152 * generation detection and assume that we have LLC on GEN6/7
3154 bufmgr_gem->has_llc = (IS_GEN6(bufmgr_gem->pci_device) |
3155 IS_GEN7(bufmgr_gem->pci_device));
3157 bufmgr_gem->has_llc = *gp.value;
3159 gp.param = I915_PARAM_HAS_VEBOX;
3160 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3161 bufmgr_gem->has_vebox = (ret == 0) & (*gp.value > 0);
3163 if (bufmgr_gem->gen < 4) {
3164 gp.param = I915_PARAM_NUM_FENCES_AVAIL;
3165 gp.value = &bufmgr_gem->available_fences;
3166 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3168 fprintf(stderr, "get fences failed: %d [%d]\n", ret,
3170 fprintf(stderr, "param: %d, val: %d\n", gp.param,
3172 bufmgr_gem->available_fences = 0;
3174 /* XXX The kernel reports the total number of fences,
3175 * including any that may be pinned.
3177 * We presume that there will be at least one pinned
3178 * fence for the scanout buffer, but there may be more
3179 * than one scanout and the user may be manually
3180 * pinning buffers. Let's move to execbuffer2 and
3181 * thereby forget the insanity of using fences...
3183 bufmgr_gem->available_fences -= 2;
3184 if (bufmgr_gem->available_fences < 0)
3185 bufmgr_gem->available_fences = 0;
3189 /* Let's go with one relocation per every 2 dwords (but round down a bit
3190 * since a power of two will mean an extra page allocation for the reloc
3193 * Every 4 was too few for the blender benchmark.
3195 bufmgr_gem->max_relocs = batch_size / sizeof(uint32_t) / 2 - 2;
3197 bufmgr_gem->bufmgr.bo_alloc = drm_intel_gem_bo_alloc;
3198 bufmgr_gem->bufmgr.bo_alloc_for_render =
3199 drm_intel_gem_bo_alloc_for_render;
3200 bufmgr_gem->bufmgr.bo_alloc_tiled = drm_intel_gem_bo_alloc_tiled;
3201 bufmgr_gem->bufmgr.bo_reference = drm_intel_gem_bo_reference;
3202 bufmgr_gem->bufmgr.bo_unreference = drm_intel_gem_bo_unreference;
3203 bufmgr_gem->bufmgr.bo_map = drm_intel_gem_bo_map;
3204 bufmgr_gem->bufmgr.bo_unmap = drm_intel_gem_bo_unmap;
3205 bufmgr_gem->bufmgr.bo_subdata = drm_intel_gem_bo_subdata;
3206 bufmgr_gem->bufmgr.bo_get_subdata = drm_intel_gem_bo_get_subdata;
3207 bufmgr_gem->bufmgr.bo_wait_rendering = drm_intel_gem_bo_wait_rendering;
3208 bufmgr_gem->bufmgr.bo_emit_reloc = drm_intel_gem_bo_emit_reloc;
3209 bufmgr_gem->bufmgr.bo_emit_reloc_fence = drm_intel_gem_bo_emit_reloc_fence;
3210 bufmgr_gem->bufmgr.bo_pin = drm_intel_gem_bo_pin;
3211 bufmgr_gem->bufmgr.bo_unpin = drm_intel_gem_bo_unpin;
3212 bufmgr_gem->bufmgr.bo_get_tiling = drm_intel_gem_bo_get_tiling;
3213 bufmgr_gem->bufmgr.bo_set_tiling = drm_intel_gem_bo_set_tiling;
3214 bufmgr_gem->bufmgr.bo_flink = drm_intel_gem_bo_flink;
3215 /* Use the new one if available */
3217 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec2;
3218 bufmgr_gem->bufmgr.bo_mrb_exec = drm_intel_gem_bo_mrb_exec2;
3220 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec;
3221 bufmgr_gem->bufmgr.bo_busy = drm_intel_gem_bo_busy;
3222 bufmgr_gem->bufmgr.bo_madvise = drm_intel_gem_bo_madvise;
3223 bufmgr_gem->bufmgr.destroy = drm_intel_bufmgr_gem_destroy;
3224 bufmgr_gem->bufmgr.debug = 0;
3225 bufmgr_gem->bufmgr.check_aperture_space =
3226 drm_intel_gem_check_aperture_space;
3227 bufmgr_gem->bufmgr.bo_disable_reuse = drm_intel_gem_bo_disable_reuse;
3228 bufmgr_gem->bufmgr.bo_is_reusable = drm_intel_gem_bo_is_reusable;
3229 bufmgr_gem->bufmgr.get_pipe_from_crtc_id =
3230 drm_intel_gem_get_pipe_from_crtc_id;
3231 bufmgr_gem->bufmgr.bo_references = drm_intel_gem_bo_references;
3233 DRMINITLISTHEAD(&bufmgr_gem->named);
3234 init_cache_buckets(bufmgr_gem);
3236 DRMINITLISTHEAD(&bufmgr_gem->vma_cache);
3237 bufmgr_gem->vma_max = -1; /* unlimited by default */
3239 return &bufmgr_gem->bufmgr;