1 /**************************************************************************
3 * Copyright © 2007 Red Hat Inc.
4 * Copyright © 2007-2012 Intel Corporation
5 * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
29 **************************************************************************/
31 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
32 * Keith Whitwell <keithw-at-tungstengraphics-dot-com>
33 * Eric Anholt <eric@anholt.net>
34 * Dave Airlie <airlied@linux.ie>
42 #include <xf86atomic.h>
50 #include <sys/ioctl.h>
52 #include <sys/types.h>
57 #define ETIME ETIMEDOUT
60 #include "libdrm_lists.h"
61 #include "intel_bufmgr.h"
62 #include "intel_bufmgr_priv.h"
63 #include "intel_chipset.h"
64 #include "intel_aub.h"
77 #define memclear(s) memset(&s, 0, sizeof(s))
79 #define DBG(...) do { \
80 if (bufmgr_gem->bufmgr.debug) \
81 fprintf(stderr, __VA_ARGS__); \
84 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
86 typedef struct _drm_intel_bo_gem drm_intel_bo_gem;
88 struct drm_intel_gem_bo_bucket {
93 typedef struct _drm_intel_bufmgr_gem {
94 drm_intel_bufmgr bufmgr;
102 pthread_mutex_t lock;
104 struct drm_i915_gem_exec_object *exec_objects;
105 struct drm_i915_gem_exec_object2 *exec2_objects;
106 drm_intel_bo **exec_bos;
110 /** Array of lists of cached gem objects of power-of-two sizes */
111 struct drm_intel_gem_bo_bucket cache_bucket[14 * 4];
115 drmMMListHead managers;
118 drmMMListHead vma_cache;
119 int vma_count, vma_open, vma_max;
122 int available_fences;
125 unsigned int has_bsd : 1;
126 unsigned int has_blt : 1;
127 unsigned int has_relaxed_fencing : 1;
128 unsigned int has_llc : 1;
129 unsigned int has_wait_timeout : 1;
130 unsigned int bo_reuse : 1;
131 unsigned int no_exec : 1;
132 unsigned int has_vebox : 1;
138 } drm_intel_bufmgr_gem;
140 #define DRM_INTEL_RELOC_FENCE (1<<0)
142 typedef struct _drm_intel_reloc_target_info {
145 } drm_intel_reloc_target;
147 struct _drm_intel_bo_gem {
155 * Kenel-assigned global name for this object
157 * List contains both flink named and prime fd'd objects
159 unsigned int global_name;
160 drmMMListHead name_list;
163 * Index of the buffer within the validation list while preparing a
164 * batchbuffer execution.
169 * Current tiling mode
171 uint32_t tiling_mode;
172 uint32_t swizzle_mode;
173 unsigned long stride;
177 /** Array passed to the DRM containing relocation information. */
178 struct drm_i915_gem_relocation_entry *relocs;
180 * Array of info structs corresponding to relocs[i].target_handle etc
182 drm_intel_reloc_target *reloc_target_info;
183 /** Number of entries in relocs */
185 /** Mapped address for the buffer, saved across map/unmap cycles */
187 /** GTT virtual address for the buffer, saved across map/unmap cycles */
190 * Virtual address of the buffer allocated by user, used for userptr
195 drmMMListHead vma_list;
201 * Boolean of whether this BO and its children have been included in
202 * the current drm_intel_bufmgr_check_aperture_space() total.
204 bool included_in_check_aperture;
207 * Boolean of whether this buffer has been used as a relocation
208 * target and had its size accounted for, and thus can't have any
209 * further relocations added to it.
211 bool used_as_reloc_target;
214 * Boolean of whether we have encountered an error whilst building the relocation tree.
219 * Boolean of whether this buffer can be re-used
224 * Boolean of whether the GPU is definitely not accessing the buffer.
226 * This is only valid when reusable, since non-reusable
227 * buffers are those that have been shared wth other
228 * processes, so we don't know their state.
233 * Boolean of whether this buffer was allocated with userptr
238 * Size in bytes of this buffer and its relocation descendents.
240 * Used to avoid costly tree walking in
241 * drm_intel_bufmgr_check_aperture in the common case.
246 * Number of potential fence registers required by this buffer and its
249 int reloc_tree_fences;
251 /** Flags that we may need to do the SW_FINSIH ioctl on unmap. */
252 bool mapped_cpu_write;
256 drm_intel_aub_annotation *aub_annotations;
257 unsigned aub_annotation_count;
261 drm_intel_gem_estimate_batch_space(drm_intel_bo ** bo_array, int count);
264 drm_intel_gem_compute_batch_space(drm_intel_bo ** bo_array, int count);
267 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
268 uint32_t * swizzle_mode);
271 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
272 uint32_t tiling_mode,
275 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
278 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo);
280 static void drm_intel_gem_bo_free(drm_intel_bo *bo);
283 drm_intel_gem_bo_tile_size(drm_intel_bufmgr_gem *bufmgr_gem, unsigned long size,
284 uint32_t *tiling_mode)
286 unsigned long min_size, max_size;
289 if (*tiling_mode == I915_TILING_NONE)
292 /* 965+ just need multiples of page size for tiling */
293 if (bufmgr_gem->gen >= 4)
294 return ROUND_UP_TO(size, 4096);
296 /* Older chips need powers of two, of at least 512k or 1M */
297 if (bufmgr_gem->gen == 3) {
298 min_size = 1024*1024;
299 max_size = 128*1024*1024;
302 max_size = 64*1024*1024;
305 if (size > max_size) {
306 *tiling_mode = I915_TILING_NONE;
310 /* Do we need to allocate every page for the fence? */
311 if (bufmgr_gem->has_relaxed_fencing)
312 return ROUND_UP_TO(size, 4096);
314 for (i = min_size; i < size; i <<= 1)
321 * Round a given pitch up to the minimum required for X tiling on a
322 * given chip. We use 512 as the minimum to allow for a later tiling
326 drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem,
327 unsigned long pitch, uint32_t *tiling_mode)
329 unsigned long tile_width;
332 /* If untiled, then just align it so that we can do rendering
333 * to it with the 3D engine.
335 if (*tiling_mode == I915_TILING_NONE)
336 return ALIGN(pitch, 64);
338 if (*tiling_mode == I915_TILING_X
339 || (IS_915(bufmgr_gem->pci_device)
340 && *tiling_mode == I915_TILING_Y))
345 /* 965 is flexible */
346 if (bufmgr_gem->gen >= 4)
347 return ROUND_UP_TO(pitch, tile_width);
349 /* The older hardware has a maximum pitch of 8192 with tiled
350 * surfaces, so fallback to untiled if it's too large.
353 *tiling_mode = I915_TILING_NONE;
354 return ALIGN(pitch, 64);
357 /* Pre-965 needs power of two tile width */
358 for (i = tile_width; i < pitch; i <<= 1)
364 static struct drm_intel_gem_bo_bucket *
365 drm_intel_gem_bo_bucket_for_size(drm_intel_bufmgr_gem *bufmgr_gem,
370 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
371 struct drm_intel_gem_bo_bucket *bucket =
372 &bufmgr_gem->cache_bucket[i];
373 if (bucket->size >= size) {
382 drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem *bufmgr_gem)
386 for (i = 0; i < bufmgr_gem->exec_count; i++) {
387 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
388 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
390 if (bo_gem->relocs == NULL) {
391 DBG("%2d: %d (%s)\n", i, bo_gem->gem_handle,
396 for (j = 0; j < bo_gem->reloc_count; j++) {
397 drm_intel_bo *target_bo = bo_gem->reloc_target_info[j].bo;
398 drm_intel_bo_gem *target_gem =
399 (drm_intel_bo_gem *) target_bo;
401 DBG("%2d: %d (%s)@0x%08llx -> "
402 "%d (%s)@0x%08lx + 0x%08x\n",
404 bo_gem->gem_handle, bo_gem->name,
405 (unsigned long long)bo_gem->relocs[j].offset,
406 target_gem->gem_handle,
409 bo_gem->relocs[j].delta);
415 drm_intel_gem_bo_reference(drm_intel_bo *bo)
417 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
419 atomic_inc(&bo_gem->refcount);
423 * Adds the given buffer to the list of buffers to be validated (moved into the
424 * appropriate memory type) with the next batch submission.
426 * If a buffer is validated multiple times in a batch submission, it ends up
427 * with the intersection of the memory type flags and the union of the
431 drm_intel_add_validate_buffer(drm_intel_bo *bo)
433 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
434 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
437 if (bo_gem->validate_index != -1)
440 /* Extend the array of validation entries as necessary. */
441 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
442 int new_size = bufmgr_gem->exec_size * 2;
447 bufmgr_gem->exec_objects =
448 realloc(bufmgr_gem->exec_objects,
449 sizeof(*bufmgr_gem->exec_objects) * new_size);
450 bufmgr_gem->exec_bos =
451 realloc(bufmgr_gem->exec_bos,
452 sizeof(*bufmgr_gem->exec_bos) * new_size);
453 bufmgr_gem->exec_size = new_size;
456 index = bufmgr_gem->exec_count;
457 bo_gem->validate_index = index;
458 /* Fill in array entry */
459 bufmgr_gem->exec_objects[index].handle = bo_gem->gem_handle;
460 bufmgr_gem->exec_objects[index].relocation_count = bo_gem->reloc_count;
461 bufmgr_gem->exec_objects[index].relocs_ptr = (uintptr_t) bo_gem->relocs;
462 bufmgr_gem->exec_objects[index].alignment = 0;
463 bufmgr_gem->exec_objects[index].offset = 0;
464 bufmgr_gem->exec_bos[index] = bo;
465 bufmgr_gem->exec_count++;
469 drm_intel_add_validate_buffer2(drm_intel_bo *bo, int need_fence)
471 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
472 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
475 if (bo_gem->validate_index != -1) {
477 bufmgr_gem->exec2_objects[bo_gem->validate_index].flags |=
478 EXEC_OBJECT_NEEDS_FENCE;
482 /* Extend the array of validation entries as necessary. */
483 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
484 int new_size = bufmgr_gem->exec_size * 2;
489 bufmgr_gem->exec2_objects =
490 realloc(bufmgr_gem->exec2_objects,
491 sizeof(*bufmgr_gem->exec2_objects) * new_size);
492 bufmgr_gem->exec_bos =
493 realloc(bufmgr_gem->exec_bos,
494 sizeof(*bufmgr_gem->exec_bos) * new_size);
495 bufmgr_gem->exec_size = new_size;
498 index = bufmgr_gem->exec_count;
499 bo_gem->validate_index = index;
500 /* Fill in array entry */
501 bufmgr_gem->exec2_objects[index].handle = bo_gem->gem_handle;
502 bufmgr_gem->exec2_objects[index].relocation_count = bo_gem->reloc_count;
503 bufmgr_gem->exec2_objects[index].relocs_ptr = (uintptr_t)bo_gem->relocs;
504 bufmgr_gem->exec2_objects[index].alignment = 0;
505 bufmgr_gem->exec2_objects[index].offset = 0;
506 bufmgr_gem->exec_bos[index] = bo;
507 bufmgr_gem->exec2_objects[index].flags = 0;
508 bufmgr_gem->exec2_objects[index].rsvd1 = 0;
509 bufmgr_gem->exec2_objects[index].rsvd2 = 0;
511 bufmgr_gem->exec2_objects[index].flags |=
512 EXEC_OBJECT_NEEDS_FENCE;
514 bufmgr_gem->exec_count++;
517 #define RELOC_BUF_SIZE(x) ((I915_RELOC_HEADER + x * I915_RELOC0_STRIDE) * \
521 drm_intel_bo_gem_set_in_aperture_size(drm_intel_bufmgr_gem *bufmgr_gem,
522 drm_intel_bo_gem *bo_gem)
526 assert(!bo_gem->used_as_reloc_target);
528 /* The older chipsets are far-less flexible in terms of tiling,
529 * and require tiled buffer to be size aligned in the aperture.
530 * This means that in the worst possible case we will need a hole
531 * twice as large as the object in order for it to fit into the
532 * aperture. Optimal packing is for wimps.
534 size = bo_gem->bo.size;
535 if (bufmgr_gem->gen < 4 && bo_gem->tiling_mode != I915_TILING_NONE) {
538 if (bufmgr_gem->has_relaxed_fencing) {
539 if (bufmgr_gem->gen == 3)
540 min_size = 1024*1024;
544 while (min_size < size)
549 /* Account for worst-case alignment. */
553 bo_gem->reloc_tree_size = size;
557 drm_intel_setup_reloc_list(drm_intel_bo *bo)
559 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
560 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
561 unsigned int max_relocs = bufmgr_gem->max_relocs;
563 if (bo->size / 4 < max_relocs)
564 max_relocs = bo->size / 4;
566 bo_gem->relocs = malloc(max_relocs *
567 sizeof(struct drm_i915_gem_relocation_entry));
568 bo_gem->reloc_target_info = malloc(max_relocs *
569 sizeof(drm_intel_reloc_target));
570 if (bo_gem->relocs == NULL || bo_gem->reloc_target_info == NULL) {
571 bo_gem->has_error = true;
573 free (bo_gem->relocs);
574 bo_gem->relocs = NULL;
576 free (bo_gem->reloc_target_info);
577 bo_gem->reloc_target_info = NULL;
586 drm_intel_gem_bo_busy(drm_intel_bo *bo)
588 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
589 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
590 struct drm_i915_gem_busy busy;
593 if (bo_gem->reusable && bo_gem->idle)
597 busy.handle = bo_gem->gem_handle;
599 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_BUSY, &busy);
601 bo_gem->idle = !busy.busy;
606 return (ret == 0 && busy.busy);
610 drm_intel_gem_bo_madvise_internal(drm_intel_bufmgr_gem *bufmgr_gem,
611 drm_intel_bo_gem *bo_gem, int state)
613 struct drm_i915_gem_madvise madv;
616 madv.handle = bo_gem->gem_handle;
619 drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MADVISE, &madv);
621 return madv.retained;
625 drm_intel_gem_bo_madvise(drm_intel_bo *bo, int madv)
627 return drm_intel_gem_bo_madvise_internal
628 ((drm_intel_bufmgr_gem *) bo->bufmgr,
629 (drm_intel_bo_gem *) bo,
633 /* drop the oldest entries that have been purged by the kernel */
635 drm_intel_gem_bo_cache_purge_bucket(drm_intel_bufmgr_gem *bufmgr_gem,
636 struct drm_intel_gem_bo_bucket *bucket)
638 while (!DRMLISTEMPTY(&bucket->head)) {
639 drm_intel_bo_gem *bo_gem;
641 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
642 bucket->head.next, head);
643 if (drm_intel_gem_bo_madvise_internal
644 (bufmgr_gem, bo_gem, I915_MADV_DONTNEED))
647 DRMLISTDEL(&bo_gem->head);
648 drm_intel_gem_bo_free(&bo_gem->bo);
652 static drm_intel_bo *
653 drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr,
657 uint32_t tiling_mode,
658 unsigned long stride)
660 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
661 drm_intel_bo_gem *bo_gem;
662 unsigned int page_size = getpagesize();
664 struct drm_intel_gem_bo_bucket *bucket;
665 bool alloc_from_cache;
666 unsigned long bo_size;
667 bool for_render = false;
669 if (flags & BO_ALLOC_FOR_RENDER)
672 /* Round the allocated size up to a power of two number of pages. */
673 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, size);
675 /* If we don't have caching at this size, don't actually round the
678 if (bucket == NULL) {
680 if (bo_size < page_size)
683 bo_size = bucket->size;
686 pthread_mutex_lock(&bufmgr_gem->lock);
687 /* Get a buffer out of the cache if available */
689 alloc_from_cache = false;
690 if (bucket != NULL && !DRMLISTEMPTY(&bucket->head)) {
692 /* Allocate new render-target BOs from the tail (MRU)
693 * of the list, as it will likely be hot in the GPU
694 * cache and in the aperture for us.
696 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
697 bucket->head.prev, head);
698 DRMLISTDEL(&bo_gem->head);
699 alloc_from_cache = true;
701 /* For non-render-target BOs (where we're probably
702 * going to map it first thing in order to fill it
703 * with data), check if the last BO in the cache is
704 * unbusy, and only reuse in that case. Otherwise,
705 * allocating a new buffer is probably faster than
706 * waiting for the GPU to finish.
708 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
709 bucket->head.next, head);
710 if (!drm_intel_gem_bo_busy(&bo_gem->bo)) {
711 alloc_from_cache = true;
712 DRMLISTDEL(&bo_gem->head);
716 if (alloc_from_cache) {
717 if (!drm_intel_gem_bo_madvise_internal
718 (bufmgr_gem, bo_gem, I915_MADV_WILLNEED)) {
719 drm_intel_gem_bo_free(&bo_gem->bo);
720 drm_intel_gem_bo_cache_purge_bucket(bufmgr_gem,
725 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
728 drm_intel_gem_bo_free(&bo_gem->bo);
733 pthread_mutex_unlock(&bufmgr_gem->lock);
735 if (!alloc_from_cache) {
736 struct drm_i915_gem_create create;
738 bo_gem = calloc(1, sizeof(*bo_gem));
742 bo_gem->bo.size = bo_size;
745 create.size = bo_size;
747 ret = drmIoctl(bufmgr_gem->fd,
748 DRM_IOCTL_I915_GEM_CREATE,
750 bo_gem->gem_handle = create.handle;
751 bo_gem->bo.handle = bo_gem->gem_handle;
756 bo_gem->bo.bufmgr = bufmgr;
758 bo_gem->tiling_mode = I915_TILING_NONE;
759 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
762 /* drm_intel_gem_bo_free calls DRMLISTDEL() for an uninitialized
763 list (vma_list), so better set the list head here */
764 DRMINITLISTHEAD(&bo_gem->name_list);
765 DRMINITLISTHEAD(&bo_gem->vma_list);
766 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
769 drm_intel_gem_bo_free(&bo_gem->bo);
775 atomic_set(&bo_gem->refcount, 1);
776 bo_gem->validate_index = -1;
777 bo_gem->reloc_tree_fences = 0;
778 bo_gem->used_as_reloc_target = false;
779 bo_gem->has_error = false;
780 bo_gem->reusable = true;
781 bo_gem->aub_annotations = NULL;
782 bo_gem->aub_annotation_count = 0;
784 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
786 DBG("bo_create: buf %d (%s) %ldb\n",
787 bo_gem->gem_handle, bo_gem->name, size);
792 static drm_intel_bo *
793 drm_intel_gem_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
796 unsigned int alignment)
798 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size,
800 I915_TILING_NONE, 0);
803 static drm_intel_bo *
804 drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr,
807 unsigned int alignment)
809 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, 0,
810 I915_TILING_NONE, 0);
813 static drm_intel_bo *
814 drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
815 int x, int y, int cpp, uint32_t *tiling_mode,
816 unsigned long *pitch, unsigned long flags)
818 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
819 unsigned long size, stride;
823 unsigned long aligned_y, height_alignment;
825 tiling = *tiling_mode;
827 /* If we're tiled, our allocations are in 8 or 32-row blocks,
828 * so failure to align our height means that we won't allocate
831 * If we're untiled, we still have to align to 2 rows high
832 * because the data port accesses 2x2 blocks even if the
833 * bottom row isn't to be rendered, so failure to align means
834 * we could walk off the end of the GTT and fault. This is
835 * documented on 965, and may be the case on older chipsets
836 * too so we try to be careful.
839 height_alignment = 2;
841 if ((bufmgr_gem->gen == 2) && tiling != I915_TILING_NONE)
842 height_alignment = 16;
843 else if (tiling == I915_TILING_X
844 || (IS_915(bufmgr_gem->pci_device)
845 && tiling == I915_TILING_Y))
846 height_alignment = 8;
847 else if (tiling == I915_TILING_Y)
848 height_alignment = 32;
849 aligned_y = ALIGN(y, height_alignment);
852 stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, tiling_mode);
853 size = stride * aligned_y;
854 size = drm_intel_gem_bo_tile_size(bufmgr_gem, size, tiling_mode);
855 } while (*tiling_mode != tiling);
858 if (tiling == I915_TILING_NONE)
861 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, flags,
865 static drm_intel_bo *
866 drm_intel_gem_bo_alloc_userptr(drm_intel_bufmgr *bufmgr,
869 uint32_t tiling_mode,
874 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
875 drm_intel_bo_gem *bo_gem;
877 struct drm_i915_gem_userptr userptr;
879 /* Tiling with userptr surfaces is not supported
880 * on all hardware so refuse it for time being.
882 if (tiling_mode != I915_TILING_NONE)
885 bo_gem = calloc(1, sizeof(*bo_gem));
889 bo_gem->bo.size = size;
892 userptr.user_ptr = (__u64)((unsigned long)addr);
893 userptr.user_size = size;
894 userptr.flags = flags;
896 ret = drmIoctl(bufmgr_gem->fd,
897 DRM_IOCTL_I915_GEM_USERPTR,
900 DBG("bo_create_userptr: "
901 "ioctl failed with user ptr %p size 0x%lx, "
902 "user flags 0x%lx\n", addr, size, flags);
907 bo_gem->gem_handle = userptr.handle;
908 bo_gem->bo.handle = bo_gem->gem_handle;
909 bo_gem->bo.bufmgr = bufmgr;
910 bo_gem->is_userptr = true;
911 bo_gem->bo.virtual = addr;
912 /* Save the address provided by user */
913 bo_gem->user_virtual = addr;
914 bo_gem->tiling_mode = I915_TILING_NONE;
915 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
918 DRMINITLISTHEAD(&bo_gem->name_list);
919 DRMINITLISTHEAD(&bo_gem->vma_list);
922 atomic_set(&bo_gem->refcount, 1);
923 bo_gem->validate_index = -1;
924 bo_gem->reloc_tree_fences = 0;
925 bo_gem->used_as_reloc_target = false;
926 bo_gem->has_error = false;
927 bo_gem->reusable = false;
929 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
931 DBG("bo_create_userptr: "
932 "ptr %p buf %d (%s) size %ldb, stride 0x%x, tile mode %d\n",
933 addr, bo_gem->gem_handle, bo_gem->name,
934 size, stride, tiling_mode);
940 * Returns a drm_intel_bo wrapping the given buffer object handle.
942 * This can be used when one application needs to pass a buffer object
945 drm_public drm_intel_bo *
946 drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
950 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
951 drm_intel_bo_gem *bo_gem;
953 struct drm_gem_open open_arg;
954 struct drm_i915_gem_get_tiling get_tiling;
957 /* At the moment most applications only have a few named bo.
958 * For instance, in a DRI client only the render buffers passed
959 * between X and the client are named. And since X returns the
960 * alternating names for the front/back buffer a linear search
961 * provides a sufficiently fast match.
963 pthread_mutex_lock(&bufmgr_gem->lock);
964 for (list = bufmgr_gem->named.next;
965 list != &bufmgr_gem->named;
967 bo_gem = DRMLISTENTRY(drm_intel_bo_gem, list, name_list);
968 if (bo_gem->global_name == handle) {
969 drm_intel_gem_bo_reference(&bo_gem->bo);
970 pthread_mutex_unlock(&bufmgr_gem->lock);
976 open_arg.name = handle;
977 ret = drmIoctl(bufmgr_gem->fd,
981 DBG("Couldn't reference %s handle 0x%08x: %s\n",
982 name, handle, strerror(errno));
983 pthread_mutex_unlock(&bufmgr_gem->lock);
986 /* Now see if someone has used a prime handle to get this
987 * object from the kernel before by looking through the list
988 * again for a matching gem_handle
990 for (list = bufmgr_gem->named.next;
991 list != &bufmgr_gem->named;
993 bo_gem = DRMLISTENTRY(drm_intel_bo_gem, list, name_list);
994 if (bo_gem->gem_handle == open_arg.handle) {
995 drm_intel_gem_bo_reference(&bo_gem->bo);
996 pthread_mutex_unlock(&bufmgr_gem->lock);
1001 bo_gem = calloc(1, sizeof(*bo_gem));
1003 pthread_mutex_unlock(&bufmgr_gem->lock);
1007 bo_gem->bo.size = open_arg.size;
1008 bo_gem->bo.offset = 0;
1009 bo_gem->bo.offset64 = 0;
1010 bo_gem->bo.virtual = NULL;
1011 bo_gem->bo.bufmgr = bufmgr;
1012 bo_gem->name = name;
1013 atomic_set(&bo_gem->refcount, 1);
1014 bo_gem->validate_index = -1;
1015 bo_gem->gem_handle = open_arg.handle;
1016 bo_gem->bo.handle = open_arg.handle;
1017 bo_gem->global_name = handle;
1018 bo_gem->reusable = false;
1020 memclear(get_tiling);
1021 get_tiling.handle = bo_gem->gem_handle;
1022 ret = drmIoctl(bufmgr_gem->fd,
1023 DRM_IOCTL_I915_GEM_GET_TILING,
1026 drm_intel_gem_bo_unreference(&bo_gem->bo);
1027 pthread_mutex_unlock(&bufmgr_gem->lock);
1030 bo_gem->tiling_mode = get_tiling.tiling_mode;
1031 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
1032 /* XXX stride is unknown */
1033 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
1035 DRMINITLISTHEAD(&bo_gem->vma_list);
1036 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
1037 pthread_mutex_unlock(&bufmgr_gem->lock);
1038 DBG("bo_create_from_handle: %d (%s)\n", handle, bo_gem->name);
1044 drm_intel_gem_bo_free(drm_intel_bo *bo)
1046 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1047 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1048 struct drm_gem_close close;
1051 DRMLISTDEL(&bo_gem->vma_list);
1052 if (bo_gem->mem_virtual) {
1053 VG(VALGRIND_FREELIKE_BLOCK(bo_gem->mem_virtual, 0));
1054 drm_munmap(bo_gem->mem_virtual, bo_gem->bo.size);
1055 bufmgr_gem->vma_count--;
1057 if (bo_gem->gtt_virtual) {
1058 drm_munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
1059 bufmgr_gem->vma_count--;
1062 /* Close this object */
1064 close.handle = bo_gem->gem_handle;
1065 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close);
1067 DBG("DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
1068 bo_gem->gem_handle, bo_gem->name, strerror(errno));
1070 free(bo_gem->aub_annotations);
1075 drm_intel_gem_bo_mark_mmaps_incoherent(drm_intel_bo *bo)
1078 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1080 if (bo_gem->mem_virtual)
1081 VALGRIND_MAKE_MEM_NOACCESS(bo_gem->mem_virtual, bo->size);
1083 if (bo_gem->gtt_virtual)
1084 VALGRIND_MAKE_MEM_NOACCESS(bo_gem->gtt_virtual, bo->size);
1088 /** Frees all cached buffers significantly older than @time. */
1090 drm_intel_gem_cleanup_bo_cache(drm_intel_bufmgr_gem *bufmgr_gem, time_t time)
1094 if (bufmgr_gem->time == time)
1097 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
1098 struct drm_intel_gem_bo_bucket *bucket =
1099 &bufmgr_gem->cache_bucket[i];
1101 while (!DRMLISTEMPTY(&bucket->head)) {
1102 drm_intel_bo_gem *bo_gem;
1104 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1105 bucket->head.next, head);
1106 if (time - bo_gem->free_time <= 1)
1109 DRMLISTDEL(&bo_gem->head);
1111 drm_intel_gem_bo_free(&bo_gem->bo);
1115 bufmgr_gem->time = time;
1118 static void drm_intel_gem_bo_purge_vma_cache(drm_intel_bufmgr_gem *bufmgr_gem)
1122 DBG("%s: cached=%d, open=%d, limit=%d\n", __FUNCTION__,
1123 bufmgr_gem->vma_count, bufmgr_gem->vma_open, bufmgr_gem->vma_max);
1125 if (bufmgr_gem->vma_max < 0)
1128 /* We may need to evict a few entries in order to create new mmaps */
1129 limit = bufmgr_gem->vma_max - 2*bufmgr_gem->vma_open;
1133 while (bufmgr_gem->vma_count > limit) {
1134 drm_intel_bo_gem *bo_gem;
1136 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1137 bufmgr_gem->vma_cache.next,
1139 assert(bo_gem->map_count == 0);
1140 DRMLISTDELINIT(&bo_gem->vma_list);
1142 if (bo_gem->mem_virtual) {
1143 drm_munmap(bo_gem->mem_virtual, bo_gem->bo.size);
1144 bo_gem->mem_virtual = NULL;
1145 bufmgr_gem->vma_count--;
1147 if (bo_gem->gtt_virtual) {
1148 drm_munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
1149 bo_gem->gtt_virtual = NULL;
1150 bufmgr_gem->vma_count--;
1155 static void drm_intel_gem_bo_close_vma(drm_intel_bufmgr_gem *bufmgr_gem,
1156 drm_intel_bo_gem *bo_gem)
1158 bufmgr_gem->vma_open--;
1159 DRMLISTADDTAIL(&bo_gem->vma_list, &bufmgr_gem->vma_cache);
1160 if (bo_gem->mem_virtual)
1161 bufmgr_gem->vma_count++;
1162 if (bo_gem->gtt_virtual)
1163 bufmgr_gem->vma_count++;
1164 drm_intel_gem_bo_purge_vma_cache(bufmgr_gem);
1167 static void drm_intel_gem_bo_open_vma(drm_intel_bufmgr_gem *bufmgr_gem,
1168 drm_intel_bo_gem *bo_gem)
1170 bufmgr_gem->vma_open++;
1171 DRMLISTDEL(&bo_gem->vma_list);
1172 if (bo_gem->mem_virtual)
1173 bufmgr_gem->vma_count--;
1174 if (bo_gem->gtt_virtual)
1175 bufmgr_gem->vma_count--;
1176 drm_intel_gem_bo_purge_vma_cache(bufmgr_gem);
1180 drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time)
1182 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1183 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1184 struct drm_intel_gem_bo_bucket *bucket;
1187 /* Unreference all the target buffers */
1188 for (i = 0; i < bo_gem->reloc_count; i++) {
1189 if (bo_gem->reloc_target_info[i].bo != bo) {
1190 drm_intel_gem_bo_unreference_locked_timed(bo_gem->
1191 reloc_target_info[i].bo,
1195 bo_gem->reloc_count = 0;
1196 bo_gem->used_as_reloc_target = false;
1198 DBG("bo_unreference final: %d (%s)\n",
1199 bo_gem->gem_handle, bo_gem->name);
1201 /* release memory associated with this object */
1202 if (bo_gem->reloc_target_info) {
1203 free(bo_gem->reloc_target_info);
1204 bo_gem->reloc_target_info = NULL;
1206 if (bo_gem->relocs) {
1207 free(bo_gem->relocs);
1208 bo_gem->relocs = NULL;
1211 /* Clear any left-over mappings */
1212 if (bo_gem->map_count) {
1213 DBG("bo freed with non-zero map-count %d\n", bo_gem->map_count);
1214 bo_gem->map_count = 0;
1215 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1216 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1219 DRMLISTDEL(&bo_gem->name_list);
1221 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, bo->size);
1222 /* Put the buffer into our internal cache for reuse if we can. */
1223 if (bufmgr_gem->bo_reuse && bo_gem->reusable && bucket != NULL &&
1224 drm_intel_gem_bo_madvise_internal(bufmgr_gem, bo_gem,
1225 I915_MADV_DONTNEED)) {
1226 bo_gem->free_time = time;
1228 bo_gem->name = NULL;
1229 bo_gem->validate_index = -1;
1231 DRMLISTADDTAIL(&bo_gem->head, &bucket->head);
1233 drm_intel_gem_bo_free(bo);
1237 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
1240 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1242 assert(atomic_read(&bo_gem->refcount) > 0);
1243 if (atomic_dec_and_test(&bo_gem->refcount))
1244 drm_intel_gem_bo_unreference_final(bo, time);
1247 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo)
1249 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1251 assert(atomic_read(&bo_gem->refcount) > 0);
1253 if (atomic_add_unless(&bo_gem->refcount, -1, 1)) {
1254 drm_intel_bufmgr_gem *bufmgr_gem =
1255 (drm_intel_bufmgr_gem *) bo->bufmgr;
1256 struct timespec time;
1258 clock_gettime(CLOCK_MONOTONIC, &time);
1260 pthread_mutex_lock(&bufmgr_gem->lock);
1262 if (atomic_dec_and_test(&bo_gem->refcount)) {
1263 drm_intel_gem_bo_unreference_final(bo, time.tv_sec);
1264 drm_intel_gem_cleanup_bo_cache(bufmgr_gem, time.tv_sec);
1267 pthread_mutex_unlock(&bufmgr_gem->lock);
1271 static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable)
1273 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1274 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1275 struct drm_i915_gem_set_domain set_domain;
1278 if (bo_gem->is_userptr) {
1279 /* Return the same user ptr */
1280 bo->virtual = bo_gem->user_virtual;
1284 pthread_mutex_lock(&bufmgr_gem->lock);
1286 if (bo_gem->map_count++ == 0)
1287 drm_intel_gem_bo_open_vma(bufmgr_gem, bo_gem);
1289 if (!bo_gem->mem_virtual) {
1290 struct drm_i915_gem_mmap mmap_arg;
1292 DBG("bo_map: %d (%s), map_count=%d\n",
1293 bo_gem->gem_handle, bo_gem->name, bo_gem->map_count);
1296 mmap_arg.handle = bo_gem->gem_handle;
1297 mmap_arg.size = bo->size;
1298 ret = drmIoctl(bufmgr_gem->fd,
1299 DRM_IOCTL_I915_GEM_MMAP,
1303 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1304 __FILE__, __LINE__, bo_gem->gem_handle,
1305 bo_gem->name, strerror(errno));
1306 if (--bo_gem->map_count == 0)
1307 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1308 pthread_mutex_unlock(&bufmgr_gem->lock);
1311 VG(VALGRIND_MALLOCLIKE_BLOCK(mmap_arg.addr_ptr, mmap_arg.size, 0, 1));
1312 bo_gem->mem_virtual = (void *)(uintptr_t) mmap_arg.addr_ptr;
1314 DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1315 bo_gem->mem_virtual);
1316 bo->virtual = bo_gem->mem_virtual;
1318 memclear(set_domain);
1319 set_domain.handle = bo_gem->gem_handle;
1320 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
1322 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
1324 set_domain.write_domain = 0;
1325 ret = drmIoctl(bufmgr_gem->fd,
1326 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1329 DBG("%s:%d: Error setting to CPU domain %d: %s\n",
1330 __FILE__, __LINE__, bo_gem->gem_handle,
1335 bo_gem->mapped_cpu_write = true;
1337 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1338 VG(VALGRIND_MAKE_MEM_DEFINED(bo_gem->mem_virtual, bo->size));
1339 pthread_mutex_unlock(&bufmgr_gem->lock);
1345 map_gtt(drm_intel_bo *bo)
1347 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1348 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1351 if (bo_gem->is_userptr)
1354 if (bo_gem->map_count++ == 0)
1355 drm_intel_gem_bo_open_vma(bufmgr_gem, bo_gem);
1357 /* Get a mapping of the buffer if we haven't before. */
1358 if (bo_gem->gtt_virtual == NULL) {
1359 struct drm_i915_gem_mmap_gtt mmap_arg;
1361 DBG("bo_map_gtt: mmap %d (%s), map_count=%d\n",
1362 bo_gem->gem_handle, bo_gem->name, bo_gem->map_count);
1365 mmap_arg.handle = bo_gem->gem_handle;
1367 /* Get the fake offset back... */
1368 ret = drmIoctl(bufmgr_gem->fd,
1369 DRM_IOCTL_I915_GEM_MMAP_GTT,
1373 DBG("%s:%d: Error preparing buffer map %d (%s): %s .\n",
1375 bo_gem->gem_handle, bo_gem->name,
1377 if (--bo_gem->map_count == 0)
1378 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1383 bo_gem->gtt_virtual = drm_mmap(0, bo->size, PROT_READ | PROT_WRITE,
1384 MAP_SHARED, bufmgr_gem->fd,
1386 if (bo_gem->gtt_virtual == MAP_FAILED) {
1387 bo_gem->gtt_virtual = NULL;
1389 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1391 bo_gem->gem_handle, bo_gem->name,
1393 if (--bo_gem->map_count == 0)
1394 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1399 bo->virtual = bo_gem->gtt_virtual;
1401 DBG("bo_map_gtt: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1402 bo_gem->gtt_virtual);
1408 drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
1410 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1411 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1412 struct drm_i915_gem_set_domain set_domain;
1415 pthread_mutex_lock(&bufmgr_gem->lock);
1419 pthread_mutex_unlock(&bufmgr_gem->lock);
1423 /* Now move it to the GTT domain so that the GPU and CPU
1424 * caches are flushed and the GPU isn't actively using the
1427 * The pagefault handler does this domain change for us when
1428 * it has unbound the BO from the GTT, but it's up to us to
1429 * tell it when we're about to use things if we had done
1430 * rendering and it still happens to be bound to the GTT.
1432 memclear(set_domain);
1433 set_domain.handle = bo_gem->gem_handle;
1434 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1435 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
1436 ret = drmIoctl(bufmgr_gem->fd,
1437 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1440 DBG("%s:%d: Error setting domain %d: %s\n",
1441 __FILE__, __LINE__, bo_gem->gem_handle,
1445 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1446 VG(VALGRIND_MAKE_MEM_DEFINED(bo_gem->gtt_virtual, bo->size));
1447 pthread_mutex_unlock(&bufmgr_gem->lock);
1453 * Performs a mapping of the buffer object like the normal GTT
1454 * mapping, but avoids waiting for the GPU to be done reading from or
1455 * rendering to the buffer.
1457 * This is used in the implementation of GL_ARB_map_buffer_range: The
1458 * user asks to create a buffer, then does a mapping, fills some
1459 * space, runs a drawing command, then asks to map it again without
1460 * synchronizing because it guarantees that it won't write over the
1461 * data that the GPU is busy using (or, more specifically, that if it
1462 * does write over the data, it acknowledges that rendering is
1467 drm_intel_gem_bo_map_unsynchronized(drm_intel_bo *bo)
1469 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1470 #ifdef HAVE_VALGRIND
1471 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1475 /* If the CPU cache isn't coherent with the GTT, then use a
1476 * regular synchronized mapping. The problem is that we don't
1477 * track where the buffer was last used on the CPU side in
1478 * terms of drm_intel_bo_map vs drm_intel_gem_bo_map_gtt, so
1479 * we would potentially corrupt the buffer even when the user
1480 * does reasonable things.
1482 if (!bufmgr_gem->has_llc)
1483 return drm_intel_gem_bo_map_gtt(bo);
1485 pthread_mutex_lock(&bufmgr_gem->lock);
1489 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1490 VG(VALGRIND_MAKE_MEM_DEFINED(bo_gem->gtt_virtual, bo->size));
1493 pthread_mutex_unlock(&bufmgr_gem->lock);
1498 static int drm_intel_gem_bo_unmap(drm_intel_bo *bo)
1500 drm_intel_bufmgr_gem *bufmgr_gem;
1501 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1507 if (bo_gem->is_userptr)
1510 bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1512 pthread_mutex_lock(&bufmgr_gem->lock);
1514 if (bo_gem->map_count <= 0) {
1515 DBG("attempted to unmap an unmapped bo\n");
1516 pthread_mutex_unlock(&bufmgr_gem->lock);
1517 /* Preserve the old behaviour of just treating this as a
1518 * no-op rather than reporting the error.
1523 if (bo_gem->mapped_cpu_write) {
1524 struct drm_i915_gem_sw_finish sw_finish;
1526 /* Cause a flush to happen if the buffer's pinned for
1527 * scanout, so the results show up in a timely manner.
1528 * Unlike GTT set domains, this only does work if the
1529 * buffer should be scanout-related.
1531 memclear(sw_finish);
1532 sw_finish.handle = bo_gem->gem_handle;
1533 ret = drmIoctl(bufmgr_gem->fd,
1534 DRM_IOCTL_I915_GEM_SW_FINISH,
1536 ret = ret == -1 ? -errno : 0;
1538 bo_gem->mapped_cpu_write = false;
1541 /* We need to unmap after every innovation as we cannot track
1542 * an open vma for every bo as that will exhaasut the system
1543 * limits and cause later failures.
1545 if (--bo_gem->map_count == 0) {
1546 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1547 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1550 pthread_mutex_unlock(&bufmgr_gem->lock);
1556 drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo)
1558 return drm_intel_gem_bo_unmap(bo);
1562 drm_intel_gem_bo_subdata(drm_intel_bo *bo, unsigned long offset,
1563 unsigned long size, const void *data)
1565 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1566 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1567 struct drm_i915_gem_pwrite pwrite;
1570 if (bo_gem->is_userptr)
1574 pwrite.handle = bo_gem->gem_handle;
1575 pwrite.offset = offset;
1577 pwrite.data_ptr = (uint64_t) (uintptr_t) data;
1578 ret = drmIoctl(bufmgr_gem->fd,
1579 DRM_IOCTL_I915_GEM_PWRITE,
1583 DBG("%s:%d: Error writing data to buffer %d: (%d %d) %s .\n",
1584 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1585 (int)size, strerror(errno));
1592 drm_intel_gem_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id)
1594 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1595 struct drm_i915_get_pipe_from_crtc_id get_pipe_from_crtc_id;
1598 memclear(get_pipe_from_crtc_id);
1599 get_pipe_from_crtc_id.crtc_id = crtc_id;
1600 ret = drmIoctl(bufmgr_gem->fd,
1601 DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID,
1602 &get_pipe_from_crtc_id);
1604 /* We return -1 here to signal that we don't
1605 * know which pipe is associated with this crtc.
1606 * This lets the caller know that this information
1607 * isn't available; using the wrong pipe for
1608 * vblank waiting can cause the chipset to lock up
1613 return get_pipe_from_crtc_id.pipe;
1617 drm_intel_gem_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
1618 unsigned long size, void *data)
1620 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1621 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1622 struct drm_i915_gem_pread pread;
1625 if (bo_gem->is_userptr)
1629 pread.handle = bo_gem->gem_handle;
1630 pread.offset = offset;
1632 pread.data_ptr = (uint64_t) (uintptr_t) data;
1633 ret = drmIoctl(bufmgr_gem->fd,
1634 DRM_IOCTL_I915_GEM_PREAD,
1638 DBG("%s:%d: Error reading data from buffer %d: (%d %d) %s .\n",
1639 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1640 (int)size, strerror(errno));
1646 /** Waits for all GPU rendering with the object to have completed. */
1648 drm_intel_gem_bo_wait_rendering(drm_intel_bo *bo)
1650 drm_intel_gem_bo_start_gtt_access(bo, 1);
1654 * Waits on a BO for the given amount of time.
1656 * @bo: buffer object to wait for
1657 * @timeout_ns: amount of time to wait in nanoseconds.
1658 * If value is less than 0, an infinite wait will occur.
1660 * Returns 0 if the wait was successful ie. the last batch referencing the
1661 * object has completed within the allotted time. Otherwise some negative return
1662 * value describes the error. Of particular interest is -ETIME when the wait has
1663 * failed to yield the desired result.
1665 * Similar to drm_intel_gem_bo_wait_rendering except a timeout parameter allows
1666 * the operation to give up after a certain amount of time. Another subtle
1667 * difference is the internal locking semantics are different (this variant does
1668 * not hold the lock for the duration of the wait). This makes the wait subject
1669 * to a larger userspace race window.
1671 * The implementation shall wait until the object is no longer actively
1672 * referenced within a batch buffer at the time of the call. The wait will
1673 * not guarantee that the buffer is re-issued via another thread, or an flinked
1674 * handle. Userspace must make sure this race does not occur if such precision
1677 * Note that some kernels have broken the inifite wait for negative values
1678 * promise, upgrade to latest stable kernels if this is the case.
1681 drm_intel_gem_bo_wait(drm_intel_bo *bo, int64_t timeout_ns)
1683 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1684 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1685 struct drm_i915_gem_wait wait;
1688 if (!bufmgr_gem->has_wait_timeout) {
1689 DBG("%s:%d: Timed wait is not supported. Falling back to "
1690 "infinite wait\n", __FILE__, __LINE__);
1692 drm_intel_gem_bo_wait_rendering(bo);
1695 return drm_intel_gem_bo_busy(bo) ? -ETIME : 0;
1700 wait.bo_handle = bo_gem->gem_handle;
1701 wait.timeout_ns = timeout_ns;
1702 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_WAIT, &wait);
1710 * Sets the object to the GTT read and possibly write domain, used by the X
1711 * 2D driver in the absence of kernel support to do drm_intel_gem_bo_map_gtt().
1713 * In combination with drm_intel_gem_bo_pin() and manual fence management, we
1714 * can do tiled pixmaps this way.
1717 drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable)
1719 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1720 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1721 struct drm_i915_gem_set_domain set_domain;
1724 memclear(set_domain);
1725 set_domain.handle = bo_gem->gem_handle;
1726 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1727 set_domain.write_domain = write_enable ? I915_GEM_DOMAIN_GTT : 0;
1728 ret = drmIoctl(bufmgr_gem->fd,
1729 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1732 DBG("%s:%d: Error setting memory domains %d (%08x %08x): %s .\n",
1733 __FILE__, __LINE__, bo_gem->gem_handle,
1734 set_domain.read_domains, set_domain.write_domain,
1740 drm_intel_bufmgr_gem_destroy(drm_intel_bufmgr *bufmgr)
1742 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1745 free(bufmgr_gem->exec2_objects);
1746 free(bufmgr_gem->exec_objects);
1747 free(bufmgr_gem->exec_bos);
1748 free(bufmgr_gem->aub_filename);
1750 pthread_mutex_destroy(&bufmgr_gem->lock);
1752 /* Free any cached buffer objects we were going to reuse */
1753 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
1754 struct drm_intel_gem_bo_bucket *bucket =
1755 &bufmgr_gem->cache_bucket[i];
1756 drm_intel_bo_gem *bo_gem;
1758 while (!DRMLISTEMPTY(&bucket->head)) {
1759 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1760 bucket->head.next, head);
1761 DRMLISTDEL(&bo_gem->head);
1763 drm_intel_gem_bo_free(&bo_gem->bo);
1771 * Adds the target buffer to the validation list and adds the relocation
1772 * to the reloc_buffer's relocation list.
1774 * The relocation entry at the given offset must already contain the
1775 * precomputed relocation value, because the kernel will optimize out
1776 * the relocation entry write when the buffer hasn't moved from the
1777 * last known offset in target_bo.
1780 do_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1781 drm_intel_bo *target_bo, uint32_t target_offset,
1782 uint32_t read_domains, uint32_t write_domain,
1785 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1786 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1787 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
1788 bool fenced_command;
1790 if (bo_gem->has_error)
1793 if (target_bo_gem->has_error) {
1794 bo_gem->has_error = true;
1798 /* We never use HW fences for rendering on 965+ */
1799 if (bufmgr_gem->gen >= 4)
1802 fenced_command = need_fence;
1803 if (target_bo_gem->tiling_mode == I915_TILING_NONE)
1806 /* Create a new relocation list if needed */
1807 if (bo_gem->relocs == NULL && drm_intel_setup_reloc_list(bo))
1810 /* Check overflow */
1811 assert(bo_gem->reloc_count < bufmgr_gem->max_relocs);
1814 assert(offset <= bo->size - 4);
1815 assert((write_domain & (write_domain - 1)) == 0);
1817 /* An object needing a fence is a tiled buffer, so it won't have
1818 * relocs to other buffers.
1821 assert(target_bo_gem->reloc_count == 0);
1822 target_bo_gem->reloc_tree_fences = 1;
1825 /* Make sure that we're not adding a reloc to something whose size has
1826 * already been accounted for.
1828 assert(!bo_gem->used_as_reloc_target);
1829 if (target_bo_gem != bo_gem) {
1830 target_bo_gem->used_as_reloc_target = true;
1831 bo_gem->reloc_tree_size += target_bo_gem->reloc_tree_size;
1832 bo_gem->reloc_tree_fences += target_bo_gem->reloc_tree_fences;
1835 bo_gem->relocs[bo_gem->reloc_count].offset = offset;
1836 bo_gem->relocs[bo_gem->reloc_count].delta = target_offset;
1837 bo_gem->relocs[bo_gem->reloc_count].target_handle =
1838 target_bo_gem->gem_handle;
1839 bo_gem->relocs[bo_gem->reloc_count].read_domains = read_domains;
1840 bo_gem->relocs[bo_gem->reloc_count].write_domain = write_domain;
1841 bo_gem->relocs[bo_gem->reloc_count].presumed_offset = target_bo->offset64;
1843 bo_gem->reloc_target_info[bo_gem->reloc_count].bo = target_bo;
1844 if (target_bo != bo)
1845 drm_intel_gem_bo_reference(target_bo);
1847 bo_gem->reloc_target_info[bo_gem->reloc_count].flags =
1848 DRM_INTEL_RELOC_FENCE;
1850 bo_gem->reloc_target_info[bo_gem->reloc_count].flags = 0;
1852 bo_gem->reloc_count++;
1858 drm_intel_gem_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1859 drm_intel_bo *target_bo, uint32_t target_offset,
1860 uint32_t read_domains, uint32_t write_domain)
1862 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1864 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1865 read_domains, write_domain,
1866 !bufmgr_gem->fenced_relocs);
1870 drm_intel_gem_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
1871 drm_intel_bo *target_bo,
1872 uint32_t target_offset,
1873 uint32_t read_domains, uint32_t write_domain)
1875 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1876 read_domains, write_domain, true);
1880 drm_intel_gem_bo_get_reloc_count(drm_intel_bo *bo)
1882 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1884 return bo_gem->reloc_count;
1888 * Removes existing relocation entries in the BO after "start".
1890 * This allows a user to avoid a two-step process for state setup with
1891 * counting up all the buffer objects and doing a
1892 * drm_intel_bufmgr_check_aperture_space() before emitting any of the
1893 * relocations for the state setup. Instead, save the state of the
1894 * batchbuffer including drm_intel_gem_get_reloc_count(), emit all the
1895 * state, and then check if it still fits in the aperture.
1897 * Any further drm_intel_bufmgr_check_aperture_space() queries
1898 * involving this buffer in the tree are undefined after this call.
1901 drm_intel_gem_bo_clear_relocs(drm_intel_bo *bo, int start)
1903 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1904 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1906 struct timespec time;
1908 clock_gettime(CLOCK_MONOTONIC, &time);
1910 assert(bo_gem->reloc_count >= start);
1912 /* Unreference the cleared target buffers */
1913 pthread_mutex_lock(&bufmgr_gem->lock);
1915 for (i = start; i < bo_gem->reloc_count; i++) {
1916 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) bo_gem->reloc_target_info[i].bo;
1917 if (&target_bo_gem->bo != bo) {
1918 bo_gem->reloc_tree_fences -= target_bo_gem->reloc_tree_fences;
1919 drm_intel_gem_bo_unreference_locked_timed(&target_bo_gem->bo,
1923 bo_gem->reloc_count = start;
1925 pthread_mutex_unlock(&bufmgr_gem->lock);
1930 * Walk the tree of relocations rooted at BO and accumulate the list of
1931 * validations to be performed and update the relocation buffers with
1932 * index values into the validation list.
1935 drm_intel_gem_bo_process_reloc(drm_intel_bo *bo)
1937 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1940 if (bo_gem->relocs == NULL)
1943 for (i = 0; i < bo_gem->reloc_count; i++) {
1944 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1946 if (target_bo == bo)
1949 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1951 /* Continue walking the tree depth-first. */
1952 drm_intel_gem_bo_process_reloc(target_bo);
1954 /* Add the target to the validate list */
1955 drm_intel_add_validate_buffer(target_bo);
1960 drm_intel_gem_bo_process_reloc2(drm_intel_bo *bo)
1962 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1965 if (bo_gem->relocs == NULL)
1968 for (i = 0; i < bo_gem->reloc_count; i++) {
1969 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1972 if (target_bo == bo)
1975 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1977 /* Continue walking the tree depth-first. */
1978 drm_intel_gem_bo_process_reloc2(target_bo);
1980 need_fence = (bo_gem->reloc_target_info[i].flags &
1981 DRM_INTEL_RELOC_FENCE);
1983 /* Add the target to the validate list */
1984 drm_intel_add_validate_buffer2(target_bo, need_fence);
1990 drm_intel_update_buffer_offsets(drm_intel_bufmgr_gem *bufmgr_gem)
1994 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1995 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1996 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1998 /* Update the buffer offset */
1999 if (bufmgr_gem->exec_objects[i].offset != bo->offset64) {
2000 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
2001 bo_gem->gem_handle, bo_gem->name, bo->offset64,
2002 (unsigned long long)bufmgr_gem->exec_objects[i].
2004 bo->offset64 = bufmgr_gem->exec_objects[i].offset;
2005 bo->offset = bufmgr_gem->exec_objects[i].offset;
2011 drm_intel_update_buffer_offsets2 (drm_intel_bufmgr_gem *bufmgr_gem)
2015 for (i = 0; i < bufmgr_gem->exec_count; i++) {
2016 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
2017 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
2019 /* Update the buffer offset */
2020 if (bufmgr_gem->exec2_objects[i].offset != bo->offset64) {
2021 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
2022 bo_gem->gem_handle, bo_gem->name, bo->offset64,
2023 (unsigned long long)bufmgr_gem->exec2_objects[i].offset);
2024 bo->offset64 = bufmgr_gem->exec2_objects[i].offset;
2025 bo->offset = bufmgr_gem->exec2_objects[i].offset;
2031 aub_out(drm_intel_bufmgr_gem *bufmgr_gem, uint32_t data)
2033 fwrite(&data, 1, 4, bufmgr_gem->aub_file);
2037 aub_out_data(drm_intel_bufmgr_gem *bufmgr_gem, void *data, size_t size)
2039 fwrite(data, 1, size, bufmgr_gem->aub_file);
2043 aub_write_bo_data(drm_intel_bo *bo, uint32_t offset, uint32_t size)
2045 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2046 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2050 data = malloc(bo->size);
2051 drm_intel_bo_get_subdata(bo, offset, size, data);
2053 /* Easy mode: write out bo with no relocations */
2054 if (!bo_gem->reloc_count) {
2055 aub_out_data(bufmgr_gem, data, size);
2060 /* Otherwise, handle the relocations while writing. */
2061 for (i = 0; i < size / 4; i++) {
2063 for (r = 0; r < bo_gem->reloc_count; r++) {
2064 struct drm_i915_gem_relocation_entry *reloc;
2065 drm_intel_reloc_target *info;
2067 reloc = &bo_gem->relocs[r];
2068 info = &bo_gem->reloc_target_info[r];
2070 if (reloc->offset == offset + i * 4) {
2071 drm_intel_bo_gem *target_gem;
2074 target_gem = (drm_intel_bo_gem *)info->bo;
2077 val += target_gem->aub_offset;
2079 aub_out(bufmgr_gem, val);
2084 if (r == bo_gem->reloc_count) {
2085 /* no relocation, just the data */
2086 aub_out(bufmgr_gem, data[i]);
2094 aub_bo_get_address(drm_intel_bo *bo)
2096 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2097 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2099 /* Give the object a graphics address in the AUB file. We
2100 * don't just use the GEM object address because we do AUB
2101 * dumping before execution -- we want to successfully log
2102 * when the hardware might hang, and we might even want to aub
2103 * capture for a driver trying to execute on a different
2104 * generation of hardware by disabling the actual kernel exec
2107 bo_gem->aub_offset = bufmgr_gem->aub_offset;
2108 bufmgr_gem->aub_offset += bo->size;
2109 /* XXX: Handle aperture overflow. */
2110 assert(bufmgr_gem->aub_offset < 256 * 1024 * 1024);
2114 aub_write_trace_block(drm_intel_bo *bo, uint32_t type, uint32_t subtype,
2115 uint32_t offset, uint32_t size)
2117 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2118 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2121 CMD_AUB_TRACE_HEADER_BLOCK |
2122 ((bufmgr_gem->gen >= 8 ? 6 : 5) - 2));
2124 AUB_TRACE_MEMTYPE_GTT | type | AUB_TRACE_OP_DATA_WRITE);
2125 aub_out(bufmgr_gem, subtype);
2126 aub_out(bufmgr_gem, bo_gem->aub_offset + offset);
2127 aub_out(bufmgr_gem, size);
2128 if (bufmgr_gem->gen >= 8)
2129 aub_out(bufmgr_gem, 0);
2130 aub_write_bo_data(bo, offset, size);
2134 * Break up large objects into multiple writes. Otherwise a 128kb VBO
2135 * would overflow the 16 bits of size field in the packet header and
2136 * everything goes badly after that.
2139 aub_write_large_trace_block(drm_intel_bo *bo, uint32_t type, uint32_t subtype,
2140 uint32_t offset, uint32_t size)
2142 uint32_t block_size;
2143 uint32_t sub_offset;
2145 for (sub_offset = 0; sub_offset < size; sub_offset += block_size) {
2146 block_size = size - sub_offset;
2148 if (block_size > 8 * 4096)
2149 block_size = 8 * 4096;
2151 aub_write_trace_block(bo, type, subtype, offset + sub_offset,
2157 aub_write_bo(drm_intel_bo *bo)
2159 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2160 uint32_t offset = 0;
2163 aub_bo_get_address(bo);
2165 /* Write out each annotated section separately. */
2166 for (i = 0; i < bo_gem->aub_annotation_count; ++i) {
2167 drm_intel_aub_annotation *annotation =
2168 &bo_gem->aub_annotations[i];
2169 uint32_t ending_offset = annotation->ending_offset;
2170 if (ending_offset > bo->size)
2171 ending_offset = bo->size;
2172 if (ending_offset > offset) {
2173 aub_write_large_trace_block(bo, annotation->type,
2174 annotation->subtype,
2176 ending_offset - offset);
2177 offset = ending_offset;
2181 /* Write out any remaining unannotated data */
2182 if (offset < bo->size) {
2183 aub_write_large_trace_block(bo, AUB_TRACE_TYPE_NOTYPE, 0,
2184 offset, bo->size - offset);
2189 * Make a ringbuffer on fly and dump it
2192 aub_build_dump_ringbuffer(drm_intel_bufmgr_gem *bufmgr_gem,
2193 uint32_t batch_buffer, int ring_flag)
2195 uint32_t ringbuffer[4096];
2196 int ring = AUB_TRACE_TYPE_RING_PRB0; /* The default ring */
2199 if (ring_flag == I915_EXEC_BSD)
2200 ring = AUB_TRACE_TYPE_RING_PRB1;
2201 else if (ring_flag == I915_EXEC_BLT)
2202 ring = AUB_TRACE_TYPE_RING_PRB2;
2204 /* Make a ring buffer to execute our batchbuffer. */
2205 memset(ringbuffer, 0, sizeof(ringbuffer));
2206 if (bufmgr_gem->gen >= 8) {
2207 ringbuffer[ring_count++] = AUB_MI_BATCH_BUFFER_START | (3 - 2);
2208 ringbuffer[ring_count++] = batch_buffer;
2209 ringbuffer[ring_count++] = 0;
2211 ringbuffer[ring_count++] = AUB_MI_BATCH_BUFFER_START;
2212 ringbuffer[ring_count++] = batch_buffer;
2215 /* Write out the ring. This appears to trigger execution of
2216 * the ring in the simulator.
2219 CMD_AUB_TRACE_HEADER_BLOCK |
2220 ((bufmgr_gem->gen >= 8 ? 6 : 5) - 2));
2222 AUB_TRACE_MEMTYPE_GTT | ring | AUB_TRACE_OP_COMMAND_WRITE);
2223 aub_out(bufmgr_gem, 0); /* general/surface subtype */
2224 aub_out(bufmgr_gem, bufmgr_gem->aub_offset);
2225 aub_out(bufmgr_gem, ring_count * 4);
2226 if (bufmgr_gem->gen >= 8)
2227 aub_out(bufmgr_gem, 0);
2229 /* FIXME: Need some flush operations here? */
2230 aub_out_data(bufmgr_gem, ringbuffer, ring_count * 4);
2232 /* Update offset pointer */
2233 bufmgr_gem->aub_offset += 4096;
2237 drm_intel_gem_bo_aub_dump_bmp(drm_intel_bo *bo,
2238 int x1, int y1, int width, int height,
2239 enum aub_dump_bmp_format format,
2240 int pitch, int offset)
2242 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2243 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
2247 case AUB_DUMP_BMP_FORMAT_8BIT:
2250 case AUB_DUMP_BMP_FORMAT_ARGB_4444:
2253 case AUB_DUMP_BMP_FORMAT_ARGB_0888:
2254 case AUB_DUMP_BMP_FORMAT_ARGB_8888:
2258 printf("Unknown AUB dump format %d\n", format);
2262 if (!bufmgr_gem->aub_file)
2265 aub_out(bufmgr_gem, CMD_AUB_DUMP_BMP | 4);
2266 aub_out(bufmgr_gem, (y1 << 16) | x1);
2271 aub_out(bufmgr_gem, (height << 16) | width);
2272 aub_out(bufmgr_gem, bo_gem->aub_offset + offset);
2274 ((bo_gem->tiling_mode != I915_TILING_NONE) ? (1 << 2) : 0) |
2275 ((bo_gem->tiling_mode == I915_TILING_Y) ? (1 << 3) : 0));
2279 aub_exec(drm_intel_bo *bo, int ring_flag, int used)
2281 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2282 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2284 bool batch_buffer_needs_annotations;
2286 if (!bufmgr_gem->aub_file)
2289 /* If batch buffer is not annotated, annotate it the best we
2292 batch_buffer_needs_annotations = bo_gem->aub_annotation_count == 0;
2293 if (batch_buffer_needs_annotations) {
2294 drm_intel_aub_annotation annotations[2] = {
2295 { AUB_TRACE_TYPE_BATCH, 0, used },
2296 { AUB_TRACE_TYPE_NOTYPE, 0, bo->size }
2298 drm_intel_bufmgr_gem_set_aub_annotations(bo, annotations, 2);
2301 /* Write out all buffers to AUB memory */
2302 for (i = 0; i < bufmgr_gem->exec_count; i++) {
2303 aub_write_bo(bufmgr_gem->exec_bos[i]);
2306 /* Remove any annotations we added */
2307 if (batch_buffer_needs_annotations)
2308 drm_intel_bufmgr_gem_set_aub_annotations(bo, NULL, 0);
2310 /* Dump ring buffer */
2311 aub_build_dump_ringbuffer(bufmgr_gem, bo_gem->aub_offset, ring_flag);
2313 fflush(bufmgr_gem->aub_file);
2316 * One frame has been dumped. So reset the aub_offset for the next frame.
2318 * FIXME: Can we do this?
2320 bufmgr_gem->aub_offset = 0x10000;
2324 drm_intel_gem_bo_exec(drm_intel_bo *bo, int used,
2325 drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
2327 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2328 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2329 struct drm_i915_gem_execbuffer execbuf;
2332 if (bo_gem->has_error)
2335 pthread_mutex_lock(&bufmgr_gem->lock);
2336 /* Update indices and set up the validate list. */
2337 drm_intel_gem_bo_process_reloc(bo);
2339 /* Add the batch buffer to the validation list. There are no
2340 * relocations pointing to it.
2342 drm_intel_add_validate_buffer(bo);
2345 execbuf.buffers_ptr = (uintptr_t) bufmgr_gem->exec_objects;
2346 execbuf.buffer_count = bufmgr_gem->exec_count;
2347 execbuf.batch_start_offset = 0;
2348 execbuf.batch_len = used;
2349 execbuf.cliprects_ptr = (uintptr_t) cliprects;
2350 execbuf.num_cliprects = num_cliprects;
2354 ret = drmIoctl(bufmgr_gem->fd,
2355 DRM_IOCTL_I915_GEM_EXECBUFFER,
2359 if (errno == ENOSPC) {
2360 DBG("Execbuffer fails to pin. "
2361 "Estimate: %u. Actual: %u. Available: %u\n",
2362 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
2365 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
2368 (unsigned int)bufmgr_gem->gtt_size);
2371 drm_intel_update_buffer_offsets(bufmgr_gem);
2373 if (bufmgr_gem->bufmgr.debug)
2374 drm_intel_gem_dump_validation_list(bufmgr_gem);
2376 for (i = 0; i < bufmgr_gem->exec_count; i++) {
2377 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
2378 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2380 bo_gem->idle = false;
2382 /* Disconnect the buffer from the validate list */
2383 bo_gem->validate_index = -1;
2384 bufmgr_gem->exec_bos[i] = NULL;
2386 bufmgr_gem->exec_count = 0;
2387 pthread_mutex_unlock(&bufmgr_gem->lock);
2393 do_exec2(drm_intel_bo *bo, int used, drm_intel_context *ctx,
2394 drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
2397 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
2398 struct drm_i915_gem_execbuffer2 execbuf;
2402 switch (flags & 0x7) {
2406 if (!bufmgr_gem->has_blt)
2410 if (!bufmgr_gem->has_bsd)
2413 case I915_EXEC_VEBOX:
2414 if (!bufmgr_gem->has_vebox)
2417 case I915_EXEC_RENDER:
2418 case I915_EXEC_DEFAULT:
2422 pthread_mutex_lock(&bufmgr_gem->lock);
2423 /* Update indices and set up the validate list. */
2424 drm_intel_gem_bo_process_reloc2(bo);
2426 /* Add the batch buffer to the validation list. There are no relocations
2429 drm_intel_add_validate_buffer2(bo, 0);
2432 execbuf.buffers_ptr = (uintptr_t)bufmgr_gem->exec2_objects;
2433 execbuf.buffer_count = bufmgr_gem->exec_count;
2434 execbuf.batch_start_offset = 0;
2435 execbuf.batch_len = used;
2436 execbuf.cliprects_ptr = (uintptr_t)cliprects;
2437 execbuf.num_cliprects = num_cliprects;
2440 execbuf.flags = flags;
2442 i915_execbuffer2_set_context_id(execbuf, 0);
2444 i915_execbuffer2_set_context_id(execbuf, ctx->ctx_id);
2447 aub_exec(bo, flags, used);
2449 if (bufmgr_gem->no_exec)
2450 goto skip_execution;
2452 ret = drmIoctl(bufmgr_gem->fd,
2453 DRM_IOCTL_I915_GEM_EXECBUFFER2,
2457 if (ret == -ENOSPC) {
2458 DBG("Execbuffer fails to pin. "
2459 "Estimate: %u. Actual: %u. Available: %u\n",
2460 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
2461 bufmgr_gem->exec_count),
2462 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
2463 bufmgr_gem->exec_count),
2464 (unsigned int) bufmgr_gem->gtt_size);
2467 drm_intel_update_buffer_offsets2(bufmgr_gem);
2470 if (bufmgr_gem->bufmgr.debug)
2471 drm_intel_gem_dump_validation_list(bufmgr_gem);
2473 for (i = 0; i < bufmgr_gem->exec_count; i++) {
2474 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
2475 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
2477 bo_gem->idle = false;
2479 /* Disconnect the buffer from the validate list */
2480 bo_gem->validate_index = -1;
2481 bufmgr_gem->exec_bos[i] = NULL;
2483 bufmgr_gem->exec_count = 0;
2484 pthread_mutex_unlock(&bufmgr_gem->lock);
2490 drm_intel_gem_bo_exec2(drm_intel_bo *bo, int used,
2491 drm_clip_rect_t *cliprects, int num_cliprects,
2494 return do_exec2(bo, used, NULL, cliprects, num_cliprects, DR4,
2499 drm_intel_gem_bo_mrb_exec2(drm_intel_bo *bo, int used,
2500 drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
2503 return do_exec2(bo, used, NULL, cliprects, num_cliprects, DR4,
2508 drm_intel_gem_bo_context_exec(drm_intel_bo *bo, drm_intel_context *ctx,
2509 int used, unsigned int flags)
2511 return do_exec2(bo, used, ctx, NULL, 0, 0, flags);
2515 drm_intel_gem_bo_pin(drm_intel_bo *bo, uint32_t alignment)
2517 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2518 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2519 struct drm_i915_gem_pin pin;
2523 pin.handle = bo_gem->gem_handle;
2524 pin.alignment = alignment;
2526 ret = drmIoctl(bufmgr_gem->fd,
2527 DRM_IOCTL_I915_GEM_PIN,
2532 bo->offset64 = pin.offset;
2533 bo->offset = pin.offset;
2538 drm_intel_gem_bo_unpin(drm_intel_bo *bo)
2540 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2541 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2542 struct drm_i915_gem_unpin unpin;
2546 unpin.handle = bo_gem->gem_handle;
2548 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_UNPIN, &unpin);
2556 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
2557 uint32_t tiling_mode,
2560 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2561 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2562 struct drm_i915_gem_set_tiling set_tiling;
2565 if (bo_gem->global_name == 0 &&
2566 tiling_mode == bo_gem->tiling_mode &&
2567 stride == bo_gem->stride)
2570 memset(&set_tiling, 0, sizeof(set_tiling));
2572 /* set_tiling is slightly broken and overwrites the
2573 * input on the error path, so we have to open code
2576 set_tiling.handle = bo_gem->gem_handle;
2577 set_tiling.tiling_mode = tiling_mode;
2578 set_tiling.stride = stride;
2580 ret = ioctl(bufmgr_gem->fd,
2581 DRM_IOCTL_I915_GEM_SET_TILING,
2583 } while (ret == -1 && (errno == EINTR || errno == EAGAIN));
2587 bo_gem->tiling_mode = set_tiling.tiling_mode;
2588 bo_gem->swizzle_mode = set_tiling.swizzle_mode;
2589 bo_gem->stride = set_tiling.stride;
2594 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
2597 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2598 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2601 /* Tiling with userptr surfaces is not supported
2602 * on all hardware so refuse it for time being.
2604 if (bo_gem->is_userptr)
2607 /* Linear buffers have no stride. By ensuring that we only ever use
2608 * stride 0 with linear buffers, we simplify our code.
2610 if (*tiling_mode == I915_TILING_NONE)
2613 ret = drm_intel_gem_bo_set_tiling_internal(bo, *tiling_mode, stride);
2615 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
2617 *tiling_mode = bo_gem->tiling_mode;
2622 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
2623 uint32_t * swizzle_mode)
2625 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2627 *tiling_mode = bo_gem->tiling_mode;
2628 *swizzle_mode = bo_gem->swizzle_mode;
2632 drm_public drm_intel_bo *
2633 drm_intel_bo_gem_create_from_prime(drm_intel_bufmgr *bufmgr, int prime_fd, int size)
2635 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
2638 drm_intel_bo_gem *bo_gem;
2639 struct drm_i915_gem_get_tiling get_tiling;
2640 drmMMListHead *list;
2642 ret = drmPrimeFDToHandle(bufmgr_gem->fd, prime_fd, &handle);
2645 * See if the kernel has already returned this buffer to us. Just as
2646 * for named buffers, we must not create two bo's pointing at the same
2649 pthread_mutex_lock(&bufmgr_gem->lock);
2650 for (list = bufmgr_gem->named.next;
2651 list != &bufmgr_gem->named;
2652 list = list->next) {
2653 bo_gem = DRMLISTENTRY(drm_intel_bo_gem, list, name_list);
2654 if (bo_gem->gem_handle == handle) {
2655 drm_intel_gem_bo_reference(&bo_gem->bo);
2656 pthread_mutex_unlock(&bufmgr_gem->lock);
2662 fprintf(stderr,"ret is %d %d\n", ret, errno);
2663 pthread_mutex_unlock(&bufmgr_gem->lock);
2667 bo_gem = calloc(1, sizeof(*bo_gem));
2669 pthread_mutex_unlock(&bufmgr_gem->lock);
2672 /* Determine size of bo. The fd-to-handle ioctl really should
2673 * return the size, but it doesn't. If we have kernel 3.12 or
2674 * later, we can lseek on the prime fd to get the size. Older
2675 * kernels will just fail, in which case we fall back to the
2676 * provided (estimated or guess size). */
2677 ret = lseek(prime_fd, 0, SEEK_END);
2679 bo_gem->bo.size = ret;
2681 bo_gem->bo.size = size;
2683 bo_gem->bo.handle = handle;
2684 bo_gem->bo.bufmgr = bufmgr;
2686 bo_gem->gem_handle = handle;
2688 atomic_set(&bo_gem->refcount, 1);
2690 bo_gem->name = "prime";
2691 bo_gem->validate_index = -1;
2692 bo_gem->reloc_tree_fences = 0;
2693 bo_gem->used_as_reloc_target = false;
2694 bo_gem->has_error = false;
2695 bo_gem->reusable = false;
2697 DRMINITLISTHEAD(&bo_gem->vma_list);
2698 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
2699 pthread_mutex_unlock(&bufmgr_gem->lock);
2701 memclear(get_tiling);
2702 get_tiling.handle = bo_gem->gem_handle;
2703 ret = drmIoctl(bufmgr_gem->fd,
2704 DRM_IOCTL_I915_GEM_GET_TILING,
2707 drm_intel_gem_bo_unreference(&bo_gem->bo);
2710 bo_gem->tiling_mode = get_tiling.tiling_mode;
2711 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
2712 /* XXX stride is unknown */
2713 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
2719 drm_intel_bo_gem_export_to_prime(drm_intel_bo *bo, int *prime_fd)
2721 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2722 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2724 pthread_mutex_lock(&bufmgr_gem->lock);
2725 if (DRMLISTEMPTY(&bo_gem->name_list))
2726 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
2727 pthread_mutex_unlock(&bufmgr_gem->lock);
2729 if (drmPrimeHandleToFD(bufmgr_gem->fd, bo_gem->gem_handle,
2730 DRM_CLOEXEC, prime_fd) != 0)
2733 bo_gem->reusable = false;
2739 drm_intel_gem_bo_flink(drm_intel_bo *bo, uint32_t * name)
2741 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2742 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2745 if (!bo_gem->global_name) {
2746 struct drm_gem_flink flink;
2749 flink.handle = bo_gem->gem_handle;
2751 pthread_mutex_lock(&bufmgr_gem->lock);
2753 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_FLINK, &flink);
2755 pthread_mutex_unlock(&bufmgr_gem->lock);
2759 bo_gem->global_name = flink.name;
2760 bo_gem->reusable = false;
2762 if (DRMLISTEMPTY(&bo_gem->name_list))
2763 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
2764 pthread_mutex_unlock(&bufmgr_gem->lock);
2767 *name = bo_gem->global_name;
2772 * Enables unlimited caching of buffer objects for reuse.
2774 * This is potentially very memory expensive, as the cache at each bucket
2775 * size is only bounded by how many buffers of that size we've managed to have
2776 * in flight at once.
2779 drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr)
2781 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
2783 bufmgr_gem->bo_reuse = true;
2787 * Enable use of fenced reloc type.
2789 * New code should enable this to avoid unnecessary fence register
2790 * allocation. If this option is not enabled, all relocs will have fence
2791 * register allocated.
2794 drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr)
2796 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
2798 if (bufmgr_gem->bufmgr.bo_exec == drm_intel_gem_bo_exec2)
2799 bufmgr_gem->fenced_relocs = true;
2803 * Return the additional aperture space required by the tree of buffer objects
2807 drm_intel_gem_bo_get_aperture_space(drm_intel_bo *bo)
2809 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2813 if (bo == NULL || bo_gem->included_in_check_aperture)
2817 bo_gem->included_in_check_aperture = true;
2819 for (i = 0; i < bo_gem->reloc_count; i++)
2821 drm_intel_gem_bo_get_aperture_space(bo_gem->
2822 reloc_target_info[i].bo);
2828 * Count the number of buffers in this list that need a fence reg
2830 * If the count is greater than the number of available regs, we'll have
2831 * to ask the caller to resubmit a batch with fewer tiled buffers.
2833 * This function over-counts if the same buffer is used multiple times.
2836 drm_intel_gem_total_fences(drm_intel_bo ** bo_array, int count)
2839 unsigned int total = 0;
2841 for (i = 0; i < count; i++) {
2842 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
2847 total += bo_gem->reloc_tree_fences;
2853 * Clear the flag set by drm_intel_gem_bo_get_aperture_space() so we're ready
2854 * for the next drm_intel_bufmgr_check_aperture_space() call.
2857 drm_intel_gem_bo_clear_aperture_space_flag(drm_intel_bo *bo)
2859 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2862 if (bo == NULL || !bo_gem->included_in_check_aperture)
2865 bo_gem->included_in_check_aperture = false;
2867 for (i = 0; i < bo_gem->reloc_count; i++)
2868 drm_intel_gem_bo_clear_aperture_space_flag(bo_gem->
2869 reloc_target_info[i].bo);
2873 * Return a conservative estimate for the amount of aperture required
2874 * for a collection of buffers. This may double-count some buffers.
2877 drm_intel_gem_estimate_batch_space(drm_intel_bo **bo_array, int count)
2880 unsigned int total = 0;
2882 for (i = 0; i < count; i++) {
2883 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
2885 total += bo_gem->reloc_tree_size;
2891 * Return the amount of aperture needed for a collection of buffers.
2892 * This avoids double counting any buffers, at the cost of looking
2893 * at every buffer in the set.
2896 drm_intel_gem_compute_batch_space(drm_intel_bo **bo_array, int count)
2899 unsigned int total = 0;
2901 for (i = 0; i < count; i++) {
2902 total += drm_intel_gem_bo_get_aperture_space(bo_array[i]);
2903 /* For the first buffer object in the array, we get an
2904 * accurate count back for its reloc_tree size (since nothing
2905 * had been flagged as being counted yet). We can save that
2906 * value out as a more conservative reloc_tree_size that
2907 * avoids double-counting target buffers. Since the first
2908 * buffer happens to usually be the batch buffer in our
2909 * callers, this can pull us back from doing the tree
2910 * walk on every new batch emit.
2913 drm_intel_bo_gem *bo_gem =
2914 (drm_intel_bo_gem *) bo_array[i];
2915 bo_gem->reloc_tree_size = total;
2919 for (i = 0; i < count; i++)
2920 drm_intel_gem_bo_clear_aperture_space_flag(bo_array[i]);
2925 * Return -1 if the batchbuffer should be flushed before attempting to
2926 * emit rendering referencing the buffers pointed to by bo_array.
2928 * This is required because if we try to emit a batchbuffer with relocations
2929 * to a tree of buffers that won't simultaneously fit in the aperture,
2930 * the rendering will return an error at a point where the software is not
2931 * prepared to recover from it.
2933 * However, we also want to emit the batchbuffer significantly before we reach
2934 * the limit, as a series of batchbuffers each of which references buffers
2935 * covering almost all of the aperture means that at each emit we end up
2936 * waiting to evict a buffer from the last rendering, and we get synchronous
2937 * performance. By emitting smaller batchbuffers, we eat some CPU overhead to
2938 * get better parallelism.
2941 drm_intel_gem_check_aperture_space(drm_intel_bo **bo_array, int count)
2943 drm_intel_bufmgr_gem *bufmgr_gem =
2944 (drm_intel_bufmgr_gem *) bo_array[0]->bufmgr;
2945 unsigned int total = 0;
2946 unsigned int threshold = bufmgr_gem->gtt_size * 3 / 4;
2949 /* Check for fence reg constraints if necessary */
2950 if (bufmgr_gem->available_fences) {
2951 total_fences = drm_intel_gem_total_fences(bo_array, count);
2952 if (total_fences > bufmgr_gem->available_fences)
2956 total = drm_intel_gem_estimate_batch_space(bo_array, count);
2958 if (total > threshold)
2959 total = drm_intel_gem_compute_batch_space(bo_array, count);
2961 if (total > threshold) {
2962 DBG("check_space: overflowed available aperture, "
2964 total / 1024, (int)bufmgr_gem->gtt_size / 1024);
2967 DBG("drm_check_space: total %dkb vs bufgr %dkb\n", total / 1024,
2968 (int)bufmgr_gem->gtt_size / 1024);
2974 * Disable buffer reuse for objects which are shared with the kernel
2975 * as scanout buffers
2978 drm_intel_gem_bo_disable_reuse(drm_intel_bo *bo)
2980 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2982 bo_gem->reusable = false;
2987 drm_intel_gem_bo_is_reusable(drm_intel_bo *bo)
2989 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2991 return bo_gem->reusable;
2995 _drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
2997 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
3000 for (i = 0; i < bo_gem->reloc_count; i++) {
3001 if (bo_gem->reloc_target_info[i].bo == target_bo)
3003 if (bo == bo_gem->reloc_target_info[i].bo)
3005 if (_drm_intel_gem_bo_references(bo_gem->reloc_target_info[i].bo,
3013 /** Return true if target_bo is referenced by bo's relocation tree. */
3015 drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
3017 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
3019 if (bo == NULL || target_bo == NULL)
3021 if (target_bo_gem->used_as_reloc_target)
3022 return _drm_intel_gem_bo_references(bo, target_bo);
3027 add_bucket(drm_intel_bufmgr_gem *bufmgr_gem, int size)
3029 unsigned int i = bufmgr_gem->num_buckets;
3031 assert(i < ARRAY_SIZE(bufmgr_gem->cache_bucket));
3033 DRMINITLISTHEAD(&bufmgr_gem->cache_bucket[i].head);
3034 bufmgr_gem->cache_bucket[i].size = size;
3035 bufmgr_gem->num_buckets++;
3039 init_cache_buckets(drm_intel_bufmgr_gem *bufmgr_gem)
3041 unsigned long size, cache_max_size = 64 * 1024 * 1024;
3043 /* OK, so power of two buckets was too wasteful of memory.
3044 * Give 3 other sizes between each power of two, to hopefully
3045 * cover things accurately enough. (The alternative is
3046 * probably to just go for exact matching of sizes, and assume
3047 * that for things like composited window resize the tiled
3048 * width/height alignment and rounding of sizes to pages will
3049 * get us useful cache hit rates anyway)
3051 add_bucket(bufmgr_gem, 4096);
3052 add_bucket(bufmgr_gem, 4096 * 2);
3053 add_bucket(bufmgr_gem, 4096 * 3);
3055 /* Initialize the linked lists for BO reuse cache. */
3056 for (size = 4 * 4096; size <= cache_max_size; size *= 2) {
3057 add_bucket(bufmgr_gem, size);
3059 add_bucket(bufmgr_gem, size + size * 1 / 4);
3060 add_bucket(bufmgr_gem, size + size * 2 / 4);
3061 add_bucket(bufmgr_gem, size + size * 3 / 4);
3066 drm_intel_bufmgr_gem_set_vma_cache_size(drm_intel_bufmgr *bufmgr, int limit)
3068 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
3070 bufmgr_gem->vma_max = limit;
3072 drm_intel_gem_bo_purge_vma_cache(bufmgr_gem);
3076 * Get the PCI ID for the device. This can be overridden by setting the
3077 * INTEL_DEVID_OVERRIDE environment variable to the desired ID.
3080 get_pci_device_id(drm_intel_bufmgr_gem *bufmgr_gem)
3082 char *devid_override;
3085 drm_i915_getparam_t gp;
3087 if (geteuid() == getuid()) {
3088 devid_override = getenv("INTEL_DEVID_OVERRIDE");
3089 if (devid_override) {
3090 bufmgr_gem->no_exec = true;
3091 return strtod(devid_override, NULL);
3096 gp.param = I915_PARAM_CHIPSET_ID;
3098 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3100 fprintf(stderr, "get chip id failed: %d [%d]\n", ret, errno);
3101 fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value);
3107 drm_intel_bufmgr_gem_get_devid(drm_intel_bufmgr *bufmgr)
3109 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
3111 return bufmgr_gem->pci_device;
3115 * Sets the AUB filename.
3117 * This function has to be called before drm_intel_bufmgr_gem_set_aub_dump()
3118 * for it to have any effect.
3121 drm_intel_bufmgr_gem_set_aub_filename(drm_intel_bufmgr *bufmgr,
3122 const char *filename)
3124 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
3126 free(bufmgr_gem->aub_filename);
3128 bufmgr_gem->aub_filename = strdup(filename);
3132 * Sets up AUB dumping.
3134 * This is a trace file format that can be used with the simulator.
3135 * Packets are emitted in a format somewhat like GPU command packets.
3136 * You can set up a GTT and upload your objects into the referenced
3137 * space, then send off batchbuffers and get BMPs out the other end.
3140 drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable)
3142 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
3143 int entry = 0x200003;
3145 int gtt_size = 0x10000;
3146 const char *filename;
3149 if (bufmgr_gem->aub_file) {
3150 fclose(bufmgr_gem->aub_file);
3151 bufmgr_gem->aub_file = NULL;
3156 if (geteuid() != getuid())
3159 if (bufmgr_gem->aub_filename)
3160 filename = bufmgr_gem->aub_filename;
3162 filename = "intel.aub";
3163 bufmgr_gem->aub_file = fopen(filename, "w+");
3164 if (!bufmgr_gem->aub_file)
3167 /* Start allocating objects from just after the GTT. */
3168 bufmgr_gem->aub_offset = gtt_size;
3170 /* Start with a (required) version packet. */
3171 aub_out(bufmgr_gem, CMD_AUB_HEADER | (13 - 2));
3173 (4 << AUB_HEADER_MAJOR_SHIFT) |
3174 (0 << AUB_HEADER_MINOR_SHIFT));
3175 for (i = 0; i < 8; i++) {
3176 aub_out(bufmgr_gem, 0); /* app name */
3178 aub_out(bufmgr_gem, 0); /* timestamp */
3179 aub_out(bufmgr_gem, 0); /* timestamp */
3180 aub_out(bufmgr_gem, 0); /* comment len */
3182 /* Set up the GTT. The max we can handle is 256M */
3183 aub_out(bufmgr_gem, CMD_AUB_TRACE_HEADER_BLOCK | ((bufmgr_gem->gen >= 8 ? 6 : 5) - 2));
3184 /* Need to use GTT_ENTRY type for recent emulator */
3185 aub_out(bufmgr_gem, AUB_TRACE_MEMTYPE_GTT_ENTRY | 0 | AUB_TRACE_OP_DATA_WRITE);
3186 aub_out(bufmgr_gem, 0); /* subtype */
3187 aub_out(bufmgr_gem, 0); /* offset */
3188 aub_out(bufmgr_gem, gtt_size); /* size */
3189 if (bufmgr_gem->gen >= 8)
3190 aub_out(bufmgr_gem, 0);
3191 for (i = 0x000; i < gtt_size; i += 4, entry += 0x1000) {
3192 aub_out(bufmgr_gem, entry);
3196 drm_public drm_intel_context *
3197 drm_intel_gem_context_create(drm_intel_bufmgr *bufmgr)
3199 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
3200 struct drm_i915_gem_context_create create;
3201 drm_intel_context *context = NULL;
3204 context = calloc(1, sizeof(*context));
3209 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_CONTEXT_CREATE, &create);
3211 DBG("DRM_IOCTL_I915_GEM_CONTEXT_CREATE failed: %s\n",
3217 context->ctx_id = create.ctx_id;
3218 context->bufmgr = bufmgr;
3224 drm_intel_gem_context_destroy(drm_intel_context *ctx)
3226 drm_intel_bufmgr_gem *bufmgr_gem;
3227 struct drm_i915_gem_context_destroy destroy;
3235 bufmgr_gem = (drm_intel_bufmgr_gem *)ctx->bufmgr;
3236 destroy.ctx_id = ctx->ctx_id;
3237 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_CONTEXT_DESTROY,
3240 fprintf(stderr, "DRM_IOCTL_I915_GEM_CONTEXT_DESTROY failed: %s\n",
3247 drm_intel_get_reset_stats(drm_intel_context *ctx,
3248 uint32_t *reset_count,
3252 drm_intel_bufmgr_gem *bufmgr_gem;
3253 struct drm_i915_reset_stats stats;
3261 bufmgr_gem = (drm_intel_bufmgr_gem *)ctx->bufmgr;
3262 stats.ctx_id = ctx->ctx_id;
3263 ret = drmIoctl(bufmgr_gem->fd,
3264 DRM_IOCTL_I915_GET_RESET_STATS,
3267 if (reset_count != NULL)
3268 *reset_count = stats.reset_count;
3271 *active = stats.batch_active;
3273 if (pending != NULL)
3274 *pending = stats.batch_pending;
3281 drm_intel_reg_read(drm_intel_bufmgr *bufmgr,
3285 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
3286 struct drm_i915_reg_read reg_read;
3290 reg_read.offset = offset;
3292 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_REG_READ, ®_read);
3294 *result = reg_read.val;
3299 drm_intel_get_subslice_total(int fd, unsigned int *subslice_total)
3301 drm_i915_getparam_t gp;
3305 gp.value = (int*)subslice_total;
3306 gp.param = I915_PARAM_SUBSLICE_TOTAL;
3307 ret = drmIoctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
3315 drm_intel_get_eu_total(int fd, unsigned int *eu_total)
3317 drm_i915_getparam_t gp;
3321 gp.value = (int*)eu_total;
3322 gp.param = I915_PARAM_EU_TOTAL;
3323 ret = drmIoctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
3331 * Annotate the given bo for use in aub dumping.
3333 * \param annotations is an array of drm_intel_aub_annotation objects
3334 * describing the type of data in various sections of the bo. Each
3335 * element of the array specifies the type and subtype of a section of
3336 * the bo, and the past-the-end offset of that section. The elements
3337 * of \c annotations must be sorted so that ending_offset is
3340 * \param count is the number of elements in the \c annotations array.
3341 * If \c count is zero, then \c annotations will not be dereferenced.
3343 * Annotations are copied into a private data structure, so caller may
3344 * re-use the memory pointed to by \c annotations after the call
3347 * Annotations are stored for the lifetime of the bo; to reset to the
3348 * default state (no annotations), call this function with a \c count
3352 drm_intel_bufmgr_gem_set_aub_annotations(drm_intel_bo *bo,
3353 drm_intel_aub_annotation *annotations,
3356 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
3357 unsigned size = sizeof(*annotations) * count;
3358 drm_intel_aub_annotation *new_annotations =
3359 count > 0 ? realloc(bo_gem->aub_annotations, size) : NULL;
3360 if (new_annotations == NULL) {
3361 free(bo_gem->aub_annotations);
3362 bo_gem->aub_annotations = NULL;
3363 bo_gem->aub_annotation_count = 0;
3366 memcpy(new_annotations, annotations, size);
3367 bo_gem->aub_annotations = new_annotations;
3368 bo_gem->aub_annotation_count = count;
3371 static pthread_mutex_t bufmgr_list_mutex = PTHREAD_MUTEX_INITIALIZER;
3372 static drmMMListHead bufmgr_list = { &bufmgr_list, &bufmgr_list };
3374 static drm_intel_bufmgr_gem *
3375 drm_intel_bufmgr_gem_find(int fd)
3377 drm_intel_bufmgr_gem *bufmgr_gem;
3379 DRMLISTFOREACHENTRY(bufmgr_gem, &bufmgr_list, managers) {
3380 if (bufmgr_gem->fd == fd) {
3381 atomic_inc(&bufmgr_gem->refcount);
3390 drm_intel_bufmgr_gem_unref(drm_intel_bufmgr *bufmgr)
3392 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
3394 if (atomic_add_unless(&bufmgr_gem->refcount, -1, 1)) {
3395 pthread_mutex_lock(&bufmgr_list_mutex);
3397 if (atomic_dec_and_test(&bufmgr_gem->refcount)) {
3398 DRMLISTDEL(&bufmgr_gem->managers);
3399 drm_intel_bufmgr_gem_destroy(bufmgr);
3402 pthread_mutex_unlock(&bufmgr_list_mutex);
3407 has_userptr(drm_intel_bufmgr_gem *bufmgr_gem)
3412 struct drm_i915_gem_userptr userptr;
3413 struct drm_gem_close close_bo;
3415 pgsz = sysconf(_SC_PAGESIZE);
3418 ret = posix_memalign(&ptr, pgsz, pgsz);
3420 DBG("Failed to get a page (%ld) for userptr detection!\n",
3426 userptr.user_ptr = (__u64)(unsigned long)ptr;
3427 userptr.user_size = pgsz;
3430 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_USERPTR, &userptr);
3432 if (errno == ENODEV && userptr.flags == 0) {
3433 userptr.flags = I915_USERPTR_UNSYNCHRONIZED;
3441 close_bo.handle = userptr.handle;
3442 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close_bo);
3445 fprintf(stderr, "Failed to release test userptr object! (%d) "
3446 "i915 kernel driver may not be sane!\n", errno);
3454 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
3455 * and manage map buffer objections.
3457 * \param fd File descriptor of the opened DRM device.
3459 drm_public drm_intel_bufmgr *
3460 drm_intel_bufmgr_gem_init(int fd, int batch_size)
3462 drm_intel_bufmgr_gem *bufmgr_gem;
3463 struct drm_i915_gem_get_aperture aperture;
3464 drm_i915_getparam_t gp;
3468 pthread_mutex_lock(&bufmgr_list_mutex);
3470 bufmgr_gem = drm_intel_bufmgr_gem_find(fd);
3474 bufmgr_gem = calloc(1, sizeof(*bufmgr_gem));
3475 if (bufmgr_gem == NULL)
3478 bufmgr_gem->fd = fd;
3479 atomic_set(&bufmgr_gem->refcount, 1);
3481 if (pthread_mutex_init(&bufmgr_gem->lock, NULL) != 0) {
3488 ret = drmIoctl(bufmgr_gem->fd,
3489 DRM_IOCTL_I915_GEM_GET_APERTURE,
3493 bufmgr_gem->gtt_size = aperture.aper_available_size;
3495 fprintf(stderr, "DRM_IOCTL_I915_GEM_APERTURE failed: %s\n",
3497 bufmgr_gem->gtt_size = 128 * 1024 * 1024;
3498 fprintf(stderr, "Assuming %dkB available aperture size.\n"
3499 "May lead to reduced performance or incorrect "
3501 (int)bufmgr_gem->gtt_size / 1024);
3504 bufmgr_gem->pci_device = get_pci_device_id(bufmgr_gem);
3506 if (IS_GEN2(bufmgr_gem->pci_device))
3507 bufmgr_gem->gen = 2;
3508 else if (IS_GEN3(bufmgr_gem->pci_device))
3509 bufmgr_gem->gen = 3;
3510 else if (IS_GEN4(bufmgr_gem->pci_device))
3511 bufmgr_gem->gen = 4;
3512 else if (IS_GEN5(bufmgr_gem->pci_device))
3513 bufmgr_gem->gen = 5;
3514 else if (IS_GEN6(bufmgr_gem->pci_device))
3515 bufmgr_gem->gen = 6;
3516 else if (IS_GEN7(bufmgr_gem->pci_device))
3517 bufmgr_gem->gen = 7;
3518 else if (IS_GEN8(bufmgr_gem->pci_device))
3519 bufmgr_gem->gen = 8;
3520 else if (IS_GEN9(bufmgr_gem->pci_device))
3521 bufmgr_gem->gen = 9;
3528 if (IS_GEN3(bufmgr_gem->pci_device) &&
3529 bufmgr_gem->gtt_size > 256*1024*1024) {
3530 /* The unmappable part of gtt on gen 3 (i.e. above 256MB) can't
3531 * be used for tiled blits. To simplify the accounting, just
3532 * substract the unmappable part (fixed to 256MB on all known
3533 * gen3 devices) if the kernel advertises it. */
3534 bufmgr_gem->gtt_size -= 256*1024*1024;
3540 gp.param = I915_PARAM_HAS_EXECBUF2;
3541 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3545 gp.param = I915_PARAM_HAS_BSD;
3546 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3547 bufmgr_gem->has_bsd = ret == 0;
3549 gp.param = I915_PARAM_HAS_BLT;
3550 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3551 bufmgr_gem->has_blt = ret == 0;
3553 gp.param = I915_PARAM_HAS_RELAXED_FENCING;
3554 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3555 bufmgr_gem->has_relaxed_fencing = ret == 0;
3557 if (has_userptr(bufmgr_gem))
3558 bufmgr_gem->bufmgr.bo_alloc_userptr =
3559 drm_intel_gem_bo_alloc_userptr;
3561 gp.param = I915_PARAM_HAS_WAIT_TIMEOUT;
3562 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3563 bufmgr_gem->has_wait_timeout = ret == 0;
3565 gp.param = I915_PARAM_HAS_LLC;
3566 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3568 /* Kernel does not supports HAS_LLC query, fallback to GPU
3569 * generation detection and assume that we have LLC on GEN6/7
3571 bufmgr_gem->has_llc = (IS_GEN6(bufmgr_gem->pci_device) |
3572 IS_GEN7(bufmgr_gem->pci_device));
3574 bufmgr_gem->has_llc = *gp.value;
3576 gp.param = I915_PARAM_HAS_VEBOX;
3577 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3578 bufmgr_gem->has_vebox = (ret == 0) & (*gp.value > 0);
3580 if (bufmgr_gem->gen < 4) {
3581 gp.param = I915_PARAM_NUM_FENCES_AVAIL;
3582 gp.value = &bufmgr_gem->available_fences;
3583 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3585 fprintf(stderr, "get fences failed: %d [%d]\n", ret,
3587 fprintf(stderr, "param: %d, val: %d\n", gp.param,
3589 bufmgr_gem->available_fences = 0;
3591 /* XXX The kernel reports the total number of fences,
3592 * including any that may be pinned.
3594 * We presume that there will be at least one pinned
3595 * fence for the scanout buffer, but there may be more
3596 * than one scanout and the user may be manually
3597 * pinning buffers. Let's move to execbuffer2 and
3598 * thereby forget the insanity of using fences...
3600 bufmgr_gem->available_fences -= 2;
3601 if (bufmgr_gem->available_fences < 0)
3602 bufmgr_gem->available_fences = 0;
3606 /* Let's go with one relocation per every 2 dwords (but round down a bit
3607 * since a power of two will mean an extra page allocation for the reloc
3610 * Every 4 was too few for the blender benchmark.
3612 bufmgr_gem->max_relocs = batch_size / sizeof(uint32_t) / 2 - 2;
3614 bufmgr_gem->bufmgr.bo_alloc = drm_intel_gem_bo_alloc;
3615 bufmgr_gem->bufmgr.bo_alloc_for_render =
3616 drm_intel_gem_bo_alloc_for_render;
3617 bufmgr_gem->bufmgr.bo_alloc_tiled = drm_intel_gem_bo_alloc_tiled;
3618 bufmgr_gem->bufmgr.bo_reference = drm_intel_gem_bo_reference;
3619 bufmgr_gem->bufmgr.bo_unreference = drm_intel_gem_bo_unreference;
3620 bufmgr_gem->bufmgr.bo_map = drm_intel_gem_bo_map;
3621 bufmgr_gem->bufmgr.bo_unmap = drm_intel_gem_bo_unmap;
3622 bufmgr_gem->bufmgr.bo_subdata = drm_intel_gem_bo_subdata;
3623 bufmgr_gem->bufmgr.bo_get_subdata = drm_intel_gem_bo_get_subdata;
3624 bufmgr_gem->bufmgr.bo_wait_rendering = drm_intel_gem_bo_wait_rendering;
3625 bufmgr_gem->bufmgr.bo_emit_reloc = drm_intel_gem_bo_emit_reloc;
3626 bufmgr_gem->bufmgr.bo_emit_reloc_fence = drm_intel_gem_bo_emit_reloc_fence;
3627 bufmgr_gem->bufmgr.bo_pin = drm_intel_gem_bo_pin;
3628 bufmgr_gem->bufmgr.bo_unpin = drm_intel_gem_bo_unpin;
3629 bufmgr_gem->bufmgr.bo_get_tiling = drm_intel_gem_bo_get_tiling;
3630 bufmgr_gem->bufmgr.bo_set_tiling = drm_intel_gem_bo_set_tiling;
3631 bufmgr_gem->bufmgr.bo_flink = drm_intel_gem_bo_flink;
3632 /* Use the new one if available */
3634 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec2;
3635 bufmgr_gem->bufmgr.bo_mrb_exec = drm_intel_gem_bo_mrb_exec2;
3637 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec;
3638 bufmgr_gem->bufmgr.bo_busy = drm_intel_gem_bo_busy;
3639 bufmgr_gem->bufmgr.bo_madvise = drm_intel_gem_bo_madvise;
3640 bufmgr_gem->bufmgr.destroy = drm_intel_bufmgr_gem_unref;
3641 bufmgr_gem->bufmgr.debug = 0;
3642 bufmgr_gem->bufmgr.check_aperture_space =
3643 drm_intel_gem_check_aperture_space;
3644 bufmgr_gem->bufmgr.bo_disable_reuse = drm_intel_gem_bo_disable_reuse;
3645 bufmgr_gem->bufmgr.bo_is_reusable = drm_intel_gem_bo_is_reusable;
3646 bufmgr_gem->bufmgr.get_pipe_from_crtc_id =
3647 drm_intel_gem_get_pipe_from_crtc_id;
3648 bufmgr_gem->bufmgr.bo_references = drm_intel_gem_bo_references;
3650 DRMINITLISTHEAD(&bufmgr_gem->named);
3651 init_cache_buckets(bufmgr_gem);
3653 DRMINITLISTHEAD(&bufmgr_gem->vma_cache);
3654 bufmgr_gem->vma_max = -1; /* unlimited by default */
3656 DRMLISTADD(&bufmgr_gem->managers, &bufmgr_list);
3659 pthread_mutex_unlock(&bufmgr_list_mutex);
3661 return bufmgr_gem != NULL ? &bufmgr_gem->bufmgr : NULL;