1 /**************************************************************************
3 * Copyright © 2007 Red Hat Inc.
4 * Copyright © 2007 Intel Corporation
5 * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
29 **************************************************************************/
31 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
32 * Keith Whitwell <keithw-at-tungstengraphics-dot-com>
33 * Eric Anholt <eric@anholt.net>
34 * Dave Airlie <airlied@linux.ie>
49 #include <sys/ioctl.h>
52 #include <sys/types.h>
55 #include "libdrm_lists.h"
56 #include "intel_atomic.h"
57 #include "intel_bufmgr.h"
58 #include "intel_bufmgr_priv.h"
59 #include "intel_chipset.h"
64 #define DBG(...) do { \
65 if (bufmgr_gem->bufmgr.debug) \
66 fprintf(stderr, __VA_ARGS__); \
69 typedef struct _drm_intel_bo_gem drm_intel_bo_gem;
71 struct drm_intel_gem_bo_bucket {
76 /* Only cache objects up to 64MB. Bigger than that, and the rounding of the
77 * size makes many operations fail that wouldn't otherwise.
79 #define DRM_INTEL_GEM_BO_BUCKETS 14
80 typedef struct _drm_intel_bufmgr_gem {
81 drm_intel_bufmgr bufmgr;
89 struct drm_i915_gem_exec_object *exec_objects;
90 drm_intel_bo **exec_bos;
94 /** Array of lists of cached gem objects of power-of-two sizes */
95 struct drm_intel_gem_bo_bucket cache_bucket[DRM_INTEL_GEM_BO_BUCKETS];
101 } drm_intel_bufmgr_gem;
103 struct _drm_intel_bo_gem {
111 * Kenel-assigned global name for this object
113 unsigned int global_name;
116 * Index of the buffer within the validation list while preparing a
117 * batchbuffer execution.
122 * Current tiling mode
124 uint32_t tiling_mode;
125 uint32_t swizzle_mode;
129 /** Array passed to the DRM containing relocation information. */
130 struct drm_i915_gem_relocation_entry *relocs;
131 /** Array of bos corresponding to relocs[i].target_handle */
132 drm_intel_bo **reloc_target_bo;
133 /** Number of entries in relocs */
135 /** Mapped address for the buffer, saved across map/unmap cycles */
137 /** GTT virtual address for the buffer, saved across map/unmap cycles */
144 * Boolean of whether this BO and its children have been included in
145 * the current drm_intel_bufmgr_check_aperture_space() total.
147 char included_in_check_aperture;
150 * Boolean of whether this buffer has been used as a relocation
151 * target and had its size accounted for, and thus can't have any
152 * further relocations added to it.
154 char used_as_reloc_target;
157 * Boolean of whether this buffer can be re-used
162 * Size in bytes of this buffer and its relocation descendents.
164 * Used to avoid costly tree walking in
165 * drm_intel_bufmgr_check_aperture in the common case.
170 * Number of potential fence registers required by this buffer and its
173 int reloc_tree_fences;
177 drm_intel_gem_estimate_batch_space(drm_intel_bo ** bo_array, int count);
180 drm_intel_gem_compute_batch_space(drm_intel_bo ** bo_array, int count);
183 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
184 uint32_t * swizzle_mode);
187 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
190 static void drm_intel_gem_bo_unreference_locked(drm_intel_bo *bo);
191 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
194 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo);
196 static void drm_intel_gem_bo_free(drm_intel_bo *bo);
199 drm_intel_gem_bo_tile_size(drm_intel_bufmgr_gem *bufmgr_gem, unsigned long size,
200 uint32_t *tiling_mode)
202 unsigned long min_size, max_size;
205 if (*tiling_mode == I915_TILING_NONE)
208 /* 965+ just need multiples of page size for tiling */
209 if (IS_I965G(bufmgr_gem))
210 return ROUND_UP_TO(size, 4096);
212 /* Older chips need powers of two, of at least 512k or 1M */
213 if (IS_I9XX(bufmgr_gem)) {
214 min_size = 1024*1024;
215 max_size = 128*1024*1024;
218 max_size = 64*1024*1024;
221 if (size > max_size) {
222 *tiling_mode = I915_TILING_NONE;
226 for (i = min_size; i < size; i <<= 1)
233 * Round a given pitch up to the minimum required for X tiling on a
234 * given chip. We use 512 as the minimum to allow for a later tiling
238 drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem,
239 unsigned long pitch, uint32_t tiling_mode)
241 unsigned long tile_width = 512;
244 if (tiling_mode == I915_TILING_NONE)
245 return ROUND_UP_TO(pitch, tile_width);
247 /* 965 is flexible */
248 if (IS_I965G(bufmgr_gem))
249 return ROUND_UP_TO(pitch, tile_width);
251 /* Pre-965 needs power of two tile width */
252 for (i = tile_width; i < pitch; i <<= 1)
258 static struct drm_intel_gem_bo_bucket *
259 drm_intel_gem_bo_bucket_for_size(drm_intel_bufmgr_gem *bufmgr_gem,
264 for (i = 0; i < DRM_INTEL_GEM_BO_BUCKETS; i++) {
265 struct drm_intel_gem_bo_bucket *bucket =
266 &bufmgr_gem->cache_bucket[i];
267 if (bucket->size >= size) {
276 drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem *bufmgr_gem)
280 for (i = 0; i < bufmgr_gem->exec_count; i++) {
281 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
282 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
284 if (bo_gem->relocs == NULL) {
285 DBG("%2d: %d (%s)\n", i, bo_gem->gem_handle,
290 for (j = 0; j < bo_gem->reloc_count; j++) {
291 drm_intel_bo *target_bo = bo_gem->reloc_target_bo[j];
292 drm_intel_bo_gem *target_gem =
293 (drm_intel_bo_gem *) target_bo;
295 DBG("%2d: %d (%s)@0x%08llx -> "
296 "%d (%s)@0x%08lx + 0x%08x\n",
298 bo_gem->gem_handle, bo_gem->name,
299 (unsigned long long)bo_gem->relocs[j].offset,
300 target_gem->gem_handle,
303 bo_gem->relocs[j].delta);
309 drm_intel_gem_bo_reference(drm_intel_bo *bo)
311 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
313 assert(atomic_read(&bo_gem->refcount) > 0);
314 atomic_inc(&bo_gem->refcount);
318 * Adds the given buffer to the list of buffers to be validated (moved into the
319 * appropriate memory type) with the next batch submission.
321 * If a buffer is validated multiple times in a batch submission, it ends up
322 * with the intersection of the memory type flags and the union of the
326 drm_intel_add_validate_buffer(drm_intel_bo *bo)
328 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
329 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
332 if (bo_gem->validate_index != -1)
335 /* Extend the array of validation entries as necessary. */
336 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
337 int new_size = bufmgr_gem->exec_size * 2;
342 bufmgr_gem->exec_objects =
343 realloc(bufmgr_gem->exec_objects,
344 sizeof(*bufmgr_gem->exec_objects) * new_size);
345 bufmgr_gem->exec_bos =
346 realloc(bufmgr_gem->exec_bos,
347 sizeof(*bufmgr_gem->exec_bos) * new_size);
348 bufmgr_gem->exec_size = new_size;
351 index = bufmgr_gem->exec_count;
352 bo_gem->validate_index = index;
353 /* Fill in array entry */
354 bufmgr_gem->exec_objects[index].handle = bo_gem->gem_handle;
355 bufmgr_gem->exec_objects[index].relocation_count = bo_gem->reloc_count;
356 bufmgr_gem->exec_objects[index].relocs_ptr = (uintptr_t) bo_gem->relocs;
357 bufmgr_gem->exec_objects[index].alignment = 0;
358 bufmgr_gem->exec_objects[index].offset = 0;
359 bufmgr_gem->exec_bos[index] = bo;
360 drm_intel_gem_bo_reference(bo);
361 bufmgr_gem->exec_count++;
364 #define RELOC_BUF_SIZE(x) ((I915_RELOC_HEADER + x * I915_RELOC0_STRIDE) * \
368 drm_intel_bo_gem_set_in_aperture_size(drm_intel_bufmgr_gem *bufmgr_gem,
369 drm_intel_bo_gem *bo_gem)
373 assert(!bo_gem->used_as_reloc_target);
375 /* The older chipsets are far-less flexible in terms of tiling,
376 * and require tiled buffer to be size aligned in the aperture.
377 * This means that in the worst possible case we will need a hole
378 * twice as large as the object in order for it to fit into the
379 * aperture. Optimal packing is for wimps.
381 size = bo_gem->bo.size;
382 if (!IS_I965G(bufmgr_gem) && bo_gem->tiling_mode != I915_TILING_NONE)
385 bo_gem->reloc_tree_size = size;
389 drm_intel_setup_reloc_list(drm_intel_bo *bo)
391 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
392 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
393 unsigned int max_relocs = bufmgr_gem->max_relocs;
395 if (bo->size / 4 < max_relocs)
396 max_relocs = bo->size / 4;
398 bo_gem->relocs = malloc(max_relocs *
399 sizeof(struct drm_i915_gem_relocation_entry));
400 bo_gem->reloc_target_bo = malloc(max_relocs * sizeof(drm_intel_bo *));
406 drm_intel_gem_bo_busy(drm_intel_bo *bo)
408 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
409 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
410 struct drm_i915_gem_busy busy;
413 memset(&busy, 0, sizeof(busy));
414 busy.handle = bo_gem->gem_handle;
416 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_BUSY, &busy);
418 return (ret == 0 && busy.busy);
422 drm_intel_gem_bo_madvise_internal(drm_intel_bufmgr_gem *bufmgr_gem,
423 drm_intel_bo_gem *bo_gem, int state)
425 struct drm_i915_gem_madvise madv;
427 madv.handle = bo_gem->gem_handle;
430 ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MADVISE, &madv);
432 return madv.retained;
436 drm_intel_gem_bo_madvise(drm_intel_bo *bo, int madv)
438 return drm_intel_gem_bo_madvise_internal
439 ((drm_intel_bufmgr_gem *) bo->bufmgr,
440 (drm_intel_bo_gem *) bo,
444 /* drop the oldest entries that have been purged by the kernel */
446 drm_intel_gem_bo_cache_purge_bucket(drm_intel_bufmgr_gem *bufmgr_gem,
447 struct drm_intel_gem_bo_bucket *bucket)
449 while (!DRMLISTEMPTY(&bucket->head)) {
450 drm_intel_bo_gem *bo_gem;
452 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
453 bucket->head.next, head);
454 if (drm_intel_gem_bo_madvise_internal
455 (bufmgr_gem, bo_gem, I915_MADV_DONTNEED))
458 DRMLISTDEL(&bo_gem->head);
459 drm_intel_gem_bo_free(&bo_gem->bo);
463 static drm_intel_bo *
464 drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr,
469 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
470 drm_intel_bo_gem *bo_gem;
471 unsigned int page_size = getpagesize();
473 struct drm_intel_gem_bo_bucket *bucket;
474 int alloc_from_cache;
475 unsigned long bo_size;
478 if (flags & BO_ALLOC_FOR_RENDER)
481 /* Round the allocated size up to a power of two number of pages. */
482 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, size);
484 /* If we don't have caching at this size, don't actually round the
487 if (bucket == NULL) {
489 if (bo_size < page_size)
492 bo_size = bucket->size;
495 pthread_mutex_lock(&bufmgr_gem->lock);
496 /* Get a buffer out of the cache if available */
498 alloc_from_cache = 0;
499 if (bucket != NULL && !DRMLISTEMPTY(&bucket->head)) {
501 /* Allocate new render-target BOs from the tail (MRU)
502 * of the list, as it will likely be hot in the GPU
503 * cache and in the aperture for us.
505 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
506 bucket->head.prev, head);
507 DRMLISTDEL(&bo_gem->head);
508 alloc_from_cache = 1;
510 /* For non-render-target BOs (where we're probably
511 * going to map it first thing in order to fill it
512 * with data), check if the last BO in the cache is
513 * unbusy, and only reuse in that case. Otherwise,
514 * allocating a new buffer is probably faster than
515 * waiting for the GPU to finish.
517 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
518 bucket->head.next, head);
519 if (!drm_intel_gem_bo_busy(&bo_gem->bo)) {
520 alloc_from_cache = 1;
521 DRMLISTDEL(&bo_gem->head);
525 if (alloc_from_cache) {
526 if (!drm_intel_gem_bo_madvise_internal
527 (bufmgr_gem, bo_gem, I915_MADV_WILLNEED)) {
528 drm_intel_gem_bo_free(&bo_gem->bo);
529 drm_intel_gem_bo_cache_purge_bucket(bufmgr_gem,
535 pthread_mutex_unlock(&bufmgr_gem->lock);
537 if (!alloc_from_cache) {
538 struct drm_i915_gem_create create;
540 bo_gem = calloc(1, sizeof(*bo_gem));
544 bo_gem->bo.size = bo_size;
545 memset(&create, 0, sizeof(create));
546 create.size = bo_size;
548 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_CREATE, &create);
549 bo_gem->gem_handle = create.handle;
550 bo_gem->bo.handle = bo_gem->gem_handle;
555 bo_gem->bo.bufmgr = bufmgr;
559 atomic_set(&bo_gem->refcount, 1);
560 bo_gem->validate_index = -1;
561 bo_gem->reloc_tree_fences = 0;
562 bo_gem->used_as_reloc_target = 0;
563 bo_gem->tiling_mode = I915_TILING_NONE;
564 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
565 bo_gem->reusable = 1;
567 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
569 DBG("bo_create: buf %d (%s) %ldb\n",
570 bo_gem->gem_handle, bo_gem->name, size);
575 static drm_intel_bo *
576 drm_intel_gem_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
579 unsigned int alignment)
581 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size,
582 BO_ALLOC_FOR_RENDER);
585 static drm_intel_bo *
586 drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr,
589 unsigned int alignment)
591 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, 0);
594 static drm_intel_bo *
595 drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
596 int x, int y, int cpp, uint32_t *tiling_mode,
597 unsigned long *pitch, unsigned long flags)
599 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
601 unsigned long size, stride, aligned_y = y;
604 if (*tiling_mode == I915_TILING_NONE)
605 aligned_y = ALIGN(y, 2);
606 else if (*tiling_mode == I915_TILING_X)
607 aligned_y = ALIGN(y, 8);
608 else if (*tiling_mode == I915_TILING_Y)
609 aligned_y = ALIGN(y, 32);
612 stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, *tiling_mode);
613 size = stride * aligned_y;
614 size = drm_intel_gem_bo_tile_size(bufmgr_gem, size, tiling_mode);
616 bo = drm_intel_gem_bo_alloc_internal(bufmgr, name, size, flags);
620 ret = drm_intel_gem_bo_set_tiling(bo, tiling_mode, stride);
622 drm_intel_gem_bo_unreference(bo);
632 * Returns a drm_intel_bo wrapping the given buffer object handle.
634 * This can be used when one application needs to pass a buffer object
638 drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
642 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
643 drm_intel_bo_gem *bo_gem;
645 struct drm_gem_open open_arg;
646 struct drm_i915_gem_get_tiling get_tiling;
648 bo_gem = calloc(1, sizeof(*bo_gem));
652 memset(&open_arg, 0, sizeof(open_arg));
653 open_arg.name = handle;
654 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_OPEN, &open_arg);
656 fprintf(stderr, "Couldn't reference %s handle 0x%08x: %s\n",
657 name, handle, strerror(errno));
661 bo_gem->bo.size = open_arg.size;
662 bo_gem->bo.offset = 0;
663 bo_gem->bo.virtual = NULL;
664 bo_gem->bo.bufmgr = bufmgr;
666 atomic_set(&bo_gem->refcount, 1);
667 bo_gem->validate_index = -1;
668 bo_gem->gem_handle = open_arg.handle;
669 bo_gem->global_name = handle;
670 bo_gem->reusable = 0;
672 memset(&get_tiling, 0, sizeof(get_tiling));
673 get_tiling.handle = bo_gem->gem_handle;
674 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_GET_TILING, &get_tiling);
676 drm_intel_gem_bo_unreference(&bo_gem->bo);
679 bo_gem->tiling_mode = get_tiling.tiling_mode;
680 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
681 if (bo_gem->tiling_mode == I915_TILING_NONE)
682 bo_gem->reloc_tree_fences = 0;
684 bo_gem->reloc_tree_fences = 1;
685 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
687 DBG("bo_create_from_handle: %d (%s)\n", handle, bo_gem->name);
693 drm_intel_gem_bo_free(drm_intel_bo *bo)
695 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
696 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
697 struct drm_gem_close close;
700 if (bo_gem->mem_virtual)
701 munmap(bo_gem->mem_virtual, bo_gem->bo.size);
702 if (bo_gem->gtt_virtual)
703 munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
705 free(bo_gem->reloc_target_bo);
706 free(bo_gem->relocs);
708 /* Close this object */
709 memset(&close, 0, sizeof(close));
710 close.handle = bo_gem->gem_handle;
711 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close);
714 "DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
715 bo_gem->gem_handle, bo_gem->name, strerror(errno));
720 /** Frees all cached buffers significantly older than @time. */
722 drm_intel_gem_cleanup_bo_cache(drm_intel_bufmgr_gem *bufmgr_gem, time_t time)
726 for (i = 0; i < DRM_INTEL_GEM_BO_BUCKETS; i++) {
727 struct drm_intel_gem_bo_bucket *bucket =
728 &bufmgr_gem->cache_bucket[i];
730 while (!DRMLISTEMPTY(&bucket->head)) {
731 drm_intel_bo_gem *bo_gem;
733 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
734 bucket->head.next, head);
735 if (time - bo_gem->free_time <= 1)
738 DRMLISTDEL(&bo_gem->head);
740 drm_intel_gem_bo_free(&bo_gem->bo);
746 drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time)
748 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
749 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
750 struct drm_intel_gem_bo_bucket *bucket;
751 uint32_t tiling_mode;
754 /* Unreference all the target buffers */
755 for (i = 0; i < bo_gem->reloc_count; i++) {
756 drm_intel_gem_bo_unreference_locked_timed(bo_gem->
760 bo_gem->reloc_count = 0;
761 bo_gem->used_as_reloc_target = 0;
763 DBG("bo_unreference final: %d (%s)\n",
764 bo_gem->gem_handle, bo_gem->name);
766 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, bo->size);
767 /* Put the buffer into our internal cache for reuse if we can. */
768 tiling_mode = I915_TILING_NONE;
769 if (bufmgr_gem->bo_reuse && bo_gem->reusable && bucket != NULL &&
770 drm_intel_gem_bo_set_tiling(bo, &tiling_mode, 0) == 0 &&
771 drm_intel_gem_bo_madvise_internal(bufmgr_gem, bo_gem,
772 I915_MADV_DONTNEED)) {
773 bo_gem->free_time = time;
776 bo_gem->validate_index = -1;
778 DRMLISTADDTAIL(&bo_gem->head, &bucket->head);
780 drm_intel_gem_cleanup_bo_cache(bufmgr_gem, time);
782 drm_intel_gem_bo_free(bo);
786 static void drm_intel_gem_bo_unreference_locked(drm_intel_bo *bo)
788 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
790 assert(atomic_read(&bo_gem->refcount) > 0);
791 if (atomic_dec_and_test(&bo_gem->refcount)) {
792 struct timespec time;
794 clock_gettime(CLOCK_MONOTONIC, &time);
795 drm_intel_gem_bo_unreference_final(bo, time.tv_sec);
799 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
802 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
804 assert(atomic_read(&bo_gem->refcount) > 0);
805 if (atomic_dec_and_test(&bo_gem->refcount))
806 drm_intel_gem_bo_unreference_final(bo, time);
809 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo)
811 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
813 assert(atomic_read(&bo_gem->refcount) > 0);
814 if (atomic_dec_and_test(&bo_gem->refcount)) {
815 drm_intel_bufmgr_gem *bufmgr_gem =
816 (drm_intel_bufmgr_gem *) bo->bufmgr;
817 struct timespec time;
819 clock_gettime(CLOCK_MONOTONIC, &time);
821 pthread_mutex_lock(&bufmgr_gem->lock);
822 drm_intel_gem_bo_unreference_final(bo, time.tv_sec);
823 pthread_mutex_unlock(&bufmgr_gem->lock);
827 static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable)
829 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
830 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
831 struct drm_i915_gem_set_domain set_domain;
834 pthread_mutex_lock(&bufmgr_gem->lock);
836 /* Allow recursive mapping. Mesa may recursively map buffers with
837 * nested display loops.
839 if (!bo_gem->mem_virtual) {
840 struct drm_i915_gem_mmap mmap_arg;
842 DBG("bo_map: %d (%s)\n", bo_gem->gem_handle, bo_gem->name);
844 memset(&mmap_arg, 0, sizeof(mmap_arg));
845 mmap_arg.handle = bo_gem->gem_handle;
847 mmap_arg.size = bo->size;
848 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MMAP, &mmap_arg);
851 "%s:%d: Error mapping buffer %d (%s): %s .\n",
852 __FILE__, __LINE__, bo_gem->gem_handle,
853 bo_gem->name, strerror(errno));
854 pthread_mutex_unlock(&bufmgr_gem->lock);
857 bo_gem->mem_virtual = (void *)(uintptr_t) mmap_arg.addr_ptr;
859 DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
860 bo_gem->mem_virtual);
861 bo->virtual = bo_gem->mem_virtual;
863 set_domain.handle = bo_gem->gem_handle;
864 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
866 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
868 set_domain.write_domain = 0;
870 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN,
872 } while (ret == -1 && errno == EINTR);
874 fprintf(stderr, "%s:%d: Error setting to CPU domain %d: %s\n",
875 __FILE__, __LINE__, bo_gem->gem_handle,
877 pthread_mutex_unlock(&bufmgr_gem->lock);
881 pthread_mutex_unlock(&bufmgr_gem->lock);
886 int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
888 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
889 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
890 struct drm_i915_gem_set_domain set_domain;
893 pthread_mutex_lock(&bufmgr_gem->lock);
895 /* Get a mapping of the buffer if we haven't before. */
896 if (bo_gem->gtt_virtual == NULL) {
897 struct drm_i915_gem_mmap_gtt mmap_arg;
899 DBG("bo_map_gtt: mmap %d (%s)\n", bo_gem->gem_handle,
902 memset(&mmap_arg, 0, sizeof(mmap_arg));
903 mmap_arg.handle = bo_gem->gem_handle;
905 /* Get the fake offset back... */
906 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MMAP_GTT,
910 "%s:%d: Error preparing buffer map %d (%s): %s .\n",
912 bo_gem->gem_handle, bo_gem->name,
914 pthread_mutex_unlock(&bufmgr_gem->lock);
919 bo_gem->gtt_virtual = mmap(0, bo->size, PROT_READ | PROT_WRITE,
920 MAP_SHARED, bufmgr_gem->fd,
922 if (bo_gem->gtt_virtual == MAP_FAILED) {
924 "%s:%d: Error mapping buffer %d (%s): %s .\n",
926 bo_gem->gem_handle, bo_gem->name,
928 pthread_mutex_unlock(&bufmgr_gem->lock);
933 bo->virtual = bo_gem->gtt_virtual;
935 DBG("bo_map_gtt: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
936 bo_gem->gtt_virtual);
938 /* Now move it to the GTT domain so that the CPU caches are flushed */
939 set_domain.handle = bo_gem->gem_handle;
940 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
941 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
943 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN,
945 } while (ret == -1 && errno == EINTR);
948 fprintf(stderr, "%s:%d: Error setting domain %d: %s\n",
949 __FILE__, __LINE__, bo_gem->gem_handle,
953 pthread_mutex_unlock(&bufmgr_gem->lock);
958 int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo)
960 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
961 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
967 assert(bo_gem->gtt_virtual != NULL);
969 pthread_mutex_lock(&bufmgr_gem->lock);
971 pthread_mutex_unlock(&bufmgr_gem->lock);
976 static int drm_intel_gem_bo_unmap(drm_intel_bo *bo)
978 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
979 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
980 struct drm_i915_gem_sw_finish sw_finish;
986 assert(bo_gem->mem_virtual != NULL);
988 pthread_mutex_lock(&bufmgr_gem->lock);
990 /* Cause a flush to happen if the buffer's pinned for scanout, so the
991 * results show up in a timely manner.
993 sw_finish.handle = bo_gem->gem_handle;
995 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_SW_FINISH,
997 } while (ret == -1 && errno == EINTR);
1000 pthread_mutex_unlock(&bufmgr_gem->lock);
1005 drm_intel_gem_bo_subdata(drm_intel_bo *bo, unsigned long offset,
1006 unsigned long size, const void *data)
1008 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1009 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1010 struct drm_i915_gem_pwrite pwrite;
1013 memset(&pwrite, 0, sizeof(pwrite));
1014 pwrite.handle = bo_gem->gem_handle;
1015 pwrite.offset = offset;
1017 pwrite.data_ptr = (uint64_t) (uintptr_t) data;
1019 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_PWRITE, &pwrite);
1020 } while (ret == -1 && errno == EINTR);
1023 "%s:%d: Error writing data to buffer %d: (%d %d) %s .\n",
1024 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1025 (int)size, strerror(errno));
1031 drm_intel_gem_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id)
1033 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1034 struct drm_i915_get_pipe_from_crtc_id get_pipe_from_crtc_id;
1037 get_pipe_from_crtc_id.crtc_id = crtc_id;
1038 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID,
1039 &get_pipe_from_crtc_id);
1041 /* We return -1 here to signal that we don't
1042 * know which pipe is associated with this crtc.
1043 * This lets the caller know that this information
1044 * isn't available; using the wrong pipe for
1045 * vblank waiting can cause the chipset to lock up
1050 return get_pipe_from_crtc_id.pipe;
1054 drm_intel_gem_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
1055 unsigned long size, void *data)
1057 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1058 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1059 struct drm_i915_gem_pread pread;
1062 memset(&pread, 0, sizeof(pread));
1063 pread.handle = bo_gem->gem_handle;
1064 pread.offset = offset;
1066 pread.data_ptr = (uint64_t) (uintptr_t) data;
1068 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_PREAD, &pread);
1069 } while (ret == -1 && errno == EINTR);
1072 "%s:%d: Error reading data from buffer %d: (%d %d) %s .\n",
1073 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1074 (int)size, strerror(errno));
1079 /** Waits for all GPU rendering to the object to have completed. */
1081 drm_intel_gem_bo_wait_rendering(drm_intel_bo *bo)
1083 drm_intel_gem_bo_start_gtt_access(bo, 0);
1087 * Sets the object to the GTT read and possibly write domain, used by the X
1088 * 2D driver in the absence of kernel support to do drm_intel_gem_bo_map_gtt().
1090 * In combination with drm_intel_gem_bo_pin() and manual fence management, we
1091 * can do tiled pixmaps this way.
1094 drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable)
1096 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1097 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1098 struct drm_i915_gem_set_domain set_domain;
1101 set_domain.handle = bo_gem->gem_handle;
1102 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1103 set_domain.write_domain = write_enable ? I915_GEM_DOMAIN_GTT : 0;
1105 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN,
1107 } while (ret == -1 && errno == EINTR);
1110 "%s:%d: Error setting memory domains %d (%08x %08x): %s .\n",
1111 __FILE__, __LINE__, bo_gem->gem_handle,
1112 set_domain.read_domains, set_domain.write_domain,
1118 drm_intel_bufmgr_gem_destroy(drm_intel_bufmgr *bufmgr)
1120 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1123 free(bufmgr_gem->exec_objects);
1124 free(bufmgr_gem->exec_bos);
1126 pthread_mutex_destroy(&bufmgr_gem->lock);
1128 /* Free any cached buffer objects we were going to reuse */
1129 for (i = 0; i < DRM_INTEL_GEM_BO_BUCKETS; i++) {
1130 struct drm_intel_gem_bo_bucket *bucket =
1131 &bufmgr_gem->cache_bucket[i];
1132 drm_intel_bo_gem *bo_gem;
1134 while (!DRMLISTEMPTY(&bucket->head)) {
1135 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1136 bucket->head.next, head);
1137 DRMLISTDEL(&bo_gem->head);
1139 drm_intel_gem_bo_free(&bo_gem->bo);
1147 * Adds the target buffer to the validation list and adds the relocation
1148 * to the reloc_buffer's relocation list.
1150 * The relocation entry at the given offset must already contain the
1151 * precomputed relocation value, because the kernel will optimize out
1152 * the relocation entry write when the buffer hasn't moved from the
1153 * last known offset in target_bo.
1156 drm_intel_gem_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1157 drm_intel_bo *target_bo, uint32_t target_offset,
1158 uint32_t read_domains, uint32_t write_domain)
1160 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1161 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1162 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
1164 pthread_mutex_lock(&bufmgr_gem->lock);
1166 /* Create a new relocation list if needed */
1167 if (bo_gem->relocs == NULL)
1168 drm_intel_setup_reloc_list(bo);
1170 /* Check overflow */
1171 assert(bo_gem->reloc_count < bufmgr_gem->max_relocs);
1174 assert(offset <= bo->size - 4);
1175 assert((write_domain & (write_domain - 1)) == 0);
1177 /* Make sure that we're not adding a reloc to something whose size has
1178 * already been accounted for.
1180 assert(!bo_gem->used_as_reloc_target);
1181 bo_gem->reloc_tree_size += target_bo_gem->reloc_tree_size;
1182 bo_gem->reloc_tree_fences += target_bo_gem->reloc_tree_fences;
1184 /* Flag the target to disallow further relocations in it. */
1185 target_bo_gem->used_as_reloc_target = 1;
1187 bo_gem->relocs[bo_gem->reloc_count].offset = offset;
1188 bo_gem->relocs[bo_gem->reloc_count].delta = target_offset;
1189 bo_gem->relocs[bo_gem->reloc_count].target_handle =
1190 target_bo_gem->gem_handle;
1191 bo_gem->relocs[bo_gem->reloc_count].read_domains = read_domains;
1192 bo_gem->relocs[bo_gem->reloc_count].write_domain = write_domain;
1193 bo_gem->relocs[bo_gem->reloc_count].presumed_offset = target_bo->offset;
1195 bo_gem->reloc_target_bo[bo_gem->reloc_count] = target_bo;
1196 drm_intel_gem_bo_reference(target_bo);
1198 bo_gem->reloc_count++;
1200 pthread_mutex_unlock(&bufmgr_gem->lock);
1206 * Walk the tree of relocations rooted at BO and accumulate the list of
1207 * validations to be performed and update the relocation buffers with
1208 * index values into the validation list.
1211 drm_intel_gem_bo_process_reloc(drm_intel_bo *bo)
1213 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1216 if (bo_gem->relocs == NULL)
1219 for (i = 0; i < bo_gem->reloc_count; i++) {
1220 drm_intel_bo *target_bo = bo_gem->reloc_target_bo[i];
1222 /* Continue walking the tree depth-first. */
1223 drm_intel_gem_bo_process_reloc(target_bo);
1225 /* Add the target to the validate list */
1226 drm_intel_add_validate_buffer(target_bo);
1231 drm_intel_update_buffer_offsets(drm_intel_bufmgr_gem *bufmgr_gem)
1235 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1236 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1237 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1239 /* Update the buffer offset */
1240 if (bufmgr_gem->exec_objects[i].offset != bo->offset) {
1241 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1242 bo_gem->gem_handle, bo_gem->name, bo->offset,
1243 (unsigned long long)bufmgr_gem->exec_objects[i].
1245 bo->offset = bufmgr_gem->exec_objects[i].offset;
1251 drm_intel_gem_bo_exec(drm_intel_bo *bo, int used,
1252 drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
1254 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1255 struct drm_i915_gem_execbuffer execbuf;
1258 pthread_mutex_lock(&bufmgr_gem->lock);
1259 /* Update indices and set up the validate list. */
1260 drm_intel_gem_bo_process_reloc(bo);
1262 /* Add the batch buffer to the validation list. There are no
1263 * relocations pointing to it.
1265 drm_intel_add_validate_buffer(bo);
1267 execbuf.buffers_ptr = (uintptr_t) bufmgr_gem->exec_objects;
1268 execbuf.buffer_count = bufmgr_gem->exec_count;
1269 execbuf.batch_start_offset = 0;
1270 execbuf.batch_len = used;
1271 execbuf.cliprects_ptr = (uintptr_t) cliprects;
1272 execbuf.num_cliprects = num_cliprects;
1277 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_EXECBUFFER,
1279 } while (ret != 0 && errno == EAGAIN);
1281 if (ret != 0 && errno == ENOMEM) {
1283 "Execbuffer fails to pin. "
1284 "Estimate: %u. Actual: %u. Available: %u\n",
1285 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
1288 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
1291 (unsigned int)bufmgr_gem->gtt_size);
1293 drm_intel_update_buffer_offsets(bufmgr_gem);
1295 if (bufmgr_gem->bufmgr.debug)
1296 drm_intel_gem_dump_validation_list(bufmgr_gem);
1298 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1299 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1300 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1302 /* Disconnect the buffer from the validate list */
1303 bo_gem->validate_index = -1;
1304 drm_intel_gem_bo_unreference_locked(bo);
1305 bufmgr_gem->exec_bos[i] = NULL;
1307 bufmgr_gem->exec_count = 0;
1308 pthread_mutex_unlock(&bufmgr_gem->lock);
1314 drm_intel_gem_bo_pin(drm_intel_bo *bo, uint32_t alignment)
1316 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1317 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1318 struct drm_i915_gem_pin pin;
1321 memset(&pin, 0, sizeof(pin));
1322 pin.handle = bo_gem->gem_handle;
1323 pin.alignment = alignment;
1326 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_PIN, &pin);
1327 } while (ret == -1 && errno == EINTR);
1332 bo->offset = pin.offset;
1337 drm_intel_gem_bo_unpin(drm_intel_bo *bo)
1339 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1340 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1341 struct drm_i915_gem_unpin unpin;
1344 memset(&unpin, 0, sizeof(unpin));
1345 unpin.handle = bo_gem->gem_handle;
1347 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_UNPIN, &unpin);
1355 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1358 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1359 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1360 struct drm_i915_gem_set_tiling set_tiling;
1363 if (bo_gem->global_name == 0 && *tiling_mode == bo_gem->tiling_mode)
1366 /* If we're going from non-tiling to tiling, bump fence count */
1367 if (bo_gem->tiling_mode == I915_TILING_NONE)
1368 bo_gem->reloc_tree_fences++;
1370 memset(&set_tiling, 0, sizeof(set_tiling));
1371 set_tiling.handle = bo_gem->gem_handle;
1372 set_tiling.tiling_mode = *tiling_mode;
1373 set_tiling.stride = stride;
1375 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_SET_TILING, &set_tiling);
1377 *tiling_mode = bo_gem->tiling_mode;
1380 bo_gem->tiling_mode = set_tiling.tiling_mode;
1381 bo_gem->swizzle_mode = set_tiling.swizzle_mode;
1383 /* If we're going from tiling to non-tiling, drop fence count */
1384 if (bo_gem->tiling_mode == I915_TILING_NONE)
1385 bo_gem->reloc_tree_fences--;
1387 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
1389 *tiling_mode = bo_gem->tiling_mode;
1394 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1395 uint32_t * swizzle_mode)
1397 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1399 *tiling_mode = bo_gem->tiling_mode;
1400 *swizzle_mode = bo_gem->swizzle_mode;
1405 drm_intel_gem_bo_flink(drm_intel_bo *bo, uint32_t * name)
1407 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1408 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1409 struct drm_gem_flink flink;
1412 if (!bo_gem->global_name) {
1413 memset(&flink, 0, sizeof(flink));
1414 flink.handle = bo_gem->gem_handle;
1416 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_FLINK, &flink);
1419 bo_gem->global_name = flink.name;
1420 bo_gem->reusable = 0;
1423 *name = bo_gem->global_name;
1428 * Enables unlimited caching of buffer objects for reuse.
1430 * This is potentially very memory expensive, as the cache at each bucket
1431 * size is only bounded by how many buffers of that size we've managed to have
1432 * in flight at once.
1435 drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr)
1437 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1439 bufmgr_gem->bo_reuse = 1;
1443 * Return the additional aperture space required by the tree of buffer objects
1447 drm_intel_gem_bo_get_aperture_space(drm_intel_bo *bo)
1449 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1453 if (bo == NULL || bo_gem->included_in_check_aperture)
1457 bo_gem->included_in_check_aperture = 1;
1459 for (i = 0; i < bo_gem->reloc_count; i++)
1461 drm_intel_gem_bo_get_aperture_space(bo_gem->
1462 reloc_target_bo[i]);
1468 * Count the number of buffers in this list that need a fence reg
1470 * If the count is greater than the number of available regs, we'll have
1471 * to ask the caller to resubmit a batch with fewer tiled buffers.
1473 * This function over-counts if the same buffer is used multiple times.
1476 drm_intel_gem_total_fences(drm_intel_bo ** bo_array, int count)
1479 unsigned int total = 0;
1481 for (i = 0; i < count; i++) {
1482 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
1487 total += bo_gem->reloc_tree_fences;
1493 * Clear the flag set by drm_intel_gem_bo_get_aperture_space() so we're ready
1494 * for the next drm_intel_bufmgr_check_aperture_space() call.
1497 drm_intel_gem_bo_clear_aperture_space_flag(drm_intel_bo *bo)
1499 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1502 if (bo == NULL || !bo_gem->included_in_check_aperture)
1505 bo_gem->included_in_check_aperture = 0;
1507 for (i = 0; i < bo_gem->reloc_count; i++)
1508 drm_intel_gem_bo_clear_aperture_space_flag(bo_gem->
1509 reloc_target_bo[i]);
1513 * Return a conservative estimate for the amount of aperture required
1514 * for a collection of buffers. This may double-count some buffers.
1517 drm_intel_gem_estimate_batch_space(drm_intel_bo **bo_array, int count)
1520 unsigned int total = 0;
1522 for (i = 0; i < count; i++) {
1523 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
1525 total += bo_gem->reloc_tree_size;
1531 * Return the amount of aperture needed for a collection of buffers.
1532 * This avoids double counting any buffers, at the cost of looking
1533 * at every buffer in the set.
1536 drm_intel_gem_compute_batch_space(drm_intel_bo **bo_array, int count)
1539 unsigned int total = 0;
1541 for (i = 0; i < count; i++) {
1542 total += drm_intel_gem_bo_get_aperture_space(bo_array[i]);
1543 /* For the first buffer object in the array, we get an
1544 * accurate count back for its reloc_tree size (since nothing
1545 * had been flagged as being counted yet). We can save that
1546 * value out as a more conservative reloc_tree_size that
1547 * avoids double-counting target buffers. Since the first
1548 * buffer happens to usually be the batch buffer in our
1549 * callers, this can pull us back from doing the tree
1550 * walk on every new batch emit.
1553 drm_intel_bo_gem *bo_gem =
1554 (drm_intel_bo_gem *) bo_array[i];
1555 bo_gem->reloc_tree_size = total;
1559 for (i = 0; i < count; i++)
1560 drm_intel_gem_bo_clear_aperture_space_flag(bo_array[i]);
1565 * Return -1 if the batchbuffer should be flushed before attempting to
1566 * emit rendering referencing the buffers pointed to by bo_array.
1568 * This is required because if we try to emit a batchbuffer with relocations
1569 * to a tree of buffers that won't simultaneously fit in the aperture,
1570 * the rendering will return an error at a point where the software is not
1571 * prepared to recover from it.
1573 * However, we also want to emit the batchbuffer significantly before we reach
1574 * the limit, as a series of batchbuffers each of which references buffers
1575 * covering almost all of the aperture means that at each emit we end up
1576 * waiting to evict a buffer from the last rendering, and we get synchronous
1577 * performance. By emitting smaller batchbuffers, we eat some CPU overhead to
1578 * get better parallelism.
1581 drm_intel_gem_check_aperture_space(drm_intel_bo **bo_array, int count)
1583 drm_intel_bufmgr_gem *bufmgr_gem =
1584 (drm_intel_bufmgr_gem *) bo_array[0]->bufmgr;
1585 unsigned int total = 0;
1586 unsigned int threshold = bufmgr_gem->gtt_size * 3 / 4;
1589 /* Check for fence reg constraints if necessary */
1590 if (bufmgr_gem->available_fences) {
1591 total_fences = drm_intel_gem_total_fences(bo_array, count);
1592 if (total_fences > bufmgr_gem->available_fences)
1596 total = drm_intel_gem_estimate_batch_space(bo_array, count);
1598 if (total > threshold)
1599 total = drm_intel_gem_compute_batch_space(bo_array, count);
1601 if (total > threshold) {
1602 DBG("check_space: overflowed available aperture, "
1604 total / 1024, (int)bufmgr_gem->gtt_size / 1024);
1607 DBG("drm_check_space: total %dkb vs bufgr %dkb\n", total / 1024,
1608 (int)bufmgr_gem->gtt_size / 1024);
1614 * Disable buffer reuse for objects which are shared with the kernel
1615 * as scanout buffers
1618 drm_intel_gem_bo_disable_reuse(drm_intel_bo *bo)
1620 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1622 bo_gem->reusable = 0;
1627 _drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
1629 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1632 for (i = 0; i < bo_gem->reloc_count; i++) {
1633 if (bo_gem->reloc_target_bo[i] == target_bo)
1635 if (_drm_intel_gem_bo_references(bo_gem->reloc_target_bo[i],
1643 /** Return true if target_bo is referenced by bo's relocation tree. */
1645 drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
1647 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
1649 if (bo == NULL || target_bo == NULL)
1651 if (target_bo_gem->used_as_reloc_target)
1652 return _drm_intel_gem_bo_references(bo, target_bo);
1657 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
1658 * and manage map buffer objections.
1660 * \param fd File descriptor of the opened DRM device.
1663 drm_intel_bufmgr_gem_init(int fd, int batch_size)
1665 drm_intel_bufmgr_gem *bufmgr_gem;
1666 struct drm_i915_gem_get_aperture aperture;
1667 drm_i915_getparam_t gp;
1671 bufmgr_gem = calloc(1, sizeof(*bufmgr_gem));
1672 bufmgr_gem->fd = fd;
1674 if (pthread_mutex_init(&bufmgr_gem->lock, NULL) != 0) {
1679 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
1682 bufmgr_gem->gtt_size = aperture.aper_available_size;
1684 fprintf(stderr, "DRM_IOCTL_I915_GEM_APERTURE failed: %s\n",
1686 bufmgr_gem->gtt_size = 128 * 1024 * 1024;
1687 fprintf(stderr, "Assuming %dkB available aperture size.\n"
1688 "May lead to reduced performance or incorrect "
1690 (int)bufmgr_gem->gtt_size / 1024);
1693 gp.param = I915_PARAM_CHIPSET_ID;
1694 gp.value = &bufmgr_gem->pci_device;
1695 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
1697 fprintf(stderr, "get chip id failed: %d [%d]\n", ret, errno);
1698 fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value);
1701 if (!IS_I965G(bufmgr_gem)) {
1702 gp.param = I915_PARAM_NUM_FENCES_AVAIL;
1703 gp.value = &bufmgr_gem->available_fences;
1704 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
1706 fprintf(stderr, "get fences failed: %d [%d]\n", ret,
1708 fprintf(stderr, "param: %d, val: %d\n", gp.param,
1710 bufmgr_gem->available_fences = 0;
1714 /* Let's go with one relocation per every 2 dwords (but round down a bit
1715 * since a power of two will mean an extra page allocation for the reloc
1718 * Every 4 was too few for the blender benchmark.
1720 bufmgr_gem->max_relocs = batch_size / sizeof(uint32_t) / 2 - 2;
1722 bufmgr_gem->bufmgr.bo_alloc = drm_intel_gem_bo_alloc;
1723 bufmgr_gem->bufmgr.bo_alloc_for_render =
1724 drm_intel_gem_bo_alloc_for_render;
1725 bufmgr_gem->bufmgr.bo_alloc_tiled = drm_intel_gem_bo_alloc_tiled;
1726 bufmgr_gem->bufmgr.bo_reference = drm_intel_gem_bo_reference;
1727 bufmgr_gem->bufmgr.bo_unreference = drm_intel_gem_bo_unreference;
1728 bufmgr_gem->bufmgr.bo_map = drm_intel_gem_bo_map;
1729 bufmgr_gem->bufmgr.bo_unmap = drm_intel_gem_bo_unmap;
1730 bufmgr_gem->bufmgr.bo_subdata = drm_intel_gem_bo_subdata;
1731 bufmgr_gem->bufmgr.bo_get_subdata = drm_intel_gem_bo_get_subdata;
1732 bufmgr_gem->bufmgr.bo_wait_rendering = drm_intel_gem_bo_wait_rendering;
1733 bufmgr_gem->bufmgr.bo_emit_reloc = drm_intel_gem_bo_emit_reloc;
1734 bufmgr_gem->bufmgr.bo_pin = drm_intel_gem_bo_pin;
1735 bufmgr_gem->bufmgr.bo_unpin = drm_intel_gem_bo_unpin;
1736 bufmgr_gem->bufmgr.bo_get_tiling = drm_intel_gem_bo_get_tiling;
1737 bufmgr_gem->bufmgr.bo_set_tiling = drm_intel_gem_bo_set_tiling;
1738 bufmgr_gem->bufmgr.bo_flink = drm_intel_gem_bo_flink;
1739 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec;
1740 bufmgr_gem->bufmgr.bo_busy = drm_intel_gem_bo_busy;
1741 bufmgr_gem->bufmgr.bo_madvise = drm_intel_gem_bo_madvise;
1742 bufmgr_gem->bufmgr.destroy = drm_intel_bufmgr_gem_destroy;
1743 bufmgr_gem->bufmgr.debug = 0;
1744 bufmgr_gem->bufmgr.check_aperture_space =
1745 drm_intel_gem_check_aperture_space;
1746 bufmgr_gem->bufmgr.bo_disable_reuse = drm_intel_gem_bo_disable_reuse;
1747 bufmgr_gem->bufmgr.get_pipe_from_crtc_id =
1748 drm_intel_gem_get_pipe_from_crtc_id;
1749 bufmgr_gem->bufmgr.bo_references = drm_intel_gem_bo_references;
1751 /* Initialize the linked lists for BO reuse cache. */
1752 for (i = 0, size = 4096; i < DRM_INTEL_GEM_BO_BUCKETS; i++, size *= 2) {
1753 DRMINITLISTHEAD(&bufmgr_gem->cache_bucket[i].head);
1754 bufmgr_gem->cache_bucket[i].size = size;
1757 return &bufmgr_gem->bufmgr;