1 /**************************************************************************
3 * Copyright © 2007 Red Hat Inc.
4 * Copyright © 2007 Intel Corporation
5 * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
29 **************************************************************************/
31 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
32 * Keith Whitwell <keithw-at-tungstengraphics-dot-com>
33 * Eric Anholt <eric@anholt.net>
34 * Dave Airlie <airlied@linux.ie>
42 #include <xf86atomic.h>
50 #include <sys/ioctl.h>
53 #include <sys/types.h>
57 #include "libdrm_lists.h"
58 #include "intel_bufmgr.h"
59 #include "intel_bufmgr_priv.h"
60 #include "intel_chipset.h"
73 #define VG_CLEAR(s) VG(memset(&s, 0, sizeof(s)))
75 #define DBG(...) do { \
76 if (bufmgr_gem->bufmgr.debug) \
77 fprintf(stderr, __VA_ARGS__); \
80 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
82 typedef struct _drm_intel_bo_gem drm_intel_bo_gem;
84 struct drm_intel_gem_bo_bucket {
89 typedef struct _drm_intel_bufmgr_gem {
90 drm_intel_bufmgr bufmgr;
98 struct drm_i915_gem_exec_object *exec_objects;
99 struct drm_i915_gem_exec_object2 *exec2_objects;
100 drm_intel_bo **exec_bos;
104 /** Array of lists of cached gem objects of power-of-two sizes */
105 struct drm_intel_gem_bo_bucket cache_bucket[14 * 4];
110 drmMMListHead vma_cache;
111 int vma_count, vma_open, vma_max;
114 int available_fences;
117 unsigned int has_bsd : 1;
118 unsigned int has_blt : 1;
119 unsigned int has_relaxed_fencing : 1;
120 unsigned int has_llc : 1;
121 unsigned int bo_reuse : 1;
123 } drm_intel_bufmgr_gem;
125 #define DRM_INTEL_RELOC_FENCE (1<<0)
127 typedef struct _drm_intel_reloc_target_info {
130 } drm_intel_reloc_target;
132 struct _drm_intel_bo_gem {
140 * Kenel-assigned global name for this object
142 unsigned int global_name;
143 drmMMListHead name_list;
146 * Index of the buffer within the validation list while preparing a
147 * batchbuffer execution.
152 * Current tiling mode
154 uint32_t tiling_mode;
155 uint32_t swizzle_mode;
156 unsigned long stride;
160 /** Array passed to the DRM containing relocation information. */
161 struct drm_i915_gem_relocation_entry *relocs;
163 * Array of info structs corresponding to relocs[i].target_handle etc
165 drm_intel_reloc_target *reloc_target_info;
166 /** Number of entries in relocs */
168 /** Mapped address for the buffer, saved across map/unmap cycles */
170 /** GTT virtual address for the buffer, saved across map/unmap cycles */
173 drmMMListHead vma_list;
179 * Boolean of whether this BO and its children have been included in
180 * the current drm_intel_bufmgr_check_aperture_space() total.
182 bool included_in_check_aperture;
185 * Boolean of whether this buffer has been used as a relocation
186 * target and had its size accounted for, and thus can't have any
187 * further relocations added to it.
189 bool used_as_reloc_target;
192 * Boolean of whether we have encountered an error whilst building the relocation tree.
197 * Boolean of whether this buffer can be re-used
202 * Size in bytes of this buffer and its relocation descendents.
204 * Used to avoid costly tree walking in
205 * drm_intel_bufmgr_check_aperture in the common case.
210 * Number of potential fence registers required by this buffer and its
213 int reloc_tree_fences;
215 /** Flags that we may need to do the SW_FINSIH ioctl on unmap. */
216 bool mapped_cpu_write;
220 drm_intel_gem_estimate_batch_space(drm_intel_bo ** bo_array, int count);
223 drm_intel_gem_compute_batch_space(drm_intel_bo ** bo_array, int count);
226 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
227 uint32_t * swizzle_mode);
230 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
231 uint32_t tiling_mode,
234 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
237 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo);
239 static void drm_intel_gem_bo_free(drm_intel_bo *bo);
242 drm_intel_gem_bo_tile_size(drm_intel_bufmgr_gem *bufmgr_gem, unsigned long size,
243 uint32_t *tiling_mode)
245 unsigned long min_size, max_size;
248 if (*tiling_mode == I915_TILING_NONE)
251 /* 965+ just need multiples of page size for tiling */
252 if (bufmgr_gem->gen >= 4)
253 return ROUND_UP_TO(size, 4096);
255 /* Older chips need powers of two, of at least 512k or 1M */
256 if (bufmgr_gem->gen == 3) {
257 min_size = 1024*1024;
258 max_size = 128*1024*1024;
261 max_size = 64*1024*1024;
264 if (size > max_size) {
265 *tiling_mode = I915_TILING_NONE;
269 /* Do we need to allocate every page for the fence? */
270 if (bufmgr_gem->has_relaxed_fencing)
271 return ROUND_UP_TO(size, 4096);
273 for (i = min_size; i < size; i <<= 1)
280 * Round a given pitch up to the minimum required for X tiling on a
281 * given chip. We use 512 as the minimum to allow for a later tiling
285 drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem,
286 unsigned long pitch, uint32_t *tiling_mode)
288 unsigned long tile_width;
291 /* If untiled, then just align it so that we can do rendering
292 * to it with the 3D engine.
294 if (*tiling_mode == I915_TILING_NONE)
295 return ALIGN(pitch, 64);
297 if (*tiling_mode == I915_TILING_X
298 || (IS_915(bufmgr_gem->pci_device)
299 && *tiling_mode == I915_TILING_Y))
304 /* 965 is flexible */
305 if (bufmgr_gem->gen >= 4)
306 return ROUND_UP_TO(pitch, tile_width);
308 /* The older hardware has a maximum pitch of 8192 with tiled
309 * surfaces, so fallback to untiled if it's too large.
312 *tiling_mode = I915_TILING_NONE;
313 return ALIGN(pitch, 64);
316 /* Pre-965 needs power of two tile width */
317 for (i = tile_width; i < pitch; i <<= 1)
323 static struct drm_intel_gem_bo_bucket *
324 drm_intel_gem_bo_bucket_for_size(drm_intel_bufmgr_gem *bufmgr_gem,
329 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
330 struct drm_intel_gem_bo_bucket *bucket =
331 &bufmgr_gem->cache_bucket[i];
332 if (bucket->size >= size) {
341 drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem *bufmgr_gem)
345 for (i = 0; i < bufmgr_gem->exec_count; i++) {
346 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
347 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
349 if (bo_gem->relocs == NULL) {
350 DBG("%2d: %d (%s)\n", i, bo_gem->gem_handle,
355 for (j = 0; j < bo_gem->reloc_count; j++) {
356 drm_intel_bo *target_bo = bo_gem->reloc_target_info[j].bo;
357 drm_intel_bo_gem *target_gem =
358 (drm_intel_bo_gem *) target_bo;
360 DBG("%2d: %d (%s)@0x%08llx -> "
361 "%d (%s)@0x%08lx + 0x%08x\n",
363 bo_gem->gem_handle, bo_gem->name,
364 (unsigned long long)bo_gem->relocs[j].offset,
365 target_gem->gem_handle,
368 bo_gem->relocs[j].delta);
374 drm_intel_gem_bo_reference(drm_intel_bo *bo)
376 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
378 atomic_inc(&bo_gem->refcount);
382 * Adds the given buffer to the list of buffers to be validated (moved into the
383 * appropriate memory type) with the next batch submission.
385 * If a buffer is validated multiple times in a batch submission, it ends up
386 * with the intersection of the memory type flags and the union of the
390 drm_intel_add_validate_buffer(drm_intel_bo *bo)
392 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
393 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
396 if (bo_gem->validate_index != -1)
399 /* Extend the array of validation entries as necessary. */
400 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
401 int new_size = bufmgr_gem->exec_size * 2;
406 bufmgr_gem->exec_objects =
407 realloc(bufmgr_gem->exec_objects,
408 sizeof(*bufmgr_gem->exec_objects) * new_size);
409 bufmgr_gem->exec_bos =
410 realloc(bufmgr_gem->exec_bos,
411 sizeof(*bufmgr_gem->exec_bos) * new_size);
412 bufmgr_gem->exec_size = new_size;
415 index = bufmgr_gem->exec_count;
416 bo_gem->validate_index = index;
417 /* Fill in array entry */
418 bufmgr_gem->exec_objects[index].handle = bo_gem->gem_handle;
419 bufmgr_gem->exec_objects[index].relocation_count = bo_gem->reloc_count;
420 bufmgr_gem->exec_objects[index].relocs_ptr = (uintptr_t) bo_gem->relocs;
421 bufmgr_gem->exec_objects[index].alignment = 0;
422 bufmgr_gem->exec_objects[index].offset = 0;
423 bufmgr_gem->exec_bos[index] = bo;
424 bufmgr_gem->exec_count++;
428 drm_intel_add_validate_buffer2(drm_intel_bo *bo, int need_fence)
430 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
431 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
434 if (bo_gem->validate_index != -1) {
436 bufmgr_gem->exec2_objects[bo_gem->validate_index].flags |=
437 EXEC_OBJECT_NEEDS_FENCE;
441 /* Extend the array of validation entries as necessary. */
442 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
443 int new_size = bufmgr_gem->exec_size * 2;
448 bufmgr_gem->exec2_objects =
449 realloc(bufmgr_gem->exec2_objects,
450 sizeof(*bufmgr_gem->exec2_objects) * new_size);
451 bufmgr_gem->exec_bos =
452 realloc(bufmgr_gem->exec_bos,
453 sizeof(*bufmgr_gem->exec_bos) * new_size);
454 bufmgr_gem->exec_size = new_size;
457 index = bufmgr_gem->exec_count;
458 bo_gem->validate_index = index;
459 /* Fill in array entry */
460 bufmgr_gem->exec2_objects[index].handle = bo_gem->gem_handle;
461 bufmgr_gem->exec2_objects[index].relocation_count = bo_gem->reloc_count;
462 bufmgr_gem->exec2_objects[index].relocs_ptr = (uintptr_t)bo_gem->relocs;
463 bufmgr_gem->exec2_objects[index].alignment = 0;
464 bufmgr_gem->exec2_objects[index].offset = 0;
465 bufmgr_gem->exec_bos[index] = bo;
466 bufmgr_gem->exec2_objects[index].flags = 0;
467 bufmgr_gem->exec2_objects[index].rsvd1 = 0;
468 bufmgr_gem->exec2_objects[index].rsvd2 = 0;
470 bufmgr_gem->exec2_objects[index].flags |=
471 EXEC_OBJECT_NEEDS_FENCE;
473 bufmgr_gem->exec_count++;
476 #define RELOC_BUF_SIZE(x) ((I915_RELOC_HEADER + x * I915_RELOC0_STRIDE) * \
480 drm_intel_bo_gem_set_in_aperture_size(drm_intel_bufmgr_gem *bufmgr_gem,
481 drm_intel_bo_gem *bo_gem)
485 assert(!bo_gem->used_as_reloc_target);
487 /* The older chipsets are far-less flexible in terms of tiling,
488 * and require tiled buffer to be size aligned in the aperture.
489 * This means that in the worst possible case we will need a hole
490 * twice as large as the object in order for it to fit into the
491 * aperture. Optimal packing is for wimps.
493 size = bo_gem->bo.size;
494 if (bufmgr_gem->gen < 4 && bo_gem->tiling_mode != I915_TILING_NONE) {
497 if (bufmgr_gem->has_relaxed_fencing) {
498 if (bufmgr_gem->gen == 3)
499 min_size = 1024*1024;
503 while (min_size < size)
508 /* Account for worst-case alignment. */
512 bo_gem->reloc_tree_size = size;
516 drm_intel_setup_reloc_list(drm_intel_bo *bo)
518 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
519 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
520 unsigned int max_relocs = bufmgr_gem->max_relocs;
522 if (bo->size / 4 < max_relocs)
523 max_relocs = bo->size / 4;
525 bo_gem->relocs = malloc(max_relocs *
526 sizeof(struct drm_i915_gem_relocation_entry));
527 bo_gem->reloc_target_info = malloc(max_relocs *
528 sizeof(drm_intel_reloc_target));
529 if (bo_gem->relocs == NULL || bo_gem->reloc_target_info == NULL) {
530 bo_gem->has_error = true;
532 free (bo_gem->relocs);
533 bo_gem->relocs = NULL;
535 free (bo_gem->reloc_target_info);
536 bo_gem->reloc_target_info = NULL;
545 drm_intel_gem_bo_busy(drm_intel_bo *bo)
547 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
548 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
549 struct drm_i915_gem_busy busy;
553 busy.handle = bo_gem->gem_handle;
555 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_BUSY, &busy);
557 return (ret == 0 && busy.busy);
561 drm_intel_gem_bo_madvise_internal(drm_intel_bufmgr_gem *bufmgr_gem,
562 drm_intel_bo_gem *bo_gem, int state)
564 struct drm_i915_gem_madvise madv;
567 madv.handle = bo_gem->gem_handle;
570 drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MADVISE, &madv);
572 return madv.retained;
576 drm_intel_gem_bo_madvise(drm_intel_bo *bo, int madv)
578 return drm_intel_gem_bo_madvise_internal
579 ((drm_intel_bufmgr_gem *) bo->bufmgr,
580 (drm_intel_bo_gem *) bo,
584 /* drop the oldest entries that have been purged by the kernel */
586 drm_intel_gem_bo_cache_purge_bucket(drm_intel_bufmgr_gem *bufmgr_gem,
587 struct drm_intel_gem_bo_bucket *bucket)
589 while (!DRMLISTEMPTY(&bucket->head)) {
590 drm_intel_bo_gem *bo_gem;
592 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
593 bucket->head.next, head);
594 if (drm_intel_gem_bo_madvise_internal
595 (bufmgr_gem, bo_gem, I915_MADV_DONTNEED))
598 DRMLISTDEL(&bo_gem->head);
599 drm_intel_gem_bo_free(&bo_gem->bo);
603 static drm_intel_bo *
604 drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr,
608 uint32_t tiling_mode,
609 unsigned long stride)
611 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
612 drm_intel_bo_gem *bo_gem;
613 unsigned int page_size = getpagesize();
615 struct drm_intel_gem_bo_bucket *bucket;
616 bool alloc_from_cache;
617 unsigned long bo_size;
618 bool for_render = false;
620 if (flags & BO_ALLOC_FOR_RENDER)
623 /* Round the allocated size up to a power of two number of pages. */
624 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, size);
626 /* If we don't have caching at this size, don't actually round the
629 if (bucket == NULL) {
631 if (bo_size < page_size)
634 bo_size = bucket->size;
637 pthread_mutex_lock(&bufmgr_gem->lock);
638 /* Get a buffer out of the cache if available */
640 alloc_from_cache = false;
641 if (bucket != NULL && !DRMLISTEMPTY(&bucket->head)) {
643 /* Allocate new render-target BOs from the tail (MRU)
644 * of the list, as it will likely be hot in the GPU
645 * cache and in the aperture for us.
647 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
648 bucket->head.prev, head);
649 DRMLISTDEL(&bo_gem->head);
650 alloc_from_cache = true;
652 /* For non-render-target BOs (where we're probably
653 * going to map it first thing in order to fill it
654 * with data), check if the last BO in the cache is
655 * unbusy, and only reuse in that case. Otherwise,
656 * allocating a new buffer is probably faster than
657 * waiting for the GPU to finish.
659 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
660 bucket->head.next, head);
661 if (!drm_intel_gem_bo_busy(&bo_gem->bo)) {
662 alloc_from_cache = true;
663 DRMLISTDEL(&bo_gem->head);
667 if (alloc_from_cache) {
668 if (!drm_intel_gem_bo_madvise_internal
669 (bufmgr_gem, bo_gem, I915_MADV_WILLNEED)) {
670 drm_intel_gem_bo_free(&bo_gem->bo);
671 drm_intel_gem_bo_cache_purge_bucket(bufmgr_gem,
676 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
679 drm_intel_gem_bo_free(&bo_gem->bo);
684 pthread_mutex_unlock(&bufmgr_gem->lock);
686 if (!alloc_from_cache) {
687 struct drm_i915_gem_create create;
689 bo_gem = calloc(1, sizeof(*bo_gem));
693 bo_gem->bo.size = bo_size;
696 create.size = bo_size;
698 ret = drmIoctl(bufmgr_gem->fd,
699 DRM_IOCTL_I915_GEM_CREATE,
701 bo_gem->gem_handle = create.handle;
702 bo_gem->bo.handle = bo_gem->gem_handle;
707 bo_gem->bo.bufmgr = bufmgr;
709 bo_gem->tiling_mode = I915_TILING_NONE;
710 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
713 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
716 drm_intel_gem_bo_free(&bo_gem->bo);
720 DRMINITLISTHEAD(&bo_gem->name_list);
721 DRMINITLISTHEAD(&bo_gem->vma_list);
725 atomic_set(&bo_gem->refcount, 1);
726 bo_gem->validate_index = -1;
727 bo_gem->reloc_tree_fences = 0;
728 bo_gem->used_as_reloc_target = false;
729 bo_gem->has_error = false;
730 bo_gem->reusable = true;
732 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
734 DBG("bo_create: buf %d (%s) %ldb\n",
735 bo_gem->gem_handle, bo_gem->name, size);
740 static drm_intel_bo *
741 drm_intel_gem_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
744 unsigned int alignment)
746 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size,
748 I915_TILING_NONE, 0);
751 static drm_intel_bo *
752 drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr,
755 unsigned int alignment)
757 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, 0,
758 I915_TILING_NONE, 0);
761 static drm_intel_bo *
762 drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
763 int x, int y, int cpp, uint32_t *tiling_mode,
764 unsigned long *pitch, unsigned long flags)
766 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
767 unsigned long size, stride;
771 unsigned long aligned_y, height_alignment;
773 tiling = *tiling_mode;
775 /* If we're tiled, our allocations are in 8 or 32-row blocks,
776 * so failure to align our height means that we won't allocate
779 * If we're untiled, we still have to align to 2 rows high
780 * because the data port accesses 2x2 blocks even if the
781 * bottom row isn't to be rendered, so failure to align means
782 * we could walk off the end of the GTT and fault. This is
783 * documented on 965, and may be the case on older chipsets
784 * too so we try to be careful.
787 height_alignment = 2;
789 if ((bufmgr_gem->gen == 2) && tiling != I915_TILING_NONE)
790 height_alignment = 16;
791 else if (tiling == I915_TILING_X
792 || (IS_915(bufmgr_gem->pci_device)
793 && tiling == I915_TILING_Y))
794 height_alignment = 8;
795 else if (tiling == I915_TILING_Y)
796 height_alignment = 32;
797 aligned_y = ALIGN(y, height_alignment);
800 stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, tiling_mode);
801 size = stride * aligned_y;
802 size = drm_intel_gem_bo_tile_size(bufmgr_gem, size, tiling_mode);
803 } while (*tiling_mode != tiling);
806 if (tiling == I915_TILING_NONE)
809 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, flags,
814 * Returns a drm_intel_bo wrapping the given buffer object handle.
816 * This can be used when one application needs to pass a buffer object
820 drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
824 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
825 drm_intel_bo_gem *bo_gem;
827 struct drm_gem_open open_arg;
828 struct drm_i915_gem_get_tiling get_tiling;
831 /* At the moment most applications only have a few named bo.
832 * For instance, in a DRI client only the render buffers passed
833 * between X and the client are named. And since X returns the
834 * alternating names for the front/back buffer a linear search
835 * provides a sufficiently fast match.
837 for (list = bufmgr_gem->named.next;
838 list != &bufmgr_gem->named;
840 bo_gem = DRMLISTENTRY(drm_intel_bo_gem, list, name_list);
841 if (bo_gem->global_name == handle) {
842 drm_intel_gem_bo_reference(&bo_gem->bo);
847 bo_gem = calloc(1, sizeof(*bo_gem));
852 open_arg.name = handle;
853 ret = drmIoctl(bufmgr_gem->fd,
857 DBG("Couldn't reference %s handle 0x%08x: %s\n",
858 name, handle, strerror(errno));
862 bo_gem->bo.size = open_arg.size;
863 bo_gem->bo.offset = 0;
864 bo_gem->bo.virtual = NULL;
865 bo_gem->bo.bufmgr = bufmgr;
867 atomic_set(&bo_gem->refcount, 1);
868 bo_gem->validate_index = -1;
869 bo_gem->gem_handle = open_arg.handle;
870 bo_gem->bo.handle = open_arg.handle;
871 bo_gem->global_name = handle;
872 bo_gem->reusable = false;
874 VG_CLEAR(get_tiling);
875 get_tiling.handle = bo_gem->gem_handle;
876 ret = drmIoctl(bufmgr_gem->fd,
877 DRM_IOCTL_I915_GEM_GET_TILING,
880 drm_intel_gem_bo_unreference(&bo_gem->bo);
883 bo_gem->tiling_mode = get_tiling.tiling_mode;
884 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
885 /* XXX stride is unknown */
886 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
888 DRMINITLISTHEAD(&bo_gem->vma_list);
889 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
890 DBG("bo_create_from_handle: %d (%s)\n", handle, bo_gem->name);
896 drm_intel_gem_bo_free(drm_intel_bo *bo)
898 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
899 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
900 struct drm_gem_close close;
903 DRMLISTDEL(&bo_gem->vma_list);
904 if (bo_gem->mem_virtual) {
905 VG(VALGRIND_FREELIKE_BLOCK(bo_gem->mem_virtual, 0));
906 munmap(bo_gem->mem_virtual, bo_gem->bo.size);
907 bufmgr_gem->vma_count--;
909 if (bo_gem->gtt_virtual) {
910 munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
911 bufmgr_gem->vma_count--;
914 /* Close this object */
916 close.handle = bo_gem->gem_handle;
917 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close);
919 DBG("DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
920 bo_gem->gem_handle, bo_gem->name, strerror(errno));
925 /** Frees all cached buffers significantly older than @time. */
927 drm_intel_gem_cleanup_bo_cache(drm_intel_bufmgr_gem *bufmgr_gem, time_t time)
931 if (bufmgr_gem->time == time)
934 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
935 struct drm_intel_gem_bo_bucket *bucket =
936 &bufmgr_gem->cache_bucket[i];
938 while (!DRMLISTEMPTY(&bucket->head)) {
939 drm_intel_bo_gem *bo_gem;
941 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
942 bucket->head.next, head);
943 if (time - bo_gem->free_time <= 1)
946 DRMLISTDEL(&bo_gem->head);
948 drm_intel_gem_bo_free(&bo_gem->bo);
952 bufmgr_gem->time = time;
955 static void drm_intel_gem_bo_purge_vma_cache(drm_intel_bufmgr_gem *bufmgr_gem)
959 DBG("%s: cached=%d, open=%d, limit=%d\n", __FUNCTION__,
960 bufmgr_gem->vma_count, bufmgr_gem->vma_open, bufmgr_gem->vma_max);
962 if (bufmgr_gem->vma_max < 0)
965 /* We may need to evict a few entries in order to create new mmaps */
966 limit = bufmgr_gem->vma_max - 2*bufmgr_gem->vma_open;
970 while (bufmgr_gem->vma_count > limit) {
971 drm_intel_bo_gem *bo_gem;
973 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
974 bufmgr_gem->vma_cache.next,
976 assert(bo_gem->map_count == 0);
977 DRMLISTDELINIT(&bo_gem->vma_list);
979 if (bo_gem->mem_virtual) {
980 munmap(bo_gem->mem_virtual, bo_gem->bo.size);
981 bo_gem->mem_virtual = NULL;
982 bufmgr_gem->vma_count--;
984 if (bo_gem->gtt_virtual) {
985 munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
986 bo_gem->gtt_virtual = NULL;
987 bufmgr_gem->vma_count--;
992 static void drm_intel_gem_bo_close_vma(drm_intel_bufmgr_gem *bufmgr_gem,
993 drm_intel_bo_gem *bo_gem)
995 bufmgr_gem->vma_open--;
996 DRMLISTADDTAIL(&bo_gem->vma_list, &bufmgr_gem->vma_cache);
997 if (bo_gem->mem_virtual)
998 bufmgr_gem->vma_count++;
999 if (bo_gem->gtt_virtual)
1000 bufmgr_gem->vma_count++;
1001 drm_intel_gem_bo_purge_vma_cache(bufmgr_gem);
1004 static void drm_intel_gem_bo_open_vma(drm_intel_bufmgr_gem *bufmgr_gem,
1005 drm_intel_bo_gem *bo_gem)
1007 bufmgr_gem->vma_open++;
1008 DRMLISTDEL(&bo_gem->vma_list);
1009 if (bo_gem->mem_virtual)
1010 bufmgr_gem->vma_count--;
1011 if (bo_gem->gtt_virtual)
1012 bufmgr_gem->vma_count--;
1013 drm_intel_gem_bo_purge_vma_cache(bufmgr_gem);
1017 drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time)
1019 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1020 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1021 struct drm_intel_gem_bo_bucket *bucket;
1024 /* Unreference all the target buffers */
1025 for (i = 0; i < bo_gem->reloc_count; i++) {
1026 if (bo_gem->reloc_target_info[i].bo != bo) {
1027 drm_intel_gem_bo_unreference_locked_timed(bo_gem->
1028 reloc_target_info[i].bo,
1032 bo_gem->reloc_count = 0;
1033 bo_gem->used_as_reloc_target = false;
1035 DBG("bo_unreference final: %d (%s)\n",
1036 bo_gem->gem_handle, bo_gem->name);
1038 /* release memory associated with this object */
1039 if (bo_gem->reloc_target_info) {
1040 free(bo_gem->reloc_target_info);
1041 bo_gem->reloc_target_info = NULL;
1043 if (bo_gem->relocs) {
1044 free(bo_gem->relocs);
1045 bo_gem->relocs = NULL;
1048 /* Clear any left-over mappings */
1049 if (bo_gem->map_count) {
1050 DBG("bo freed with non-zero map-count %d\n", bo_gem->map_count);
1051 bo_gem->map_count = 0;
1052 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1055 DRMLISTDEL(&bo_gem->name_list);
1057 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, bo->size);
1058 /* Put the buffer into our internal cache for reuse if we can. */
1059 if (bufmgr_gem->bo_reuse && bo_gem->reusable && bucket != NULL &&
1060 drm_intel_gem_bo_madvise_internal(bufmgr_gem, bo_gem,
1061 I915_MADV_DONTNEED)) {
1062 bo_gem->free_time = time;
1064 bo_gem->name = NULL;
1065 bo_gem->validate_index = -1;
1067 DRMLISTADDTAIL(&bo_gem->head, &bucket->head);
1069 drm_intel_gem_bo_free(bo);
1073 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
1076 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1078 assert(atomic_read(&bo_gem->refcount) > 0);
1079 if (atomic_dec_and_test(&bo_gem->refcount))
1080 drm_intel_gem_bo_unreference_final(bo, time);
1083 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo)
1085 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1087 assert(atomic_read(&bo_gem->refcount) > 0);
1088 if (atomic_dec_and_test(&bo_gem->refcount)) {
1089 drm_intel_bufmgr_gem *bufmgr_gem =
1090 (drm_intel_bufmgr_gem *) bo->bufmgr;
1091 struct timespec time;
1093 clock_gettime(CLOCK_MONOTONIC, &time);
1095 pthread_mutex_lock(&bufmgr_gem->lock);
1096 drm_intel_gem_bo_unreference_final(bo, time.tv_sec);
1097 drm_intel_gem_cleanup_bo_cache(bufmgr_gem, time.tv_sec);
1098 pthread_mutex_unlock(&bufmgr_gem->lock);
1102 static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable)
1104 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1105 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1106 struct drm_i915_gem_set_domain set_domain;
1109 pthread_mutex_lock(&bufmgr_gem->lock);
1111 if (bo_gem->map_count++ == 0)
1112 drm_intel_gem_bo_open_vma(bufmgr_gem, bo_gem);
1114 if (!bo_gem->mem_virtual) {
1115 struct drm_i915_gem_mmap mmap_arg;
1117 DBG("bo_map: %d (%s), map_count=%d\n",
1118 bo_gem->gem_handle, bo_gem->name, bo_gem->map_count);
1121 mmap_arg.handle = bo_gem->gem_handle;
1122 mmap_arg.offset = 0;
1123 mmap_arg.size = bo->size;
1124 ret = drmIoctl(bufmgr_gem->fd,
1125 DRM_IOCTL_I915_GEM_MMAP,
1129 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1130 __FILE__, __LINE__, bo_gem->gem_handle,
1131 bo_gem->name, strerror(errno));
1132 if (--bo_gem->map_count == 0)
1133 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1134 pthread_mutex_unlock(&bufmgr_gem->lock);
1137 VG(VALGRIND_MALLOCLIKE_BLOCK(mmap_arg.addr_ptr, mmap_arg.size, 0, 1));
1138 bo_gem->mem_virtual = (void *)(uintptr_t) mmap_arg.addr_ptr;
1140 DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1141 bo_gem->mem_virtual);
1142 bo->virtual = bo_gem->mem_virtual;
1144 VG_CLEAR(set_domain);
1145 set_domain.handle = bo_gem->gem_handle;
1146 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
1148 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
1150 set_domain.write_domain = 0;
1151 ret = drmIoctl(bufmgr_gem->fd,
1152 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1155 DBG("%s:%d: Error setting to CPU domain %d: %s\n",
1156 __FILE__, __LINE__, bo_gem->gem_handle,
1161 bo_gem->mapped_cpu_write = true;
1163 pthread_mutex_unlock(&bufmgr_gem->lock);
1168 int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
1170 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1171 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1172 struct drm_i915_gem_set_domain set_domain;
1175 pthread_mutex_lock(&bufmgr_gem->lock);
1177 if (bo_gem->map_count++ == 0)
1178 drm_intel_gem_bo_open_vma(bufmgr_gem, bo_gem);
1180 /* Get a mapping of the buffer if we haven't before. */
1181 if (bo_gem->gtt_virtual == NULL) {
1182 struct drm_i915_gem_mmap_gtt mmap_arg;
1184 DBG("bo_map_gtt: mmap %d (%s), map_count=%d\n",
1185 bo_gem->gem_handle, bo_gem->name, bo_gem->map_count);
1188 mmap_arg.handle = bo_gem->gem_handle;
1190 /* Get the fake offset back... */
1191 ret = drmIoctl(bufmgr_gem->fd,
1192 DRM_IOCTL_I915_GEM_MMAP_GTT,
1196 DBG("%s:%d: Error preparing buffer map %d (%s): %s .\n",
1198 bo_gem->gem_handle, bo_gem->name,
1200 if (--bo_gem->map_count == 0)
1201 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1202 pthread_mutex_unlock(&bufmgr_gem->lock);
1207 bo_gem->gtt_virtual = mmap(0, bo->size, PROT_READ | PROT_WRITE,
1208 MAP_SHARED, bufmgr_gem->fd,
1210 if (bo_gem->gtt_virtual == MAP_FAILED) {
1211 bo_gem->gtt_virtual = NULL;
1213 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1215 bo_gem->gem_handle, bo_gem->name,
1217 if (--bo_gem->map_count == 0)
1218 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1219 pthread_mutex_unlock(&bufmgr_gem->lock);
1224 bo->virtual = bo_gem->gtt_virtual;
1226 DBG("bo_map_gtt: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1227 bo_gem->gtt_virtual);
1229 /* Now move it to the GTT domain so that the CPU caches are flushed */
1230 VG_CLEAR(set_domain);
1231 set_domain.handle = bo_gem->gem_handle;
1232 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1233 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
1234 ret = drmIoctl(bufmgr_gem->fd,
1235 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1238 DBG("%s:%d: Error setting domain %d: %s\n",
1239 __FILE__, __LINE__, bo_gem->gem_handle,
1243 pthread_mutex_unlock(&bufmgr_gem->lock);
1248 static int drm_intel_gem_bo_unmap(drm_intel_bo *bo)
1250 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1251 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1257 pthread_mutex_lock(&bufmgr_gem->lock);
1259 if (bo_gem->map_count <= 0) {
1260 DBG("attempted to unmap an unmapped bo\n");
1261 pthread_mutex_unlock(&bufmgr_gem->lock);
1262 /* Preserve the old behaviour of just treating this as a
1263 * no-op rather than reporting the error.
1268 if (bo_gem->mapped_cpu_write) {
1269 struct drm_i915_gem_sw_finish sw_finish;
1271 /* Cause a flush to happen if the buffer's pinned for
1272 * scanout, so the results show up in a timely manner.
1273 * Unlike GTT set domains, this only does work if the
1274 * buffer should be scanout-related.
1276 VG_CLEAR(sw_finish);
1277 sw_finish.handle = bo_gem->gem_handle;
1278 ret = drmIoctl(bufmgr_gem->fd,
1279 DRM_IOCTL_I915_GEM_SW_FINISH,
1281 ret = ret == -1 ? -errno : 0;
1283 bo_gem->mapped_cpu_write = false;
1286 /* We need to unmap after every innovation as we cannot track
1287 * an open vma for every bo as that will exhaasut the system
1288 * limits and cause later failures.
1290 if (--bo_gem->map_count == 0) {
1291 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1294 pthread_mutex_unlock(&bufmgr_gem->lock);
1299 int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo)
1301 return drm_intel_gem_bo_unmap(bo);
1305 drm_intel_gem_bo_subdata(drm_intel_bo *bo, unsigned long offset,
1306 unsigned long size, const void *data)
1308 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1309 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1310 struct drm_i915_gem_pwrite pwrite;
1314 pwrite.handle = bo_gem->gem_handle;
1315 pwrite.offset = offset;
1317 pwrite.data_ptr = (uint64_t) (uintptr_t) data;
1318 ret = drmIoctl(bufmgr_gem->fd,
1319 DRM_IOCTL_I915_GEM_PWRITE,
1323 DBG("%s:%d: Error writing data to buffer %d: (%d %d) %s .\n",
1324 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1325 (int)size, strerror(errno));
1332 drm_intel_gem_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id)
1334 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1335 struct drm_i915_get_pipe_from_crtc_id get_pipe_from_crtc_id;
1338 VG_CLEAR(get_pipe_from_crtc_id);
1339 get_pipe_from_crtc_id.crtc_id = crtc_id;
1340 ret = drmIoctl(bufmgr_gem->fd,
1341 DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID,
1342 &get_pipe_from_crtc_id);
1344 /* We return -1 here to signal that we don't
1345 * know which pipe is associated with this crtc.
1346 * This lets the caller know that this information
1347 * isn't available; using the wrong pipe for
1348 * vblank waiting can cause the chipset to lock up
1353 return get_pipe_from_crtc_id.pipe;
1357 drm_intel_gem_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
1358 unsigned long size, void *data)
1360 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1361 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1362 struct drm_i915_gem_pread pread;
1366 pread.handle = bo_gem->gem_handle;
1367 pread.offset = offset;
1369 pread.data_ptr = (uint64_t) (uintptr_t) data;
1370 ret = drmIoctl(bufmgr_gem->fd,
1371 DRM_IOCTL_I915_GEM_PREAD,
1375 DBG("%s:%d: Error reading data from buffer %d: (%d %d) %s .\n",
1376 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1377 (int)size, strerror(errno));
1383 /** Waits for all GPU rendering with the object to have completed. */
1385 drm_intel_gem_bo_wait_rendering(drm_intel_bo *bo)
1387 drm_intel_gem_bo_start_gtt_access(bo, 1);
1391 * Sets the object to the GTT read and possibly write domain, used by the X
1392 * 2D driver in the absence of kernel support to do drm_intel_gem_bo_map_gtt().
1394 * In combination with drm_intel_gem_bo_pin() and manual fence management, we
1395 * can do tiled pixmaps this way.
1398 drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable)
1400 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1401 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1402 struct drm_i915_gem_set_domain set_domain;
1405 VG_CLEAR(set_domain);
1406 set_domain.handle = bo_gem->gem_handle;
1407 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1408 set_domain.write_domain = write_enable ? I915_GEM_DOMAIN_GTT : 0;
1409 ret = drmIoctl(bufmgr_gem->fd,
1410 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1413 DBG("%s:%d: Error setting memory domains %d (%08x %08x): %s .\n",
1414 __FILE__, __LINE__, bo_gem->gem_handle,
1415 set_domain.read_domains, set_domain.write_domain,
1421 drm_intel_bufmgr_gem_destroy(drm_intel_bufmgr *bufmgr)
1423 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1426 free(bufmgr_gem->exec2_objects);
1427 free(bufmgr_gem->exec_objects);
1428 free(bufmgr_gem->exec_bos);
1430 pthread_mutex_destroy(&bufmgr_gem->lock);
1432 /* Free any cached buffer objects we were going to reuse */
1433 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
1434 struct drm_intel_gem_bo_bucket *bucket =
1435 &bufmgr_gem->cache_bucket[i];
1436 drm_intel_bo_gem *bo_gem;
1438 while (!DRMLISTEMPTY(&bucket->head)) {
1439 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1440 bucket->head.next, head);
1441 DRMLISTDEL(&bo_gem->head);
1443 drm_intel_gem_bo_free(&bo_gem->bo);
1451 * Adds the target buffer to the validation list and adds the relocation
1452 * to the reloc_buffer's relocation list.
1454 * The relocation entry at the given offset must already contain the
1455 * precomputed relocation value, because the kernel will optimize out
1456 * the relocation entry write when the buffer hasn't moved from the
1457 * last known offset in target_bo.
1460 do_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1461 drm_intel_bo *target_bo, uint32_t target_offset,
1462 uint32_t read_domains, uint32_t write_domain,
1465 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1466 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1467 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
1468 bool fenced_command;
1470 if (bo_gem->has_error)
1473 if (target_bo_gem->has_error) {
1474 bo_gem->has_error = true;
1478 /* We never use HW fences for rendering on 965+ */
1479 if (bufmgr_gem->gen >= 4)
1482 fenced_command = need_fence;
1483 if (target_bo_gem->tiling_mode == I915_TILING_NONE)
1486 /* Create a new relocation list if needed */
1487 if (bo_gem->relocs == NULL && drm_intel_setup_reloc_list(bo))
1490 /* Check overflow */
1491 assert(bo_gem->reloc_count < bufmgr_gem->max_relocs);
1494 assert(offset <= bo->size - 4);
1495 assert((write_domain & (write_domain - 1)) == 0);
1497 /* Make sure that we're not adding a reloc to something whose size has
1498 * already been accounted for.
1500 assert(!bo_gem->used_as_reloc_target);
1501 if (target_bo_gem != bo_gem) {
1502 target_bo_gem->used_as_reloc_target = true;
1503 bo_gem->reloc_tree_size += target_bo_gem->reloc_tree_size;
1505 /* An object needing a fence is a tiled buffer, so it won't have
1506 * relocs to other buffers.
1509 target_bo_gem->reloc_tree_fences = 1;
1510 bo_gem->reloc_tree_fences += target_bo_gem->reloc_tree_fences;
1512 bo_gem->relocs[bo_gem->reloc_count].offset = offset;
1513 bo_gem->relocs[bo_gem->reloc_count].delta = target_offset;
1514 bo_gem->relocs[bo_gem->reloc_count].target_handle =
1515 target_bo_gem->gem_handle;
1516 bo_gem->relocs[bo_gem->reloc_count].read_domains = read_domains;
1517 bo_gem->relocs[bo_gem->reloc_count].write_domain = write_domain;
1518 bo_gem->relocs[bo_gem->reloc_count].presumed_offset = target_bo->offset;
1520 bo_gem->reloc_target_info[bo_gem->reloc_count].bo = target_bo;
1521 if (target_bo != bo)
1522 drm_intel_gem_bo_reference(target_bo);
1524 bo_gem->reloc_target_info[bo_gem->reloc_count].flags =
1525 DRM_INTEL_RELOC_FENCE;
1527 bo_gem->reloc_target_info[bo_gem->reloc_count].flags = 0;
1529 bo_gem->reloc_count++;
1535 drm_intel_gem_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1536 drm_intel_bo *target_bo, uint32_t target_offset,
1537 uint32_t read_domains, uint32_t write_domain)
1539 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1541 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1542 read_domains, write_domain,
1543 !bufmgr_gem->fenced_relocs);
1547 drm_intel_gem_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
1548 drm_intel_bo *target_bo,
1549 uint32_t target_offset,
1550 uint32_t read_domains, uint32_t write_domain)
1552 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1553 read_domains, write_domain, true);
1557 drm_intel_gem_bo_get_reloc_count(drm_intel_bo *bo)
1559 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1561 return bo_gem->reloc_count;
1565 * Removes existing relocation entries in the BO after "start".
1567 * This allows a user to avoid a two-step process for state setup with
1568 * counting up all the buffer objects and doing a
1569 * drm_intel_bufmgr_check_aperture_space() before emitting any of the
1570 * relocations for the state setup. Instead, save the state of the
1571 * batchbuffer including drm_intel_gem_get_reloc_count(), emit all the
1572 * state, and then check if it still fits in the aperture.
1574 * Any further drm_intel_bufmgr_check_aperture_space() queries
1575 * involving this buffer in the tree are undefined after this call.
1578 drm_intel_gem_bo_clear_relocs(drm_intel_bo *bo, int start)
1580 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1582 struct timespec time;
1584 clock_gettime(CLOCK_MONOTONIC, &time);
1586 assert(bo_gem->reloc_count >= start);
1587 /* Unreference the cleared target buffers */
1588 for (i = start; i < bo_gem->reloc_count; i++) {
1589 if (bo_gem->reloc_target_info[i].bo != bo) {
1590 drm_intel_gem_bo_unreference_locked_timed(bo_gem->
1591 reloc_target_info[i].bo,
1595 bo_gem->reloc_count = start;
1599 * Walk the tree of relocations rooted at BO and accumulate the list of
1600 * validations to be performed and update the relocation buffers with
1601 * index values into the validation list.
1604 drm_intel_gem_bo_process_reloc(drm_intel_bo *bo)
1606 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1609 if (bo_gem->relocs == NULL)
1612 for (i = 0; i < bo_gem->reloc_count; i++) {
1613 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1615 if (target_bo == bo)
1618 /* Continue walking the tree depth-first. */
1619 drm_intel_gem_bo_process_reloc(target_bo);
1621 /* Add the target to the validate list */
1622 drm_intel_add_validate_buffer(target_bo);
1627 drm_intel_gem_bo_process_reloc2(drm_intel_bo *bo)
1629 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1632 if (bo_gem->relocs == NULL)
1635 for (i = 0; i < bo_gem->reloc_count; i++) {
1636 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1639 if (target_bo == bo)
1642 /* Continue walking the tree depth-first. */
1643 drm_intel_gem_bo_process_reloc2(target_bo);
1645 need_fence = (bo_gem->reloc_target_info[i].flags &
1646 DRM_INTEL_RELOC_FENCE);
1648 /* Add the target to the validate list */
1649 drm_intel_add_validate_buffer2(target_bo, need_fence);
1655 drm_intel_update_buffer_offsets(drm_intel_bufmgr_gem *bufmgr_gem)
1659 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1660 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1661 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1663 /* Update the buffer offset */
1664 if (bufmgr_gem->exec_objects[i].offset != bo->offset) {
1665 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1666 bo_gem->gem_handle, bo_gem->name, bo->offset,
1667 (unsigned long long)bufmgr_gem->exec_objects[i].
1669 bo->offset = bufmgr_gem->exec_objects[i].offset;
1675 drm_intel_update_buffer_offsets2 (drm_intel_bufmgr_gem *bufmgr_gem)
1679 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1680 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1681 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1683 /* Update the buffer offset */
1684 if (bufmgr_gem->exec2_objects[i].offset != bo->offset) {
1685 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1686 bo_gem->gem_handle, bo_gem->name, bo->offset,
1687 (unsigned long long)bufmgr_gem->exec2_objects[i].offset);
1688 bo->offset = bufmgr_gem->exec2_objects[i].offset;
1694 drm_intel_gem_bo_exec(drm_intel_bo *bo, int used,
1695 drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
1697 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1698 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1699 struct drm_i915_gem_execbuffer execbuf;
1702 if (bo_gem->has_error)
1705 pthread_mutex_lock(&bufmgr_gem->lock);
1706 /* Update indices and set up the validate list. */
1707 drm_intel_gem_bo_process_reloc(bo);
1709 /* Add the batch buffer to the validation list. There are no
1710 * relocations pointing to it.
1712 drm_intel_add_validate_buffer(bo);
1715 execbuf.buffers_ptr = (uintptr_t) bufmgr_gem->exec_objects;
1716 execbuf.buffer_count = bufmgr_gem->exec_count;
1717 execbuf.batch_start_offset = 0;
1718 execbuf.batch_len = used;
1719 execbuf.cliprects_ptr = (uintptr_t) cliprects;
1720 execbuf.num_cliprects = num_cliprects;
1724 ret = drmIoctl(bufmgr_gem->fd,
1725 DRM_IOCTL_I915_GEM_EXECBUFFER,
1729 if (errno == ENOSPC) {
1730 DBG("Execbuffer fails to pin. "
1731 "Estimate: %u. Actual: %u. Available: %u\n",
1732 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
1735 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
1738 (unsigned int)bufmgr_gem->gtt_size);
1741 drm_intel_update_buffer_offsets(bufmgr_gem);
1743 if (bufmgr_gem->bufmgr.debug)
1744 drm_intel_gem_dump_validation_list(bufmgr_gem);
1746 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1747 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1748 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1750 /* Disconnect the buffer from the validate list */
1751 bo_gem->validate_index = -1;
1752 bufmgr_gem->exec_bos[i] = NULL;
1754 bufmgr_gem->exec_count = 0;
1755 pthread_mutex_unlock(&bufmgr_gem->lock);
1761 drm_intel_gem_bo_mrb_exec2(drm_intel_bo *bo, int used,
1762 drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
1765 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1766 struct drm_i915_gem_execbuffer2 execbuf;
1769 switch (flags & 0x7) {
1773 if (!bufmgr_gem->has_blt)
1777 if (!bufmgr_gem->has_bsd)
1780 case I915_EXEC_RENDER:
1781 case I915_EXEC_DEFAULT:
1785 pthread_mutex_lock(&bufmgr_gem->lock);
1786 /* Update indices and set up the validate list. */
1787 drm_intel_gem_bo_process_reloc2(bo);
1789 /* Add the batch buffer to the validation list. There are no relocations
1792 drm_intel_add_validate_buffer2(bo, 0);
1795 execbuf.buffers_ptr = (uintptr_t)bufmgr_gem->exec2_objects;
1796 execbuf.buffer_count = bufmgr_gem->exec_count;
1797 execbuf.batch_start_offset = 0;
1798 execbuf.batch_len = used;
1799 execbuf.cliprects_ptr = (uintptr_t)cliprects;
1800 execbuf.num_cliprects = num_cliprects;
1803 execbuf.flags = flags;
1807 ret = drmIoctl(bufmgr_gem->fd,
1808 DRM_IOCTL_I915_GEM_EXECBUFFER2,
1812 if (ret == -ENOSPC) {
1813 DBG("Execbuffer fails to pin. "
1814 "Estimate: %u. Actual: %u. Available: %u\n",
1815 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
1816 bufmgr_gem->exec_count),
1817 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
1818 bufmgr_gem->exec_count),
1819 (unsigned int) bufmgr_gem->gtt_size);
1822 drm_intel_update_buffer_offsets2(bufmgr_gem);
1824 if (bufmgr_gem->bufmgr.debug)
1825 drm_intel_gem_dump_validation_list(bufmgr_gem);
1827 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1828 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1829 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1831 /* Disconnect the buffer from the validate list */
1832 bo_gem->validate_index = -1;
1833 bufmgr_gem->exec_bos[i] = NULL;
1835 bufmgr_gem->exec_count = 0;
1836 pthread_mutex_unlock(&bufmgr_gem->lock);
1842 drm_intel_gem_bo_exec2(drm_intel_bo *bo, int used,
1843 drm_clip_rect_t *cliprects, int num_cliprects,
1846 return drm_intel_gem_bo_mrb_exec2(bo, used,
1847 cliprects, num_cliprects, DR4,
1852 drm_intel_gem_bo_pin(drm_intel_bo *bo, uint32_t alignment)
1854 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1855 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1856 struct drm_i915_gem_pin pin;
1860 pin.handle = bo_gem->gem_handle;
1861 pin.alignment = alignment;
1863 ret = drmIoctl(bufmgr_gem->fd,
1864 DRM_IOCTL_I915_GEM_PIN,
1869 bo->offset = pin.offset;
1874 drm_intel_gem_bo_unpin(drm_intel_bo *bo)
1876 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1877 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1878 struct drm_i915_gem_unpin unpin;
1882 unpin.handle = bo_gem->gem_handle;
1884 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_UNPIN, &unpin);
1892 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
1893 uint32_t tiling_mode,
1896 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1897 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1898 struct drm_i915_gem_set_tiling set_tiling;
1901 if (bo_gem->global_name == 0 &&
1902 tiling_mode == bo_gem->tiling_mode &&
1903 stride == bo_gem->stride)
1906 memset(&set_tiling, 0, sizeof(set_tiling));
1908 /* set_tiling is slightly broken and overwrites the
1909 * input on the error path, so we have to open code
1912 set_tiling.handle = bo_gem->gem_handle;
1913 set_tiling.tiling_mode = tiling_mode;
1914 set_tiling.stride = stride;
1916 ret = ioctl(bufmgr_gem->fd,
1917 DRM_IOCTL_I915_GEM_SET_TILING,
1919 } while (ret == -1 && (errno == EINTR || errno == EAGAIN));
1923 bo_gem->tiling_mode = set_tiling.tiling_mode;
1924 bo_gem->swizzle_mode = set_tiling.swizzle_mode;
1925 bo_gem->stride = set_tiling.stride;
1930 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1933 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1934 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1937 /* Linear buffers have no stride. By ensuring that we only ever use
1938 * stride 0 with linear buffers, we simplify our code.
1940 if (*tiling_mode == I915_TILING_NONE)
1943 ret = drm_intel_gem_bo_set_tiling_internal(bo, *tiling_mode, stride);
1945 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
1947 *tiling_mode = bo_gem->tiling_mode;
1952 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1953 uint32_t * swizzle_mode)
1955 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1957 *tiling_mode = bo_gem->tiling_mode;
1958 *swizzle_mode = bo_gem->swizzle_mode;
1963 drm_intel_gem_bo_flink(drm_intel_bo *bo, uint32_t * name)
1965 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1966 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1969 if (!bo_gem->global_name) {
1970 struct drm_gem_flink flink;
1973 flink.handle = bo_gem->gem_handle;
1975 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_FLINK, &flink);
1979 bo_gem->global_name = flink.name;
1980 bo_gem->reusable = false;
1982 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
1985 *name = bo_gem->global_name;
1990 * Enables unlimited caching of buffer objects for reuse.
1992 * This is potentially very memory expensive, as the cache at each bucket
1993 * size is only bounded by how many buffers of that size we've managed to have
1994 * in flight at once.
1997 drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr)
1999 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
2001 bufmgr_gem->bo_reuse = true;
2005 * Enable use of fenced reloc type.
2007 * New code should enable this to avoid unnecessary fence register
2008 * allocation. If this option is not enabled, all relocs will have fence
2009 * register allocated.
2012 drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr)
2014 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
2016 if (bufmgr_gem->bufmgr.bo_exec == drm_intel_gem_bo_exec2)
2017 bufmgr_gem->fenced_relocs = true;
2021 * Return the additional aperture space required by the tree of buffer objects
2025 drm_intel_gem_bo_get_aperture_space(drm_intel_bo *bo)
2027 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2031 if (bo == NULL || bo_gem->included_in_check_aperture)
2035 bo_gem->included_in_check_aperture = true;
2037 for (i = 0; i < bo_gem->reloc_count; i++)
2039 drm_intel_gem_bo_get_aperture_space(bo_gem->
2040 reloc_target_info[i].bo);
2046 * Count the number of buffers in this list that need a fence reg
2048 * If the count is greater than the number of available regs, we'll have
2049 * to ask the caller to resubmit a batch with fewer tiled buffers.
2051 * This function over-counts if the same buffer is used multiple times.
2054 drm_intel_gem_total_fences(drm_intel_bo ** bo_array, int count)
2057 unsigned int total = 0;
2059 for (i = 0; i < count; i++) {
2060 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
2065 total += bo_gem->reloc_tree_fences;
2071 * Clear the flag set by drm_intel_gem_bo_get_aperture_space() so we're ready
2072 * for the next drm_intel_bufmgr_check_aperture_space() call.
2075 drm_intel_gem_bo_clear_aperture_space_flag(drm_intel_bo *bo)
2077 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2080 if (bo == NULL || !bo_gem->included_in_check_aperture)
2083 bo_gem->included_in_check_aperture = false;
2085 for (i = 0; i < bo_gem->reloc_count; i++)
2086 drm_intel_gem_bo_clear_aperture_space_flag(bo_gem->
2087 reloc_target_info[i].bo);
2091 * Return a conservative estimate for the amount of aperture required
2092 * for a collection of buffers. This may double-count some buffers.
2095 drm_intel_gem_estimate_batch_space(drm_intel_bo **bo_array, int count)
2098 unsigned int total = 0;
2100 for (i = 0; i < count; i++) {
2101 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
2103 total += bo_gem->reloc_tree_size;
2109 * Return the amount of aperture needed for a collection of buffers.
2110 * This avoids double counting any buffers, at the cost of looking
2111 * at every buffer in the set.
2114 drm_intel_gem_compute_batch_space(drm_intel_bo **bo_array, int count)
2117 unsigned int total = 0;
2119 for (i = 0; i < count; i++) {
2120 total += drm_intel_gem_bo_get_aperture_space(bo_array[i]);
2121 /* For the first buffer object in the array, we get an
2122 * accurate count back for its reloc_tree size (since nothing
2123 * had been flagged as being counted yet). We can save that
2124 * value out as a more conservative reloc_tree_size that
2125 * avoids double-counting target buffers. Since the first
2126 * buffer happens to usually be the batch buffer in our
2127 * callers, this can pull us back from doing the tree
2128 * walk on every new batch emit.
2131 drm_intel_bo_gem *bo_gem =
2132 (drm_intel_bo_gem *) bo_array[i];
2133 bo_gem->reloc_tree_size = total;
2137 for (i = 0; i < count; i++)
2138 drm_intel_gem_bo_clear_aperture_space_flag(bo_array[i]);
2143 * Return -1 if the batchbuffer should be flushed before attempting to
2144 * emit rendering referencing the buffers pointed to by bo_array.
2146 * This is required because if we try to emit a batchbuffer with relocations
2147 * to a tree of buffers that won't simultaneously fit in the aperture,
2148 * the rendering will return an error at a point where the software is not
2149 * prepared to recover from it.
2151 * However, we also want to emit the batchbuffer significantly before we reach
2152 * the limit, as a series of batchbuffers each of which references buffers
2153 * covering almost all of the aperture means that at each emit we end up
2154 * waiting to evict a buffer from the last rendering, and we get synchronous
2155 * performance. By emitting smaller batchbuffers, we eat some CPU overhead to
2156 * get better parallelism.
2159 drm_intel_gem_check_aperture_space(drm_intel_bo **bo_array, int count)
2161 drm_intel_bufmgr_gem *bufmgr_gem =
2162 (drm_intel_bufmgr_gem *) bo_array[0]->bufmgr;
2163 unsigned int total = 0;
2164 unsigned int threshold = bufmgr_gem->gtt_size * 3 / 4;
2167 /* Check for fence reg constraints if necessary */
2168 if (bufmgr_gem->available_fences) {
2169 total_fences = drm_intel_gem_total_fences(bo_array, count);
2170 if (total_fences > bufmgr_gem->available_fences)
2174 total = drm_intel_gem_estimate_batch_space(bo_array, count);
2176 if (total > threshold)
2177 total = drm_intel_gem_compute_batch_space(bo_array, count);
2179 if (total > threshold) {
2180 DBG("check_space: overflowed available aperture, "
2182 total / 1024, (int)bufmgr_gem->gtt_size / 1024);
2185 DBG("drm_check_space: total %dkb vs bufgr %dkb\n", total / 1024,
2186 (int)bufmgr_gem->gtt_size / 1024);
2192 * Disable buffer reuse for objects which are shared with the kernel
2193 * as scanout buffers
2196 drm_intel_gem_bo_disable_reuse(drm_intel_bo *bo)
2198 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2200 bo_gem->reusable = false;
2205 drm_intel_gem_bo_is_reusable(drm_intel_bo *bo)
2207 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2209 return bo_gem->reusable;
2213 _drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
2215 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2218 for (i = 0; i < bo_gem->reloc_count; i++) {
2219 if (bo_gem->reloc_target_info[i].bo == target_bo)
2221 if (bo == bo_gem->reloc_target_info[i].bo)
2223 if (_drm_intel_gem_bo_references(bo_gem->reloc_target_info[i].bo,
2231 /** Return true if target_bo is referenced by bo's relocation tree. */
2233 drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
2235 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
2237 if (bo == NULL || target_bo == NULL)
2239 if (target_bo_gem->used_as_reloc_target)
2240 return _drm_intel_gem_bo_references(bo, target_bo);
2245 add_bucket(drm_intel_bufmgr_gem *bufmgr_gem, int size)
2247 unsigned int i = bufmgr_gem->num_buckets;
2249 assert(i < ARRAY_SIZE(bufmgr_gem->cache_bucket));
2251 DRMINITLISTHEAD(&bufmgr_gem->cache_bucket[i].head);
2252 bufmgr_gem->cache_bucket[i].size = size;
2253 bufmgr_gem->num_buckets++;
2257 init_cache_buckets(drm_intel_bufmgr_gem *bufmgr_gem)
2259 unsigned long size, cache_max_size = 64 * 1024 * 1024;
2261 /* OK, so power of two buckets was too wasteful of memory.
2262 * Give 3 other sizes between each power of two, to hopefully
2263 * cover things accurately enough. (The alternative is
2264 * probably to just go for exact matching of sizes, and assume
2265 * that for things like composited window resize the tiled
2266 * width/height alignment and rounding of sizes to pages will
2267 * get us useful cache hit rates anyway)
2269 add_bucket(bufmgr_gem, 4096);
2270 add_bucket(bufmgr_gem, 4096 * 2);
2271 add_bucket(bufmgr_gem, 4096 * 3);
2273 /* Initialize the linked lists for BO reuse cache. */
2274 for (size = 4 * 4096; size <= cache_max_size; size *= 2) {
2275 add_bucket(bufmgr_gem, size);
2277 add_bucket(bufmgr_gem, size + size * 1 / 4);
2278 add_bucket(bufmgr_gem, size + size * 2 / 4);
2279 add_bucket(bufmgr_gem, size + size * 3 / 4);
2284 drm_intel_bufmgr_gem_set_vma_cache_size(drm_intel_bufmgr *bufmgr, int limit)
2286 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
2288 bufmgr_gem->vma_max = limit;
2290 drm_intel_gem_bo_purge_vma_cache(bufmgr_gem);
2294 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
2295 * and manage map buffer objections.
2297 * \param fd File descriptor of the opened DRM device.
2300 drm_intel_bufmgr_gem_init(int fd, int batch_size)
2302 drm_intel_bufmgr_gem *bufmgr_gem;
2303 struct drm_i915_gem_get_aperture aperture;
2304 drm_i915_getparam_t gp;
2308 bufmgr_gem = calloc(1, sizeof(*bufmgr_gem));
2309 if (bufmgr_gem == NULL)
2312 bufmgr_gem->fd = fd;
2314 if (pthread_mutex_init(&bufmgr_gem->lock, NULL) != 0) {
2319 ret = drmIoctl(bufmgr_gem->fd,
2320 DRM_IOCTL_I915_GEM_GET_APERTURE,
2324 bufmgr_gem->gtt_size = aperture.aper_available_size;
2326 fprintf(stderr, "DRM_IOCTL_I915_GEM_APERTURE failed: %s\n",
2328 bufmgr_gem->gtt_size = 128 * 1024 * 1024;
2329 fprintf(stderr, "Assuming %dkB available aperture size.\n"
2330 "May lead to reduced performance or incorrect "
2332 (int)bufmgr_gem->gtt_size / 1024);
2336 gp.param = I915_PARAM_CHIPSET_ID;
2337 gp.value = &bufmgr_gem->pci_device;
2338 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2340 fprintf(stderr, "get chip id failed: %d [%d]\n", ret, errno);
2341 fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value);
2344 if (IS_GEN2(bufmgr_gem->pci_device))
2345 bufmgr_gem->gen = 2;
2346 else if (IS_GEN3(bufmgr_gem->pci_device))
2347 bufmgr_gem->gen = 3;
2348 else if (IS_GEN4(bufmgr_gem->pci_device))
2349 bufmgr_gem->gen = 4;
2350 else if (IS_GEN5(bufmgr_gem->pci_device))
2351 bufmgr_gem->gen = 5;
2352 else if (IS_GEN6(bufmgr_gem->pci_device))
2353 bufmgr_gem->gen = 6;
2354 else if (IS_GEN7(bufmgr_gem->pci_device))
2355 bufmgr_gem->gen = 7;
2359 if (IS_GEN3(bufmgr_gem->pci_device) &&
2360 bufmgr_gem->gtt_size > 256*1024*1024) {
2361 /* The unmappable part of gtt on gen 3 (i.e. above 256MB) can't
2362 * be used for tiled blits. To simplify the accounting, just
2363 * substract the unmappable part (fixed to 256MB on all known
2364 * gen3 devices) if the kernel advertises it. */
2365 bufmgr_gem->gtt_size -= 256*1024*1024;
2370 gp.param = I915_PARAM_HAS_EXECBUF2;
2371 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2375 gp.param = I915_PARAM_HAS_BSD;
2376 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2377 bufmgr_gem->has_bsd = ret == 0;
2379 gp.param = I915_PARAM_HAS_BLT;
2380 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2381 bufmgr_gem->has_blt = ret == 0;
2383 gp.param = I915_PARAM_HAS_RELAXED_FENCING;
2384 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2385 bufmgr_gem->has_relaxed_fencing = ret == 0;
2387 gp.param = I915_PARAM_HAS_LLC;
2388 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2389 if (ret == -EINVAL) {
2390 /* Kernel does not supports HAS_LLC query, fallback to GPU
2391 * generation detection and assume that we have LLC on GEN6/7
2393 bufmgr_gem->has_llc = (IS_GEN6(bufmgr_gem->pci_device) |
2394 IS_GEN7(bufmgr_gem->pci_device));
2396 bufmgr_gem->has_llc = ret == 0;
2398 if (bufmgr_gem->gen < 4) {
2399 gp.param = I915_PARAM_NUM_FENCES_AVAIL;
2400 gp.value = &bufmgr_gem->available_fences;
2401 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2403 fprintf(stderr, "get fences failed: %d [%d]\n", ret,
2405 fprintf(stderr, "param: %d, val: %d\n", gp.param,
2407 bufmgr_gem->available_fences = 0;
2409 /* XXX The kernel reports the total number of fences,
2410 * including any that may be pinned.
2412 * We presume that there will be at least one pinned
2413 * fence for the scanout buffer, but there may be more
2414 * than one scanout and the user may be manually
2415 * pinning buffers. Let's move to execbuffer2 and
2416 * thereby forget the insanity of using fences...
2418 bufmgr_gem->available_fences -= 2;
2419 if (bufmgr_gem->available_fences < 0)
2420 bufmgr_gem->available_fences = 0;
2424 /* Let's go with one relocation per every 2 dwords (but round down a bit
2425 * since a power of two will mean an extra page allocation for the reloc
2428 * Every 4 was too few for the blender benchmark.
2430 bufmgr_gem->max_relocs = batch_size / sizeof(uint32_t) / 2 - 2;
2432 bufmgr_gem->bufmgr.bo_alloc = drm_intel_gem_bo_alloc;
2433 bufmgr_gem->bufmgr.bo_alloc_for_render =
2434 drm_intel_gem_bo_alloc_for_render;
2435 bufmgr_gem->bufmgr.bo_alloc_tiled = drm_intel_gem_bo_alloc_tiled;
2436 bufmgr_gem->bufmgr.bo_reference = drm_intel_gem_bo_reference;
2437 bufmgr_gem->bufmgr.bo_unreference = drm_intel_gem_bo_unreference;
2438 bufmgr_gem->bufmgr.bo_map = drm_intel_gem_bo_map;
2439 bufmgr_gem->bufmgr.bo_unmap = drm_intel_gem_bo_unmap;
2440 bufmgr_gem->bufmgr.bo_subdata = drm_intel_gem_bo_subdata;
2441 bufmgr_gem->bufmgr.bo_get_subdata = drm_intel_gem_bo_get_subdata;
2442 bufmgr_gem->bufmgr.bo_wait_rendering = drm_intel_gem_bo_wait_rendering;
2443 bufmgr_gem->bufmgr.bo_emit_reloc = drm_intel_gem_bo_emit_reloc;
2444 bufmgr_gem->bufmgr.bo_emit_reloc_fence = drm_intel_gem_bo_emit_reloc_fence;
2445 bufmgr_gem->bufmgr.bo_pin = drm_intel_gem_bo_pin;
2446 bufmgr_gem->bufmgr.bo_unpin = drm_intel_gem_bo_unpin;
2447 bufmgr_gem->bufmgr.bo_get_tiling = drm_intel_gem_bo_get_tiling;
2448 bufmgr_gem->bufmgr.bo_set_tiling = drm_intel_gem_bo_set_tiling;
2449 bufmgr_gem->bufmgr.bo_flink = drm_intel_gem_bo_flink;
2450 /* Use the new one if available */
2452 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec2;
2453 bufmgr_gem->bufmgr.bo_mrb_exec = drm_intel_gem_bo_mrb_exec2;
2455 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec;
2456 bufmgr_gem->bufmgr.bo_busy = drm_intel_gem_bo_busy;
2457 bufmgr_gem->bufmgr.bo_madvise = drm_intel_gem_bo_madvise;
2458 bufmgr_gem->bufmgr.destroy = drm_intel_bufmgr_gem_destroy;
2459 bufmgr_gem->bufmgr.debug = 0;
2460 bufmgr_gem->bufmgr.check_aperture_space =
2461 drm_intel_gem_check_aperture_space;
2462 bufmgr_gem->bufmgr.bo_disable_reuse = drm_intel_gem_bo_disable_reuse;
2463 bufmgr_gem->bufmgr.bo_is_reusable = drm_intel_gem_bo_is_reusable;
2464 bufmgr_gem->bufmgr.get_pipe_from_crtc_id =
2465 drm_intel_gem_get_pipe_from_crtc_id;
2466 bufmgr_gem->bufmgr.bo_references = drm_intel_gem_bo_references;
2468 DRMINITLISTHEAD(&bufmgr_gem->named);
2469 init_cache_buckets(bufmgr_gem);
2471 DRMINITLISTHEAD(&bufmgr_gem->vma_cache);
2472 bufmgr_gem->vma_max = -1; /* unlimited by default */
2474 return &bufmgr_gem->bufmgr;