1 /**************************************************************************
3 * Copyright © 2007 Red Hat Inc.
4 * Copyright © 2007 Intel Corporation
5 * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
29 **************************************************************************/
31 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
32 * Keith Whitwell <keithw-at-tungstengraphics-dot-com>
33 * Eric Anholt <eric@anholt.net>
34 * Dave Airlie <airlied@linux.ie>
49 #include <sys/ioctl.h>
52 #include <sys/types.h>
55 #include "libdrm_lists.h"
56 #include "intel_atomic.h"
57 #include "intel_bufmgr.h"
58 #include "intel_bufmgr_priv.h"
59 #include "intel_chipset.h"
64 #define DBG(...) do { \
65 if (bufmgr_gem->bufmgr.debug) \
66 fprintf(stderr, __VA_ARGS__); \
69 typedef struct _drm_intel_bo_gem drm_intel_bo_gem;
71 struct drm_intel_gem_bo_bucket {
76 /* Only cache objects up to 64MB. Bigger than that, and the rounding of the
77 * size makes many operations fail that wouldn't otherwise.
79 #define DRM_INTEL_GEM_BO_BUCKETS 14
80 typedef struct _drm_intel_bufmgr_gem {
81 drm_intel_bufmgr bufmgr;
89 struct drm_i915_gem_exec_object *exec_objects;
90 drm_intel_bo **exec_bos;
94 /** Array of lists of cached gem objects of power-of-two sizes */
95 struct drm_intel_gem_bo_bucket cache_bucket[DRM_INTEL_GEM_BO_BUCKETS];
101 } drm_intel_bufmgr_gem;
103 struct _drm_intel_bo_gem {
111 * Kenel-assigned global name for this object
113 unsigned int global_name;
116 * Index of the buffer within the validation list while preparing a
117 * batchbuffer execution.
122 * Current tiling mode
124 uint32_t tiling_mode;
125 uint32_t swizzle_mode;
129 /** Array passed to the DRM containing relocation information. */
130 struct drm_i915_gem_relocation_entry *relocs;
131 /** Array of bos corresponding to relocs[i].target_handle */
132 drm_intel_bo **reloc_target_bo;
133 /** Number of entries in relocs */
135 /** Mapped address for the buffer, saved across map/unmap cycles */
137 /** GTT virtual address for the buffer, saved across map/unmap cycles */
144 * Boolean of whether this BO and its children have been included in
145 * the current drm_intel_bufmgr_check_aperture_space() total.
147 char included_in_check_aperture;
150 * Boolean of whether this buffer has been used as a relocation
151 * target and had its size accounted for, and thus can't have any
152 * further relocations added to it.
154 char used_as_reloc_target;
157 * Boolean of whether this buffer can be re-used
162 * Size in bytes of this buffer and its relocation descendents.
164 * Used to avoid costly tree walking in
165 * drm_intel_bufmgr_check_aperture in the common case.
170 * Number of potential fence registers required by this buffer and its
173 int reloc_tree_fences;
177 drm_intel_gem_estimate_batch_space(drm_intel_bo ** bo_array, int count);
180 drm_intel_gem_compute_batch_space(drm_intel_bo ** bo_array, int count);
183 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
184 uint32_t * swizzle_mode);
187 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
190 static void drm_intel_gem_bo_unreference_locked(drm_intel_bo *bo);
191 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
194 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo);
196 static void drm_intel_gem_bo_free(drm_intel_bo *bo);
199 drm_intel_gem_bo_tile_size(drm_intel_bufmgr_gem *bufmgr_gem, unsigned long size,
200 uint32_t *tiling_mode)
202 unsigned long min_size, max_size;
205 if (*tiling_mode == I915_TILING_NONE)
208 /* 965+ just need multiples of page size for tiling */
209 if (IS_I965G(bufmgr_gem))
210 return ROUND_UP_TO(size, 4096);
212 /* Older chips need powers of two, of at least 512k or 1M */
213 if (IS_I9XX(bufmgr_gem)) {
214 min_size = 1024*1024;
215 max_size = 128*1024*1024;
218 max_size = 64*1024*1024;
221 if (size > max_size) {
222 *tiling_mode = I915_TILING_NONE;
226 for (i = min_size; i < size; i <<= 1)
233 * Round a given pitch up to the minimum required for X tiling on a
234 * given chip. We use 512 as the minimum to allow for a later tiling
238 drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem,
239 unsigned long pitch, uint32_t tiling_mode)
241 unsigned long tile_width = 512;
244 if (tiling_mode == I915_TILING_NONE)
245 return ROUND_UP_TO(pitch, tile_width);
247 /* 965 is flexible */
248 if (IS_I965G(bufmgr_gem))
249 return ROUND_UP_TO(pitch, tile_width);
251 /* Pre-965 needs power of two tile width */
252 for (i = tile_width; i < pitch; i <<= 1)
258 static struct drm_intel_gem_bo_bucket *
259 drm_intel_gem_bo_bucket_for_size(drm_intel_bufmgr_gem *bufmgr_gem,
264 for (i = 0; i < DRM_INTEL_GEM_BO_BUCKETS; i++) {
265 struct drm_intel_gem_bo_bucket *bucket =
266 &bufmgr_gem->cache_bucket[i];
267 if (bucket->size >= size) {
276 drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem *bufmgr_gem)
280 for (i = 0; i < bufmgr_gem->exec_count; i++) {
281 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
282 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
284 if (bo_gem->relocs == NULL) {
285 DBG("%2d: %d (%s)\n", i, bo_gem->gem_handle,
290 for (j = 0; j < bo_gem->reloc_count; j++) {
291 drm_intel_bo *target_bo = bo_gem->reloc_target_bo[j];
292 drm_intel_bo_gem *target_gem =
293 (drm_intel_bo_gem *) target_bo;
295 DBG("%2d: %d (%s)@0x%08llx -> "
296 "%d (%s)@0x%08lx + 0x%08x\n",
298 bo_gem->gem_handle, bo_gem->name,
299 (unsigned long long)bo_gem->relocs[j].offset,
300 target_gem->gem_handle,
303 bo_gem->relocs[j].delta);
309 drm_intel_gem_bo_reference(drm_intel_bo *bo)
311 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
313 assert(atomic_read(&bo_gem->refcount) > 0);
314 atomic_inc(&bo_gem->refcount);
318 * Adds the given buffer to the list of buffers to be validated (moved into the
319 * appropriate memory type) with the next batch submission.
321 * If a buffer is validated multiple times in a batch submission, it ends up
322 * with the intersection of the memory type flags and the union of the
326 drm_intel_add_validate_buffer(drm_intel_bo *bo)
328 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
329 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
332 if (bo_gem->validate_index != -1)
335 /* Extend the array of validation entries as necessary. */
336 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
337 int new_size = bufmgr_gem->exec_size * 2;
342 bufmgr_gem->exec_objects =
343 realloc(bufmgr_gem->exec_objects,
344 sizeof(*bufmgr_gem->exec_objects) * new_size);
345 bufmgr_gem->exec_bos =
346 realloc(bufmgr_gem->exec_bos,
347 sizeof(*bufmgr_gem->exec_bos) * new_size);
348 bufmgr_gem->exec_size = new_size;
351 index = bufmgr_gem->exec_count;
352 bo_gem->validate_index = index;
353 /* Fill in array entry */
354 bufmgr_gem->exec_objects[index].handle = bo_gem->gem_handle;
355 bufmgr_gem->exec_objects[index].relocation_count = bo_gem->reloc_count;
356 bufmgr_gem->exec_objects[index].relocs_ptr = (uintptr_t) bo_gem->relocs;
357 bufmgr_gem->exec_objects[index].alignment = 0;
358 bufmgr_gem->exec_objects[index].offset = 0;
359 bufmgr_gem->exec_bos[index] = bo;
360 drm_intel_gem_bo_reference(bo);
361 bufmgr_gem->exec_count++;
364 #define RELOC_BUF_SIZE(x) ((I915_RELOC_HEADER + x * I915_RELOC0_STRIDE) * \
368 drm_intel_bo_gem_set_in_aperture_size(drm_intel_bufmgr_gem *bufmgr_gem,
369 drm_intel_bo_gem *bo_gem)
373 assert(!bo_gem->used_as_reloc_target);
375 /* The older chipsets are far-less flexible in terms of tiling,
376 * and require tiled buffer to be size aligned in the aperture.
377 * This means that in the worst possible case we will need a hole
378 * twice as large as the object in order for it to fit into the
379 * aperture. Optimal packing is for wimps.
381 size = bo_gem->bo.size;
382 if (!IS_I965G(bufmgr_gem) && bo_gem->tiling_mode != I915_TILING_NONE)
385 bo_gem->reloc_tree_size = size;
389 drm_intel_setup_reloc_list(drm_intel_bo *bo)
391 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
392 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
393 unsigned int max_relocs = bufmgr_gem->max_relocs;
395 if (bo->size / 4 < max_relocs)
396 max_relocs = bo->size / 4;
398 bo_gem->relocs = malloc(max_relocs *
399 sizeof(struct drm_i915_gem_relocation_entry));
400 bo_gem->reloc_target_bo = malloc(max_relocs * sizeof(drm_intel_bo *));
406 drm_intel_gem_bo_busy(drm_intel_bo *bo)
408 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
409 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
410 struct drm_i915_gem_busy busy;
413 memset(&busy, 0, sizeof(busy));
414 busy.handle = bo_gem->gem_handle;
417 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_BUSY, &busy);
418 } while (ret == -1 && errno == EINTR);
420 return (ret == 0 && busy.busy);
424 drm_intel_gem_bo_madvise_internal(drm_intel_bufmgr_gem *bufmgr_gem,
425 drm_intel_bo_gem *bo_gem, int state)
427 struct drm_i915_gem_madvise madv;
429 madv.handle = bo_gem->gem_handle;
432 ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MADVISE, &madv);
434 return madv.retained;
438 drm_intel_gem_bo_madvise(drm_intel_bo *bo, int madv)
440 return drm_intel_gem_bo_madvise_internal
441 ((drm_intel_bufmgr_gem *) bo->bufmgr,
442 (drm_intel_bo_gem *) bo,
446 /* drop the oldest entries that have been purged by the kernel */
448 drm_intel_gem_bo_cache_purge_bucket(drm_intel_bufmgr_gem *bufmgr_gem,
449 struct drm_intel_gem_bo_bucket *bucket)
451 while (!DRMLISTEMPTY(&bucket->head)) {
452 drm_intel_bo_gem *bo_gem;
454 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
455 bucket->head.next, head);
456 if (drm_intel_gem_bo_madvise_internal
457 (bufmgr_gem, bo_gem, I915_MADV_DONTNEED))
460 DRMLISTDEL(&bo_gem->head);
461 drm_intel_gem_bo_free(&bo_gem->bo);
465 static drm_intel_bo *
466 drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr,
471 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
472 drm_intel_bo_gem *bo_gem;
473 unsigned int page_size = getpagesize();
475 struct drm_intel_gem_bo_bucket *bucket;
476 int alloc_from_cache;
477 unsigned long bo_size;
480 if (flags & BO_ALLOC_FOR_RENDER)
483 /* Round the allocated size up to a power of two number of pages. */
484 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, size);
486 /* If we don't have caching at this size, don't actually round the
489 if (bucket == NULL) {
491 if (bo_size < page_size)
494 bo_size = bucket->size;
497 pthread_mutex_lock(&bufmgr_gem->lock);
498 /* Get a buffer out of the cache if available */
500 alloc_from_cache = 0;
501 if (bucket != NULL && !DRMLISTEMPTY(&bucket->head)) {
503 /* Allocate new render-target BOs from the tail (MRU)
504 * of the list, as it will likely be hot in the GPU
505 * cache and in the aperture for us.
507 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
508 bucket->head.prev, head);
509 DRMLISTDEL(&bo_gem->head);
510 alloc_from_cache = 1;
512 /* For non-render-target BOs (where we're probably
513 * going to map it first thing in order to fill it
514 * with data), check if the last BO in the cache is
515 * unbusy, and only reuse in that case. Otherwise,
516 * allocating a new buffer is probably faster than
517 * waiting for the GPU to finish.
519 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
520 bucket->head.next, head);
521 if (!drm_intel_gem_bo_busy(&bo_gem->bo)) {
522 alloc_from_cache = 1;
523 DRMLISTDEL(&bo_gem->head);
527 if (alloc_from_cache) {
528 if (!drm_intel_gem_bo_madvise_internal
529 (bufmgr_gem, bo_gem, I915_MADV_WILLNEED)) {
530 drm_intel_gem_bo_free(&bo_gem->bo);
531 drm_intel_gem_bo_cache_purge_bucket(bufmgr_gem,
537 pthread_mutex_unlock(&bufmgr_gem->lock);
539 if (!alloc_from_cache) {
540 struct drm_i915_gem_create create;
542 bo_gem = calloc(1, sizeof(*bo_gem));
546 bo_gem->bo.size = bo_size;
547 memset(&create, 0, sizeof(create));
548 create.size = bo_size;
551 ret = ioctl(bufmgr_gem->fd,
552 DRM_IOCTL_I915_GEM_CREATE,
554 } while (ret == -1 && errno == EINTR);
555 bo_gem->gem_handle = create.handle;
556 bo_gem->bo.handle = bo_gem->gem_handle;
561 bo_gem->bo.bufmgr = bufmgr;
565 atomic_set(&bo_gem->refcount, 1);
566 bo_gem->validate_index = -1;
567 bo_gem->reloc_tree_fences = 0;
568 bo_gem->used_as_reloc_target = 0;
569 bo_gem->tiling_mode = I915_TILING_NONE;
570 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
571 bo_gem->reusable = 1;
573 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
575 DBG("bo_create: buf %d (%s) %ldb\n",
576 bo_gem->gem_handle, bo_gem->name, size);
581 static drm_intel_bo *
582 drm_intel_gem_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
585 unsigned int alignment)
587 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size,
588 BO_ALLOC_FOR_RENDER);
591 static drm_intel_bo *
592 drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr,
595 unsigned int alignment)
597 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, 0);
600 static drm_intel_bo *
601 drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
602 int x, int y, int cpp, uint32_t *tiling_mode,
603 unsigned long *pitch, unsigned long flags)
605 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
607 unsigned long size, stride, aligned_y = y;
610 if (*tiling_mode == I915_TILING_NONE)
611 aligned_y = ALIGN(y, 2);
612 else if (*tiling_mode == I915_TILING_X)
613 aligned_y = ALIGN(y, 8);
614 else if (*tiling_mode == I915_TILING_Y)
615 aligned_y = ALIGN(y, 32);
618 stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, *tiling_mode);
619 size = stride * aligned_y;
620 size = drm_intel_gem_bo_tile_size(bufmgr_gem, size, tiling_mode);
622 bo = drm_intel_gem_bo_alloc_internal(bufmgr, name, size, flags);
626 ret = drm_intel_gem_bo_set_tiling(bo, tiling_mode, stride);
628 drm_intel_gem_bo_unreference(bo);
638 * Returns a drm_intel_bo wrapping the given buffer object handle.
640 * This can be used when one application needs to pass a buffer object
644 drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
648 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
649 drm_intel_bo_gem *bo_gem;
651 struct drm_gem_open open_arg;
652 struct drm_i915_gem_get_tiling get_tiling;
654 bo_gem = calloc(1, sizeof(*bo_gem));
658 memset(&open_arg, 0, sizeof(open_arg));
659 open_arg.name = handle;
661 ret = ioctl(bufmgr_gem->fd,
664 } while (ret == -1 && errno == EINTR);
666 fprintf(stderr, "Couldn't reference %s handle 0x%08x: %s\n",
667 name, handle, strerror(errno));
671 bo_gem->bo.size = open_arg.size;
672 bo_gem->bo.offset = 0;
673 bo_gem->bo.virtual = NULL;
674 bo_gem->bo.bufmgr = bufmgr;
676 atomic_set(&bo_gem->refcount, 1);
677 bo_gem->validate_index = -1;
678 bo_gem->gem_handle = open_arg.handle;
679 bo_gem->global_name = handle;
680 bo_gem->reusable = 0;
682 memset(&get_tiling, 0, sizeof(get_tiling));
683 get_tiling.handle = bo_gem->gem_handle;
684 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_GET_TILING, &get_tiling);
686 drm_intel_gem_bo_unreference(&bo_gem->bo);
689 bo_gem->tiling_mode = get_tiling.tiling_mode;
690 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
691 if (bo_gem->tiling_mode == I915_TILING_NONE)
692 bo_gem->reloc_tree_fences = 0;
694 bo_gem->reloc_tree_fences = 1;
695 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
697 DBG("bo_create_from_handle: %d (%s)\n", handle, bo_gem->name);
703 drm_intel_gem_bo_free(drm_intel_bo *bo)
705 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
706 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
707 struct drm_gem_close close;
710 if (bo_gem->mem_virtual)
711 munmap(bo_gem->mem_virtual, bo_gem->bo.size);
712 if (bo_gem->gtt_virtual)
713 munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
715 free(bo_gem->reloc_target_bo);
716 free(bo_gem->relocs);
718 /* Close this object */
719 memset(&close, 0, sizeof(close));
720 close.handle = bo_gem->gem_handle;
721 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close);
724 "DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
725 bo_gem->gem_handle, bo_gem->name, strerror(errno));
730 /** Frees all cached buffers significantly older than @time. */
732 drm_intel_gem_cleanup_bo_cache(drm_intel_bufmgr_gem *bufmgr_gem, time_t time)
736 for (i = 0; i < DRM_INTEL_GEM_BO_BUCKETS; i++) {
737 struct drm_intel_gem_bo_bucket *bucket =
738 &bufmgr_gem->cache_bucket[i];
740 while (!DRMLISTEMPTY(&bucket->head)) {
741 drm_intel_bo_gem *bo_gem;
743 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
744 bucket->head.next, head);
745 if (time - bo_gem->free_time <= 1)
748 DRMLISTDEL(&bo_gem->head);
750 drm_intel_gem_bo_free(&bo_gem->bo);
756 drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time)
758 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
759 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
760 struct drm_intel_gem_bo_bucket *bucket;
761 uint32_t tiling_mode;
764 /* Unreference all the target buffers */
765 for (i = 0; i < bo_gem->reloc_count; i++) {
766 drm_intel_gem_bo_unreference_locked_timed(bo_gem->
770 bo_gem->reloc_count = 0;
771 bo_gem->used_as_reloc_target = 0;
773 DBG("bo_unreference final: %d (%s)\n",
774 bo_gem->gem_handle, bo_gem->name);
776 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, bo->size);
777 /* Put the buffer into our internal cache for reuse if we can. */
778 tiling_mode = I915_TILING_NONE;
779 if (bufmgr_gem->bo_reuse && bo_gem->reusable && bucket != NULL &&
780 drm_intel_gem_bo_set_tiling(bo, &tiling_mode, 0) == 0 &&
781 drm_intel_gem_bo_madvise_internal(bufmgr_gem, bo_gem,
782 I915_MADV_DONTNEED)) {
783 bo_gem->free_time = time;
786 bo_gem->validate_index = -1;
788 DRMLISTADDTAIL(&bo_gem->head, &bucket->head);
790 drm_intel_gem_cleanup_bo_cache(bufmgr_gem, time);
792 drm_intel_gem_bo_free(bo);
796 static void drm_intel_gem_bo_unreference_locked(drm_intel_bo *bo)
798 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
800 assert(atomic_read(&bo_gem->refcount) > 0);
801 if (atomic_dec_and_test(&bo_gem->refcount)) {
802 struct timespec time;
804 clock_gettime(CLOCK_MONOTONIC, &time);
805 drm_intel_gem_bo_unreference_final(bo, time.tv_sec);
809 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
812 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
814 assert(atomic_read(&bo_gem->refcount) > 0);
815 if (atomic_dec_and_test(&bo_gem->refcount))
816 drm_intel_gem_bo_unreference_final(bo, time);
819 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo)
821 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
823 assert(atomic_read(&bo_gem->refcount) > 0);
824 if (atomic_dec_and_test(&bo_gem->refcount)) {
825 drm_intel_bufmgr_gem *bufmgr_gem =
826 (drm_intel_bufmgr_gem *) bo->bufmgr;
827 struct timespec time;
829 clock_gettime(CLOCK_MONOTONIC, &time);
831 pthread_mutex_lock(&bufmgr_gem->lock);
832 drm_intel_gem_bo_unreference_final(bo, time.tv_sec);
833 pthread_mutex_unlock(&bufmgr_gem->lock);
837 static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable)
839 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
840 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
841 struct drm_i915_gem_set_domain set_domain;
844 pthread_mutex_lock(&bufmgr_gem->lock);
846 /* Allow recursive mapping. Mesa may recursively map buffers with
847 * nested display loops.
849 if (!bo_gem->mem_virtual) {
850 struct drm_i915_gem_mmap mmap_arg;
852 DBG("bo_map: %d (%s)\n", bo_gem->gem_handle, bo_gem->name);
854 memset(&mmap_arg, 0, sizeof(mmap_arg));
855 mmap_arg.handle = bo_gem->gem_handle;
857 mmap_arg.size = bo->size;
859 ret = ioctl(bufmgr_gem->fd,
860 DRM_IOCTL_I915_GEM_MMAP,
862 } while (ret == -1 && errno == EINTR);
865 "%s:%d: Error mapping buffer %d (%s): %s .\n",
866 __FILE__, __LINE__, bo_gem->gem_handle,
867 bo_gem->name, strerror(errno));
868 pthread_mutex_unlock(&bufmgr_gem->lock);
871 bo_gem->mem_virtual = (void *)(uintptr_t) mmap_arg.addr_ptr;
873 DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
874 bo_gem->mem_virtual);
875 bo->virtual = bo_gem->mem_virtual;
877 set_domain.handle = bo_gem->gem_handle;
878 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
880 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
882 set_domain.write_domain = 0;
884 ret = ioctl(bufmgr_gem->fd,
885 DRM_IOCTL_I915_GEM_SET_DOMAIN,
887 } while (ret == -1 && errno == EINTR);
889 fprintf(stderr, "%s:%d: Error setting to CPU domain %d: %s\n",
890 __FILE__, __LINE__, bo_gem->gem_handle,
892 pthread_mutex_unlock(&bufmgr_gem->lock);
896 pthread_mutex_unlock(&bufmgr_gem->lock);
901 int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
903 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
904 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
905 struct drm_i915_gem_set_domain set_domain;
908 pthread_mutex_lock(&bufmgr_gem->lock);
910 /* Get a mapping of the buffer if we haven't before. */
911 if (bo_gem->gtt_virtual == NULL) {
912 struct drm_i915_gem_mmap_gtt mmap_arg;
914 DBG("bo_map_gtt: mmap %d (%s)\n", bo_gem->gem_handle,
917 memset(&mmap_arg, 0, sizeof(mmap_arg));
918 mmap_arg.handle = bo_gem->gem_handle;
920 /* Get the fake offset back... */
922 ret = ioctl(bufmgr_gem->fd,
923 DRM_IOCTL_I915_GEM_MMAP_GTT,
925 } while (ret == -1 && errno == EINTR);
928 "%s:%d: Error preparing buffer map %d (%s): %s .\n",
930 bo_gem->gem_handle, bo_gem->name,
932 pthread_mutex_unlock(&bufmgr_gem->lock);
937 bo_gem->gtt_virtual = mmap(0, bo->size, PROT_READ | PROT_WRITE,
938 MAP_SHARED, bufmgr_gem->fd,
940 if (bo_gem->gtt_virtual == MAP_FAILED) {
942 "%s:%d: Error mapping buffer %d (%s): %s .\n",
944 bo_gem->gem_handle, bo_gem->name,
946 pthread_mutex_unlock(&bufmgr_gem->lock);
951 bo->virtual = bo_gem->gtt_virtual;
953 DBG("bo_map_gtt: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
954 bo_gem->gtt_virtual);
956 /* Now move it to the GTT domain so that the CPU caches are flushed */
957 set_domain.handle = bo_gem->gem_handle;
958 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
959 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
961 ret = ioctl(bufmgr_gem->fd,
962 DRM_IOCTL_I915_GEM_SET_DOMAIN,
964 } while (ret == -1 && errno == EINTR);
967 fprintf(stderr, "%s:%d: Error setting domain %d: %s\n",
968 __FILE__, __LINE__, bo_gem->gem_handle,
972 pthread_mutex_unlock(&bufmgr_gem->lock);
977 int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo)
979 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
980 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
986 assert(bo_gem->gtt_virtual != NULL);
988 pthread_mutex_lock(&bufmgr_gem->lock);
990 pthread_mutex_unlock(&bufmgr_gem->lock);
995 static int drm_intel_gem_bo_unmap(drm_intel_bo *bo)
997 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
998 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
999 struct drm_i915_gem_sw_finish sw_finish;
1005 assert(bo_gem->mem_virtual != NULL);
1007 pthread_mutex_lock(&bufmgr_gem->lock);
1009 /* Cause a flush to happen if the buffer's pinned for scanout, so the
1010 * results show up in a timely manner.
1012 sw_finish.handle = bo_gem->gem_handle;
1014 ret = ioctl(bufmgr_gem->fd,
1015 DRM_IOCTL_I915_GEM_SW_FINISH,
1017 } while (ret == -1 && errno == EINTR);
1020 pthread_mutex_unlock(&bufmgr_gem->lock);
1025 drm_intel_gem_bo_subdata(drm_intel_bo *bo, unsigned long offset,
1026 unsigned long size, const void *data)
1028 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1029 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1030 struct drm_i915_gem_pwrite pwrite;
1033 memset(&pwrite, 0, sizeof(pwrite));
1034 pwrite.handle = bo_gem->gem_handle;
1035 pwrite.offset = offset;
1037 pwrite.data_ptr = (uint64_t) (uintptr_t) data;
1039 ret = ioctl(bufmgr_gem->fd,
1040 DRM_IOCTL_I915_GEM_PWRITE,
1042 } while (ret == -1 && errno == EINTR);
1045 "%s:%d: Error writing data to buffer %d: (%d %d) %s .\n",
1046 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1047 (int)size, strerror(errno));
1053 drm_intel_gem_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id)
1055 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1056 struct drm_i915_get_pipe_from_crtc_id get_pipe_from_crtc_id;
1059 get_pipe_from_crtc_id.crtc_id = crtc_id;
1060 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID,
1061 &get_pipe_from_crtc_id);
1063 /* We return -1 here to signal that we don't
1064 * know which pipe is associated with this crtc.
1065 * This lets the caller know that this information
1066 * isn't available; using the wrong pipe for
1067 * vblank waiting can cause the chipset to lock up
1072 return get_pipe_from_crtc_id.pipe;
1076 drm_intel_gem_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
1077 unsigned long size, void *data)
1079 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1080 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1081 struct drm_i915_gem_pread pread;
1084 memset(&pread, 0, sizeof(pread));
1085 pread.handle = bo_gem->gem_handle;
1086 pread.offset = offset;
1088 pread.data_ptr = (uint64_t) (uintptr_t) data;
1090 ret = ioctl(bufmgr_gem->fd,
1091 DRM_IOCTL_I915_GEM_PREAD,
1093 } while (ret == -1 && errno == EINTR);
1096 "%s:%d: Error reading data from buffer %d: (%d %d) %s .\n",
1097 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1098 (int)size, strerror(errno));
1103 /** Waits for all GPU rendering to the object to have completed. */
1105 drm_intel_gem_bo_wait_rendering(drm_intel_bo *bo)
1107 drm_intel_gem_bo_start_gtt_access(bo, 0);
1111 * Sets the object to the GTT read and possibly write domain, used by the X
1112 * 2D driver in the absence of kernel support to do drm_intel_gem_bo_map_gtt().
1114 * In combination with drm_intel_gem_bo_pin() and manual fence management, we
1115 * can do tiled pixmaps this way.
1118 drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable)
1120 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1121 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1122 struct drm_i915_gem_set_domain set_domain;
1125 set_domain.handle = bo_gem->gem_handle;
1126 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1127 set_domain.write_domain = write_enable ? I915_GEM_DOMAIN_GTT : 0;
1129 ret = ioctl(bufmgr_gem->fd,
1130 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1132 } while (ret == -1 && errno == EINTR);
1135 "%s:%d: Error setting memory domains %d (%08x %08x): %s .\n",
1136 __FILE__, __LINE__, bo_gem->gem_handle,
1137 set_domain.read_domains, set_domain.write_domain,
1143 drm_intel_bufmgr_gem_destroy(drm_intel_bufmgr *bufmgr)
1145 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1148 free(bufmgr_gem->exec_objects);
1149 free(bufmgr_gem->exec_bos);
1151 pthread_mutex_destroy(&bufmgr_gem->lock);
1153 /* Free any cached buffer objects we were going to reuse */
1154 for (i = 0; i < DRM_INTEL_GEM_BO_BUCKETS; i++) {
1155 struct drm_intel_gem_bo_bucket *bucket =
1156 &bufmgr_gem->cache_bucket[i];
1157 drm_intel_bo_gem *bo_gem;
1159 while (!DRMLISTEMPTY(&bucket->head)) {
1160 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1161 bucket->head.next, head);
1162 DRMLISTDEL(&bo_gem->head);
1164 drm_intel_gem_bo_free(&bo_gem->bo);
1172 * Adds the target buffer to the validation list and adds the relocation
1173 * to the reloc_buffer's relocation list.
1175 * The relocation entry at the given offset must already contain the
1176 * precomputed relocation value, because the kernel will optimize out
1177 * the relocation entry write when the buffer hasn't moved from the
1178 * last known offset in target_bo.
1181 drm_intel_gem_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1182 drm_intel_bo *target_bo, uint32_t target_offset,
1183 uint32_t read_domains, uint32_t write_domain)
1185 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1186 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1187 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
1189 pthread_mutex_lock(&bufmgr_gem->lock);
1191 /* Create a new relocation list if needed */
1192 if (bo_gem->relocs == NULL)
1193 drm_intel_setup_reloc_list(bo);
1195 /* Check overflow */
1196 assert(bo_gem->reloc_count < bufmgr_gem->max_relocs);
1199 assert(offset <= bo->size - 4);
1200 assert((write_domain & (write_domain - 1)) == 0);
1202 /* Make sure that we're not adding a reloc to something whose size has
1203 * already been accounted for.
1205 assert(!bo_gem->used_as_reloc_target);
1206 bo_gem->reloc_tree_size += target_bo_gem->reloc_tree_size;
1207 bo_gem->reloc_tree_fences += target_bo_gem->reloc_tree_fences;
1209 /* Flag the target to disallow further relocations in it. */
1210 target_bo_gem->used_as_reloc_target = 1;
1212 bo_gem->relocs[bo_gem->reloc_count].offset = offset;
1213 bo_gem->relocs[bo_gem->reloc_count].delta = target_offset;
1214 bo_gem->relocs[bo_gem->reloc_count].target_handle =
1215 target_bo_gem->gem_handle;
1216 bo_gem->relocs[bo_gem->reloc_count].read_domains = read_domains;
1217 bo_gem->relocs[bo_gem->reloc_count].write_domain = write_domain;
1218 bo_gem->relocs[bo_gem->reloc_count].presumed_offset = target_bo->offset;
1220 bo_gem->reloc_target_bo[bo_gem->reloc_count] = target_bo;
1221 drm_intel_gem_bo_reference(target_bo);
1223 bo_gem->reloc_count++;
1225 pthread_mutex_unlock(&bufmgr_gem->lock);
1231 * Walk the tree of relocations rooted at BO and accumulate the list of
1232 * validations to be performed and update the relocation buffers with
1233 * index values into the validation list.
1236 drm_intel_gem_bo_process_reloc(drm_intel_bo *bo)
1238 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1241 if (bo_gem->relocs == NULL)
1244 for (i = 0; i < bo_gem->reloc_count; i++) {
1245 drm_intel_bo *target_bo = bo_gem->reloc_target_bo[i];
1247 /* Continue walking the tree depth-first. */
1248 drm_intel_gem_bo_process_reloc(target_bo);
1250 /* Add the target to the validate list */
1251 drm_intel_add_validate_buffer(target_bo);
1256 drm_intel_update_buffer_offsets(drm_intel_bufmgr_gem *bufmgr_gem)
1260 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1261 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1262 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1264 /* Update the buffer offset */
1265 if (bufmgr_gem->exec_objects[i].offset != bo->offset) {
1266 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1267 bo_gem->gem_handle, bo_gem->name, bo->offset,
1268 (unsigned long long)bufmgr_gem->exec_objects[i].
1270 bo->offset = bufmgr_gem->exec_objects[i].offset;
1276 drm_intel_gem_bo_exec(drm_intel_bo *bo, int used,
1277 drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
1279 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1280 struct drm_i915_gem_execbuffer execbuf;
1283 pthread_mutex_lock(&bufmgr_gem->lock);
1284 /* Update indices and set up the validate list. */
1285 drm_intel_gem_bo_process_reloc(bo);
1287 /* Add the batch buffer to the validation list. There are no
1288 * relocations pointing to it.
1290 drm_intel_add_validate_buffer(bo);
1292 execbuf.buffers_ptr = (uintptr_t) bufmgr_gem->exec_objects;
1293 execbuf.buffer_count = bufmgr_gem->exec_count;
1294 execbuf.batch_start_offset = 0;
1295 execbuf.batch_len = used;
1296 execbuf.cliprects_ptr = (uintptr_t) cliprects;
1297 execbuf.num_cliprects = num_cliprects;
1302 ret = ioctl(bufmgr_gem->fd,
1303 DRM_IOCTL_I915_GEM_EXECBUFFER,
1305 } while (ret != 0 && errno == EAGAIN);
1307 if (ret != 0 && errno == ENOMEM) {
1309 "Execbuffer fails to pin. "
1310 "Estimate: %u. Actual: %u. Available: %u\n",
1311 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
1314 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
1317 (unsigned int)bufmgr_gem->gtt_size);
1319 drm_intel_update_buffer_offsets(bufmgr_gem);
1321 if (bufmgr_gem->bufmgr.debug)
1322 drm_intel_gem_dump_validation_list(bufmgr_gem);
1324 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1325 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1326 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1328 /* Disconnect the buffer from the validate list */
1329 bo_gem->validate_index = -1;
1330 drm_intel_gem_bo_unreference_locked(bo);
1331 bufmgr_gem->exec_bos[i] = NULL;
1333 bufmgr_gem->exec_count = 0;
1334 pthread_mutex_unlock(&bufmgr_gem->lock);
1340 drm_intel_gem_bo_pin(drm_intel_bo *bo, uint32_t alignment)
1342 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1343 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1344 struct drm_i915_gem_pin pin;
1347 memset(&pin, 0, sizeof(pin));
1348 pin.handle = bo_gem->gem_handle;
1349 pin.alignment = alignment;
1352 ret = ioctl(bufmgr_gem->fd,
1353 DRM_IOCTL_I915_GEM_PIN,
1355 } while (ret == -1 && errno == EINTR);
1360 bo->offset = pin.offset;
1365 drm_intel_gem_bo_unpin(drm_intel_bo *bo)
1367 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1368 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1369 struct drm_i915_gem_unpin unpin;
1372 memset(&unpin, 0, sizeof(unpin));
1373 unpin.handle = bo_gem->gem_handle;
1375 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_UNPIN, &unpin);
1383 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1386 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1387 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1388 struct drm_i915_gem_set_tiling set_tiling;
1391 if (bo_gem->global_name == 0 && *tiling_mode == bo_gem->tiling_mode)
1394 /* If we're going from non-tiling to tiling, bump fence count */
1395 if (bo_gem->tiling_mode == I915_TILING_NONE)
1396 bo_gem->reloc_tree_fences++;
1398 memset(&set_tiling, 0, sizeof(set_tiling));
1399 set_tiling.handle = bo_gem->gem_handle;
1400 set_tiling.tiling_mode = *tiling_mode;
1401 set_tiling.stride = stride;
1404 ret = ioctl(bufmgr_gem->fd,
1405 DRM_IOCTL_I915_GEM_SET_TILING,
1407 } while (ret == -1 && errno == EINTR);
1409 *tiling_mode = bo_gem->tiling_mode;
1412 bo_gem->tiling_mode = set_tiling.tiling_mode;
1413 bo_gem->swizzle_mode = set_tiling.swizzle_mode;
1415 /* If we're going from tiling to non-tiling, drop fence count */
1416 if (bo_gem->tiling_mode == I915_TILING_NONE)
1417 bo_gem->reloc_tree_fences--;
1419 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
1421 *tiling_mode = bo_gem->tiling_mode;
1426 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1427 uint32_t * swizzle_mode)
1429 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1431 *tiling_mode = bo_gem->tiling_mode;
1432 *swizzle_mode = bo_gem->swizzle_mode;
1437 drm_intel_gem_bo_flink(drm_intel_bo *bo, uint32_t * name)
1439 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1440 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1441 struct drm_gem_flink flink;
1444 if (!bo_gem->global_name) {
1445 memset(&flink, 0, sizeof(flink));
1446 flink.handle = bo_gem->gem_handle;
1448 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_FLINK, &flink);
1451 bo_gem->global_name = flink.name;
1452 bo_gem->reusable = 0;
1455 *name = bo_gem->global_name;
1460 * Enables unlimited caching of buffer objects for reuse.
1462 * This is potentially very memory expensive, as the cache at each bucket
1463 * size is only bounded by how many buffers of that size we've managed to have
1464 * in flight at once.
1467 drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr)
1469 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1471 bufmgr_gem->bo_reuse = 1;
1475 * Return the additional aperture space required by the tree of buffer objects
1479 drm_intel_gem_bo_get_aperture_space(drm_intel_bo *bo)
1481 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1485 if (bo == NULL || bo_gem->included_in_check_aperture)
1489 bo_gem->included_in_check_aperture = 1;
1491 for (i = 0; i < bo_gem->reloc_count; i++)
1493 drm_intel_gem_bo_get_aperture_space(bo_gem->
1494 reloc_target_bo[i]);
1500 * Count the number of buffers in this list that need a fence reg
1502 * If the count is greater than the number of available regs, we'll have
1503 * to ask the caller to resubmit a batch with fewer tiled buffers.
1505 * This function over-counts if the same buffer is used multiple times.
1508 drm_intel_gem_total_fences(drm_intel_bo ** bo_array, int count)
1511 unsigned int total = 0;
1513 for (i = 0; i < count; i++) {
1514 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
1519 total += bo_gem->reloc_tree_fences;
1525 * Clear the flag set by drm_intel_gem_bo_get_aperture_space() so we're ready
1526 * for the next drm_intel_bufmgr_check_aperture_space() call.
1529 drm_intel_gem_bo_clear_aperture_space_flag(drm_intel_bo *bo)
1531 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1534 if (bo == NULL || !bo_gem->included_in_check_aperture)
1537 bo_gem->included_in_check_aperture = 0;
1539 for (i = 0; i < bo_gem->reloc_count; i++)
1540 drm_intel_gem_bo_clear_aperture_space_flag(bo_gem->
1541 reloc_target_bo[i]);
1545 * Return a conservative estimate for the amount of aperture required
1546 * for a collection of buffers. This may double-count some buffers.
1549 drm_intel_gem_estimate_batch_space(drm_intel_bo **bo_array, int count)
1552 unsigned int total = 0;
1554 for (i = 0; i < count; i++) {
1555 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
1557 total += bo_gem->reloc_tree_size;
1563 * Return the amount of aperture needed for a collection of buffers.
1564 * This avoids double counting any buffers, at the cost of looking
1565 * at every buffer in the set.
1568 drm_intel_gem_compute_batch_space(drm_intel_bo **bo_array, int count)
1571 unsigned int total = 0;
1573 for (i = 0; i < count; i++) {
1574 total += drm_intel_gem_bo_get_aperture_space(bo_array[i]);
1575 /* For the first buffer object in the array, we get an
1576 * accurate count back for its reloc_tree size (since nothing
1577 * had been flagged as being counted yet). We can save that
1578 * value out as a more conservative reloc_tree_size that
1579 * avoids double-counting target buffers. Since the first
1580 * buffer happens to usually be the batch buffer in our
1581 * callers, this can pull us back from doing the tree
1582 * walk on every new batch emit.
1585 drm_intel_bo_gem *bo_gem =
1586 (drm_intel_bo_gem *) bo_array[i];
1587 bo_gem->reloc_tree_size = total;
1591 for (i = 0; i < count; i++)
1592 drm_intel_gem_bo_clear_aperture_space_flag(bo_array[i]);
1597 * Return -1 if the batchbuffer should be flushed before attempting to
1598 * emit rendering referencing the buffers pointed to by bo_array.
1600 * This is required because if we try to emit a batchbuffer with relocations
1601 * to a tree of buffers that won't simultaneously fit in the aperture,
1602 * the rendering will return an error at a point where the software is not
1603 * prepared to recover from it.
1605 * However, we also want to emit the batchbuffer significantly before we reach
1606 * the limit, as a series of batchbuffers each of which references buffers
1607 * covering almost all of the aperture means that at each emit we end up
1608 * waiting to evict a buffer from the last rendering, and we get synchronous
1609 * performance. By emitting smaller batchbuffers, we eat some CPU overhead to
1610 * get better parallelism.
1613 drm_intel_gem_check_aperture_space(drm_intel_bo **bo_array, int count)
1615 drm_intel_bufmgr_gem *bufmgr_gem =
1616 (drm_intel_bufmgr_gem *) bo_array[0]->bufmgr;
1617 unsigned int total = 0;
1618 unsigned int threshold = bufmgr_gem->gtt_size * 3 / 4;
1621 /* Check for fence reg constraints if necessary */
1622 if (bufmgr_gem->available_fences) {
1623 total_fences = drm_intel_gem_total_fences(bo_array, count);
1624 if (total_fences > bufmgr_gem->available_fences)
1628 total = drm_intel_gem_estimate_batch_space(bo_array, count);
1630 if (total > threshold)
1631 total = drm_intel_gem_compute_batch_space(bo_array, count);
1633 if (total > threshold) {
1634 DBG("check_space: overflowed available aperture, "
1636 total / 1024, (int)bufmgr_gem->gtt_size / 1024);
1639 DBG("drm_check_space: total %dkb vs bufgr %dkb\n", total / 1024,
1640 (int)bufmgr_gem->gtt_size / 1024);
1646 * Disable buffer reuse for objects which are shared with the kernel
1647 * as scanout buffers
1650 drm_intel_gem_bo_disable_reuse(drm_intel_bo *bo)
1652 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1654 bo_gem->reusable = 0;
1659 _drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
1661 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1664 for (i = 0; i < bo_gem->reloc_count; i++) {
1665 if (bo_gem->reloc_target_bo[i] == target_bo)
1667 if (_drm_intel_gem_bo_references(bo_gem->reloc_target_bo[i],
1675 /** Return true if target_bo is referenced by bo's relocation tree. */
1677 drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
1679 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
1681 if (bo == NULL || target_bo == NULL)
1683 if (target_bo_gem->used_as_reloc_target)
1684 return _drm_intel_gem_bo_references(bo, target_bo);
1689 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
1690 * and manage map buffer objections.
1692 * \param fd File descriptor of the opened DRM device.
1695 drm_intel_bufmgr_gem_init(int fd, int batch_size)
1697 drm_intel_bufmgr_gem *bufmgr_gem;
1698 struct drm_i915_gem_get_aperture aperture;
1699 drm_i915_getparam_t gp;
1703 bufmgr_gem = calloc(1, sizeof(*bufmgr_gem));
1704 bufmgr_gem->fd = fd;
1706 if (pthread_mutex_init(&bufmgr_gem->lock, NULL) != 0) {
1711 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
1714 bufmgr_gem->gtt_size = aperture.aper_available_size;
1716 fprintf(stderr, "DRM_IOCTL_I915_GEM_APERTURE failed: %s\n",
1718 bufmgr_gem->gtt_size = 128 * 1024 * 1024;
1719 fprintf(stderr, "Assuming %dkB available aperture size.\n"
1720 "May lead to reduced performance or incorrect "
1722 (int)bufmgr_gem->gtt_size / 1024);
1725 gp.param = I915_PARAM_CHIPSET_ID;
1726 gp.value = &bufmgr_gem->pci_device;
1727 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
1729 fprintf(stderr, "get chip id failed: %d [%d]\n", ret, errno);
1730 fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value);
1733 if (!IS_I965G(bufmgr_gem)) {
1734 gp.param = I915_PARAM_NUM_FENCES_AVAIL;
1735 gp.value = &bufmgr_gem->available_fences;
1736 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
1738 fprintf(stderr, "get fences failed: %d [%d]\n", ret,
1740 fprintf(stderr, "param: %d, val: %d\n", gp.param,
1742 bufmgr_gem->available_fences = 0;
1746 /* Let's go with one relocation per every 2 dwords (but round down a bit
1747 * since a power of two will mean an extra page allocation for the reloc
1750 * Every 4 was too few for the blender benchmark.
1752 bufmgr_gem->max_relocs = batch_size / sizeof(uint32_t) / 2 - 2;
1754 bufmgr_gem->bufmgr.bo_alloc = drm_intel_gem_bo_alloc;
1755 bufmgr_gem->bufmgr.bo_alloc_for_render =
1756 drm_intel_gem_bo_alloc_for_render;
1757 bufmgr_gem->bufmgr.bo_alloc_tiled = drm_intel_gem_bo_alloc_tiled;
1758 bufmgr_gem->bufmgr.bo_reference = drm_intel_gem_bo_reference;
1759 bufmgr_gem->bufmgr.bo_unreference = drm_intel_gem_bo_unreference;
1760 bufmgr_gem->bufmgr.bo_map = drm_intel_gem_bo_map;
1761 bufmgr_gem->bufmgr.bo_unmap = drm_intel_gem_bo_unmap;
1762 bufmgr_gem->bufmgr.bo_subdata = drm_intel_gem_bo_subdata;
1763 bufmgr_gem->bufmgr.bo_get_subdata = drm_intel_gem_bo_get_subdata;
1764 bufmgr_gem->bufmgr.bo_wait_rendering = drm_intel_gem_bo_wait_rendering;
1765 bufmgr_gem->bufmgr.bo_emit_reloc = drm_intel_gem_bo_emit_reloc;
1766 bufmgr_gem->bufmgr.bo_pin = drm_intel_gem_bo_pin;
1767 bufmgr_gem->bufmgr.bo_unpin = drm_intel_gem_bo_unpin;
1768 bufmgr_gem->bufmgr.bo_get_tiling = drm_intel_gem_bo_get_tiling;
1769 bufmgr_gem->bufmgr.bo_set_tiling = drm_intel_gem_bo_set_tiling;
1770 bufmgr_gem->bufmgr.bo_flink = drm_intel_gem_bo_flink;
1771 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec;
1772 bufmgr_gem->bufmgr.bo_busy = drm_intel_gem_bo_busy;
1773 bufmgr_gem->bufmgr.bo_madvise = drm_intel_gem_bo_madvise;
1774 bufmgr_gem->bufmgr.destroy = drm_intel_bufmgr_gem_destroy;
1775 bufmgr_gem->bufmgr.debug = 0;
1776 bufmgr_gem->bufmgr.check_aperture_space =
1777 drm_intel_gem_check_aperture_space;
1778 bufmgr_gem->bufmgr.bo_disable_reuse = drm_intel_gem_bo_disable_reuse;
1779 bufmgr_gem->bufmgr.get_pipe_from_crtc_id =
1780 drm_intel_gem_get_pipe_from_crtc_id;
1781 bufmgr_gem->bufmgr.bo_references = drm_intel_gem_bo_references;
1783 /* Initialize the linked lists for BO reuse cache. */
1784 for (i = 0, size = 4096; i < DRM_INTEL_GEM_BO_BUCKETS; i++, size *= 2) {
1785 DRMINITLISTHEAD(&bufmgr_gem->cache_bucket[i].head);
1786 bufmgr_gem->cache_bucket[i].size = size;
1789 return &bufmgr_gem->bufmgr;