1 /**************************************************************************
3 * Copyright © 2007 Red Hat Inc.
4 * Copyright © 2007 Intel Corporation
5 * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
29 **************************************************************************/
31 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
32 * Keith Whitwell <keithw-at-tungstengraphics-dot-com>
33 * Eric Anholt <eric@anholt.net>
34 * Dave Airlie <airlied@linux.ie>
49 #include <sys/ioctl.h>
52 #include <sys/types.h>
55 #include "libdrm_lists.h"
56 #include "intel_atomic.h"
57 #include "intel_bufmgr.h"
58 #include "intel_bufmgr_priv.h"
59 #include "intel_chipset.h"
64 #define DBG(...) do { \
65 if (bufmgr_gem->bufmgr.debug) \
66 fprintf(stderr, __VA_ARGS__); \
69 typedef struct _drm_intel_bo_gem drm_intel_bo_gem;
71 struct drm_intel_gem_bo_bucket {
76 /* Only cache objects up to 64MB. Bigger than that, and the rounding of the
77 * size makes many operations fail that wouldn't otherwise.
79 #define DRM_INTEL_GEM_BO_BUCKETS 14
80 typedef struct _drm_intel_bufmgr_gem {
81 drm_intel_bufmgr bufmgr;
89 struct drm_i915_gem_exec_object *exec_objects;
90 drm_intel_bo **exec_bos;
94 /** Array of lists of cached gem objects of power-of-two sizes */
95 struct drm_intel_gem_bo_bucket cache_bucket[DRM_INTEL_GEM_BO_BUCKETS];
101 } drm_intel_bufmgr_gem;
103 struct _drm_intel_bo_gem {
111 * Kenel-assigned global name for this object
113 unsigned int global_name;
116 * Index of the buffer within the validation list while preparing a
117 * batchbuffer execution.
122 * Current tiling mode
124 uint32_t tiling_mode;
125 uint32_t swizzle_mode;
129 /** Array passed to the DRM containing relocation information. */
130 struct drm_i915_gem_relocation_entry *relocs;
131 /** Array of bos corresponding to relocs[i].target_handle */
132 drm_intel_bo **reloc_target_bo;
133 /** Number of entries in relocs */
135 /** Mapped address for the buffer, saved across map/unmap cycles */
137 /** GTT virtual address for the buffer, saved across map/unmap cycles */
144 * Boolean of whether this BO and its children have been included in
145 * the current drm_intel_bufmgr_check_aperture_space() total.
147 char included_in_check_aperture;
150 * Boolean of whether this buffer has been used as a relocation
151 * target and had its size accounted for, and thus can't have any
152 * further relocations added to it.
154 char used_as_reloc_target;
157 * Boolean of whether this buffer can be re-used
162 * Size in bytes of this buffer and its relocation descendents.
164 * Used to avoid costly tree walking in
165 * drm_intel_bufmgr_check_aperture in the common case.
170 * Number of potential fence registers required by this buffer and its
173 int reloc_tree_fences;
177 drm_intel_gem_estimate_batch_space(drm_intel_bo ** bo_array, int count);
180 drm_intel_gem_compute_batch_space(drm_intel_bo ** bo_array, int count);
183 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
184 uint32_t * swizzle_mode);
187 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
190 static void drm_intel_gem_bo_unreference_locked(drm_intel_bo *bo);
191 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
194 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo);
196 static void drm_intel_gem_bo_free(drm_intel_bo *bo);
199 drm_intel_gem_bo_tile_size(drm_intel_bufmgr_gem *bufmgr_gem, unsigned long size,
200 uint32_t *tiling_mode)
202 unsigned long min_size, max_size;
205 if (*tiling_mode == I915_TILING_NONE)
208 /* 965+ just need multiples of page size for tiling */
209 if (IS_I965G(bufmgr_gem))
210 return ROUND_UP_TO(size, 4096);
212 /* Older chips need powers of two, of at least 512k or 1M */
213 if (IS_I9XX(bufmgr_gem)) {
214 min_size = 1024*1024;
215 max_size = 128*1024*1024;
218 max_size = 64*1024*1024;
221 if (size > max_size) {
222 *tiling_mode = I915_TILING_NONE;
226 for (i = min_size; i < size; i <<= 1)
233 * Round a given pitch up to the minimum required for X tiling on a
234 * given chip. We use 512 as the minimum to allow for a later tiling
238 drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem,
239 unsigned long pitch, uint32_t tiling_mode)
241 unsigned long tile_width = 512;
244 if (tiling_mode == I915_TILING_NONE)
245 return ROUND_UP_TO(pitch, tile_width);
247 /* 965 is flexible */
248 if (IS_I965G(bufmgr_gem))
249 return ROUND_UP_TO(pitch, tile_width);
251 /* Pre-965 needs power of two tile width */
252 for (i = tile_width; i < pitch; i <<= 1)
258 static struct drm_intel_gem_bo_bucket *
259 drm_intel_gem_bo_bucket_for_size(drm_intel_bufmgr_gem *bufmgr_gem,
264 for (i = 0; i < DRM_INTEL_GEM_BO_BUCKETS; i++) {
265 struct drm_intel_gem_bo_bucket *bucket =
266 &bufmgr_gem->cache_bucket[i];
267 if (bucket->size >= size) {
276 drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem *bufmgr_gem)
280 for (i = 0; i < bufmgr_gem->exec_count; i++) {
281 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
282 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
284 if (bo_gem->relocs == NULL) {
285 DBG("%2d: %d (%s)\n", i, bo_gem->gem_handle,
290 for (j = 0; j < bo_gem->reloc_count; j++) {
291 drm_intel_bo *target_bo = bo_gem->reloc_target_bo[j];
292 drm_intel_bo_gem *target_gem =
293 (drm_intel_bo_gem *) target_bo;
295 DBG("%2d: %d (%s)@0x%08llx -> "
296 "%d (%s)@0x%08lx + 0x%08x\n",
298 bo_gem->gem_handle, bo_gem->name,
299 (unsigned long long)bo_gem->relocs[j].offset,
300 target_gem->gem_handle,
303 bo_gem->relocs[j].delta);
309 drm_intel_gem_bo_reference(drm_intel_bo *bo)
311 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
313 assert(atomic_read(&bo_gem->refcount) > 0);
314 atomic_inc(&bo_gem->refcount);
318 * Adds the given buffer to the list of buffers to be validated (moved into the
319 * appropriate memory type) with the next batch submission.
321 * If a buffer is validated multiple times in a batch submission, it ends up
322 * with the intersection of the memory type flags and the union of the
326 drm_intel_add_validate_buffer(drm_intel_bo *bo)
328 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
329 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
332 if (bo_gem->validate_index != -1)
335 /* Extend the array of validation entries as necessary. */
336 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
337 int new_size = bufmgr_gem->exec_size * 2;
342 bufmgr_gem->exec_objects =
343 realloc(bufmgr_gem->exec_objects,
344 sizeof(*bufmgr_gem->exec_objects) * new_size);
345 bufmgr_gem->exec_bos =
346 realloc(bufmgr_gem->exec_bos,
347 sizeof(*bufmgr_gem->exec_bos) * new_size);
348 bufmgr_gem->exec_size = new_size;
351 index = bufmgr_gem->exec_count;
352 bo_gem->validate_index = index;
353 /* Fill in array entry */
354 bufmgr_gem->exec_objects[index].handle = bo_gem->gem_handle;
355 bufmgr_gem->exec_objects[index].relocation_count = bo_gem->reloc_count;
356 bufmgr_gem->exec_objects[index].relocs_ptr = (uintptr_t) bo_gem->relocs;
357 bufmgr_gem->exec_objects[index].alignment = 0;
358 bufmgr_gem->exec_objects[index].offset = 0;
359 bufmgr_gem->exec_bos[index] = bo;
360 drm_intel_gem_bo_reference(bo);
361 bufmgr_gem->exec_count++;
364 #define RELOC_BUF_SIZE(x) ((I915_RELOC_HEADER + x * I915_RELOC0_STRIDE) * \
368 drm_intel_setup_reloc_list(drm_intel_bo *bo)
370 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
371 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
372 unsigned int max_relocs = bufmgr_gem->max_relocs;
374 if (bo->size / 4 < max_relocs)
375 max_relocs = bo->size / 4;
377 bo_gem->relocs = malloc(max_relocs *
378 sizeof(struct drm_i915_gem_relocation_entry));
379 bo_gem->reloc_target_bo = malloc(max_relocs * sizeof(drm_intel_bo *));
385 drm_intel_gem_bo_busy(drm_intel_bo *bo)
387 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
388 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
389 struct drm_i915_gem_busy busy;
392 memset(&busy, 0, sizeof(busy));
393 busy.handle = bo_gem->gem_handle;
395 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_BUSY, &busy);
397 return (ret == 0 && busy.busy);
401 drm_intel_gem_bo_madvise_internal(drm_intel_bufmgr_gem *bufmgr_gem,
402 drm_intel_bo_gem *bo_gem, int state)
404 struct drm_i915_gem_madvise madv;
406 madv.handle = bo_gem->gem_handle;
409 ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MADVISE, &madv);
411 return madv.retained;
415 drm_intel_gem_bo_madvise(drm_intel_bo *bo, int madv)
417 return drm_intel_gem_bo_madvise_internal
418 ((drm_intel_bufmgr_gem *) bo->bufmgr,
419 (drm_intel_bo_gem *) bo,
423 /* drop the oldest entries that have been purged by the kernel */
425 drm_intel_gem_bo_cache_purge_bucket(drm_intel_bufmgr_gem *bufmgr_gem,
426 struct drm_intel_gem_bo_bucket *bucket)
428 while (!DRMLISTEMPTY(&bucket->head)) {
429 drm_intel_bo_gem *bo_gem;
431 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
432 bucket->head.next, head);
433 if (drm_intel_gem_bo_madvise_internal
434 (bufmgr_gem, bo_gem, I915_MADV_DONTNEED))
437 DRMLISTDEL(&bo_gem->head);
438 drm_intel_gem_bo_free(&bo_gem->bo);
442 static drm_intel_bo *
443 drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr,
448 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
449 drm_intel_bo_gem *bo_gem;
450 unsigned int page_size = getpagesize();
452 struct drm_intel_gem_bo_bucket *bucket;
453 int alloc_from_cache;
454 unsigned long bo_size;
457 if (flags & BO_ALLOC_FOR_RENDER)
460 /* Round the allocated size up to a power of two number of pages. */
461 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, size);
463 /* If we don't have caching at this size, don't actually round the
466 if (bucket == NULL) {
468 if (bo_size < page_size)
471 bo_size = bucket->size;
474 pthread_mutex_lock(&bufmgr_gem->lock);
475 /* Get a buffer out of the cache if available */
477 alloc_from_cache = 0;
478 if (bucket != NULL && !DRMLISTEMPTY(&bucket->head)) {
480 /* Allocate new render-target BOs from the tail (MRU)
481 * of the list, as it will likely be hot in the GPU
482 * cache and in the aperture for us.
484 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
485 bucket->head.prev, head);
486 DRMLISTDEL(&bo_gem->head);
487 alloc_from_cache = 1;
489 /* For non-render-target BOs (where we're probably
490 * going to map it first thing in order to fill it
491 * with data), check if the last BO in the cache is
492 * unbusy, and only reuse in that case. Otherwise,
493 * allocating a new buffer is probably faster than
494 * waiting for the GPU to finish.
496 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
497 bucket->head.next, head);
498 if (!drm_intel_gem_bo_busy(&bo_gem->bo)) {
499 alloc_from_cache = 1;
500 DRMLISTDEL(&bo_gem->head);
504 if (alloc_from_cache) {
505 if (!drm_intel_gem_bo_madvise_internal
506 (bufmgr_gem, bo_gem, I915_MADV_WILLNEED)) {
507 drm_intel_gem_bo_free(&bo_gem->bo);
508 drm_intel_gem_bo_cache_purge_bucket(bufmgr_gem,
514 pthread_mutex_unlock(&bufmgr_gem->lock);
516 if (!alloc_from_cache) {
517 struct drm_i915_gem_create create;
519 bo_gem = calloc(1, sizeof(*bo_gem));
523 bo_gem->bo.size = bo_size;
524 memset(&create, 0, sizeof(create));
525 create.size = bo_size;
527 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_CREATE, &create);
528 bo_gem->gem_handle = create.handle;
529 bo_gem->bo.handle = bo_gem->gem_handle;
534 bo_gem->bo.bufmgr = bufmgr;
538 atomic_set(&bo_gem->refcount, 1);
539 bo_gem->validate_index = -1;
540 bo_gem->reloc_tree_size = bo_gem->bo.size;
541 bo_gem->reloc_tree_fences = 0;
542 bo_gem->used_as_reloc_target = 0;
543 bo_gem->tiling_mode = I915_TILING_NONE;
544 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
545 bo_gem->reusable = 1;
547 DBG("bo_create: buf %d (%s) %ldb\n",
548 bo_gem->gem_handle, bo_gem->name, size);
553 static drm_intel_bo *
554 drm_intel_gem_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
557 unsigned int alignment)
559 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size,
560 BO_ALLOC_FOR_RENDER);
563 static drm_intel_bo *
564 drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr,
567 unsigned int alignment)
569 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, 0);
572 static drm_intel_bo *
573 drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
574 int x, int y, int cpp, uint32_t *tiling_mode,
575 unsigned long *pitch, unsigned long flags)
577 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
579 unsigned long size, stride, aligned_y = y;
582 if (*tiling_mode == I915_TILING_NONE)
583 aligned_y = ALIGN(y, 2);
584 else if (*tiling_mode == I915_TILING_X)
585 aligned_y = ALIGN(y, 8);
586 else if (*tiling_mode == I915_TILING_Y)
587 aligned_y = ALIGN(y, 32);
590 stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, *tiling_mode);
591 size = stride * aligned_y;
592 size = drm_intel_gem_bo_tile_size(bufmgr_gem, size, tiling_mode);
594 bo = drm_intel_gem_bo_alloc_internal(bufmgr, name, size, flags);
598 ret = drm_intel_gem_bo_set_tiling(bo, tiling_mode, stride);
600 drm_intel_gem_bo_unreference(bo);
610 * Returns a drm_intel_bo wrapping the given buffer object handle.
612 * This can be used when one application needs to pass a buffer object
616 drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
620 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
621 drm_intel_bo_gem *bo_gem;
623 struct drm_gem_open open_arg;
624 struct drm_i915_gem_get_tiling get_tiling;
626 bo_gem = calloc(1, sizeof(*bo_gem));
630 memset(&open_arg, 0, sizeof(open_arg));
631 open_arg.name = handle;
632 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_OPEN, &open_arg);
634 fprintf(stderr, "Couldn't reference %s handle 0x%08x: %s\n",
635 name, handle, strerror(errno));
639 bo_gem->bo.size = open_arg.size;
640 bo_gem->bo.offset = 0;
641 bo_gem->bo.virtual = NULL;
642 bo_gem->bo.bufmgr = bufmgr;
644 atomic_set(&bo_gem->refcount, 1);
645 bo_gem->validate_index = -1;
646 bo_gem->gem_handle = open_arg.handle;
647 bo_gem->global_name = handle;
648 bo_gem->reusable = 0;
650 memset(&get_tiling, 0, sizeof(get_tiling));
651 get_tiling.handle = bo_gem->gem_handle;
652 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_GET_TILING, &get_tiling);
654 drm_intel_gem_bo_unreference(&bo_gem->bo);
657 bo_gem->tiling_mode = get_tiling.tiling_mode;
658 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
659 if (bo_gem->tiling_mode == I915_TILING_NONE)
660 bo_gem->reloc_tree_fences = 0;
662 bo_gem->reloc_tree_fences = 1;
664 DBG("bo_create_from_handle: %d (%s)\n", handle, bo_gem->name);
670 drm_intel_gem_bo_free(drm_intel_bo *bo)
672 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
673 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
674 struct drm_gem_close close;
677 if (bo_gem->mem_virtual)
678 munmap(bo_gem->mem_virtual, bo_gem->bo.size);
679 if (bo_gem->gtt_virtual)
680 munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
682 free(bo_gem->reloc_target_bo);
683 free(bo_gem->relocs);
685 /* Close this object */
686 memset(&close, 0, sizeof(close));
687 close.handle = bo_gem->gem_handle;
688 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close);
691 "DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
692 bo_gem->gem_handle, bo_gem->name, strerror(errno));
697 /** Frees all cached buffers significantly older than @time. */
699 drm_intel_gem_cleanup_bo_cache(drm_intel_bufmgr_gem *bufmgr_gem, time_t time)
703 for (i = 0; i < DRM_INTEL_GEM_BO_BUCKETS; i++) {
704 struct drm_intel_gem_bo_bucket *bucket =
705 &bufmgr_gem->cache_bucket[i];
707 while (!DRMLISTEMPTY(&bucket->head)) {
708 drm_intel_bo_gem *bo_gem;
710 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
711 bucket->head.next, head);
712 if (time - bo_gem->free_time <= 1)
715 DRMLISTDEL(&bo_gem->head);
717 drm_intel_gem_bo_free(&bo_gem->bo);
723 drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time)
725 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
726 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
727 struct drm_intel_gem_bo_bucket *bucket;
728 uint32_t tiling_mode;
731 /* Unreference all the target buffers */
732 for (i = 0; i < bo_gem->reloc_count; i++) {
733 drm_intel_gem_bo_unreference_locked_timed(bo_gem->
738 DBG("bo_unreference final: %d (%s)\n",
739 bo_gem->gem_handle, bo_gem->name);
741 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, bo->size);
742 /* Put the buffer into our internal cache for reuse if we can. */
743 tiling_mode = I915_TILING_NONE;
744 if (bufmgr_gem->bo_reuse && bo_gem->reusable && bucket != NULL &&
745 drm_intel_gem_bo_set_tiling(bo, &tiling_mode, 0) == 0 &&
746 drm_intel_gem_bo_madvise_internal(bufmgr_gem, bo_gem,
747 I915_MADV_DONTNEED)) {
748 bo_gem->free_time = time;
751 bo_gem->validate_index = -1;
752 bo_gem->reloc_count = 0;
754 DRMLISTADDTAIL(&bo_gem->head, &bucket->head);
756 drm_intel_gem_cleanup_bo_cache(bufmgr_gem, time);
758 drm_intel_gem_bo_free(bo);
762 static void drm_intel_gem_bo_unreference_locked(drm_intel_bo *bo)
764 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
766 assert(atomic_read(&bo_gem->refcount) > 0);
767 if (atomic_dec_and_test(&bo_gem->refcount)) {
768 struct timespec time;
770 clock_gettime(CLOCK_MONOTONIC, &time);
771 drm_intel_gem_bo_unreference_final(bo, time.tv_sec);
775 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
778 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
780 assert(atomic_read(&bo_gem->refcount) > 0);
781 if (atomic_dec_and_test(&bo_gem->refcount))
782 drm_intel_gem_bo_unreference_final(bo, time);
785 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo)
787 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
789 assert(atomic_read(&bo_gem->refcount) > 0);
790 if (atomic_dec_and_test(&bo_gem->refcount)) {
791 drm_intel_bufmgr_gem *bufmgr_gem =
792 (drm_intel_bufmgr_gem *) bo->bufmgr;
793 struct timespec time;
795 clock_gettime(CLOCK_MONOTONIC, &time);
797 pthread_mutex_lock(&bufmgr_gem->lock);
798 drm_intel_gem_bo_unreference_final(bo, time.tv_sec);
799 pthread_mutex_unlock(&bufmgr_gem->lock);
803 static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable)
805 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
806 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
807 struct drm_i915_gem_set_domain set_domain;
810 pthread_mutex_lock(&bufmgr_gem->lock);
812 /* Allow recursive mapping. Mesa may recursively map buffers with
813 * nested display loops.
815 if (!bo_gem->mem_virtual) {
816 struct drm_i915_gem_mmap mmap_arg;
818 DBG("bo_map: %d (%s)\n", bo_gem->gem_handle, bo_gem->name);
820 memset(&mmap_arg, 0, sizeof(mmap_arg));
821 mmap_arg.handle = bo_gem->gem_handle;
823 mmap_arg.size = bo->size;
824 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MMAP, &mmap_arg);
827 "%s:%d: Error mapping buffer %d (%s): %s .\n",
828 __FILE__, __LINE__, bo_gem->gem_handle,
829 bo_gem->name, strerror(errno));
830 pthread_mutex_unlock(&bufmgr_gem->lock);
833 bo_gem->mem_virtual = (void *)(uintptr_t) mmap_arg.addr_ptr;
835 DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
836 bo_gem->mem_virtual);
837 bo->virtual = bo_gem->mem_virtual;
839 set_domain.handle = bo_gem->gem_handle;
840 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
842 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
844 set_domain.write_domain = 0;
846 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN,
848 } while (ret == -1 && errno == EINTR);
850 fprintf(stderr, "%s:%d: Error setting to CPU domain %d: %s\n",
851 __FILE__, __LINE__, bo_gem->gem_handle,
853 pthread_mutex_unlock(&bufmgr_gem->lock);
857 pthread_mutex_unlock(&bufmgr_gem->lock);
862 int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
864 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
865 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
866 struct drm_i915_gem_set_domain set_domain;
869 pthread_mutex_lock(&bufmgr_gem->lock);
871 /* Get a mapping of the buffer if we haven't before. */
872 if (bo_gem->gtt_virtual == NULL) {
873 struct drm_i915_gem_mmap_gtt mmap_arg;
875 DBG("bo_map_gtt: mmap %d (%s)\n", bo_gem->gem_handle,
878 memset(&mmap_arg, 0, sizeof(mmap_arg));
879 mmap_arg.handle = bo_gem->gem_handle;
881 /* Get the fake offset back... */
882 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MMAP_GTT,
886 "%s:%d: Error preparing buffer map %d (%s): %s .\n",
888 bo_gem->gem_handle, bo_gem->name,
890 pthread_mutex_unlock(&bufmgr_gem->lock);
895 bo_gem->gtt_virtual = mmap(0, bo->size, PROT_READ | PROT_WRITE,
896 MAP_SHARED, bufmgr_gem->fd,
898 if (bo_gem->gtt_virtual == MAP_FAILED) {
900 "%s:%d: Error mapping buffer %d (%s): %s .\n",
902 bo_gem->gem_handle, bo_gem->name,
904 pthread_mutex_unlock(&bufmgr_gem->lock);
909 bo->virtual = bo_gem->gtt_virtual;
911 DBG("bo_map_gtt: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
912 bo_gem->gtt_virtual);
914 /* Now move it to the GTT domain so that the CPU caches are flushed */
915 set_domain.handle = bo_gem->gem_handle;
916 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
917 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
919 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN,
921 } while (ret == -1 && errno == EINTR);
924 fprintf(stderr, "%s:%d: Error setting domain %d: %s\n",
925 __FILE__, __LINE__, bo_gem->gem_handle,
929 pthread_mutex_unlock(&bufmgr_gem->lock);
934 int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo)
936 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
937 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
943 assert(bo_gem->gtt_virtual != NULL);
945 pthread_mutex_lock(&bufmgr_gem->lock);
947 pthread_mutex_unlock(&bufmgr_gem->lock);
952 static int drm_intel_gem_bo_unmap(drm_intel_bo *bo)
954 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
955 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
956 struct drm_i915_gem_sw_finish sw_finish;
962 assert(bo_gem->mem_virtual != NULL);
964 pthread_mutex_lock(&bufmgr_gem->lock);
966 /* Cause a flush to happen if the buffer's pinned for scanout, so the
967 * results show up in a timely manner.
969 sw_finish.handle = bo_gem->gem_handle;
971 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_SW_FINISH,
973 } while (ret == -1 && errno == EINTR);
976 pthread_mutex_unlock(&bufmgr_gem->lock);
981 drm_intel_gem_bo_subdata(drm_intel_bo *bo, unsigned long offset,
982 unsigned long size, const void *data)
984 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
985 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
986 struct drm_i915_gem_pwrite pwrite;
989 memset(&pwrite, 0, sizeof(pwrite));
990 pwrite.handle = bo_gem->gem_handle;
991 pwrite.offset = offset;
993 pwrite.data_ptr = (uint64_t) (uintptr_t) data;
995 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_PWRITE, &pwrite);
996 } while (ret == -1 && errno == EINTR);
999 "%s:%d: Error writing data to buffer %d: (%d %d) %s .\n",
1000 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1001 (int)size, strerror(errno));
1007 drm_intel_gem_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id)
1009 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1010 struct drm_i915_get_pipe_from_crtc_id get_pipe_from_crtc_id;
1013 get_pipe_from_crtc_id.crtc_id = crtc_id;
1014 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID,
1015 &get_pipe_from_crtc_id);
1017 /* We return -1 here to signal that we don't
1018 * know which pipe is associated with this crtc.
1019 * This lets the caller know that this information
1020 * isn't available; using the wrong pipe for
1021 * vblank waiting can cause the chipset to lock up
1026 return get_pipe_from_crtc_id.pipe;
1030 drm_intel_gem_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
1031 unsigned long size, void *data)
1033 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1034 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1035 struct drm_i915_gem_pread pread;
1038 memset(&pread, 0, sizeof(pread));
1039 pread.handle = bo_gem->gem_handle;
1040 pread.offset = offset;
1042 pread.data_ptr = (uint64_t) (uintptr_t) data;
1044 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_PREAD, &pread);
1045 } while (ret == -1 && errno == EINTR);
1048 "%s:%d: Error reading data from buffer %d: (%d %d) %s .\n",
1049 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1050 (int)size, strerror(errno));
1055 /** Waits for all GPU rendering to the object to have completed. */
1057 drm_intel_gem_bo_wait_rendering(drm_intel_bo *bo)
1059 drm_intel_gem_bo_start_gtt_access(bo, 0);
1063 * Sets the object to the GTT read and possibly write domain, used by the X
1064 * 2D driver in the absence of kernel support to do drm_intel_gem_bo_map_gtt().
1066 * In combination with drm_intel_gem_bo_pin() and manual fence management, we
1067 * can do tiled pixmaps this way.
1070 drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable)
1072 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1073 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1074 struct drm_i915_gem_set_domain set_domain;
1077 set_domain.handle = bo_gem->gem_handle;
1078 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1079 set_domain.write_domain = write_enable ? I915_GEM_DOMAIN_GTT : 0;
1081 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN,
1083 } while (ret == -1 && errno == EINTR);
1086 "%s:%d: Error setting memory domains %d (%08x %08x): %s .\n",
1087 __FILE__, __LINE__, bo_gem->gem_handle,
1088 set_domain.read_domains, set_domain.write_domain,
1094 drm_intel_bufmgr_gem_destroy(drm_intel_bufmgr *bufmgr)
1096 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1099 free(bufmgr_gem->exec_objects);
1100 free(bufmgr_gem->exec_bos);
1102 pthread_mutex_destroy(&bufmgr_gem->lock);
1104 /* Free any cached buffer objects we were going to reuse */
1105 for (i = 0; i < DRM_INTEL_GEM_BO_BUCKETS; i++) {
1106 struct drm_intel_gem_bo_bucket *bucket =
1107 &bufmgr_gem->cache_bucket[i];
1108 drm_intel_bo_gem *bo_gem;
1110 while (!DRMLISTEMPTY(&bucket->head)) {
1111 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1112 bucket->head.next, head);
1113 DRMLISTDEL(&bo_gem->head);
1115 drm_intel_gem_bo_free(&bo_gem->bo);
1123 * Adds the target buffer to the validation list and adds the relocation
1124 * to the reloc_buffer's relocation list.
1126 * The relocation entry at the given offset must already contain the
1127 * precomputed relocation value, because the kernel will optimize out
1128 * the relocation entry write when the buffer hasn't moved from the
1129 * last known offset in target_bo.
1132 drm_intel_gem_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1133 drm_intel_bo *target_bo, uint32_t target_offset,
1134 uint32_t read_domains, uint32_t write_domain)
1136 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1137 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1138 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
1140 pthread_mutex_lock(&bufmgr_gem->lock);
1142 /* Create a new relocation list if needed */
1143 if (bo_gem->relocs == NULL)
1144 drm_intel_setup_reloc_list(bo);
1146 /* Check overflow */
1147 assert(bo_gem->reloc_count < bufmgr_gem->max_relocs);
1150 assert(offset <= bo->size - 4);
1151 assert((write_domain & (write_domain - 1)) == 0);
1153 /* Make sure that we're not adding a reloc to something whose size has
1154 * already been accounted for.
1156 assert(!bo_gem->used_as_reloc_target);
1157 bo_gem->reloc_tree_size += target_bo_gem->reloc_tree_size;
1158 bo_gem->reloc_tree_fences += target_bo_gem->reloc_tree_fences;
1160 /* Flag the target to disallow further relocations in it. */
1161 target_bo_gem->used_as_reloc_target = 1;
1163 bo_gem->relocs[bo_gem->reloc_count].offset = offset;
1164 bo_gem->relocs[bo_gem->reloc_count].delta = target_offset;
1165 bo_gem->relocs[bo_gem->reloc_count].target_handle =
1166 target_bo_gem->gem_handle;
1167 bo_gem->relocs[bo_gem->reloc_count].read_domains = read_domains;
1168 bo_gem->relocs[bo_gem->reloc_count].write_domain = write_domain;
1169 bo_gem->relocs[bo_gem->reloc_count].presumed_offset = target_bo->offset;
1171 bo_gem->reloc_target_bo[bo_gem->reloc_count] = target_bo;
1172 drm_intel_gem_bo_reference(target_bo);
1174 bo_gem->reloc_count++;
1176 pthread_mutex_unlock(&bufmgr_gem->lock);
1182 * Walk the tree of relocations rooted at BO and accumulate the list of
1183 * validations to be performed and update the relocation buffers with
1184 * index values into the validation list.
1187 drm_intel_gem_bo_process_reloc(drm_intel_bo *bo)
1189 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1192 if (bo_gem->relocs == NULL)
1195 for (i = 0; i < bo_gem->reloc_count; i++) {
1196 drm_intel_bo *target_bo = bo_gem->reloc_target_bo[i];
1198 /* Continue walking the tree depth-first. */
1199 drm_intel_gem_bo_process_reloc(target_bo);
1201 /* Add the target to the validate list */
1202 drm_intel_add_validate_buffer(target_bo);
1207 drm_intel_update_buffer_offsets(drm_intel_bufmgr_gem *bufmgr_gem)
1211 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1212 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1213 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1215 /* Update the buffer offset */
1216 if (bufmgr_gem->exec_objects[i].offset != bo->offset) {
1217 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1218 bo_gem->gem_handle, bo_gem->name, bo->offset,
1219 (unsigned long long)bufmgr_gem->exec_objects[i].
1221 bo->offset = bufmgr_gem->exec_objects[i].offset;
1227 drm_intel_gem_bo_exec(drm_intel_bo *bo, int used,
1228 drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
1230 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1231 struct drm_i915_gem_execbuffer execbuf;
1234 pthread_mutex_lock(&bufmgr_gem->lock);
1235 /* Update indices and set up the validate list. */
1236 drm_intel_gem_bo_process_reloc(bo);
1238 /* Add the batch buffer to the validation list. There are no
1239 * relocations pointing to it.
1241 drm_intel_add_validate_buffer(bo);
1243 execbuf.buffers_ptr = (uintptr_t) bufmgr_gem->exec_objects;
1244 execbuf.buffer_count = bufmgr_gem->exec_count;
1245 execbuf.batch_start_offset = 0;
1246 execbuf.batch_len = used;
1247 execbuf.cliprects_ptr = (uintptr_t) cliprects;
1248 execbuf.num_cliprects = num_cliprects;
1253 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_EXECBUFFER,
1255 } while (ret != 0 && errno == EAGAIN);
1257 if (ret != 0 && errno == ENOMEM) {
1259 "Execbuffer fails to pin. "
1260 "Estimate: %u. Actual: %u. Available: %u\n",
1261 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
1264 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
1267 (unsigned int)bufmgr_gem->gtt_size);
1269 drm_intel_update_buffer_offsets(bufmgr_gem);
1271 if (bufmgr_gem->bufmgr.debug)
1272 drm_intel_gem_dump_validation_list(bufmgr_gem);
1274 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1275 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1276 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1278 /* Disconnect the buffer from the validate list */
1279 bo_gem->validate_index = -1;
1280 drm_intel_gem_bo_unreference_locked(bo);
1281 bufmgr_gem->exec_bos[i] = NULL;
1283 bufmgr_gem->exec_count = 0;
1284 pthread_mutex_unlock(&bufmgr_gem->lock);
1290 drm_intel_gem_bo_pin(drm_intel_bo *bo, uint32_t alignment)
1292 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1293 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1294 struct drm_i915_gem_pin pin;
1297 memset(&pin, 0, sizeof(pin));
1298 pin.handle = bo_gem->gem_handle;
1299 pin.alignment = alignment;
1302 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_PIN, &pin);
1303 } while (ret == -1 && errno == EINTR);
1308 bo->offset = pin.offset;
1313 drm_intel_gem_bo_unpin(drm_intel_bo *bo)
1315 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1316 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1317 struct drm_i915_gem_unpin unpin;
1320 memset(&unpin, 0, sizeof(unpin));
1321 unpin.handle = bo_gem->gem_handle;
1323 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_UNPIN, &unpin);
1331 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1334 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1335 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1336 struct drm_i915_gem_set_tiling set_tiling;
1339 if (bo_gem->global_name == 0 && *tiling_mode == bo_gem->tiling_mode)
1342 /* If we're going from non-tiling to tiling, bump fence count */
1343 if (bo_gem->tiling_mode == I915_TILING_NONE)
1344 bo_gem->reloc_tree_fences++;
1346 memset(&set_tiling, 0, sizeof(set_tiling));
1347 set_tiling.handle = bo_gem->gem_handle;
1348 set_tiling.tiling_mode = *tiling_mode;
1349 set_tiling.stride = stride;
1351 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_SET_TILING, &set_tiling);
1353 *tiling_mode = bo_gem->tiling_mode;
1356 bo_gem->tiling_mode = set_tiling.tiling_mode;
1357 bo_gem->swizzle_mode = set_tiling.swizzle_mode;
1359 /* If we're going from tiling to non-tiling, drop fence count */
1360 if (bo_gem->tiling_mode == I915_TILING_NONE)
1361 bo_gem->reloc_tree_fences--;
1363 *tiling_mode = bo_gem->tiling_mode;
1368 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1369 uint32_t * swizzle_mode)
1371 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1373 *tiling_mode = bo_gem->tiling_mode;
1374 *swizzle_mode = bo_gem->swizzle_mode;
1379 drm_intel_gem_bo_flink(drm_intel_bo *bo, uint32_t * name)
1381 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1382 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1383 struct drm_gem_flink flink;
1386 if (!bo_gem->global_name) {
1387 memset(&flink, 0, sizeof(flink));
1388 flink.handle = bo_gem->gem_handle;
1390 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_FLINK, &flink);
1393 bo_gem->global_name = flink.name;
1394 bo_gem->reusable = 0;
1397 *name = bo_gem->global_name;
1402 * Enables unlimited caching of buffer objects for reuse.
1404 * This is potentially very memory expensive, as the cache at each bucket
1405 * size is only bounded by how many buffers of that size we've managed to have
1406 * in flight at once.
1409 drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr)
1411 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1413 bufmgr_gem->bo_reuse = 1;
1417 * Return the additional aperture space required by the tree of buffer objects
1421 drm_intel_gem_bo_get_aperture_space(drm_intel_bo *bo)
1423 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1427 if (bo == NULL || bo_gem->included_in_check_aperture)
1431 bo_gem->included_in_check_aperture = 1;
1433 for (i = 0; i < bo_gem->reloc_count; i++)
1435 drm_intel_gem_bo_get_aperture_space(bo_gem->
1436 reloc_target_bo[i]);
1442 * Count the number of buffers in this list that need a fence reg
1444 * If the count is greater than the number of available regs, we'll have
1445 * to ask the caller to resubmit a batch with fewer tiled buffers.
1447 * This function over-counts if the same buffer is used multiple times.
1450 drm_intel_gem_total_fences(drm_intel_bo ** bo_array, int count)
1453 unsigned int total = 0;
1455 for (i = 0; i < count; i++) {
1456 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
1461 total += bo_gem->reloc_tree_fences;
1467 * Clear the flag set by drm_intel_gem_bo_get_aperture_space() so we're ready
1468 * for the next drm_intel_bufmgr_check_aperture_space() call.
1471 drm_intel_gem_bo_clear_aperture_space_flag(drm_intel_bo *bo)
1473 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1476 if (bo == NULL || !bo_gem->included_in_check_aperture)
1479 bo_gem->included_in_check_aperture = 0;
1481 for (i = 0; i < bo_gem->reloc_count; i++)
1482 drm_intel_gem_bo_clear_aperture_space_flag(bo_gem->
1483 reloc_target_bo[i]);
1487 * Return a conservative estimate for the amount of aperture required
1488 * for a collection of buffers. This may double-count some buffers.
1491 drm_intel_gem_estimate_batch_space(drm_intel_bo **bo_array, int count)
1494 unsigned int total = 0;
1496 for (i = 0; i < count; i++) {
1497 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
1499 total += bo_gem->reloc_tree_size;
1505 * Return the amount of aperture needed for a collection of buffers.
1506 * This avoids double counting any buffers, at the cost of looking
1507 * at every buffer in the set.
1510 drm_intel_gem_compute_batch_space(drm_intel_bo **bo_array, int count)
1513 unsigned int total = 0;
1515 for (i = 0; i < count; i++) {
1516 total += drm_intel_gem_bo_get_aperture_space(bo_array[i]);
1517 /* For the first buffer object in the array, we get an
1518 * accurate count back for its reloc_tree size (since nothing
1519 * had been flagged as being counted yet). We can save that
1520 * value out as a more conservative reloc_tree_size that
1521 * avoids double-counting target buffers. Since the first
1522 * buffer happens to usually be the batch buffer in our
1523 * callers, this can pull us back from doing the tree
1524 * walk on every new batch emit.
1527 drm_intel_bo_gem *bo_gem =
1528 (drm_intel_bo_gem *) bo_array[i];
1529 bo_gem->reloc_tree_size = total;
1533 for (i = 0; i < count; i++)
1534 drm_intel_gem_bo_clear_aperture_space_flag(bo_array[i]);
1539 * Return -1 if the batchbuffer should be flushed before attempting to
1540 * emit rendering referencing the buffers pointed to by bo_array.
1542 * This is required because if we try to emit a batchbuffer with relocations
1543 * to a tree of buffers that won't simultaneously fit in the aperture,
1544 * the rendering will return an error at a point where the software is not
1545 * prepared to recover from it.
1547 * However, we also want to emit the batchbuffer significantly before we reach
1548 * the limit, as a series of batchbuffers each of which references buffers
1549 * covering almost all of the aperture means that at each emit we end up
1550 * waiting to evict a buffer from the last rendering, and we get synchronous
1551 * performance. By emitting smaller batchbuffers, we eat some CPU overhead to
1552 * get better parallelism.
1555 drm_intel_gem_check_aperture_space(drm_intel_bo **bo_array, int count)
1557 drm_intel_bufmgr_gem *bufmgr_gem =
1558 (drm_intel_bufmgr_gem *) bo_array[0]->bufmgr;
1559 unsigned int total = 0;
1560 unsigned int threshold = bufmgr_gem->gtt_size * 3 / 4;
1563 /* Check for fence reg constraints if necessary */
1564 if (bufmgr_gem->available_fences) {
1565 total_fences = drm_intel_gem_total_fences(bo_array, count);
1566 if (total_fences > bufmgr_gem->available_fences)
1570 total = drm_intel_gem_estimate_batch_space(bo_array, count);
1572 if (total > threshold)
1573 total = drm_intel_gem_compute_batch_space(bo_array, count);
1575 if (total > threshold) {
1576 DBG("check_space: overflowed available aperture, "
1578 total / 1024, (int)bufmgr_gem->gtt_size / 1024);
1581 DBG("drm_check_space: total %dkb vs bufgr %dkb\n", total / 1024,
1582 (int)bufmgr_gem->gtt_size / 1024);
1588 * Disable buffer reuse for objects which are shared with the kernel
1589 * as scanout buffers
1592 drm_intel_gem_bo_disable_reuse(drm_intel_bo *bo)
1594 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1596 bo_gem->reusable = 0;
1601 _drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
1603 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1606 for (i = 0; i < bo_gem->reloc_count; i++) {
1607 if (bo_gem->reloc_target_bo[i] == target_bo)
1609 if (_drm_intel_gem_bo_references(bo_gem->reloc_target_bo[i],
1617 /** Return true if target_bo is referenced by bo's relocation tree. */
1619 drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
1621 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
1623 if (bo == NULL || target_bo == NULL)
1625 if (target_bo_gem->used_as_reloc_target)
1626 return _drm_intel_gem_bo_references(bo, target_bo);
1631 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
1632 * and manage map buffer objections.
1634 * \param fd File descriptor of the opened DRM device.
1637 drm_intel_bufmgr_gem_init(int fd, int batch_size)
1639 drm_intel_bufmgr_gem *bufmgr_gem;
1640 struct drm_i915_gem_get_aperture aperture;
1641 drm_i915_getparam_t gp;
1645 bufmgr_gem = calloc(1, sizeof(*bufmgr_gem));
1646 bufmgr_gem->fd = fd;
1648 if (pthread_mutex_init(&bufmgr_gem->lock, NULL) != 0) {
1653 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
1656 bufmgr_gem->gtt_size = aperture.aper_available_size;
1658 fprintf(stderr, "DRM_IOCTL_I915_GEM_APERTURE failed: %s\n",
1660 bufmgr_gem->gtt_size = 128 * 1024 * 1024;
1661 fprintf(stderr, "Assuming %dkB available aperture size.\n"
1662 "May lead to reduced performance or incorrect "
1664 (int)bufmgr_gem->gtt_size / 1024);
1667 gp.param = I915_PARAM_CHIPSET_ID;
1668 gp.value = &bufmgr_gem->pci_device;
1669 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
1671 fprintf(stderr, "get chip id failed: %d [%d]\n", ret, errno);
1672 fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value);
1675 if (!IS_I965G(bufmgr_gem)) {
1676 gp.param = I915_PARAM_NUM_FENCES_AVAIL;
1677 gp.value = &bufmgr_gem->available_fences;
1678 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
1680 fprintf(stderr, "get fences failed: %d [%d]\n", ret,
1682 fprintf(stderr, "param: %d, val: %d\n", gp.param,
1684 bufmgr_gem->available_fences = 0;
1688 /* Let's go with one relocation per every 2 dwords (but round down a bit
1689 * since a power of two will mean an extra page allocation for the reloc
1692 * Every 4 was too few for the blender benchmark.
1694 bufmgr_gem->max_relocs = batch_size / sizeof(uint32_t) / 2 - 2;
1696 bufmgr_gem->bufmgr.bo_alloc = drm_intel_gem_bo_alloc;
1697 bufmgr_gem->bufmgr.bo_alloc_for_render =
1698 drm_intel_gem_bo_alloc_for_render;
1699 bufmgr_gem->bufmgr.bo_alloc_tiled = drm_intel_gem_bo_alloc_tiled;
1700 bufmgr_gem->bufmgr.bo_reference = drm_intel_gem_bo_reference;
1701 bufmgr_gem->bufmgr.bo_unreference = drm_intel_gem_bo_unreference;
1702 bufmgr_gem->bufmgr.bo_map = drm_intel_gem_bo_map;
1703 bufmgr_gem->bufmgr.bo_unmap = drm_intel_gem_bo_unmap;
1704 bufmgr_gem->bufmgr.bo_subdata = drm_intel_gem_bo_subdata;
1705 bufmgr_gem->bufmgr.bo_get_subdata = drm_intel_gem_bo_get_subdata;
1706 bufmgr_gem->bufmgr.bo_wait_rendering = drm_intel_gem_bo_wait_rendering;
1707 bufmgr_gem->bufmgr.bo_emit_reloc = drm_intel_gem_bo_emit_reloc;
1708 bufmgr_gem->bufmgr.bo_pin = drm_intel_gem_bo_pin;
1709 bufmgr_gem->bufmgr.bo_unpin = drm_intel_gem_bo_unpin;
1710 bufmgr_gem->bufmgr.bo_get_tiling = drm_intel_gem_bo_get_tiling;
1711 bufmgr_gem->bufmgr.bo_set_tiling = drm_intel_gem_bo_set_tiling;
1712 bufmgr_gem->bufmgr.bo_flink = drm_intel_gem_bo_flink;
1713 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec;
1714 bufmgr_gem->bufmgr.bo_busy = drm_intel_gem_bo_busy;
1715 bufmgr_gem->bufmgr.bo_madvise = drm_intel_gem_bo_madvise;
1716 bufmgr_gem->bufmgr.destroy = drm_intel_bufmgr_gem_destroy;
1717 bufmgr_gem->bufmgr.debug = 0;
1718 bufmgr_gem->bufmgr.check_aperture_space =
1719 drm_intel_gem_check_aperture_space;
1720 bufmgr_gem->bufmgr.bo_disable_reuse = drm_intel_gem_bo_disable_reuse;
1721 bufmgr_gem->bufmgr.get_pipe_from_crtc_id =
1722 drm_intel_gem_get_pipe_from_crtc_id;
1723 bufmgr_gem->bufmgr.bo_references = drm_intel_gem_bo_references;
1725 /* Initialize the linked lists for BO reuse cache. */
1726 for (i = 0, size = 4096; i < DRM_INTEL_GEM_BO_BUCKETS; i++, size *= 2) {
1727 DRMINITLISTHEAD(&bufmgr_gem->cache_bucket[i].head);
1728 bufmgr_gem->cache_bucket[i].size = size;
1731 return &bufmgr_gem->bufmgr;