1 /**************************************************************************
3 * Copyright © 2007 Red Hat Inc.
4 * Copyright © 2007 Intel Corporation
5 * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
29 **************************************************************************/
31 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
32 * Keith Whitwell <keithw-at-tungstengraphics-dot-com>
33 * Eric Anholt <eric@anholt.net>
34 * Dave Airlie <airlied@linux.ie>
49 #include <sys/ioctl.h>
52 #include <sys/types.h>
55 #include "libdrm_lists.h"
56 #include "intel_atomic.h"
57 #include "intel_bufmgr.h"
58 #include "intel_bufmgr_priv.h"
59 #include "intel_chipset.h"
64 #define DBG(...) do { \
65 if (bufmgr_gem->bufmgr.debug) \
66 fprintf(stderr, __VA_ARGS__); \
69 typedef struct _drm_intel_bo_gem drm_intel_bo_gem;
71 struct drm_intel_gem_bo_bucket {
76 /* Only cache objects up to 64MB. Bigger than that, and the rounding of the
77 * size makes many operations fail that wouldn't otherwise.
79 #define DRM_INTEL_GEM_BO_BUCKETS 14
80 typedef struct _drm_intel_bufmgr_gem {
81 drm_intel_bufmgr bufmgr;
89 struct drm_i915_gem_exec_object *exec_objects;
90 struct drm_i915_gem_exec_object2 *exec2_objects;
91 drm_intel_bo **exec_bos;
95 /** Array of lists of cached gem objects of power-of-two sizes */
96 struct drm_intel_gem_bo_bucket cache_bucket[DRM_INTEL_GEM_BO_BUCKETS];
104 } drm_intel_bufmgr_gem;
106 #define DRM_INTEL_RELOC_FENCE (1<<0)
108 typedef struct _drm_intel_reloc_target_info {
111 } drm_intel_reloc_target;
113 struct _drm_intel_bo_gem {
121 * Kenel-assigned global name for this object
123 unsigned int global_name;
126 * Index of the buffer within the validation list while preparing a
127 * batchbuffer execution.
132 * Current tiling mode
134 uint32_t tiling_mode;
135 uint32_t swizzle_mode;
139 /** Array passed to the DRM containing relocation information. */
140 struct drm_i915_gem_relocation_entry *relocs;
142 * Array of info structs corresponding to relocs[i].target_handle etc
144 drm_intel_reloc_target *reloc_target_info;
145 /** Number of entries in relocs */
147 /** Mapped address for the buffer, saved across map/unmap cycles */
149 /** GTT virtual address for the buffer, saved across map/unmap cycles */
156 * Boolean of whether this BO and its children have been included in
157 * the current drm_intel_bufmgr_check_aperture_space() total.
159 char included_in_check_aperture;
162 * Boolean of whether this buffer has been used as a relocation
163 * target and had its size accounted for, and thus can't have any
164 * further relocations added to it.
166 char used_as_reloc_target;
169 * Boolean of whether we have encountered an error whilst building the relocation tree.
174 * Boolean of whether this buffer can be re-used
179 * Size in bytes of this buffer and its relocation descendents.
181 * Used to avoid costly tree walking in
182 * drm_intel_bufmgr_check_aperture in the common case.
187 * Number of potential fence registers required by this buffer and its
190 int reloc_tree_fences;
194 drm_intel_gem_estimate_batch_space(drm_intel_bo ** bo_array, int count);
197 drm_intel_gem_compute_batch_space(drm_intel_bo ** bo_array, int count);
200 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
201 uint32_t * swizzle_mode);
204 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
207 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
210 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo);
212 static void drm_intel_gem_bo_free(drm_intel_bo *bo);
215 drm_intel_gem_bo_tile_size(drm_intel_bufmgr_gem *bufmgr_gem, unsigned long size,
216 uint32_t *tiling_mode)
218 unsigned long min_size, max_size;
221 if (*tiling_mode == I915_TILING_NONE)
224 /* 965+ just need multiples of page size for tiling */
225 if (bufmgr_gem->gen >= 4)
226 return ROUND_UP_TO(size, 4096);
228 /* Older chips need powers of two, of at least 512k or 1M */
229 if (bufmgr_gem->gen == 3) {
230 min_size = 1024*1024;
231 max_size = 128*1024*1024;
234 max_size = 64*1024*1024;
237 if (size > max_size) {
238 *tiling_mode = I915_TILING_NONE;
242 for (i = min_size; i < size; i <<= 1)
249 * Round a given pitch up to the minimum required for X tiling on a
250 * given chip. We use 512 as the minimum to allow for a later tiling
254 drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem,
255 unsigned long pitch, uint32_t tiling_mode)
257 unsigned long tile_width = 512;
260 if (tiling_mode == I915_TILING_NONE)
263 /* 965 is flexible */
264 if (bufmgr_gem->gen >= 4)
265 return ROUND_UP_TO(pitch, tile_width);
267 /* Pre-965 needs power of two tile width */
268 for (i = tile_width; i < pitch; i <<= 1)
274 static struct drm_intel_gem_bo_bucket *
275 drm_intel_gem_bo_bucket_for_size(drm_intel_bufmgr_gem *bufmgr_gem,
280 for (i = 0; i < DRM_INTEL_GEM_BO_BUCKETS; i++) {
281 struct drm_intel_gem_bo_bucket *bucket =
282 &bufmgr_gem->cache_bucket[i];
283 if (bucket->size >= size) {
292 drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem *bufmgr_gem)
296 for (i = 0; i < bufmgr_gem->exec_count; i++) {
297 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
298 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
300 if (bo_gem->relocs == NULL) {
301 DBG("%2d: %d (%s)\n", i, bo_gem->gem_handle,
306 for (j = 0; j < bo_gem->reloc_count; j++) {
307 drm_intel_bo *target_bo = bo_gem->reloc_target_info[j].bo;
308 drm_intel_bo_gem *target_gem =
309 (drm_intel_bo_gem *) target_bo;
311 DBG("%2d: %d (%s)@0x%08llx -> "
312 "%d (%s)@0x%08lx + 0x%08x\n",
314 bo_gem->gem_handle, bo_gem->name,
315 (unsigned long long)bo_gem->relocs[j].offset,
316 target_gem->gem_handle,
319 bo_gem->relocs[j].delta);
325 drm_intel_gem_bo_reference(drm_intel_bo *bo)
327 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
329 assert(atomic_read(&bo_gem->refcount) > 0);
330 atomic_inc(&bo_gem->refcount);
334 * Adds the given buffer to the list of buffers to be validated (moved into the
335 * appropriate memory type) with the next batch submission.
337 * If a buffer is validated multiple times in a batch submission, it ends up
338 * with the intersection of the memory type flags and the union of the
342 drm_intel_add_validate_buffer(drm_intel_bo *bo)
344 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
345 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
348 if (bo_gem->validate_index != -1)
351 /* Extend the array of validation entries as necessary. */
352 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
353 int new_size = bufmgr_gem->exec_size * 2;
358 bufmgr_gem->exec_objects =
359 realloc(bufmgr_gem->exec_objects,
360 sizeof(*bufmgr_gem->exec_objects) * new_size);
361 bufmgr_gem->exec_bos =
362 realloc(bufmgr_gem->exec_bos,
363 sizeof(*bufmgr_gem->exec_bos) * new_size);
364 bufmgr_gem->exec_size = new_size;
367 index = bufmgr_gem->exec_count;
368 bo_gem->validate_index = index;
369 /* Fill in array entry */
370 bufmgr_gem->exec_objects[index].handle = bo_gem->gem_handle;
371 bufmgr_gem->exec_objects[index].relocation_count = bo_gem->reloc_count;
372 bufmgr_gem->exec_objects[index].relocs_ptr = (uintptr_t) bo_gem->relocs;
373 bufmgr_gem->exec_objects[index].alignment = 0;
374 bufmgr_gem->exec_objects[index].offset = 0;
375 bufmgr_gem->exec_bos[index] = bo;
376 bufmgr_gem->exec_count++;
380 drm_intel_add_validate_buffer2(drm_intel_bo *bo, int need_fence)
382 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
383 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
386 if (bo_gem->validate_index != -1) {
388 bufmgr_gem->exec2_objects[bo_gem->validate_index].flags |=
389 EXEC_OBJECT_NEEDS_FENCE;
393 /* Extend the array of validation entries as necessary. */
394 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
395 int new_size = bufmgr_gem->exec_size * 2;
400 bufmgr_gem->exec2_objects =
401 realloc(bufmgr_gem->exec2_objects,
402 sizeof(*bufmgr_gem->exec2_objects) * new_size);
403 bufmgr_gem->exec_bos =
404 realloc(bufmgr_gem->exec_bos,
405 sizeof(*bufmgr_gem->exec_bos) * new_size);
406 bufmgr_gem->exec_size = new_size;
409 index = bufmgr_gem->exec_count;
410 bo_gem->validate_index = index;
411 /* Fill in array entry */
412 bufmgr_gem->exec2_objects[index].handle = bo_gem->gem_handle;
413 bufmgr_gem->exec2_objects[index].relocation_count = bo_gem->reloc_count;
414 bufmgr_gem->exec2_objects[index].relocs_ptr = (uintptr_t)bo_gem->relocs;
415 bufmgr_gem->exec2_objects[index].alignment = 0;
416 bufmgr_gem->exec2_objects[index].offset = 0;
417 bufmgr_gem->exec_bos[index] = bo;
418 bufmgr_gem->exec2_objects[index].flags = 0;
419 bufmgr_gem->exec2_objects[index].rsvd1 = 0;
420 bufmgr_gem->exec2_objects[index].rsvd2 = 0;
422 bufmgr_gem->exec2_objects[index].flags |=
423 EXEC_OBJECT_NEEDS_FENCE;
425 bufmgr_gem->exec_count++;
428 #define RELOC_BUF_SIZE(x) ((I915_RELOC_HEADER + x * I915_RELOC0_STRIDE) * \
432 drm_intel_bo_gem_set_in_aperture_size(drm_intel_bufmgr_gem *bufmgr_gem,
433 drm_intel_bo_gem *bo_gem)
437 assert(!bo_gem->used_as_reloc_target);
439 /* The older chipsets are far-less flexible in terms of tiling,
440 * and require tiled buffer to be size aligned in the aperture.
441 * This means that in the worst possible case we will need a hole
442 * twice as large as the object in order for it to fit into the
443 * aperture. Optimal packing is for wimps.
445 size = bo_gem->bo.size;
446 if (bufmgr_gem->gen < 4 && bo_gem->tiling_mode != I915_TILING_NONE)
449 bo_gem->reloc_tree_size = size;
453 drm_intel_setup_reloc_list(drm_intel_bo *bo)
455 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
456 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
457 unsigned int max_relocs = bufmgr_gem->max_relocs;
459 if (bo->size / 4 < max_relocs)
460 max_relocs = bo->size / 4;
462 bo_gem->relocs = malloc(max_relocs *
463 sizeof(struct drm_i915_gem_relocation_entry));
464 bo_gem->reloc_target_info = malloc(max_relocs *
465 sizeof(drm_intel_reloc_target *));
466 if (bo_gem->relocs == NULL || bo_gem->reloc_target_info == NULL) {
467 bo_gem->has_error = 1;
469 free (bo_gem->relocs);
470 bo_gem->relocs = NULL;
472 free (bo_gem->reloc_target_info);
473 bo_gem->reloc_target_info = NULL;
482 drm_intel_gem_bo_busy(drm_intel_bo *bo)
484 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
485 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
486 struct drm_i915_gem_busy busy;
489 memset(&busy, 0, sizeof(busy));
490 busy.handle = bo_gem->gem_handle;
493 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_BUSY, &busy);
494 } while (ret == -1 && errno == EINTR);
496 return (ret == 0 && busy.busy);
500 drm_intel_gem_bo_madvise_internal(drm_intel_bufmgr_gem *bufmgr_gem,
501 drm_intel_bo_gem *bo_gem, int state)
503 struct drm_i915_gem_madvise madv;
505 madv.handle = bo_gem->gem_handle;
508 ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MADVISE, &madv);
510 return madv.retained;
514 drm_intel_gem_bo_madvise(drm_intel_bo *bo, int madv)
516 return drm_intel_gem_bo_madvise_internal
517 ((drm_intel_bufmgr_gem *) bo->bufmgr,
518 (drm_intel_bo_gem *) bo,
522 /* drop the oldest entries that have been purged by the kernel */
524 drm_intel_gem_bo_cache_purge_bucket(drm_intel_bufmgr_gem *bufmgr_gem,
525 struct drm_intel_gem_bo_bucket *bucket)
527 while (!DRMLISTEMPTY(&bucket->head)) {
528 drm_intel_bo_gem *bo_gem;
530 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
531 bucket->head.next, head);
532 if (drm_intel_gem_bo_madvise_internal
533 (bufmgr_gem, bo_gem, I915_MADV_DONTNEED))
536 DRMLISTDEL(&bo_gem->head);
537 drm_intel_gem_bo_free(&bo_gem->bo);
541 static drm_intel_bo *
542 drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr,
547 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
548 drm_intel_bo_gem *bo_gem;
549 unsigned int page_size = getpagesize();
551 struct drm_intel_gem_bo_bucket *bucket;
552 int alloc_from_cache;
553 unsigned long bo_size;
556 if (flags & BO_ALLOC_FOR_RENDER)
559 /* Round the allocated size up to a power of two number of pages. */
560 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, size);
562 /* If we don't have caching at this size, don't actually round the
565 if (bucket == NULL) {
567 if (bo_size < page_size)
570 bo_size = bucket->size;
573 pthread_mutex_lock(&bufmgr_gem->lock);
574 /* Get a buffer out of the cache if available */
576 alloc_from_cache = 0;
577 if (bucket != NULL && !DRMLISTEMPTY(&bucket->head)) {
579 /* Allocate new render-target BOs from the tail (MRU)
580 * of the list, as it will likely be hot in the GPU
581 * cache and in the aperture for us.
583 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
584 bucket->head.prev, head);
585 DRMLISTDEL(&bo_gem->head);
586 alloc_from_cache = 1;
588 /* For non-render-target BOs (where we're probably
589 * going to map it first thing in order to fill it
590 * with data), check if the last BO in the cache is
591 * unbusy, and only reuse in that case. Otherwise,
592 * allocating a new buffer is probably faster than
593 * waiting for the GPU to finish.
595 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
596 bucket->head.next, head);
597 if (!drm_intel_gem_bo_busy(&bo_gem->bo)) {
598 alloc_from_cache = 1;
599 DRMLISTDEL(&bo_gem->head);
603 if (alloc_from_cache) {
604 if (!drm_intel_gem_bo_madvise_internal
605 (bufmgr_gem, bo_gem, I915_MADV_WILLNEED)) {
606 drm_intel_gem_bo_free(&bo_gem->bo);
607 drm_intel_gem_bo_cache_purge_bucket(bufmgr_gem,
613 pthread_mutex_unlock(&bufmgr_gem->lock);
615 if (!alloc_from_cache) {
616 struct drm_i915_gem_create create;
618 bo_gem = calloc(1, sizeof(*bo_gem));
622 bo_gem->bo.size = bo_size;
623 memset(&create, 0, sizeof(create));
624 create.size = bo_size;
627 ret = ioctl(bufmgr_gem->fd,
628 DRM_IOCTL_I915_GEM_CREATE,
630 } while (ret == -1 && errno == EINTR);
631 bo_gem->gem_handle = create.handle;
632 bo_gem->bo.handle = bo_gem->gem_handle;
637 bo_gem->bo.bufmgr = bufmgr;
641 atomic_set(&bo_gem->refcount, 1);
642 bo_gem->validate_index = -1;
643 bo_gem->reloc_tree_fences = 0;
644 bo_gem->used_as_reloc_target = 0;
645 bo_gem->has_error = 0;
646 bo_gem->tiling_mode = I915_TILING_NONE;
647 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
648 bo_gem->reusable = 1;
650 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
652 DBG("bo_create: buf %d (%s) %ldb\n",
653 bo_gem->gem_handle, bo_gem->name, size);
658 static drm_intel_bo *
659 drm_intel_gem_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
662 unsigned int alignment)
664 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size,
665 BO_ALLOC_FOR_RENDER);
668 static drm_intel_bo *
669 drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr,
672 unsigned int alignment)
674 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, 0);
677 static drm_intel_bo *
678 drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
679 int x, int y, int cpp, uint32_t *tiling_mode,
680 unsigned long *pitch, unsigned long flags)
682 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
684 unsigned long size, stride, aligned_y = y;
687 /* If we're tiled, our allocations are in 8 or 32-row blocks,
688 * so failure to align our height means that we won't allocate
691 * If we're untiled, we still have to align to 2 rows high
692 * because the data port accesses 2x2 blocks even if the
693 * bottom row isn't to be rendered, so failure to align means
694 * we could walk off the end of the GTT and fault. This is
695 * documented on 965, and may be the case on older chipsets
696 * too so we try to be careful.
698 if (*tiling_mode == I915_TILING_NONE)
699 aligned_y = ALIGN(y, 2);
700 else if (*tiling_mode == I915_TILING_X)
701 aligned_y = ALIGN(y, 8);
702 else if (*tiling_mode == I915_TILING_Y)
703 aligned_y = ALIGN(y, 32);
706 stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, *tiling_mode);
707 size = stride * aligned_y;
708 size = drm_intel_gem_bo_tile_size(bufmgr_gem, size, tiling_mode);
710 bo = drm_intel_gem_bo_alloc_internal(bufmgr, name, size, flags);
714 ret = drm_intel_gem_bo_set_tiling(bo, tiling_mode, stride);
716 drm_intel_gem_bo_unreference(bo);
726 * Returns a drm_intel_bo wrapping the given buffer object handle.
728 * This can be used when one application needs to pass a buffer object
732 drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
736 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
737 drm_intel_bo_gem *bo_gem;
739 struct drm_gem_open open_arg;
740 struct drm_i915_gem_get_tiling get_tiling;
742 bo_gem = calloc(1, sizeof(*bo_gem));
746 memset(&open_arg, 0, sizeof(open_arg));
747 open_arg.name = handle;
749 ret = ioctl(bufmgr_gem->fd,
752 } while (ret == -1 && errno == EINTR);
754 fprintf(stderr, "Couldn't reference %s handle 0x%08x: %s\n",
755 name, handle, strerror(errno));
759 bo_gem->bo.size = open_arg.size;
760 bo_gem->bo.offset = 0;
761 bo_gem->bo.virtual = NULL;
762 bo_gem->bo.bufmgr = bufmgr;
764 atomic_set(&bo_gem->refcount, 1);
765 bo_gem->validate_index = -1;
766 bo_gem->gem_handle = open_arg.handle;
767 bo_gem->global_name = handle;
768 bo_gem->reusable = 0;
770 memset(&get_tiling, 0, sizeof(get_tiling));
771 get_tiling.handle = bo_gem->gem_handle;
772 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_GET_TILING, &get_tiling);
774 drm_intel_gem_bo_unreference(&bo_gem->bo);
777 bo_gem->tiling_mode = get_tiling.tiling_mode;
778 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
779 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
781 DBG("bo_create_from_handle: %d (%s)\n", handle, bo_gem->name);
787 drm_intel_gem_bo_free(drm_intel_bo *bo)
789 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
790 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
791 struct drm_gem_close close;
794 if (bo_gem->mem_virtual)
795 munmap(bo_gem->mem_virtual, bo_gem->bo.size);
796 if (bo_gem->gtt_virtual)
797 munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
799 /* Close this object */
800 memset(&close, 0, sizeof(close));
801 close.handle = bo_gem->gem_handle;
802 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close);
805 "DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
806 bo_gem->gem_handle, bo_gem->name, strerror(errno));
811 /** Frees all cached buffers significantly older than @time. */
813 drm_intel_gem_cleanup_bo_cache(drm_intel_bufmgr_gem *bufmgr_gem, time_t time)
817 for (i = 0; i < DRM_INTEL_GEM_BO_BUCKETS; i++) {
818 struct drm_intel_gem_bo_bucket *bucket =
819 &bufmgr_gem->cache_bucket[i];
821 while (!DRMLISTEMPTY(&bucket->head)) {
822 drm_intel_bo_gem *bo_gem;
824 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
825 bucket->head.next, head);
826 if (time - bo_gem->free_time <= 1)
829 DRMLISTDEL(&bo_gem->head);
831 drm_intel_gem_bo_free(&bo_gem->bo);
837 drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time)
839 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
840 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
841 struct drm_intel_gem_bo_bucket *bucket;
842 uint32_t tiling_mode;
845 /* Unreference all the target buffers */
846 for (i = 0; i < bo_gem->reloc_count; i++) {
847 drm_intel_gem_bo_unreference_locked_timed(bo_gem->
848 reloc_target_info[i].bo,
851 bo_gem->reloc_count = 0;
852 bo_gem->used_as_reloc_target = 0;
854 DBG("bo_unreference final: %d (%s)\n",
855 bo_gem->gem_handle, bo_gem->name);
857 /* release memory associated with this object */
858 if (bo_gem->reloc_target_info) {
859 free(bo_gem->reloc_target_info);
860 bo_gem->reloc_target_info = NULL;
862 if (bo_gem->relocs) {
863 free(bo_gem->relocs);
864 bo_gem->relocs = NULL;
867 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, bo->size);
868 /* Put the buffer into our internal cache for reuse if we can. */
869 tiling_mode = I915_TILING_NONE;
870 if (bufmgr_gem->bo_reuse && bo_gem->reusable && bucket != NULL &&
871 drm_intel_gem_bo_set_tiling(bo, &tiling_mode, 0) == 0 &&
872 drm_intel_gem_bo_madvise_internal(bufmgr_gem, bo_gem,
873 I915_MADV_DONTNEED)) {
874 bo_gem->free_time = time;
877 bo_gem->validate_index = -1;
879 DRMLISTADDTAIL(&bo_gem->head, &bucket->head);
881 drm_intel_gem_cleanup_bo_cache(bufmgr_gem, time);
883 drm_intel_gem_bo_free(bo);
887 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
890 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
892 assert(atomic_read(&bo_gem->refcount) > 0);
893 if (atomic_dec_and_test(&bo_gem->refcount))
894 drm_intel_gem_bo_unreference_final(bo, time);
897 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo)
899 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
901 assert(atomic_read(&bo_gem->refcount) > 0);
902 if (atomic_dec_and_test(&bo_gem->refcount)) {
903 drm_intel_bufmgr_gem *bufmgr_gem =
904 (drm_intel_bufmgr_gem *) bo->bufmgr;
905 struct timespec time;
907 clock_gettime(CLOCK_MONOTONIC, &time);
909 pthread_mutex_lock(&bufmgr_gem->lock);
910 drm_intel_gem_bo_unreference_final(bo, time.tv_sec);
911 pthread_mutex_unlock(&bufmgr_gem->lock);
915 static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable)
917 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
918 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
919 struct drm_i915_gem_set_domain set_domain;
922 pthread_mutex_lock(&bufmgr_gem->lock);
924 /* Allow recursive mapping. Mesa may recursively map buffers with
925 * nested display loops.
927 if (!bo_gem->mem_virtual) {
928 struct drm_i915_gem_mmap mmap_arg;
930 DBG("bo_map: %d (%s)\n", bo_gem->gem_handle, bo_gem->name);
932 memset(&mmap_arg, 0, sizeof(mmap_arg));
933 mmap_arg.handle = bo_gem->gem_handle;
935 mmap_arg.size = bo->size;
937 ret = ioctl(bufmgr_gem->fd,
938 DRM_IOCTL_I915_GEM_MMAP,
940 } while (ret == -1 && errno == EINTR);
944 "%s:%d: Error mapping buffer %d (%s): %s .\n",
945 __FILE__, __LINE__, bo_gem->gem_handle,
946 bo_gem->name, strerror(errno));
947 pthread_mutex_unlock(&bufmgr_gem->lock);
950 bo_gem->mem_virtual = (void *)(uintptr_t) mmap_arg.addr_ptr;
952 DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
953 bo_gem->mem_virtual);
954 bo->virtual = bo_gem->mem_virtual;
956 set_domain.handle = bo_gem->gem_handle;
957 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
959 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
961 set_domain.write_domain = 0;
963 ret = ioctl(bufmgr_gem->fd,
964 DRM_IOCTL_I915_GEM_SET_DOMAIN,
966 } while (ret == -1 && errno == EINTR);
969 fprintf(stderr, "%s:%d: Error setting to CPU domain %d: %s\n",
970 __FILE__, __LINE__, bo_gem->gem_handle,
972 pthread_mutex_unlock(&bufmgr_gem->lock);
976 pthread_mutex_unlock(&bufmgr_gem->lock);
981 int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
983 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
984 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
985 struct drm_i915_gem_set_domain set_domain;
988 pthread_mutex_lock(&bufmgr_gem->lock);
990 /* Get a mapping of the buffer if we haven't before. */
991 if (bo_gem->gtt_virtual == NULL) {
992 struct drm_i915_gem_mmap_gtt mmap_arg;
994 DBG("bo_map_gtt: mmap %d (%s)\n", bo_gem->gem_handle,
997 memset(&mmap_arg, 0, sizeof(mmap_arg));
998 mmap_arg.handle = bo_gem->gem_handle;
1000 /* Get the fake offset back... */
1002 ret = ioctl(bufmgr_gem->fd,
1003 DRM_IOCTL_I915_GEM_MMAP_GTT,
1005 } while (ret == -1 && errno == EINTR);
1009 "%s:%d: Error preparing buffer map %d (%s): %s .\n",
1011 bo_gem->gem_handle, bo_gem->name,
1013 pthread_mutex_unlock(&bufmgr_gem->lock);
1018 bo_gem->gtt_virtual = mmap(0, bo->size, PROT_READ | PROT_WRITE,
1019 MAP_SHARED, bufmgr_gem->fd,
1021 if (bo_gem->gtt_virtual == MAP_FAILED) {
1022 bo_gem->gtt_virtual = NULL;
1025 "%s:%d: Error mapping buffer %d (%s): %s .\n",
1027 bo_gem->gem_handle, bo_gem->name,
1029 pthread_mutex_unlock(&bufmgr_gem->lock);
1034 bo->virtual = bo_gem->gtt_virtual;
1036 DBG("bo_map_gtt: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1037 bo_gem->gtt_virtual);
1039 /* Now move it to the GTT domain so that the CPU caches are flushed */
1040 set_domain.handle = bo_gem->gem_handle;
1041 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1042 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
1044 ret = ioctl(bufmgr_gem->fd,
1045 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1047 } while (ret == -1 && errno == EINTR);
1051 fprintf(stderr, "%s:%d: Error setting domain %d: %s\n",
1052 __FILE__, __LINE__, bo_gem->gem_handle,
1056 pthread_mutex_unlock(&bufmgr_gem->lock);
1061 int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo)
1063 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1064 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1070 assert(bo_gem->gtt_virtual != NULL);
1072 pthread_mutex_lock(&bufmgr_gem->lock);
1074 pthread_mutex_unlock(&bufmgr_gem->lock);
1079 static int drm_intel_gem_bo_unmap(drm_intel_bo *bo)
1081 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1082 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1083 struct drm_i915_gem_sw_finish sw_finish;
1089 assert(bo_gem->mem_virtual != NULL);
1091 pthread_mutex_lock(&bufmgr_gem->lock);
1093 /* Cause a flush to happen if the buffer's pinned for scanout, so the
1094 * results show up in a timely manner.
1096 sw_finish.handle = bo_gem->gem_handle;
1098 ret = ioctl(bufmgr_gem->fd,
1099 DRM_IOCTL_I915_GEM_SW_FINISH,
1101 } while (ret == -1 && errno == EINTR);
1104 pthread_mutex_unlock(&bufmgr_gem->lock);
1109 drm_intel_gem_bo_subdata(drm_intel_bo *bo, unsigned long offset,
1110 unsigned long size, const void *data)
1112 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1113 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1114 struct drm_i915_gem_pwrite pwrite;
1117 memset(&pwrite, 0, sizeof(pwrite));
1118 pwrite.handle = bo_gem->gem_handle;
1119 pwrite.offset = offset;
1121 pwrite.data_ptr = (uint64_t) (uintptr_t) data;
1123 ret = ioctl(bufmgr_gem->fd,
1124 DRM_IOCTL_I915_GEM_PWRITE,
1126 } while (ret == -1 && errno == EINTR);
1129 "%s:%d: Error writing data to buffer %d: (%d %d) %s .\n",
1130 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1131 (int)size, strerror(errno));
1137 drm_intel_gem_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id)
1139 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1140 struct drm_i915_get_pipe_from_crtc_id get_pipe_from_crtc_id;
1143 get_pipe_from_crtc_id.crtc_id = crtc_id;
1144 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID,
1145 &get_pipe_from_crtc_id);
1147 /* We return -1 here to signal that we don't
1148 * know which pipe is associated with this crtc.
1149 * This lets the caller know that this information
1150 * isn't available; using the wrong pipe for
1151 * vblank waiting can cause the chipset to lock up
1156 return get_pipe_from_crtc_id.pipe;
1160 drm_intel_gem_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
1161 unsigned long size, void *data)
1163 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1164 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1165 struct drm_i915_gem_pread pread;
1168 memset(&pread, 0, sizeof(pread));
1169 pread.handle = bo_gem->gem_handle;
1170 pread.offset = offset;
1172 pread.data_ptr = (uint64_t) (uintptr_t) data;
1174 ret = ioctl(bufmgr_gem->fd,
1175 DRM_IOCTL_I915_GEM_PREAD,
1177 } while (ret == -1 && errno == EINTR);
1181 "%s:%d: Error reading data from buffer %d: (%d %d) %s .\n",
1182 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1183 (int)size, strerror(errno));
1188 /** Waits for all GPU rendering to the object to have completed. */
1190 drm_intel_gem_bo_wait_rendering(drm_intel_bo *bo)
1192 drm_intel_gem_bo_start_gtt_access(bo, 0);
1196 * Sets the object to the GTT read and possibly write domain, used by the X
1197 * 2D driver in the absence of kernel support to do drm_intel_gem_bo_map_gtt().
1199 * In combination with drm_intel_gem_bo_pin() and manual fence management, we
1200 * can do tiled pixmaps this way.
1203 drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable)
1205 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1206 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1207 struct drm_i915_gem_set_domain set_domain;
1210 set_domain.handle = bo_gem->gem_handle;
1211 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1212 set_domain.write_domain = write_enable ? I915_GEM_DOMAIN_GTT : 0;
1214 ret = ioctl(bufmgr_gem->fd,
1215 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1217 } while (ret == -1 && errno == EINTR);
1220 "%s:%d: Error setting memory domains %d (%08x %08x): %s .\n",
1221 __FILE__, __LINE__, bo_gem->gem_handle,
1222 set_domain.read_domains, set_domain.write_domain,
1228 drm_intel_bufmgr_gem_destroy(drm_intel_bufmgr *bufmgr)
1230 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1233 free(bufmgr_gem->exec2_objects);
1234 free(bufmgr_gem->exec_objects);
1235 free(bufmgr_gem->exec_bos);
1237 pthread_mutex_destroy(&bufmgr_gem->lock);
1239 /* Free any cached buffer objects we were going to reuse */
1240 for (i = 0; i < DRM_INTEL_GEM_BO_BUCKETS; i++) {
1241 struct drm_intel_gem_bo_bucket *bucket =
1242 &bufmgr_gem->cache_bucket[i];
1243 drm_intel_bo_gem *bo_gem;
1245 while (!DRMLISTEMPTY(&bucket->head)) {
1246 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1247 bucket->head.next, head);
1248 DRMLISTDEL(&bo_gem->head);
1250 drm_intel_gem_bo_free(&bo_gem->bo);
1258 * Adds the target buffer to the validation list and adds the relocation
1259 * to the reloc_buffer's relocation list.
1261 * The relocation entry at the given offset must already contain the
1262 * precomputed relocation value, because the kernel will optimize out
1263 * the relocation entry write when the buffer hasn't moved from the
1264 * last known offset in target_bo.
1267 do_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1268 drm_intel_bo *target_bo, uint32_t target_offset,
1269 uint32_t read_domains, uint32_t write_domain,
1272 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1273 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1274 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
1276 if (bo_gem->has_error)
1279 if (target_bo_gem->has_error) {
1280 bo_gem->has_error = 1;
1284 if (target_bo_gem->tiling_mode == I915_TILING_NONE)
1287 /* We never use HW fences for rendering on 965+ */
1288 if (bufmgr_gem->gen >= 4)
1291 /* Create a new relocation list if needed */
1292 if (bo_gem->relocs == NULL && drm_intel_setup_reloc_list(bo))
1295 /* Check overflow */
1296 assert(bo_gem->reloc_count < bufmgr_gem->max_relocs);
1299 assert(offset <= bo->size - 4);
1300 assert((write_domain & (write_domain - 1)) == 0);
1302 /* Make sure that we're not adding a reloc to something whose size has
1303 * already been accounted for.
1305 assert(!bo_gem->used_as_reloc_target);
1306 bo_gem->reloc_tree_size += target_bo_gem->reloc_tree_size;
1307 /* An object needing a fence is a tiled buffer, so it won't have
1308 * relocs to other buffers.
1311 target_bo_gem->reloc_tree_fences = 1;
1312 bo_gem->reloc_tree_fences += target_bo_gem->reloc_tree_fences;
1314 /* Flag the target to disallow further relocations in it. */
1315 target_bo_gem->used_as_reloc_target = 1;
1317 bo_gem->relocs[bo_gem->reloc_count].offset = offset;
1318 bo_gem->relocs[bo_gem->reloc_count].delta = target_offset;
1319 bo_gem->relocs[bo_gem->reloc_count].target_handle =
1320 target_bo_gem->gem_handle;
1321 bo_gem->relocs[bo_gem->reloc_count].read_domains = read_domains;
1322 bo_gem->relocs[bo_gem->reloc_count].write_domain = write_domain;
1323 bo_gem->relocs[bo_gem->reloc_count].presumed_offset = target_bo->offset;
1325 bo_gem->reloc_target_info[bo_gem->reloc_count].bo = target_bo;
1326 drm_intel_gem_bo_reference(target_bo);
1328 bo_gem->reloc_target_info[bo_gem->reloc_count].flags =
1329 DRM_INTEL_RELOC_FENCE;
1331 bo_gem->reloc_target_info[bo_gem->reloc_count].flags = 0;
1333 bo_gem->reloc_count++;
1339 drm_intel_gem_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1340 drm_intel_bo *target_bo, uint32_t target_offset,
1341 uint32_t read_domains, uint32_t write_domain)
1343 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1345 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1346 read_domains, write_domain,
1347 !bufmgr_gem->fenced_relocs);
1351 drm_intel_gem_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
1352 drm_intel_bo *target_bo,
1353 uint32_t target_offset,
1354 uint32_t read_domains, uint32_t write_domain)
1356 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1357 read_domains, write_domain, 1);
1361 * Walk the tree of relocations rooted at BO and accumulate the list of
1362 * validations to be performed and update the relocation buffers with
1363 * index values into the validation list.
1366 drm_intel_gem_bo_process_reloc(drm_intel_bo *bo)
1368 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1371 if (bo_gem->relocs == NULL)
1374 for (i = 0; i < bo_gem->reloc_count; i++) {
1375 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1377 /* Continue walking the tree depth-first. */
1378 drm_intel_gem_bo_process_reloc(target_bo);
1380 /* Add the target to the validate list */
1381 drm_intel_add_validate_buffer(target_bo);
1386 drm_intel_gem_bo_process_reloc2(drm_intel_bo *bo)
1388 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1391 if (bo_gem->relocs == NULL)
1394 for (i = 0; i < bo_gem->reloc_count; i++) {
1395 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1398 /* Continue walking the tree depth-first. */
1399 drm_intel_gem_bo_process_reloc2(target_bo);
1401 need_fence = (bo_gem->reloc_target_info[i].flags &
1402 DRM_INTEL_RELOC_FENCE);
1404 /* Add the target to the validate list */
1405 drm_intel_add_validate_buffer2(target_bo, need_fence);
1411 drm_intel_update_buffer_offsets(drm_intel_bufmgr_gem *bufmgr_gem)
1415 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1416 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1417 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1419 /* Update the buffer offset */
1420 if (bufmgr_gem->exec_objects[i].offset != bo->offset) {
1421 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1422 bo_gem->gem_handle, bo_gem->name, bo->offset,
1423 (unsigned long long)bufmgr_gem->exec_objects[i].
1425 bo->offset = bufmgr_gem->exec_objects[i].offset;
1431 drm_intel_update_buffer_offsets2 (drm_intel_bufmgr_gem *bufmgr_gem)
1435 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1436 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1437 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1439 /* Update the buffer offset */
1440 if (bufmgr_gem->exec2_objects[i].offset != bo->offset) {
1441 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1442 bo_gem->gem_handle, bo_gem->name, bo->offset,
1443 (unsigned long long)bufmgr_gem->exec2_objects[i].offset);
1444 bo->offset = bufmgr_gem->exec2_objects[i].offset;
1450 drm_intel_gem_bo_exec(drm_intel_bo *bo, int used,
1451 drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
1453 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1454 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1455 struct drm_i915_gem_execbuffer execbuf;
1458 if (bo_gem->has_error)
1461 pthread_mutex_lock(&bufmgr_gem->lock);
1462 /* Update indices and set up the validate list. */
1463 drm_intel_gem_bo_process_reloc(bo);
1465 /* Add the batch buffer to the validation list. There are no
1466 * relocations pointing to it.
1468 drm_intel_add_validate_buffer(bo);
1470 execbuf.buffers_ptr = (uintptr_t) bufmgr_gem->exec_objects;
1471 execbuf.buffer_count = bufmgr_gem->exec_count;
1472 execbuf.batch_start_offset = 0;
1473 execbuf.batch_len = used;
1474 execbuf.cliprects_ptr = (uintptr_t) cliprects;
1475 execbuf.num_cliprects = num_cliprects;
1480 ret = ioctl(bufmgr_gem->fd,
1481 DRM_IOCTL_I915_GEM_EXECBUFFER,
1483 } while (ret != 0 && errno == EINTR);
1487 if (errno == ENOSPC) {
1489 "Execbuffer fails to pin. "
1490 "Estimate: %u. Actual: %u. Available: %u\n",
1491 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
1494 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
1497 (unsigned int)bufmgr_gem->gtt_size);
1500 drm_intel_update_buffer_offsets(bufmgr_gem);
1502 if (bufmgr_gem->bufmgr.debug)
1503 drm_intel_gem_dump_validation_list(bufmgr_gem);
1505 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1506 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1507 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1509 /* Disconnect the buffer from the validate list */
1510 bo_gem->validate_index = -1;
1511 bufmgr_gem->exec_bos[i] = NULL;
1513 bufmgr_gem->exec_count = 0;
1514 pthread_mutex_unlock(&bufmgr_gem->lock);
1520 drm_intel_gem_bo_exec2(drm_intel_bo *bo, int used,
1521 drm_clip_rect_t *cliprects, int num_cliprects,
1524 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1525 struct drm_i915_gem_execbuffer2 execbuf;
1528 pthread_mutex_lock(&bufmgr_gem->lock);
1529 /* Update indices and set up the validate list. */
1530 drm_intel_gem_bo_process_reloc2(bo);
1532 /* Add the batch buffer to the validation list. There are no relocations
1535 drm_intel_add_validate_buffer2(bo, 0);
1537 execbuf.buffers_ptr = (uintptr_t)bufmgr_gem->exec2_objects;
1538 execbuf.buffer_count = bufmgr_gem->exec_count;
1539 execbuf.batch_start_offset = 0;
1540 execbuf.batch_len = used;
1541 execbuf.cliprects_ptr = (uintptr_t)cliprects;
1542 execbuf.num_cliprects = num_cliprects;
1550 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_EXECBUFFER2,
1552 } while (ret != 0 && errno == EAGAIN);
1554 if (ret != 0 && errno == ENOMEM) {
1556 "Execbuffer fails to pin. "
1557 "Estimate: %u. Actual: %u. Available: %u\n",
1558 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
1559 bufmgr_gem->exec_count),
1560 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
1561 bufmgr_gem->exec_count),
1562 (unsigned int) bufmgr_gem->gtt_size);
1564 drm_intel_update_buffer_offsets2(bufmgr_gem);
1566 if (bufmgr_gem->bufmgr.debug)
1567 drm_intel_gem_dump_validation_list(bufmgr_gem);
1569 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1570 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1571 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1573 /* Disconnect the buffer from the validate list */
1574 bo_gem->validate_index = -1;
1575 bufmgr_gem->exec_bos[i] = NULL;
1577 bufmgr_gem->exec_count = 0;
1578 pthread_mutex_unlock(&bufmgr_gem->lock);
1584 drm_intel_gem_bo_pin(drm_intel_bo *bo, uint32_t alignment)
1586 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1587 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1588 struct drm_i915_gem_pin pin;
1591 memset(&pin, 0, sizeof(pin));
1592 pin.handle = bo_gem->gem_handle;
1593 pin.alignment = alignment;
1596 ret = ioctl(bufmgr_gem->fd,
1597 DRM_IOCTL_I915_GEM_PIN,
1599 } while (ret == -1 && errno == EINTR);
1604 bo->offset = pin.offset;
1609 drm_intel_gem_bo_unpin(drm_intel_bo *bo)
1611 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1612 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1613 struct drm_i915_gem_unpin unpin;
1616 memset(&unpin, 0, sizeof(unpin));
1617 unpin.handle = bo_gem->gem_handle;
1619 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_UNPIN, &unpin);
1627 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1630 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1631 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1632 struct drm_i915_gem_set_tiling set_tiling;
1635 if (bo_gem->global_name == 0 && *tiling_mode == bo_gem->tiling_mode)
1638 memset(&set_tiling, 0, sizeof(set_tiling));
1639 set_tiling.handle = bo_gem->gem_handle;
1642 set_tiling.tiling_mode = *tiling_mode;
1643 set_tiling.stride = stride;
1645 ret = ioctl(bufmgr_gem->fd,
1646 DRM_IOCTL_I915_GEM_SET_TILING,
1648 } while (ret == -1 && errno == EINTR);
1649 bo_gem->tiling_mode = set_tiling.tiling_mode;
1650 bo_gem->swizzle_mode = set_tiling.swizzle_mode;
1652 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
1654 *tiling_mode = bo_gem->tiling_mode;
1655 return ret == 0 ? 0 : -errno;
1659 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1660 uint32_t * swizzle_mode)
1662 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1664 *tiling_mode = bo_gem->tiling_mode;
1665 *swizzle_mode = bo_gem->swizzle_mode;
1670 drm_intel_gem_bo_flink(drm_intel_bo *bo, uint32_t * name)
1672 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1673 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1674 struct drm_gem_flink flink;
1677 if (!bo_gem->global_name) {
1678 memset(&flink, 0, sizeof(flink));
1679 flink.handle = bo_gem->gem_handle;
1681 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_FLINK, &flink);
1684 bo_gem->global_name = flink.name;
1685 bo_gem->reusable = 0;
1688 *name = bo_gem->global_name;
1693 * Enables unlimited caching of buffer objects for reuse.
1695 * This is potentially very memory expensive, as the cache at each bucket
1696 * size is only bounded by how many buffers of that size we've managed to have
1697 * in flight at once.
1700 drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr)
1702 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1704 bufmgr_gem->bo_reuse = 1;
1708 * Enable use of fenced reloc type.
1710 * New code should enable this to avoid unnecessary fence register
1711 * allocation. If this option is not enabled, all relocs will have fence
1712 * register allocated.
1715 drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr)
1717 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
1719 if (bufmgr_gem->bufmgr.bo_exec == drm_intel_gem_bo_exec2)
1720 bufmgr_gem->fenced_relocs = 1;
1724 * Return the additional aperture space required by the tree of buffer objects
1728 drm_intel_gem_bo_get_aperture_space(drm_intel_bo *bo)
1730 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1734 if (bo == NULL || bo_gem->included_in_check_aperture)
1738 bo_gem->included_in_check_aperture = 1;
1740 for (i = 0; i < bo_gem->reloc_count; i++)
1742 drm_intel_gem_bo_get_aperture_space(bo_gem->
1743 reloc_target_info[i].bo);
1749 * Count the number of buffers in this list that need a fence reg
1751 * If the count is greater than the number of available regs, we'll have
1752 * to ask the caller to resubmit a batch with fewer tiled buffers.
1754 * This function over-counts if the same buffer is used multiple times.
1757 drm_intel_gem_total_fences(drm_intel_bo ** bo_array, int count)
1760 unsigned int total = 0;
1762 for (i = 0; i < count; i++) {
1763 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
1768 total += bo_gem->reloc_tree_fences;
1774 * Clear the flag set by drm_intel_gem_bo_get_aperture_space() so we're ready
1775 * for the next drm_intel_bufmgr_check_aperture_space() call.
1778 drm_intel_gem_bo_clear_aperture_space_flag(drm_intel_bo *bo)
1780 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1783 if (bo == NULL || !bo_gem->included_in_check_aperture)
1786 bo_gem->included_in_check_aperture = 0;
1788 for (i = 0; i < bo_gem->reloc_count; i++)
1789 drm_intel_gem_bo_clear_aperture_space_flag(bo_gem->
1790 reloc_target_info[i].bo);
1794 * Return a conservative estimate for the amount of aperture required
1795 * for a collection of buffers. This may double-count some buffers.
1798 drm_intel_gem_estimate_batch_space(drm_intel_bo **bo_array, int count)
1801 unsigned int total = 0;
1803 for (i = 0; i < count; i++) {
1804 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
1806 total += bo_gem->reloc_tree_size;
1812 * Return the amount of aperture needed for a collection of buffers.
1813 * This avoids double counting any buffers, at the cost of looking
1814 * at every buffer in the set.
1817 drm_intel_gem_compute_batch_space(drm_intel_bo **bo_array, int count)
1820 unsigned int total = 0;
1822 for (i = 0; i < count; i++) {
1823 total += drm_intel_gem_bo_get_aperture_space(bo_array[i]);
1824 /* For the first buffer object in the array, we get an
1825 * accurate count back for its reloc_tree size (since nothing
1826 * had been flagged as being counted yet). We can save that
1827 * value out as a more conservative reloc_tree_size that
1828 * avoids double-counting target buffers. Since the first
1829 * buffer happens to usually be the batch buffer in our
1830 * callers, this can pull us back from doing the tree
1831 * walk on every new batch emit.
1834 drm_intel_bo_gem *bo_gem =
1835 (drm_intel_bo_gem *) bo_array[i];
1836 bo_gem->reloc_tree_size = total;
1840 for (i = 0; i < count; i++)
1841 drm_intel_gem_bo_clear_aperture_space_flag(bo_array[i]);
1846 * Return -1 if the batchbuffer should be flushed before attempting to
1847 * emit rendering referencing the buffers pointed to by bo_array.
1849 * This is required because if we try to emit a batchbuffer with relocations
1850 * to a tree of buffers that won't simultaneously fit in the aperture,
1851 * the rendering will return an error at a point where the software is not
1852 * prepared to recover from it.
1854 * However, we also want to emit the batchbuffer significantly before we reach
1855 * the limit, as a series of batchbuffers each of which references buffers
1856 * covering almost all of the aperture means that at each emit we end up
1857 * waiting to evict a buffer from the last rendering, and we get synchronous
1858 * performance. By emitting smaller batchbuffers, we eat some CPU overhead to
1859 * get better parallelism.
1862 drm_intel_gem_check_aperture_space(drm_intel_bo **bo_array, int count)
1864 drm_intel_bufmgr_gem *bufmgr_gem =
1865 (drm_intel_bufmgr_gem *) bo_array[0]->bufmgr;
1866 unsigned int total = 0;
1867 unsigned int threshold = bufmgr_gem->gtt_size * 3 / 4;
1870 /* Check for fence reg constraints if necessary */
1871 if (bufmgr_gem->available_fences) {
1872 total_fences = drm_intel_gem_total_fences(bo_array, count);
1873 if (total_fences > bufmgr_gem->available_fences)
1877 total = drm_intel_gem_estimate_batch_space(bo_array, count);
1879 if (total > threshold)
1880 total = drm_intel_gem_compute_batch_space(bo_array, count);
1882 if (total > threshold) {
1883 DBG("check_space: overflowed available aperture, "
1885 total / 1024, (int)bufmgr_gem->gtt_size / 1024);
1888 DBG("drm_check_space: total %dkb vs bufgr %dkb\n", total / 1024,
1889 (int)bufmgr_gem->gtt_size / 1024);
1895 * Disable buffer reuse for objects which are shared with the kernel
1896 * as scanout buffers
1899 drm_intel_gem_bo_disable_reuse(drm_intel_bo *bo)
1901 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1903 bo_gem->reusable = 0;
1908 _drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
1910 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1913 for (i = 0; i < bo_gem->reloc_count; i++) {
1914 if (bo_gem->reloc_target_info[i].bo == target_bo)
1916 if (_drm_intel_gem_bo_references(bo_gem->reloc_target_info[i].bo,
1924 /** Return true if target_bo is referenced by bo's relocation tree. */
1926 drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
1928 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
1930 if (bo == NULL || target_bo == NULL)
1932 if (target_bo_gem->used_as_reloc_target)
1933 return _drm_intel_gem_bo_references(bo, target_bo);
1938 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
1939 * and manage map buffer objections.
1941 * \param fd File descriptor of the opened DRM device.
1944 drm_intel_bufmgr_gem_init(int fd, int batch_size)
1946 drm_intel_bufmgr_gem *bufmgr_gem;
1947 struct drm_i915_gem_get_aperture aperture;
1948 drm_i915_getparam_t gp;
1953 bufmgr_gem = calloc(1, sizeof(*bufmgr_gem));
1954 if (bufmgr_gem == NULL)
1957 bufmgr_gem->fd = fd;
1959 if (pthread_mutex_init(&bufmgr_gem->lock, NULL) != 0) {
1964 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
1967 bufmgr_gem->gtt_size = aperture.aper_available_size;
1969 fprintf(stderr, "DRM_IOCTL_I915_GEM_APERTURE failed: %s\n",
1971 bufmgr_gem->gtt_size = 128 * 1024 * 1024;
1972 fprintf(stderr, "Assuming %dkB available aperture size.\n"
1973 "May lead to reduced performance or incorrect "
1975 (int)bufmgr_gem->gtt_size / 1024);
1978 gp.param = I915_PARAM_CHIPSET_ID;
1979 gp.value = &bufmgr_gem->pci_device;
1980 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
1982 fprintf(stderr, "get chip id failed: %d [%d]\n", ret, errno);
1983 fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value);
1986 if (IS_GEN2(bufmgr_gem))
1987 bufmgr_gem->gen = 2;
1988 else if (IS_GEN3(bufmgr_gem))
1989 bufmgr_gem->gen = 3;
1990 else if (IS_GEN4(bufmgr_gem))
1991 bufmgr_gem->gen = 4;
1993 bufmgr_gem->gen = 6;
1995 gp.param = I915_PARAM_HAS_EXECBUF2;
1996 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2000 if (bufmgr_gem->gen < 4) {
2001 gp.param = I915_PARAM_NUM_FENCES_AVAIL;
2002 gp.value = &bufmgr_gem->available_fences;
2003 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2005 fprintf(stderr, "get fences failed: %d [%d]\n", ret,
2007 fprintf(stderr, "param: %d, val: %d\n", gp.param,
2009 bufmgr_gem->available_fences = 0;
2011 /* XXX The kernel reports the total number of fences,
2012 * including any that may be pinned.
2014 * We presume that there will be at least one pinned
2015 * fence for the scanout buffer, but there may be more
2016 * than one scanout and the user may be manually
2017 * pinning buffers. Let's move to execbuffer2 and
2018 * thereby forget the insanity of using fences...
2020 bufmgr_gem->available_fences -= 2;
2021 if (bufmgr_gem->available_fences < 0)
2022 bufmgr_gem->available_fences = 0;
2026 /* Let's go with one relocation per every 2 dwords (but round down a bit
2027 * since a power of two will mean an extra page allocation for the reloc
2030 * Every 4 was too few for the blender benchmark.
2032 bufmgr_gem->max_relocs = batch_size / sizeof(uint32_t) / 2 - 2;
2034 bufmgr_gem->bufmgr.bo_alloc = drm_intel_gem_bo_alloc;
2035 bufmgr_gem->bufmgr.bo_alloc_for_render =
2036 drm_intel_gem_bo_alloc_for_render;
2037 bufmgr_gem->bufmgr.bo_alloc_tiled = drm_intel_gem_bo_alloc_tiled;
2038 bufmgr_gem->bufmgr.bo_reference = drm_intel_gem_bo_reference;
2039 bufmgr_gem->bufmgr.bo_unreference = drm_intel_gem_bo_unreference;
2040 bufmgr_gem->bufmgr.bo_map = drm_intel_gem_bo_map;
2041 bufmgr_gem->bufmgr.bo_unmap = drm_intel_gem_bo_unmap;
2042 bufmgr_gem->bufmgr.bo_subdata = drm_intel_gem_bo_subdata;
2043 bufmgr_gem->bufmgr.bo_get_subdata = drm_intel_gem_bo_get_subdata;
2044 bufmgr_gem->bufmgr.bo_wait_rendering = drm_intel_gem_bo_wait_rendering;
2045 bufmgr_gem->bufmgr.bo_emit_reloc = drm_intel_gem_bo_emit_reloc;
2046 bufmgr_gem->bufmgr.bo_emit_reloc_fence = drm_intel_gem_bo_emit_reloc_fence;
2047 bufmgr_gem->bufmgr.bo_pin = drm_intel_gem_bo_pin;
2048 bufmgr_gem->bufmgr.bo_unpin = drm_intel_gem_bo_unpin;
2049 bufmgr_gem->bufmgr.bo_get_tiling = drm_intel_gem_bo_get_tiling;
2050 bufmgr_gem->bufmgr.bo_set_tiling = drm_intel_gem_bo_set_tiling;
2051 bufmgr_gem->bufmgr.bo_flink = drm_intel_gem_bo_flink;
2052 /* Use the new one if available */
2054 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec2;
2056 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec;
2057 bufmgr_gem->bufmgr.bo_busy = drm_intel_gem_bo_busy;
2058 bufmgr_gem->bufmgr.bo_madvise = drm_intel_gem_bo_madvise;
2059 bufmgr_gem->bufmgr.destroy = drm_intel_bufmgr_gem_destroy;
2060 bufmgr_gem->bufmgr.debug = 0;
2061 bufmgr_gem->bufmgr.check_aperture_space =
2062 drm_intel_gem_check_aperture_space;
2063 bufmgr_gem->bufmgr.bo_disable_reuse = drm_intel_gem_bo_disable_reuse;
2064 bufmgr_gem->bufmgr.get_pipe_from_crtc_id =
2065 drm_intel_gem_get_pipe_from_crtc_id;
2066 bufmgr_gem->bufmgr.bo_references = drm_intel_gem_bo_references;
2068 /* Initialize the linked lists for BO reuse cache. */
2069 for (i = 0, size = 4096; i < DRM_INTEL_GEM_BO_BUCKETS; i++, size *= 2) {
2070 DRMINITLISTHEAD(&bufmgr_gem->cache_bucket[i].head);
2071 bufmgr_gem->cache_bucket[i].size = size;
2074 return &bufmgr_gem->bufmgr;