1 /**************************************************************************
3 * Copyright © 2007 Red Hat Inc.
4 * Copyright © 2007-2012 Intel Corporation
5 * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
29 **************************************************************************/
31 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
32 * Keith Whitwell <keithw-at-tungstengraphics-dot-com>
33 * Eric Anholt <eric@anholt.net>
34 * Dave Airlie <airlied@linux.ie>
42 #include <xf86atomic.h>
50 #include <sys/ioctl.h>
52 #include <sys/types.h>
57 #define ETIME ETIMEDOUT
59 #include "libdrm_macros.h"
60 #include "libdrm_lists.h"
61 #include "intel_bufmgr.h"
62 #include "intel_bufmgr_priv.h"
63 #include "intel_chipset.h"
64 #include "intel_aub.h"
77 #define memclear(s) memset(&s, 0, sizeof(s))
79 #define DBG(...) do { \
80 if (bufmgr_gem->bufmgr.debug) \
81 fprintf(stderr, __VA_ARGS__); \
84 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
86 typedef struct _drm_intel_bo_gem drm_intel_bo_gem;
88 struct drm_intel_gem_bo_bucket {
93 typedef struct _drm_intel_bufmgr_gem {
94 drm_intel_bufmgr bufmgr;
102 pthread_mutex_t lock;
104 struct drm_i915_gem_exec_object *exec_objects;
105 struct drm_i915_gem_exec_object2 *exec2_objects;
106 drm_intel_bo **exec_bos;
110 /** Array of lists of cached gem objects of power-of-two sizes */
111 struct drm_intel_gem_bo_bucket cache_bucket[14 * 4];
115 drmMMListHead managers;
118 drmMMListHead vma_cache;
119 int vma_count, vma_open, vma_max;
122 int available_fences;
125 unsigned int has_bsd : 1;
126 unsigned int has_blt : 1;
127 unsigned int has_relaxed_fencing : 1;
128 unsigned int has_llc : 1;
129 unsigned int has_wait_timeout : 1;
130 unsigned int bo_reuse : 1;
131 unsigned int no_exec : 1;
132 unsigned int has_vebox : 1;
138 } drm_intel_bufmgr_gem;
140 #define DRM_INTEL_RELOC_FENCE (1<<0)
142 typedef struct _drm_intel_reloc_target_info {
145 } drm_intel_reloc_target;
147 struct _drm_intel_bo_gem {
155 * Kenel-assigned global name for this object
157 * List contains both flink named and prime fd'd objects
159 unsigned int global_name;
160 drmMMListHead name_list;
163 * Index of the buffer within the validation list while preparing a
164 * batchbuffer execution.
169 * Current tiling mode
171 uint32_t tiling_mode;
172 uint32_t swizzle_mode;
173 unsigned long stride;
177 /** Array passed to the DRM containing relocation information. */
178 struct drm_i915_gem_relocation_entry *relocs;
180 * Array of info structs corresponding to relocs[i].target_handle etc
182 drm_intel_reloc_target *reloc_target_info;
183 /** Number of entries in relocs */
185 /** Mapped address for the buffer, saved across map/unmap cycles */
187 /** GTT virtual address for the buffer, saved across map/unmap cycles */
190 * Virtual address of the buffer allocated by user, used for userptr
195 drmMMListHead vma_list;
201 * Boolean of whether this BO and its children have been included in
202 * the current drm_intel_bufmgr_check_aperture_space() total.
204 bool included_in_check_aperture;
207 * Boolean of whether this buffer has been used as a relocation
208 * target and had its size accounted for, and thus can't have any
209 * further relocations added to it.
211 bool used_as_reloc_target;
214 * Boolean of whether we have encountered an error whilst building the relocation tree.
219 * Boolean of whether this buffer can be re-used
224 * Boolean of whether the GPU is definitely not accessing the buffer.
226 * This is only valid when reusable, since non-reusable
227 * buffers are those that have been shared wth other
228 * processes, so we don't know their state.
233 * Boolean of whether this buffer was allocated with userptr
238 * Size in bytes of this buffer and its relocation descendents.
240 * Used to avoid costly tree walking in
241 * drm_intel_bufmgr_check_aperture in the common case.
246 * Number of potential fence registers required by this buffer and its
249 int reloc_tree_fences;
251 /** Flags that we may need to do the SW_FINSIH ioctl on unmap. */
252 bool mapped_cpu_write;
256 drm_intel_aub_annotation *aub_annotations;
257 unsigned aub_annotation_count;
261 drm_intel_gem_estimate_batch_space(drm_intel_bo ** bo_array, int count);
264 drm_intel_gem_compute_batch_space(drm_intel_bo ** bo_array, int count);
267 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
268 uint32_t * swizzle_mode);
271 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
272 uint32_t tiling_mode,
275 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
278 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo);
280 static void drm_intel_gem_bo_free(drm_intel_bo *bo);
283 drm_intel_gem_bo_tile_size(drm_intel_bufmgr_gem *bufmgr_gem, unsigned long size,
284 uint32_t *tiling_mode)
286 unsigned long min_size, max_size;
289 if (*tiling_mode == I915_TILING_NONE)
292 /* 965+ just need multiples of page size for tiling */
293 if (bufmgr_gem->gen >= 4)
294 return ROUND_UP_TO(size, 4096);
296 /* Older chips need powers of two, of at least 512k or 1M */
297 if (bufmgr_gem->gen == 3) {
298 min_size = 1024*1024;
299 max_size = 128*1024*1024;
302 max_size = 64*1024*1024;
305 if (size > max_size) {
306 *tiling_mode = I915_TILING_NONE;
310 /* Do we need to allocate every page for the fence? */
311 if (bufmgr_gem->has_relaxed_fencing)
312 return ROUND_UP_TO(size, 4096);
314 for (i = min_size; i < size; i <<= 1)
321 * Round a given pitch up to the minimum required for X tiling on a
322 * given chip. We use 512 as the minimum to allow for a later tiling
326 drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem,
327 unsigned long pitch, uint32_t *tiling_mode)
329 unsigned long tile_width;
332 /* If untiled, then just align it so that we can do rendering
333 * to it with the 3D engine.
335 if (*tiling_mode == I915_TILING_NONE)
336 return ALIGN(pitch, 64);
338 if (*tiling_mode == I915_TILING_X
339 || (IS_915(bufmgr_gem->pci_device)
340 && *tiling_mode == I915_TILING_Y))
345 /* 965 is flexible */
346 if (bufmgr_gem->gen >= 4)
347 return ROUND_UP_TO(pitch, tile_width);
349 /* The older hardware has a maximum pitch of 8192 with tiled
350 * surfaces, so fallback to untiled if it's too large.
353 *tiling_mode = I915_TILING_NONE;
354 return ALIGN(pitch, 64);
357 /* Pre-965 needs power of two tile width */
358 for (i = tile_width; i < pitch; i <<= 1)
364 static struct drm_intel_gem_bo_bucket *
365 drm_intel_gem_bo_bucket_for_size(drm_intel_bufmgr_gem *bufmgr_gem,
370 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
371 struct drm_intel_gem_bo_bucket *bucket =
372 &bufmgr_gem->cache_bucket[i];
373 if (bucket->size >= size) {
382 drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem *bufmgr_gem)
386 for (i = 0; i < bufmgr_gem->exec_count; i++) {
387 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
388 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
390 if (bo_gem->relocs == NULL) {
391 DBG("%2d: %d (%s)\n", i, bo_gem->gem_handle,
396 for (j = 0; j < bo_gem->reloc_count; j++) {
397 drm_intel_bo *target_bo = bo_gem->reloc_target_info[j].bo;
398 drm_intel_bo_gem *target_gem =
399 (drm_intel_bo_gem *) target_bo;
401 DBG("%2d: %d (%s)@0x%08llx -> "
402 "%d (%s)@0x%08lx + 0x%08x\n",
404 bo_gem->gem_handle, bo_gem->name,
405 (unsigned long long)bo_gem->relocs[j].offset,
406 target_gem->gem_handle,
409 bo_gem->relocs[j].delta);
415 drm_intel_gem_bo_reference(drm_intel_bo *bo)
417 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
419 atomic_inc(&bo_gem->refcount);
423 * Adds the given buffer to the list of buffers to be validated (moved into the
424 * appropriate memory type) with the next batch submission.
426 * If a buffer is validated multiple times in a batch submission, it ends up
427 * with the intersection of the memory type flags and the union of the
431 drm_intel_add_validate_buffer(drm_intel_bo *bo)
433 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
434 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
437 if (bo_gem->validate_index != -1)
440 /* Extend the array of validation entries as necessary. */
441 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
442 int new_size = bufmgr_gem->exec_size * 2;
447 bufmgr_gem->exec_objects =
448 realloc(bufmgr_gem->exec_objects,
449 sizeof(*bufmgr_gem->exec_objects) * new_size);
450 bufmgr_gem->exec_bos =
451 realloc(bufmgr_gem->exec_bos,
452 sizeof(*bufmgr_gem->exec_bos) * new_size);
453 bufmgr_gem->exec_size = new_size;
456 index = bufmgr_gem->exec_count;
457 bo_gem->validate_index = index;
458 /* Fill in array entry */
459 bufmgr_gem->exec_objects[index].handle = bo_gem->gem_handle;
460 bufmgr_gem->exec_objects[index].relocation_count = bo_gem->reloc_count;
461 bufmgr_gem->exec_objects[index].relocs_ptr = (uintptr_t) bo_gem->relocs;
462 bufmgr_gem->exec_objects[index].alignment = 0;
463 bufmgr_gem->exec_objects[index].offset = 0;
464 bufmgr_gem->exec_bos[index] = bo;
465 bufmgr_gem->exec_count++;
469 drm_intel_add_validate_buffer2(drm_intel_bo *bo, int need_fence)
471 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
472 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
475 if (bo_gem->validate_index != -1) {
477 bufmgr_gem->exec2_objects[bo_gem->validate_index].flags |=
478 EXEC_OBJECT_NEEDS_FENCE;
482 /* Extend the array of validation entries as necessary. */
483 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
484 int new_size = bufmgr_gem->exec_size * 2;
489 bufmgr_gem->exec2_objects =
490 realloc(bufmgr_gem->exec2_objects,
491 sizeof(*bufmgr_gem->exec2_objects) * new_size);
492 bufmgr_gem->exec_bos =
493 realloc(bufmgr_gem->exec_bos,
494 sizeof(*bufmgr_gem->exec_bos) * new_size);
495 bufmgr_gem->exec_size = new_size;
498 index = bufmgr_gem->exec_count;
499 bo_gem->validate_index = index;
500 /* Fill in array entry */
501 bufmgr_gem->exec2_objects[index].handle = bo_gem->gem_handle;
502 bufmgr_gem->exec2_objects[index].relocation_count = bo_gem->reloc_count;
503 bufmgr_gem->exec2_objects[index].relocs_ptr = (uintptr_t)bo_gem->relocs;
504 bufmgr_gem->exec2_objects[index].alignment = 0;
505 bufmgr_gem->exec2_objects[index].offset = 0;
506 bufmgr_gem->exec_bos[index] = bo;
507 bufmgr_gem->exec2_objects[index].flags = 0;
508 bufmgr_gem->exec2_objects[index].rsvd1 = 0;
509 bufmgr_gem->exec2_objects[index].rsvd2 = 0;
511 bufmgr_gem->exec2_objects[index].flags |=
512 EXEC_OBJECT_NEEDS_FENCE;
514 bufmgr_gem->exec_count++;
517 #define RELOC_BUF_SIZE(x) ((I915_RELOC_HEADER + x * I915_RELOC0_STRIDE) * \
521 drm_intel_bo_gem_set_in_aperture_size(drm_intel_bufmgr_gem *bufmgr_gem,
522 drm_intel_bo_gem *bo_gem)
526 assert(!bo_gem->used_as_reloc_target);
528 /* The older chipsets are far-less flexible in terms of tiling,
529 * and require tiled buffer to be size aligned in the aperture.
530 * This means that in the worst possible case we will need a hole
531 * twice as large as the object in order for it to fit into the
532 * aperture. Optimal packing is for wimps.
534 size = bo_gem->bo.size;
535 if (bufmgr_gem->gen < 4 && bo_gem->tiling_mode != I915_TILING_NONE) {
538 if (bufmgr_gem->has_relaxed_fencing) {
539 if (bufmgr_gem->gen == 3)
540 min_size = 1024*1024;
544 while (min_size < size)
549 /* Account for worst-case alignment. */
553 bo_gem->reloc_tree_size = size;
557 drm_intel_setup_reloc_list(drm_intel_bo *bo)
559 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
560 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
561 unsigned int max_relocs = bufmgr_gem->max_relocs;
563 if (bo->size / 4 < max_relocs)
564 max_relocs = bo->size / 4;
566 bo_gem->relocs = malloc(max_relocs *
567 sizeof(struct drm_i915_gem_relocation_entry));
568 bo_gem->reloc_target_info = malloc(max_relocs *
569 sizeof(drm_intel_reloc_target));
570 if (bo_gem->relocs == NULL || bo_gem->reloc_target_info == NULL) {
571 bo_gem->has_error = true;
573 free (bo_gem->relocs);
574 bo_gem->relocs = NULL;
576 free (bo_gem->reloc_target_info);
577 bo_gem->reloc_target_info = NULL;
586 drm_intel_gem_bo_busy(drm_intel_bo *bo)
588 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
589 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
590 struct drm_i915_gem_busy busy;
593 if (bo_gem->reusable && bo_gem->idle)
597 busy.handle = bo_gem->gem_handle;
599 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_BUSY, &busy);
601 bo_gem->idle = !busy.busy;
606 return (ret == 0 && busy.busy);
610 drm_intel_gem_bo_madvise_internal(drm_intel_bufmgr_gem *bufmgr_gem,
611 drm_intel_bo_gem *bo_gem, int state)
613 struct drm_i915_gem_madvise madv;
616 madv.handle = bo_gem->gem_handle;
619 drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MADVISE, &madv);
621 return madv.retained;
625 drm_intel_gem_bo_madvise(drm_intel_bo *bo, int madv)
627 return drm_intel_gem_bo_madvise_internal
628 ((drm_intel_bufmgr_gem *) bo->bufmgr,
629 (drm_intel_bo_gem *) bo,
633 /* drop the oldest entries that have been purged by the kernel */
635 drm_intel_gem_bo_cache_purge_bucket(drm_intel_bufmgr_gem *bufmgr_gem,
636 struct drm_intel_gem_bo_bucket *bucket)
638 while (!DRMLISTEMPTY(&bucket->head)) {
639 drm_intel_bo_gem *bo_gem;
641 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
642 bucket->head.next, head);
643 if (drm_intel_gem_bo_madvise_internal
644 (bufmgr_gem, bo_gem, I915_MADV_DONTNEED))
647 DRMLISTDEL(&bo_gem->head);
648 drm_intel_gem_bo_free(&bo_gem->bo);
652 static drm_intel_bo *
653 drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr,
657 uint32_t tiling_mode,
658 unsigned long stride)
660 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
661 drm_intel_bo_gem *bo_gem;
662 unsigned int page_size = getpagesize();
664 struct drm_intel_gem_bo_bucket *bucket;
665 bool alloc_from_cache;
666 unsigned long bo_size;
667 bool for_render = false;
669 if (flags & BO_ALLOC_FOR_RENDER)
672 /* Round the allocated size up to a power of two number of pages. */
673 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, size);
675 /* If we don't have caching at this size, don't actually round the
678 if (bucket == NULL) {
680 if (bo_size < page_size)
683 bo_size = bucket->size;
686 pthread_mutex_lock(&bufmgr_gem->lock);
687 /* Get a buffer out of the cache if available */
689 alloc_from_cache = false;
690 if (bucket != NULL && !DRMLISTEMPTY(&bucket->head)) {
692 /* Allocate new render-target BOs from the tail (MRU)
693 * of the list, as it will likely be hot in the GPU
694 * cache and in the aperture for us.
696 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
697 bucket->head.prev, head);
698 DRMLISTDEL(&bo_gem->head);
699 alloc_from_cache = true;
701 /* For non-render-target BOs (where we're probably
702 * going to map it first thing in order to fill it
703 * with data), check if the last BO in the cache is
704 * unbusy, and only reuse in that case. Otherwise,
705 * allocating a new buffer is probably faster than
706 * waiting for the GPU to finish.
708 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
709 bucket->head.next, head);
710 if (!drm_intel_gem_bo_busy(&bo_gem->bo)) {
711 alloc_from_cache = true;
712 DRMLISTDEL(&bo_gem->head);
716 if (alloc_from_cache) {
717 if (!drm_intel_gem_bo_madvise_internal
718 (bufmgr_gem, bo_gem, I915_MADV_WILLNEED)) {
719 drm_intel_gem_bo_free(&bo_gem->bo);
720 drm_intel_gem_bo_cache_purge_bucket(bufmgr_gem,
725 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
728 drm_intel_gem_bo_free(&bo_gem->bo);
733 pthread_mutex_unlock(&bufmgr_gem->lock);
735 if (!alloc_from_cache) {
736 struct drm_i915_gem_create create;
738 bo_gem = calloc(1, sizeof(*bo_gem));
742 bo_gem->bo.size = bo_size;
745 create.size = bo_size;
747 ret = drmIoctl(bufmgr_gem->fd,
748 DRM_IOCTL_I915_GEM_CREATE,
750 bo_gem->gem_handle = create.handle;
751 bo_gem->bo.handle = bo_gem->gem_handle;
756 bo_gem->bo.bufmgr = bufmgr;
758 bo_gem->tiling_mode = I915_TILING_NONE;
759 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
762 /* drm_intel_gem_bo_free calls DRMLISTDEL() for an uninitialized
763 list (vma_list), so better set the list head here */
764 DRMINITLISTHEAD(&bo_gem->name_list);
765 DRMINITLISTHEAD(&bo_gem->vma_list);
766 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
769 drm_intel_gem_bo_free(&bo_gem->bo);
775 atomic_set(&bo_gem->refcount, 1);
776 bo_gem->validate_index = -1;
777 bo_gem->reloc_tree_fences = 0;
778 bo_gem->used_as_reloc_target = false;
779 bo_gem->has_error = false;
780 bo_gem->reusable = true;
781 bo_gem->aub_annotations = NULL;
782 bo_gem->aub_annotation_count = 0;
784 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
786 DBG("bo_create: buf %d (%s) %ldb\n",
787 bo_gem->gem_handle, bo_gem->name, size);
792 static drm_intel_bo *
793 drm_intel_gem_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
796 unsigned int alignment)
798 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size,
800 I915_TILING_NONE, 0);
803 static drm_intel_bo *
804 drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr,
807 unsigned int alignment)
809 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, 0,
810 I915_TILING_NONE, 0);
813 static drm_intel_bo *
814 drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
815 int x, int y, int cpp, uint32_t *tiling_mode,
816 unsigned long *pitch, unsigned long flags)
818 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
819 unsigned long size, stride;
823 unsigned long aligned_y, height_alignment;
825 tiling = *tiling_mode;
827 /* If we're tiled, our allocations are in 8 or 32-row blocks,
828 * so failure to align our height means that we won't allocate
831 * If we're untiled, we still have to align to 2 rows high
832 * because the data port accesses 2x2 blocks even if the
833 * bottom row isn't to be rendered, so failure to align means
834 * we could walk off the end of the GTT and fault. This is
835 * documented on 965, and may be the case on older chipsets
836 * too so we try to be careful.
839 height_alignment = 2;
841 if ((bufmgr_gem->gen == 2) && tiling != I915_TILING_NONE)
842 height_alignment = 16;
843 else if (tiling == I915_TILING_X
844 || (IS_915(bufmgr_gem->pci_device)
845 && tiling == I915_TILING_Y))
846 height_alignment = 8;
847 else if (tiling == I915_TILING_Y)
848 height_alignment = 32;
849 aligned_y = ALIGN(y, height_alignment);
852 stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, tiling_mode);
853 size = stride * aligned_y;
854 size = drm_intel_gem_bo_tile_size(bufmgr_gem, size, tiling_mode);
855 } while (*tiling_mode != tiling);
858 if (tiling == I915_TILING_NONE)
861 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, flags,
865 static drm_intel_bo *
866 drm_intel_gem_bo_alloc_userptr(drm_intel_bufmgr *bufmgr,
869 uint32_t tiling_mode,
874 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
875 drm_intel_bo_gem *bo_gem;
877 struct drm_i915_gem_userptr userptr;
879 /* Tiling with userptr surfaces is not supported
880 * on all hardware so refuse it for time being.
882 if (tiling_mode != I915_TILING_NONE)
885 bo_gem = calloc(1, sizeof(*bo_gem));
889 bo_gem->bo.size = size;
892 userptr.user_ptr = (__u64)((unsigned long)addr);
893 userptr.user_size = size;
894 userptr.flags = flags;
896 ret = drmIoctl(bufmgr_gem->fd,
897 DRM_IOCTL_I915_GEM_USERPTR,
900 DBG("bo_create_userptr: "
901 "ioctl failed with user ptr %p size 0x%lx, "
902 "user flags 0x%lx\n", addr, size, flags);
907 bo_gem->gem_handle = userptr.handle;
908 bo_gem->bo.handle = bo_gem->gem_handle;
909 bo_gem->bo.bufmgr = bufmgr;
910 bo_gem->is_userptr = true;
911 bo_gem->bo.virtual = addr;
912 /* Save the address provided by user */
913 bo_gem->user_virtual = addr;
914 bo_gem->tiling_mode = I915_TILING_NONE;
915 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
918 DRMINITLISTHEAD(&bo_gem->name_list);
919 DRMINITLISTHEAD(&bo_gem->vma_list);
922 atomic_set(&bo_gem->refcount, 1);
923 bo_gem->validate_index = -1;
924 bo_gem->reloc_tree_fences = 0;
925 bo_gem->used_as_reloc_target = false;
926 bo_gem->has_error = false;
927 bo_gem->reusable = false;
929 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
931 DBG("bo_create_userptr: "
932 "ptr %p buf %d (%s) size %ldb, stride 0x%x, tile mode %d\n",
933 addr, bo_gem->gem_handle, bo_gem->name,
934 size, stride, tiling_mode);
940 has_userptr(drm_intel_bufmgr_gem *bufmgr_gem)
945 struct drm_i915_gem_userptr userptr;
946 struct drm_gem_close close_bo;
948 pgsz = sysconf(_SC_PAGESIZE);
951 ret = posix_memalign(&ptr, pgsz, pgsz);
953 DBG("Failed to get a page (%ld) for userptr detection!\n",
959 userptr.user_ptr = (__u64)(unsigned long)ptr;
960 userptr.user_size = pgsz;
963 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_USERPTR, &userptr);
965 if (errno == ENODEV && userptr.flags == 0) {
966 userptr.flags = I915_USERPTR_UNSYNCHRONIZED;
974 close_bo.handle = userptr.handle;
975 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close_bo);
978 fprintf(stderr, "Failed to release test userptr object! (%d) "
979 "i915 kernel driver may not be sane!\n", errno);
986 static drm_intel_bo *
987 check_bo_alloc_userptr(drm_intel_bufmgr *bufmgr,
990 uint32_t tiling_mode,
995 if (has_userptr((drm_intel_bufmgr_gem *)bufmgr))
996 bufmgr->bo_alloc_userptr = drm_intel_gem_bo_alloc_userptr;
998 bufmgr->bo_alloc_userptr = NULL;
1000 return drm_intel_bo_alloc_userptr(bufmgr, name, addr,
1001 tiling_mode, stride, size, flags);
1005 * Returns a drm_intel_bo wrapping the given buffer object handle.
1007 * This can be used when one application needs to pass a buffer object
1010 drm_public drm_intel_bo *
1011 drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
1013 unsigned int handle)
1015 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1016 drm_intel_bo_gem *bo_gem;
1018 struct drm_gem_open open_arg;
1019 struct drm_i915_gem_get_tiling get_tiling;
1020 drmMMListHead *list;
1022 /* At the moment most applications only have a few named bo.
1023 * For instance, in a DRI client only the render buffers passed
1024 * between X and the client are named. And since X returns the
1025 * alternating names for the front/back buffer a linear search
1026 * provides a sufficiently fast match.
1028 pthread_mutex_lock(&bufmgr_gem->lock);
1029 for (list = bufmgr_gem->named.next;
1030 list != &bufmgr_gem->named;
1031 list = list->next) {
1032 bo_gem = DRMLISTENTRY(drm_intel_bo_gem, list, name_list);
1033 if (bo_gem->global_name == handle) {
1034 drm_intel_gem_bo_reference(&bo_gem->bo);
1035 pthread_mutex_unlock(&bufmgr_gem->lock);
1041 open_arg.name = handle;
1042 ret = drmIoctl(bufmgr_gem->fd,
1046 DBG("Couldn't reference %s handle 0x%08x: %s\n",
1047 name, handle, strerror(errno));
1048 pthread_mutex_unlock(&bufmgr_gem->lock);
1051 /* Now see if someone has used a prime handle to get this
1052 * object from the kernel before by looking through the list
1053 * again for a matching gem_handle
1055 for (list = bufmgr_gem->named.next;
1056 list != &bufmgr_gem->named;
1057 list = list->next) {
1058 bo_gem = DRMLISTENTRY(drm_intel_bo_gem, list, name_list);
1059 if (bo_gem->gem_handle == open_arg.handle) {
1060 drm_intel_gem_bo_reference(&bo_gem->bo);
1061 pthread_mutex_unlock(&bufmgr_gem->lock);
1066 bo_gem = calloc(1, sizeof(*bo_gem));
1068 pthread_mutex_unlock(&bufmgr_gem->lock);
1072 bo_gem->bo.size = open_arg.size;
1073 bo_gem->bo.offset = 0;
1074 bo_gem->bo.offset64 = 0;
1075 bo_gem->bo.virtual = NULL;
1076 bo_gem->bo.bufmgr = bufmgr;
1077 bo_gem->name = name;
1078 atomic_set(&bo_gem->refcount, 1);
1079 bo_gem->validate_index = -1;
1080 bo_gem->gem_handle = open_arg.handle;
1081 bo_gem->bo.handle = open_arg.handle;
1082 bo_gem->global_name = handle;
1083 bo_gem->reusable = false;
1085 memclear(get_tiling);
1086 get_tiling.handle = bo_gem->gem_handle;
1087 ret = drmIoctl(bufmgr_gem->fd,
1088 DRM_IOCTL_I915_GEM_GET_TILING,
1091 drm_intel_gem_bo_unreference(&bo_gem->bo);
1092 pthread_mutex_unlock(&bufmgr_gem->lock);
1095 bo_gem->tiling_mode = get_tiling.tiling_mode;
1096 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
1097 /* XXX stride is unknown */
1098 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
1100 DRMINITLISTHEAD(&bo_gem->vma_list);
1101 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
1102 pthread_mutex_unlock(&bufmgr_gem->lock);
1103 DBG("bo_create_from_handle: %d (%s)\n", handle, bo_gem->name);
1109 drm_intel_gem_bo_free(drm_intel_bo *bo)
1111 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1112 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1113 struct drm_gem_close close;
1116 DRMLISTDEL(&bo_gem->vma_list);
1117 if (bo_gem->mem_virtual) {
1118 VG(VALGRIND_FREELIKE_BLOCK(bo_gem->mem_virtual, 0));
1119 drm_munmap(bo_gem->mem_virtual, bo_gem->bo.size);
1120 bufmgr_gem->vma_count--;
1122 if (bo_gem->gtt_virtual) {
1123 drm_munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
1124 bufmgr_gem->vma_count--;
1127 /* Close this object */
1129 close.handle = bo_gem->gem_handle;
1130 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close);
1132 DBG("DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
1133 bo_gem->gem_handle, bo_gem->name, strerror(errno));
1135 free(bo_gem->aub_annotations);
1140 drm_intel_gem_bo_mark_mmaps_incoherent(drm_intel_bo *bo)
1143 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1145 if (bo_gem->mem_virtual)
1146 VALGRIND_MAKE_MEM_NOACCESS(bo_gem->mem_virtual, bo->size);
1148 if (bo_gem->gtt_virtual)
1149 VALGRIND_MAKE_MEM_NOACCESS(bo_gem->gtt_virtual, bo->size);
1153 /** Frees all cached buffers significantly older than @time. */
1155 drm_intel_gem_cleanup_bo_cache(drm_intel_bufmgr_gem *bufmgr_gem, time_t time)
1159 if (bufmgr_gem->time == time)
1162 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
1163 struct drm_intel_gem_bo_bucket *bucket =
1164 &bufmgr_gem->cache_bucket[i];
1166 while (!DRMLISTEMPTY(&bucket->head)) {
1167 drm_intel_bo_gem *bo_gem;
1169 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1170 bucket->head.next, head);
1171 if (time - bo_gem->free_time <= 1)
1174 DRMLISTDEL(&bo_gem->head);
1176 drm_intel_gem_bo_free(&bo_gem->bo);
1180 bufmgr_gem->time = time;
1183 static void drm_intel_gem_bo_purge_vma_cache(drm_intel_bufmgr_gem *bufmgr_gem)
1187 DBG("%s: cached=%d, open=%d, limit=%d\n", __FUNCTION__,
1188 bufmgr_gem->vma_count, bufmgr_gem->vma_open, bufmgr_gem->vma_max);
1190 if (bufmgr_gem->vma_max < 0)
1193 /* We may need to evict a few entries in order to create new mmaps */
1194 limit = bufmgr_gem->vma_max - 2*bufmgr_gem->vma_open;
1198 while (bufmgr_gem->vma_count > limit) {
1199 drm_intel_bo_gem *bo_gem;
1201 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1202 bufmgr_gem->vma_cache.next,
1204 assert(bo_gem->map_count == 0);
1205 DRMLISTDELINIT(&bo_gem->vma_list);
1207 if (bo_gem->mem_virtual) {
1208 drm_munmap(bo_gem->mem_virtual, bo_gem->bo.size);
1209 bo_gem->mem_virtual = NULL;
1210 bufmgr_gem->vma_count--;
1212 if (bo_gem->gtt_virtual) {
1213 drm_munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
1214 bo_gem->gtt_virtual = NULL;
1215 bufmgr_gem->vma_count--;
1220 static void drm_intel_gem_bo_close_vma(drm_intel_bufmgr_gem *bufmgr_gem,
1221 drm_intel_bo_gem *bo_gem)
1223 bufmgr_gem->vma_open--;
1224 DRMLISTADDTAIL(&bo_gem->vma_list, &bufmgr_gem->vma_cache);
1225 if (bo_gem->mem_virtual)
1226 bufmgr_gem->vma_count++;
1227 if (bo_gem->gtt_virtual)
1228 bufmgr_gem->vma_count++;
1229 drm_intel_gem_bo_purge_vma_cache(bufmgr_gem);
1232 static void drm_intel_gem_bo_open_vma(drm_intel_bufmgr_gem *bufmgr_gem,
1233 drm_intel_bo_gem *bo_gem)
1235 bufmgr_gem->vma_open++;
1236 DRMLISTDEL(&bo_gem->vma_list);
1237 if (bo_gem->mem_virtual)
1238 bufmgr_gem->vma_count--;
1239 if (bo_gem->gtt_virtual)
1240 bufmgr_gem->vma_count--;
1241 drm_intel_gem_bo_purge_vma_cache(bufmgr_gem);
1245 drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time)
1247 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1248 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1249 struct drm_intel_gem_bo_bucket *bucket;
1252 /* Unreference all the target buffers */
1253 for (i = 0; i < bo_gem->reloc_count; i++) {
1254 if (bo_gem->reloc_target_info[i].bo != bo) {
1255 drm_intel_gem_bo_unreference_locked_timed(bo_gem->
1256 reloc_target_info[i].bo,
1260 bo_gem->reloc_count = 0;
1261 bo_gem->used_as_reloc_target = false;
1263 DBG("bo_unreference final: %d (%s)\n",
1264 bo_gem->gem_handle, bo_gem->name);
1266 /* release memory associated with this object */
1267 if (bo_gem->reloc_target_info) {
1268 free(bo_gem->reloc_target_info);
1269 bo_gem->reloc_target_info = NULL;
1271 if (bo_gem->relocs) {
1272 free(bo_gem->relocs);
1273 bo_gem->relocs = NULL;
1276 /* Clear any left-over mappings */
1277 if (bo_gem->map_count) {
1278 DBG("bo freed with non-zero map-count %d\n", bo_gem->map_count);
1279 bo_gem->map_count = 0;
1280 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1281 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1284 DRMLISTDEL(&bo_gem->name_list);
1286 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, bo->size);
1287 /* Put the buffer into our internal cache for reuse if we can. */
1288 if (bufmgr_gem->bo_reuse && bo_gem->reusable && bucket != NULL &&
1289 drm_intel_gem_bo_madvise_internal(bufmgr_gem, bo_gem,
1290 I915_MADV_DONTNEED)) {
1291 bo_gem->free_time = time;
1293 bo_gem->name = NULL;
1294 bo_gem->validate_index = -1;
1296 DRMLISTADDTAIL(&bo_gem->head, &bucket->head);
1298 drm_intel_gem_bo_free(bo);
1302 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
1305 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1307 assert(atomic_read(&bo_gem->refcount) > 0);
1308 if (atomic_dec_and_test(&bo_gem->refcount))
1309 drm_intel_gem_bo_unreference_final(bo, time);
1312 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo)
1314 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1316 assert(atomic_read(&bo_gem->refcount) > 0);
1318 if (atomic_add_unless(&bo_gem->refcount, -1, 1)) {
1319 drm_intel_bufmgr_gem *bufmgr_gem =
1320 (drm_intel_bufmgr_gem *) bo->bufmgr;
1321 struct timespec time;
1323 clock_gettime(CLOCK_MONOTONIC, &time);
1325 pthread_mutex_lock(&bufmgr_gem->lock);
1327 if (atomic_dec_and_test(&bo_gem->refcount)) {
1328 drm_intel_gem_bo_unreference_final(bo, time.tv_sec);
1329 drm_intel_gem_cleanup_bo_cache(bufmgr_gem, time.tv_sec);
1332 pthread_mutex_unlock(&bufmgr_gem->lock);
1336 static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable)
1338 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1339 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1340 struct drm_i915_gem_set_domain set_domain;
1343 if (bo_gem->is_userptr) {
1344 /* Return the same user ptr */
1345 bo->virtual = bo_gem->user_virtual;
1349 pthread_mutex_lock(&bufmgr_gem->lock);
1351 if (bo_gem->map_count++ == 0)
1352 drm_intel_gem_bo_open_vma(bufmgr_gem, bo_gem);
1354 if (!bo_gem->mem_virtual) {
1355 struct drm_i915_gem_mmap mmap_arg;
1357 DBG("bo_map: %d (%s), map_count=%d\n",
1358 bo_gem->gem_handle, bo_gem->name, bo_gem->map_count);
1361 mmap_arg.handle = bo_gem->gem_handle;
1362 mmap_arg.size = bo->size;
1363 ret = drmIoctl(bufmgr_gem->fd,
1364 DRM_IOCTL_I915_GEM_MMAP,
1368 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1369 __FILE__, __LINE__, bo_gem->gem_handle,
1370 bo_gem->name, strerror(errno));
1371 if (--bo_gem->map_count == 0)
1372 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1373 pthread_mutex_unlock(&bufmgr_gem->lock);
1376 VG(VALGRIND_MALLOCLIKE_BLOCK(mmap_arg.addr_ptr, mmap_arg.size, 0, 1));
1377 bo_gem->mem_virtual = (void *)(uintptr_t) mmap_arg.addr_ptr;
1379 DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1380 bo_gem->mem_virtual);
1381 bo->virtual = bo_gem->mem_virtual;
1383 memclear(set_domain);
1384 set_domain.handle = bo_gem->gem_handle;
1385 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
1387 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
1389 set_domain.write_domain = 0;
1390 ret = drmIoctl(bufmgr_gem->fd,
1391 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1394 DBG("%s:%d: Error setting to CPU domain %d: %s\n",
1395 __FILE__, __LINE__, bo_gem->gem_handle,
1400 bo_gem->mapped_cpu_write = true;
1402 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1403 VG(VALGRIND_MAKE_MEM_DEFINED(bo_gem->mem_virtual, bo->size));
1404 pthread_mutex_unlock(&bufmgr_gem->lock);
1410 map_gtt(drm_intel_bo *bo)
1412 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1413 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1416 if (bo_gem->is_userptr)
1419 if (bo_gem->map_count++ == 0)
1420 drm_intel_gem_bo_open_vma(bufmgr_gem, bo_gem);
1422 /* Get a mapping of the buffer if we haven't before. */
1423 if (bo_gem->gtt_virtual == NULL) {
1424 struct drm_i915_gem_mmap_gtt mmap_arg;
1426 DBG("bo_map_gtt: mmap %d (%s), map_count=%d\n",
1427 bo_gem->gem_handle, bo_gem->name, bo_gem->map_count);
1430 mmap_arg.handle = bo_gem->gem_handle;
1432 /* Get the fake offset back... */
1433 ret = drmIoctl(bufmgr_gem->fd,
1434 DRM_IOCTL_I915_GEM_MMAP_GTT,
1438 DBG("%s:%d: Error preparing buffer map %d (%s): %s .\n",
1440 bo_gem->gem_handle, bo_gem->name,
1442 if (--bo_gem->map_count == 0)
1443 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1448 bo_gem->gtt_virtual = drm_mmap(0, bo->size, PROT_READ | PROT_WRITE,
1449 MAP_SHARED, bufmgr_gem->fd,
1451 if (bo_gem->gtt_virtual == MAP_FAILED) {
1452 bo_gem->gtt_virtual = NULL;
1454 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1456 bo_gem->gem_handle, bo_gem->name,
1458 if (--bo_gem->map_count == 0)
1459 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1464 bo->virtual = bo_gem->gtt_virtual;
1466 DBG("bo_map_gtt: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1467 bo_gem->gtt_virtual);
1473 drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
1475 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1476 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1477 struct drm_i915_gem_set_domain set_domain;
1480 pthread_mutex_lock(&bufmgr_gem->lock);
1484 pthread_mutex_unlock(&bufmgr_gem->lock);
1488 /* Now move it to the GTT domain so that the GPU and CPU
1489 * caches are flushed and the GPU isn't actively using the
1492 * The pagefault handler does this domain change for us when
1493 * it has unbound the BO from the GTT, but it's up to us to
1494 * tell it when we're about to use things if we had done
1495 * rendering and it still happens to be bound to the GTT.
1497 memclear(set_domain);
1498 set_domain.handle = bo_gem->gem_handle;
1499 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1500 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
1501 ret = drmIoctl(bufmgr_gem->fd,
1502 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1505 DBG("%s:%d: Error setting domain %d: %s\n",
1506 __FILE__, __LINE__, bo_gem->gem_handle,
1510 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1511 VG(VALGRIND_MAKE_MEM_DEFINED(bo_gem->gtt_virtual, bo->size));
1512 pthread_mutex_unlock(&bufmgr_gem->lock);
1518 * Performs a mapping of the buffer object like the normal GTT
1519 * mapping, but avoids waiting for the GPU to be done reading from or
1520 * rendering to the buffer.
1522 * This is used in the implementation of GL_ARB_map_buffer_range: The
1523 * user asks to create a buffer, then does a mapping, fills some
1524 * space, runs a drawing command, then asks to map it again without
1525 * synchronizing because it guarantees that it won't write over the
1526 * data that the GPU is busy using (or, more specifically, that if it
1527 * does write over the data, it acknowledges that rendering is
1532 drm_intel_gem_bo_map_unsynchronized(drm_intel_bo *bo)
1534 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1535 #ifdef HAVE_VALGRIND
1536 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1540 /* If the CPU cache isn't coherent with the GTT, then use a
1541 * regular synchronized mapping. The problem is that we don't
1542 * track where the buffer was last used on the CPU side in
1543 * terms of drm_intel_bo_map vs drm_intel_gem_bo_map_gtt, so
1544 * we would potentially corrupt the buffer even when the user
1545 * does reasonable things.
1547 if (!bufmgr_gem->has_llc)
1548 return drm_intel_gem_bo_map_gtt(bo);
1550 pthread_mutex_lock(&bufmgr_gem->lock);
1554 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1555 VG(VALGRIND_MAKE_MEM_DEFINED(bo_gem->gtt_virtual, bo->size));
1558 pthread_mutex_unlock(&bufmgr_gem->lock);
1563 static int drm_intel_gem_bo_unmap(drm_intel_bo *bo)
1565 drm_intel_bufmgr_gem *bufmgr_gem;
1566 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1572 if (bo_gem->is_userptr)
1575 bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1577 pthread_mutex_lock(&bufmgr_gem->lock);
1579 if (bo_gem->map_count <= 0) {
1580 DBG("attempted to unmap an unmapped bo\n");
1581 pthread_mutex_unlock(&bufmgr_gem->lock);
1582 /* Preserve the old behaviour of just treating this as a
1583 * no-op rather than reporting the error.
1588 if (bo_gem->mapped_cpu_write) {
1589 struct drm_i915_gem_sw_finish sw_finish;
1591 /* Cause a flush to happen if the buffer's pinned for
1592 * scanout, so the results show up in a timely manner.
1593 * Unlike GTT set domains, this only does work if the
1594 * buffer should be scanout-related.
1596 memclear(sw_finish);
1597 sw_finish.handle = bo_gem->gem_handle;
1598 ret = drmIoctl(bufmgr_gem->fd,
1599 DRM_IOCTL_I915_GEM_SW_FINISH,
1601 ret = ret == -1 ? -errno : 0;
1603 bo_gem->mapped_cpu_write = false;
1606 /* We need to unmap after every innovation as we cannot track
1607 * an open vma for every bo as that will exhaasut the system
1608 * limits and cause later failures.
1610 if (--bo_gem->map_count == 0) {
1611 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1612 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1615 pthread_mutex_unlock(&bufmgr_gem->lock);
1621 drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo)
1623 return drm_intel_gem_bo_unmap(bo);
1627 drm_intel_gem_bo_subdata(drm_intel_bo *bo, unsigned long offset,
1628 unsigned long size, const void *data)
1630 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1631 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1632 struct drm_i915_gem_pwrite pwrite;
1635 if (bo_gem->is_userptr)
1639 pwrite.handle = bo_gem->gem_handle;
1640 pwrite.offset = offset;
1642 pwrite.data_ptr = (uint64_t) (uintptr_t) data;
1643 ret = drmIoctl(bufmgr_gem->fd,
1644 DRM_IOCTL_I915_GEM_PWRITE,
1648 DBG("%s:%d: Error writing data to buffer %d: (%d %d) %s .\n",
1649 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1650 (int)size, strerror(errno));
1657 drm_intel_gem_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id)
1659 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1660 struct drm_i915_get_pipe_from_crtc_id get_pipe_from_crtc_id;
1663 memclear(get_pipe_from_crtc_id);
1664 get_pipe_from_crtc_id.crtc_id = crtc_id;
1665 ret = drmIoctl(bufmgr_gem->fd,
1666 DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID,
1667 &get_pipe_from_crtc_id);
1669 /* We return -1 here to signal that we don't
1670 * know which pipe is associated with this crtc.
1671 * This lets the caller know that this information
1672 * isn't available; using the wrong pipe for
1673 * vblank waiting can cause the chipset to lock up
1678 return get_pipe_from_crtc_id.pipe;
1682 drm_intel_gem_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
1683 unsigned long size, void *data)
1685 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1686 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1687 struct drm_i915_gem_pread pread;
1690 if (bo_gem->is_userptr)
1694 pread.handle = bo_gem->gem_handle;
1695 pread.offset = offset;
1697 pread.data_ptr = (uint64_t) (uintptr_t) data;
1698 ret = drmIoctl(bufmgr_gem->fd,
1699 DRM_IOCTL_I915_GEM_PREAD,
1703 DBG("%s:%d: Error reading data from buffer %d: (%d %d) %s .\n",
1704 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1705 (int)size, strerror(errno));
1711 /** Waits for all GPU rendering with the object to have completed. */
1713 drm_intel_gem_bo_wait_rendering(drm_intel_bo *bo)
1715 drm_intel_gem_bo_start_gtt_access(bo, 1);
1719 * Waits on a BO for the given amount of time.
1721 * @bo: buffer object to wait for
1722 * @timeout_ns: amount of time to wait in nanoseconds.
1723 * If value is less than 0, an infinite wait will occur.
1725 * Returns 0 if the wait was successful ie. the last batch referencing the
1726 * object has completed within the allotted time. Otherwise some negative return
1727 * value describes the error. Of particular interest is -ETIME when the wait has
1728 * failed to yield the desired result.
1730 * Similar to drm_intel_gem_bo_wait_rendering except a timeout parameter allows
1731 * the operation to give up after a certain amount of time. Another subtle
1732 * difference is the internal locking semantics are different (this variant does
1733 * not hold the lock for the duration of the wait). This makes the wait subject
1734 * to a larger userspace race window.
1736 * The implementation shall wait until the object is no longer actively
1737 * referenced within a batch buffer at the time of the call. The wait will
1738 * not guarantee that the buffer is re-issued via another thread, or an flinked
1739 * handle. Userspace must make sure this race does not occur if such precision
1742 * Note that some kernels have broken the inifite wait for negative values
1743 * promise, upgrade to latest stable kernels if this is the case.
1746 drm_intel_gem_bo_wait(drm_intel_bo *bo, int64_t timeout_ns)
1748 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1749 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1750 struct drm_i915_gem_wait wait;
1753 if (!bufmgr_gem->has_wait_timeout) {
1754 DBG("%s:%d: Timed wait is not supported. Falling back to "
1755 "infinite wait\n", __FILE__, __LINE__);
1757 drm_intel_gem_bo_wait_rendering(bo);
1760 return drm_intel_gem_bo_busy(bo) ? -ETIME : 0;
1765 wait.bo_handle = bo_gem->gem_handle;
1766 wait.timeout_ns = timeout_ns;
1767 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_WAIT, &wait);
1775 * Sets the object to the GTT read and possibly write domain, used by the X
1776 * 2D driver in the absence of kernel support to do drm_intel_gem_bo_map_gtt().
1778 * In combination with drm_intel_gem_bo_pin() and manual fence management, we
1779 * can do tiled pixmaps this way.
1782 drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable)
1784 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1785 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1786 struct drm_i915_gem_set_domain set_domain;
1789 memclear(set_domain);
1790 set_domain.handle = bo_gem->gem_handle;
1791 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1792 set_domain.write_domain = write_enable ? I915_GEM_DOMAIN_GTT : 0;
1793 ret = drmIoctl(bufmgr_gem->fd,
1794 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1797 DBG("%s:%d: Error setting memory domains %d (%08x %08x): %s .\n",
1798 __FILE__, __LINE__, bo_gem->gem_handle,
1799 set_domain.read_domains, set_domain.write_domain,
1805 drm_intel_bufmgr_gem_destroy(drm_intel_bufmgr *bufmgr)
1807 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1810 free(bufmgr_gem->exec2_objects);
1811 free(bufmgr_gem->exec_objects);
1812 free(bufmgr_gem->exec_bos);
1813 free(bufmgr_gem->aub_filename);
1815 pthread_mutex_destroy(&bufmgr_gem->lock);
1817 /* Free any cached buffer objects we were going to reuse */
1818 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
1819 struct drm_intel_gem_bo_bucket *bucket =
1820 &bufmgr_gem->cache_bucket[i];
1821 drm_intel_bo_gem *bo_gem;
1823 while (!DRMLISTEMPTY(&bucket->head)) {
1824 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1825 bucket->head.next, head);
1826 DRMLISTDEL(&bo_gem->head);
1828 drm_intel_gem_bo_free(&bo_gem->bo);
1836 * Adds the target buffer to the validation list and adds the relocation
1837 * to the reloc_buffer's relocation list.
1839 * The relocation entry at the given offset must already contain the
1840 * precomputed relocation value, because the kernel will optimize out
1841 * the relocation entry write when the buffer hasn't moved from the
1842 * last known offset in target_bo.
1845 do_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1846 drm_intel_bo *target_bo, uint32_t target_offset,
1847 uint32_t read_domains, uint32_t write_domain,
1850 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1851 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1852 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
1853 bool fenced_command;
1855 if (bo_gem->has_error)
1858 if (target_bo_gem->has_error) {
1859 bo_gem->has_error = true;
1863 /* We never use HW fences for rendering on 965+ */
1864 if (bufmgr_gem->gen >= 4)
1867 fenced_command = need_fence;
1868 if (target_bo_gem->tiling_mode == I915_TILING_NONE)
1871 /* Create a new relocation list if needed */
1872 if (bo_gem->relocs == NULL && drm_intel_setup_reloc_list(bo))
1875 /* Check overflow */
1876 assert(bo_gem->reloc_count < bufmgr_gem->max_relocs);
1879 assert(offset <= bo->size - 4);
1880 assert((write_domain & (write_domain - 1)) == 0);
1882 /* An object needing a fence is a tiled buffer, so it won't have
1883 * relocs to other buffers.
1886 assert(target_bo_gem->reloc_count == 0);
1887 target_bo_gem->reloc_tree_fences = 1;
1890 /* Make sure that we're not adding a reloc to something whose size has
1891 * already been accounted for.
1893 assert(!bo_gem->used_as_reloc_target);
1894 if (target_bo_gem != bo_gem) {
1895 target_bo_gem->used_as_reloc_target = true;
1896 bo_gem->reloc_tree_size += target_bo_gem->reloc_tree_size;
1897 bo_gem->reloc_tree_fences += target_bo_gem->reloc_tree_fences;
1900 bo_gem->relocs[bo_gem->reloc_count].offset = offset;
1901 bo_gem->relocs[bo_gem->reloc_count].delta = target_offset;
1902 bo_gem->relocs[bo_gem->reloc_count].target_handle =
1903 target_bo_gem->gem_handle;
1904 bo_gem->relocs[bo_gem->reloc_count].read_domains = read_domains;
1905 bo_gem->relocs[bo_gem->reloc_count].write_domain = write_domain;
1906 bo_gem->relocs[bo_gem->reloc_count].presumed_offset = target_bo->offset64;
1908 bo_gem->reloc_target_info[bo_gem->reloc_count].bo = target_bo;
1909 if (target_bo != bo)
1910 drm_intel_gem_bo_reference(target_bo);
1912 bo_gem->reloc_target_info[bo_gem->reloc_count].flags =
1913 DRM_INTEL_RELOC_FENCE;
1915 bo_gem->reloc_target_info[bo_gem->reloc_count].flags = 0;
1917 bo_gem->reloc_count++;
1923 drm_intel_gem_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1924 drm_intel_bo *target_bo, uint32_t target_offset,
1925 uint32_t read_domains, uint32_t write_domain)
1927 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1929 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1930 read_domains, write_domain,
1931 !bufmgr_gem->fenced_relocs);
1935 drm_intel_gem_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
1936 drm_intel_bo *target_bo,
1937 uint32_t target_offset,
1938 uint32_t read_domains, uint32_t write_domain)
1940 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1941 read_domains, write_domain, true);
1945 drm_intel_gem_bo_get_reloc_count(drm_intel_bo *bo)
1947 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1949 return bo_gem->reloc_count;
1953 * Removes existing relocation entries in the BO after "start".
1955 * This allows a user to avoid a two-step process for state setup with
1956 * counting up all the buffer objects and doing a
1957 * drm_intel_bufmgr_check_aperture_space() before emitting any of the
1958 * relocations for the state setup. Instead, save the state of the
1959 * batchbuffer including drm_intel_gem_get_reloc_count(), emit all the
1960 * state, and then check if it still fits in the aperture.
1962 * Any further drm_intel_bufmgr_check_aperture_space() queries
1963 * involving this buffer in the tree are undefined after this call.
1966 drm_intel_gem_bo_clear_relocs(drm_intel_bo *bo, int start)
1968 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1969 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1971 struct timespec time;
1973 clock_gettime(CLOCK_MONOTONIC, &time);
1975 assert(bo_gem->reloc_count >= start);
1977 /* Unreference the cleared target buffers */
1978 pthread_mutex_lock(&bufmgr_gem->lock);
1980 for (i = start; i < bo_gem->reloc_count; i++) {
1981 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) bo_gem->reloc_target_info[i].bo;
1982 if (&target_bo_gem->bo != bo) {
1983 bo_gem->reloc_tree_fences -= target_bo_gem->reloc_tree_fences;
1984 drm_intel_gem_bo_unreference_locked_timed(&target_bo_gem->bo,
1988 bo_gem->reloc_count = start;
1990 pthread_mutex_unlock(&bufmgr_gem->lock);
1995 * Walk the tree of relocations rooted at BO and accumulate the list of
1996 * validations to be performed and update the relocation buffers with
1997 * index values into the validation list.
2000 drm_intel_gem_bo_process_reloc(drm_intel_bo *bo)
2002 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2005 if (bo_gem->relocs == NULL)
2008 for (i = 0; i < bo_gem->reloc_count; i++) {
2009 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
2011 if (target_bo == bo)
2014 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
2016 /* Continue walking the tree depth-first. */
2017 drm_intel_gem_bo_process_reloc(target_bo);
2019 /* Add the target to the validate list */
2020 drm_intel_add_validate_buffer(target_bo);
2025 drm_intel_gem_bo_process_reloc2(drm_intel_bo *bo)
2027 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
2030 if (bo_gem->relocs == NULL)
2033 for (i = 0; i < bo_gem->reloc_count; i++) {
2034 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
2037 if (target_bo == bo)
2040 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
2042 /* Continue walking the tree depth-first. */
2043 drm_intel_gem_bo_process_reloc2(target_bo);
2045 need_fence = (bo_gem->reloc_target_info[i].flags &
2046 DRM_INTEL_RELOC_FENCE);
2048 /* Add the target to the validate list */
2049 drm_intel_add_validate_buffer2(target_bo, need_fence);
2055 drm_intel_update_buffer_offsets(drm_intel_bufmgr_gem *bufmgr_gem)
2059 for (i = 0; i < bufmgr_gem->exec_count; i++) {
2060 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
2061 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2063 /* Update the buffer offset */
2064 if (bufmgr_gem->exec_objects[i].offset != bo->offset64) {
2065 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
2066 bo_gem->gem_handle, bo_gem->name, bo->offset64,
2067 (unsigned long long)bufmgr_gem->exec_objects[i].
2069 bo->offset64 = bufmgr_gem->exec_objects[i].offset;
2070 bo->offset = bufmgr_gem->exec_objects[i].offset;
2076 drm_intel_update_buffer_offsets2 (drm_intel_bufmgr_gem *bufmgr_gem)
2080 for (i = 0; i < bufmgr_gem->exec_count; i++) {
2081 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
2082 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
2084 /* Update the buffer offset */
2085 if (bufmgr_gem->exec2_objects[i].offset != bo->offset64) {
2086 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
2087 bo_gem->gem_handle, bo_gem->name, bo->offset64,
2088 (unsigned long long)bufmgr_gem->exec2_objects[i].offset);
2089 bo->offset64 = bufmgr_gem->exec2_objects[i].offset;
2090 bo->offset = bufmgr_gem->exec2_objects[i].offset;
2096 aub_out(drm_intel_bufmgr_gem *bufmgr_gem, uint32_t data)
2098 fwrite(&data, 1, 4, bufmgr_gem->aub_file);
2102 aub_out_data(drm_intel_bufmgr_gem *bufmgr_gem, void *data, size_t size)
2104 fwrite(data, 1, size, bufmgr_gem->aub_file);
2108 aub_write_bo_data(drm_intel_bo *bo, uint32_t offset, uint32_t size)
2110 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2111 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2115 data = malloc(bo->size);
2116 drm_intel_bo_get_subdata(bo, offset, size, data);
2118 /* Easy mode: write out bo with no relocations */
2119 if (!bo_gem->reloc_count) {
2120 aub_out_data(bufmgr_gem, data, size);
2125 /* Otherwise, handle the relocations while writing. */
2126 for (i = 0; i < size / 4; i++) {
2128 for (r = 0; r < bo_gem->reloc_count; r++) {
2129 struct drm_i915_gem_relocation_entry *reloc;
2130 drm_intel_reloc_target *info;
2132 reloc = &bo_gem->relocs[r];
2133 info = &bo_gem->reloc_target_info[r];
2135 if (reloc->offset == offset + i * 4) {
2136 drm_intel_bo_gem *target_gem;
2139 target_gem = (drm_intel_bo_gem *)info->bo;
2142 val += target_gem->aub_offset;
2144 aub_out(bufmgr_gem, val);
2149 if (r == bo_gem->reloc_count) {
2150 /* no relocation, just the data */
2151 aub_out(bufmgr_gem, data[i]);
2159 aub_bo_get_address(drm_intel_bo *bo)
2161 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2162 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2164 /* Give the object a graphics address in the AUB file. We
2165 * don't just use the GEM object address because we do AUB
2166 * dumping before execution -- we want to successfully log
2167 * when the hardware might hang, and we might even want to aub
2168 * capture for a driver trying to execute on a different
2169 * generation of hardware by disabling the actual kernel exec
2172 bo_gem->aub_offset = bufmgr_gem->aub_offset;
2173 bufmgr_gem->aub_offset += bo->size;
2174 /* XXX: Handle aperture overflow. */
2175 assert(bufmgr_gem->aub_offset < 256 * 1024 * 1024);
2179 aub_write_trace_block(drm_intel_bo *bo, uint32_t type, uint32_t subtype,
2180 uint32_t offset, uint32_t size)
2182 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2183 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2186 CMD_AUB_TRACE_HEADER_BLOCK |
2187 ((bufmgr_gem->gen >= 8 ? 6 : 5) - 2));
2189 AUB_TRACE_MEMTYPE_GTT | type | AUB_TRACE_OP_DATA_WRITE);
2190 aub_out(bufmgr_gem, subtype);
2191 aub_out(bufmgr_gem, bo_gem->aub_offset + offset);
2192 aub_out(bufmgr_gem, size);
2193 if (bufmgr_gem->gen >= 8)
2194 aub_out(bufmgr_gem, 0);
2195 aub_write_bo_data(bo, offset, size);
2199 * Break up large objects into multiple writes. Otherwise a 128kb VBO
2200 * would overflow the 16 bits of size field in the packet header and
2201 * everything goes badly after that.
2204 aub_write_large_trace_block(drm_intel_bo *bo, uint32_t type, uint32_t subtype,
2205 uint32_t offset, uint32_t size)
2207 uint32_t block_size;
2208 uint32_t sub_offset;
2210 for (sub_offset = 0; sub_offset < size; sub_offset += block_size) {
2211 block_size = size - sub_offset;
2213 if (block_size > 8 * 4096)
2214 block_size = 8 * 4096;
2216 aub_write_trace_block(bo, type, subtype, offset + sub_offset,
2222 aub_write_bo(drm_intel_bo *bo)
2224 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2225 uint32_t offset = 0;
2228 aub_bo_get_address(bo);
2230 /* Write out each annotated section separately. */
2231 for (i = 0; i < bo_gem->aub_annotation_count; ++i) {
2232 drm_intel_aub_annotation *annotation =
2233 &bo_gem->aub_annotations[i];
2234 uint32_t ending_offset = annotation->ending_offset;
2235 if (ending_offset > bo->size)
2236 ending_offset = bo->size;
2237 if (ending_offset > offset) {
2238 aub_write_large_trace_block(bo, annotation->type,
2239 annotation->subtype,
2241 ending_offset - offset);
2242 offset = ending_offset;
2246 /* Write out any remaining unannotated data */
2247 if (offset < bo->size) {
2248 aub_write_large_trace_block(bo, AUB_TRACE_TYPE_NOTYPE, 0,
2249 offset, bo->size - offset);
2254 * Make a ringbuffer on fly and dump it
2257 aub_build_dump_ringbuffer(drm_intel_bufmgr_gem *bufmgr_gem,
2258 uint32_t batch_buffer, int ring_flag)
2260 uint32_t ringbuffer[4096];
2261 int ring = AUB_TRACE_TYPE_RING_PRB0; /* The default ring */
2264 if (ring_flag == I915_EXEC_BSD)
2265 ring = AUB_TRACE_TYPE_RING_PRB1;
2266 else if (ring_flag == I915_EXEC_BLT)
2267 ring = AUB_TRACE_TYPE_RING_PRB2;
2269 /* Make a ring buffer to execute our batchbuffer. */
2270 memset(ringbuffer, 0, sizeof(ringbuffer));
2271 if (bufmgr_gem->gen >= 8) {
2272 ringbuffer[ring_count++] = AUB_MI_BATCH_BUFFER_START | (3 - 2);
2273 ringbuffer[ring_count++] = batch_buffer;
2274 ringbuffer[ring_count++] = 0;
2276 ringbuffer[ring_count++] = AUB_MI_BATCH_BUFFER_START;
2277 ringbuffer[ring_count++] = batch_buffer;
2280 /* Write out the ring. This appears to trigger execution of
2281 * the ring in the simulator.
2284 CMD_AUB_TRACE_HEADER_BLOCK |
2285 ((bufmgr_gem->gen >= 8 ? 6 : 5) - 2));
2287 AUB_TRACE_MEMTYPE_GTT | ring | AUB_TRACE_OP_COMMAND_WRITE);
2288 aub_out(bufmgr_gem, 0); /* general/surface subtype */
2289 aub_out(bufmgr_gem, bufmgr_gem->aub_offset);
2290 aub_out(bufmgr_gem, ring_count * 4);
2291 if (bufmgr_gem->gen >= 8)
2292 aub_out(bufmgr_gem, 0);
2294 /* FIXME: Need some flush operations here? */
2295 aub_out_data(bufmgr_gem, ringbuffer, ring_count * 4);
2297 /* Update offset pointer */
2298 bufmgr_gem->aub_offset += 4096;
2302 drm_intel_gem_bo_aub_dump_bmp(drm_intel_bo *bo,
2303 int x1, int y1, int width, int height,
2304 enum aub_dump_bmp_format format,
2305 int pitch, int offset)
2307 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2308 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
2312 case AUB_DUMP_BMP_FORMAT_8BIT:
2315 case AUB_DUMP_BMP_FORMAT_ARGB_4444:
2318 case AUB_DUMP_BMP_FORMAT_ARGB_0888:
2319 case AUB_DUMP_BMP_FORMAT_ARGB_8888:
2323 printf("Unknown AUB dump format %d\n", format);
2327 if (!bufmgr_gem->aub_file)
2330 aub_out(bufmgr_gem, CMD_AUB_DUMP_BMP | 4);
2331 aub_out(bufmgr_gem, (y1 << 16) | x1);
2336 aub_out(bufmgr_gem, (height << 16) | width);
2337 aub_out(bufmgr_gem, bo_gem->aub_offset + offset);
2339 ((bo_gem->tiling_mode != I915_TILING_NONE) ? (1 << 2) : 0) |
2340 ((bo_gem->tiling_mode == I915_TILING_Y) ? (1 << 3) : 0));
2344 aub_exec(drm_intel_bo *bo, int ring_flag, int used)
2346 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2347 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2349 bool batch_buffer_needs_annotations;
2351 if (!bufmgr_gem->aub_file)
2354 /* If batch buffer is not annotated, annotate it the best we
2357 batch_buffer_needs_annotations = bo_gem->aub_annotation_count == 0;
2358 if (batch_buffer_needs_annotations) {
2359 drm_intel_aub_annotation annotations[2] = {
2360 { AUB_TRACE_TYPE_BATCH, 0, used },
2361 { AUB_TRACE_TYPE_NOTYPE, 0, bo->size }
2363 drm_intel_bufmgr_gem_set_aub_annotations(bo, annotations, 2);
2366 /* Write out all buffers to AUB memory */
2367 for (i = 0; i < bufmgr_gem->exec_count; i++) {
2368 aub_write_bo(bufmgr_gem->exec_bos[i]);
2371 /* Remove any annotations we added */
2372 if (batch_buffer_needs_annotations)
2373 drm_intel_bufmgr_gem_set_aub_annotations(bo, NULL, 0);
2375 /* Dump ring buffer */
2376 aub_build_dump_ringbuffer(bufmgr_gem, bo_gem->aub_offset, ring_flag);
2378 fflush(bufmgr_gem->aub_file);
2381 * One frame has been dumped. So reset the aub_offset for the next frame.
2383 * FIXME: Can we do this?
2385 bufmgr_gem->aub_offset = 0x10000;
2389 drm_intel_gem_bo_exec(drm_intel_bo *bo, int used,
2390 drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
2392 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2393 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2394 struct drm_i915_gem_execbuffer execbuf;
2397 if (bo_gem->has_error)
2400 pthread_mutex_lock(&bufmgr_gem->lock);
2401 /* Update indices and set up the validate list. */
2402 drm_intel_gem_bo_process_reloc(bo);
2404 /* Add the batch buffer to the validation list. There are no
2405 * relocations pointing to it.
2407 drm_intel_add_validate_buffer(bo);
2410 execbuf.buffers_ptr = (uintptr_t) bufmgr_gem->exec_objects;
2411 execbuf.buffer_count = bufmgr_gem->exec_count;
2412 execbuf.batch_start_offset = 0;
2413 execbuf.batch_len = used;
2414 execbuf.cliprects_ptr = (uintptr_t) cliprects;
2415 execbuf.num_cliprects = num_cliprects;
2419 ret = drmIoctl(bufmgr_gem->fd,
2420 DRM_IOCTL_I915_GEM_EXECBUFFER,
2424 if (errno == ENOSPC) {
2425 DBG("Execbuffer fails to pin. "
2426 "Estimate: %u. Actual: %u. Available: %u\n",
2427 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
2430 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
2433 (unsigned int)bufmgr_gem->gtt_size);
2436 drm_intel_update_buffer_offsets(bufmgr_gem);
2438 if (bufmgr_gem->bufmgr.debug)
2439 drm_intel_gem_dump_validation_list(bufmgr_gem);
2441 for (i = 0; i < bufmgr_gem->exec_count; i++) {
2442 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
2443 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2445 bo_gem->idle = false;
2447 /* Disconnect the buffer from the validate list */
2448 bo_gem->validate_index = -1;
2449 bufmgr_gem->exec_bos[i] = NULL;
2451 bufmgr_gem->exec_count = 0;
2452 pthread_mutex_unlock(&bufmgr_gem->lock);
2458 do_exec2(drm_intel_bo *bo, int used, drm_intel_context *ctx,
2459 drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
2462 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
2463 struct drm_i915_gem_execbuffer2 execbuf;
2467 switch (flags & 0x7) {
2471 if (!bufmgr_gem->has_blt)
2475 if (!bufmgr_gem->has_bsd)
2478 case I915_EXEC_VEBOX:
2479 if (!bufmgr_gem->has_vebox)
2482 case I915_EXEC_RENDER:
2483 case I915_EXEC_DEFAULT:
2487 pthread_mutex_lock(&bufmgr_gem->lock);
2488 /* Update indices and set up the validate list. */
2489 drm_intel_gem_bo_process_reloc2(bo);
2491 /* Add the batch buffer to the validation list. There are no relocations
2494 drm_intel_add_validate_buffer2(bo, 0);
2497 execbuf.buffers_ptr = (uintptr_t)bufmgr_gem->exec2_objects;
2498 execbuf.buffer_count = bufmgr_gem->exec_count;
2499 execbuf.batch_start_offset = 0;
2500 execbuf.batch_len = used;
2501 execbuf.cliprects_ptr = (uintptr_t)cliprects;
2502 execbuf.num_cliprects = num_cliprects;
2505 execbuf.flags = flags;
2507 i915_execbuffer2_set_context_id(execbuf, 0);
2509 i915_execbuffer2_set_context_id(execbuf, ctx->ctx_id);
2512 aub_exec(bo, flags, used);
2514 if (bufmgr_gem->no_exec)
2515 goto skip_execution;
2517 ret = drmIoctl(bufmgr_gem->fd,
2518 DRM_IOCTL_I915_GEM_EXECBUFFER2,
2522 if (ret == -ENOSPC) {
2523 DBG("Execbuffer fails to pin. "
2524 "Estimate: %u. Actual: %u. Available: %u\n",
2525 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
2526 bufmgr_gem->exec_count),
2527 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
2528 bufmgr_gem->exec_count),
2529 (unsigned int) bufmgr_gem->gtt_size);
2532 drm_intel_update_buffer_offsets2(bufmgr_gem);
2535 if (bufmgr_gem->bufmgr.debug)
2536 drm_intel_gem_dump_validation_list(bufmgr_gem);
2538 for (i = 0; i < bufmgr_gem->exec_count; i++) {
2539 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
2540 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
2542 bo_gem->idle = false;
2544 /* Disconnect the buffer from the validate list */
2545 bo_gem->validate_index = -1;
2546 bufmgr_gem->exec_bos[i] = NULL;
2548 bufmgr_gem->exec_count = 0;
2549 pthread_mutex_unlock(&bufmgr_gem->lock);
2555 drm_intel_gem_bo_exec2(drm_intel_bo *bo, int used,
2556 drm_clip_rect_t *cliprects, int num_cliprects,
2559 return do_exec2(bo, used, NULL, cliprects, num_cliprects, DR4,
2564 drm_intel_gem_bo_mrb_exec2(drm_intel_bo *bo, int used,
2565 drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
2568 return do_exec2(bo, used, NULL, cliprects, num_cliprects, DR4,
2573 drm_intel_gem_bo_context_exec(drm_intel_bo *bo, drm_intel_context *ctx,
2574 int used, unsigned int flags)
2576 return do_exec2(bo, used, ctx, NULL, 0, 0, flags);
2580 drm_intel_gem_bo_pin(drm_intel_bo *bo, uint32_t alignment)
2582 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2583 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2584 struct drm_i915_gem_pin pin;
2588 pin.handle = bo_gem->gem_handle;
2589 pin.alignment = alignment;
2591 ret = drmIoctl(bufmgr_gem->fd,
2592 DRM_IOCTL_I915_GEM_PIN,
2597 bo->offset64 = pin.offset;
2598 bo->offset = pin.offset;
2603 drm_intel_gem_bo_unpin(drm_intel_bo *bo)
2605 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2606 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2607 struct drm_i915_gem_unpin unpin;
2611 unpin.handle = bo_gem->gem_handle;
2613 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_UNPIN, &unpin);
2621 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
2622 uint32_t tiling_mode,
2625 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2626 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2627 struct drm_i915_gem_set_tiling set_tiling;
2630 if (bo_gem->global_name == 0 &&
2631 tiling_mode == bo_gem->tiling_mode &&
2632 stride == bo_gem->stride)
2635 memset(&set_tiling, 0, sizeof(set_tiling));
2637 /* set_tiling is slightly broken and overwrites the
2638 * input on the error path, so we have to open code
2641 set_tiling.handle = bo_gem->gem_handle;
2642 set_tiling.tiling_mode = tiling_mode;
2643 set_tiling.stride = stride;
2645 ret = ioctl(bufmgr_gem->fd,
2646 DRM_IOCTL_I915_GEM_SET_TILING,
2648 } while (ret == -1 && (errno == EINTR || errno == EAGAIN));
2652 bo_gem->tiling_mode = set_tiling.tiling_mode;
2653 bo_gem->swizzle_mode = set_tiling.swizzle_mode;
2654 bo_gem->stride = set_tiling.stride;
2659 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
2662 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2663 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2666 /* Tiling with userptr surfaces is not supported
2667 * on all hardware so refuse it for time being.
2669 if (bo_gem->is_userptr)
2672 /* Linear buffers have no stride. By ensuring that we only ever use
2673 * stride 0 with linear buffers, we simplify our code.
2675 if (*tiling_mode == I915_TILING_NONE)
2678 ret = drm_intel_gem_bo_set_tiling_internal(bo, *tiling_mode, stride);
2680 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
2682 *tiling_mode = bo_gem->tiling_mode;
2687 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
2688 uint32_t * swizzle_mode)
2690 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2692 *tiling_mode = bo_gem->tiling_mode;
2693 *swizzle_mode = bo_gem->swizzle_mode;
2697 drm_public drm_intel_bo *
2698 drm_intel_bo_gem_create_from_prime(drm_intel_bufmgr *bufmgr, int prime_fd, int size)
2700 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
2703 drm_intel_bo_gem *bo_gem;
2704 struct drm_i915_gem_get_tiling get_tiling;
2705 drmMMListHead *list;
2707 ret = drmPrimeFDToHandle(bufmgr_gem->fd, prime_fd, &handle);
2710 * See if the kernel has already returned this buffer to us. Just as
2711 * for named buffers, we must not create two bo's pointing at the same
2714 pthread_mutex_lock(&bufmgr_gem->lock);
2715 for (list = bufmgr_gem->named.next;
2716 list != &bufmgr_gem->named;
2717 list = list->next) {
2718 bo_gem = DRMLISTENTRY(drm_intel_bo_gem, list, name_list);
2719 if (bo_gem->gem_handle == handle) {
2720 drm_intel_gem_bo_reference(&bo_gem->bo);
2721 pthread_mutex_unlock(&bufmgr_gem->lock);
2727 fprintf(stderr,"ret is %d %d\n", ret, errno);
2728 pthread_mutex_unlock(&bufmgr_gem->lock);
2732 bo_gem = calloc(1, sizeof(*bo_gem));
2734 pthread_mutex_unlock(&bufmgr_gem->lock);
2737 /* Determine size of bo. The fd-to-handle ioctl really should
2738 * return the size, but it doesn't. If we have kernel 3.12 or
2739 * later, we can lseek on the prime fd to get the size. Older
2740 * kernels will just fail, in which case we fall back to the
2741 * provided (estimated or guess size). */
2742 ret = lseek(prime_fd, 0, SEEK_END);
2744 bo_gem->bo.size = ret;
2746 bo_gem->bo.size = size;
2748 bo_gem->bo.handle = handle;
2749 bo_gem->bo.bufmgr = bufmgr;
2751 bo_gem->gem_handle = handle;
2753 atomic_set(&bo_gem->refcount, 1);
2755 bo_gem->name = "prime";
2756 bo_gem->validate_index = -1;
2757 bo_gem->reloc_tree_fences = 0;
2758 bo_gem->used_as_reloc_target = false;
2759 bo_gem->has_error = false;
2760 bo_gem->reusable = false;
2762 DRMINITLISTHEAD(&bo_gem->vma_list);
2763 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
2764 pthread_mutex_unlock(&bufmgr_gem->lock);
2766 memclear(get_tiling);
2767 get_tiling.handle = bo_gem->gem_handle;
2768 ret = drmIoctl(bufmgr_gem->fd,
2769 DRM_IOCTL_I915_GEM_GET_TILING,
2772 drm_intel_gem_bo_unreference(&bo_gem->bo);
2775 bo_gem->tiling_mode = get_tiling.tiling_mode;
2776 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
2777 /* XXX stride is unknown */
2778 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
2784 drm_intel_bo_gem_export_to_prime(drm_intel_bo *bo, int *prime_fd)
2786 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2787 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2789 pthread_mutex_lock(&bufmgr_gem->lock);
2790 if (DRMLISTEMPTY(&bo_gem->name_list))
2791 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
2792 pthread_mutex_unlock(&bufmgr_gem->lock);
2794 if (drmPrimeHandleToFD(bufmgr_gem->fd, bo_gem->gem_handle,
2795 DRM_CLOEXEC, prime_fd) != 0)
2798 bo_gem->reusable = false;
2804 drm_intel_gem_bo_flink(drm_intel_bo *bo, uint32_t * name)
2806 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2807 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2810 if (!bo_gem->global_name) {
2811 struct drm_gem_flink flink;
2814 flink.handle = bo_gem->gem_handle;
2816 pthread_mutex_lock(&bufmgr_gem->lock);
2818 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_FLINK, &flink);
2820 pthread_mutex_unlock(&bufmgr_gem->lock);
2824 bo_gem->global_name = flink.name;
2825 bo_gem->reusable = false;
2827 if (DRMLISTEMPTY(&bo_gem->name_list))
2828 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
2829 pthread_mutex_unlock(&bufmgr_gem->lock);
2832 *name = bo_gem->global_name;
2837 * Enables unlimited caching of buffer objects for reuse.
2839 * This is potentially very memory expensive, as the cache at each bucket
2840 * size is only bounded by how many buffers of that size we've managed to have
2841 * in flight at once.
2844 drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr)
2846 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
2848 bufmgr_gem->bo_reuse = true;
2852 * Enable use of fenced reloc type.
2854 * New code should enable this to avoid unnecessary fence register
2855 * allocation. If this option is not enabled, all relocs will have fence
2856 * register allocated.
2859 drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr)
2861 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
2863 if (bufmgr_gem->bufmgr.bo_exec == drm_intel_gem_bo_exec2)
2864 bufmgr_gem->fenced_relocs = true;
2868 * Return the additional aperture space required by the tree of buffer objects
2872 drm_intel_gem_bo_get_aperture_space(drm_intel_bo *bo)
2874 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2878 if (bo == NULL || bo_gem->included_in_check_aperture)
2882 bo_gem->included_in_check_aperture = true;
2884 for (i = 0; i < bo_gem->reloc_count; i++)
2886 drm_intel_gem_bo_get_aperture_space(bo_gem->
2887 reloc_target_info[i].bo);
2893 * Count the number of buffers in this list that need a fence reg
2895 * If the count is greater than the number of available regs, we'll have
2896 * to ask the caller to resubmit a batch with fewer tiled buffers.
2898 * This function over-counts if the same buffer is used multiple times.
2901 drm_intel_gem_total_fences(drm_intel_bo ** bo_array, int count)
2904 unsigned int total = 0;
2906 for (i = 0; i < count; i++) {
2907 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
2912 total += bo_gem->reloc_tree_fences;
2918 * Clear the flag set by drm_intel_gem_bo_get_aperture_space() so we're ready
2919 * for the next drm_intel_bufmgr_check_aperture_space() call.
2922 drm_intel_gem_bo_clear_aperture_space_flag(drm_intel_bo *bo)
2924 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2927 if (bo == NULL || !bo_gem->included_in_check_aperture)
2930 bo_gem->included_in_check_aperture = false;
2932 for (i = 0; i < bo_gem->reloc_count; i++)
2933 drm_intel_gem_bo_clear_aperture_space_flag(bo_gem->
2934 reloc_target_info[i].bo);
2938 * Return a conservative estimate for the amount of aperture required
2939 * for a collection of buffers. This may double-count some buffers.
2942 drm_intel_gem_estimate_batch_space(drm_intel_bo **bo_array, int count)
2945 unsigned int total = 0;
2947 for (i = 0; i < count; i++) {
2948 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
2950 total += bo_gem->reloc_tree_size;
2956 * Return the amount of aperture needed for a collection of buffers.
2957 * This avoids double counting any buffers, at the cost of looking
2958 * at every buffer in the set.
2961 drm_intel_gem_compute_batch_space(drm_intel_bo **bo_array, int count)
2964 unsigned int total = 0;
2966 for (i = 0; i < count; i++) {
2967 total += drm_intel_gem_bo_get_aperture_space(bo_array[i]);
2968 /* For the first buffer object in the array, we get an
2969 * accurate count back for its reloc_tree size (since nothing
2970 * had been flagged as being counted yet). We can save that
2971 * value out as a more conservative reloc_tree_size that
2972 * avoids double-counting target buffers. Since the first
2973 * buffer happens to usually be the batch buffer in our
2974 * callers, this can pull us back from doing the tree
2975 * walk on every new batch emit.
2978 drm_intel_bo_gem *bo_gem =
2979 (drm_intel_bo_gem *) bo_array[i];
2980 bo_gem->reloc_tree_size = total;
2984 for (i = 0; i < count; i++)
2985 drm_intel_gem_bo_clear_aperture_space_flag(bo_array[i]);
2990 * Return -1 if the batchbuffer should be flushed before attempting to
2991 * emit rendering referencing the buffers pointed to by bo_array.
2993 * This is required because if we try to emit a batchbuffer with relocations
2994 * to a tree of buffers that won't simultaneously fit in the aperture,
2995 * the rendering will return an error at a point where the software is not
2996 * prepared to recover from it.
2998 * However, we also want to emit the batchbuffer significantly before we reach
2999 * the limit, as a series of batchbuffers each of which references buffers
3000 * covering almost all of the aperture means that at each emit we end up
3001 * waiting to evict a buffer from the last rendering, and we get synchronous
3002 * performance. By emitting smaller batchbuffers, we eat some CPU overhead to
3003 * get better parallelism.
3006 drm_intel_gem_check_aperture_space(drm_intel_bo **bo_array, int count)
3008 drm_intel_bufmgr_gem *bufmgr_gem =
3009 (drm_intel_bufmgr_gem *) bo_array[0]->bufmgr;
3010 unsigned int total = 0;
3011 unsigned int threshold = bufmgr_gem->gtt_size * 3 / 4;
3014 /* Check for fence reg constraints if necessary */
3015 if (bufmgr_gem->available_fences) {
3016 total_fences = drm_intel_gem_total_fences(bo_array, count);
3017 if (total_fences > bufmgr_gem->available_fences)
3021 total = drm_intel_gem_estimate_batch_space(bo_array, count);
3023 if (total > threshold)
3024 total = drm_intel_gem_compute_batch_space(bo_array, count);
3026 if (total > threshold) {
3027 DBG("check_space: overflowed available aperture, "
3029 total / 1024, (int)bufmgr_gem->gtt_size / 1024);
3032 DBG("drm_check_space: total %dkb vs bufgr %dkb\n", total / 1024,
3033 (int)bufmgr_gem->gtt_size / 1024);
3039 * Disable buffer reuse for objects which are shared with the kernel
3040 * as scanout buffers
3043 drm_intel_gem_bo_disable_reuse(drm_intel_bo *bo)
3045 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
3047 bo_gem->reusable = false;
3052 drm_intel_gem_bo_is_reusable(drm_intel_bo *bo)
3054 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
3056 return bo_gem->reusable;
3060 _drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
3062 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
3065 for (i = 0; i < bo_gem->reloc_count; i++) {
3066 if (bo_gem->reloc_target_info[i].bo == target_bo)
3068 if (bo == bo_gem->reloc_target_info[i].bo)
3070 if (_drm_intel_gem_bo_references(bo_gem->reloc_target_info[i].bo,
3078 /** Return true if target_bo is referenced by bo's relocation tree. */
3080 drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
3082 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
3084 if (bo == NULL || target_bo == NULL)
3086 if (target_bo_gem->used_as_reloc_target)
3087 return _drm_intel_gem_bo_references(bo, target_bo);
3092 add_bucket(drm_intel_bufmgr_gem *bufmgr_gem, int size)
3094 unsigned int i = bufmgr_gem->num_buckets;
3096 assert(i < ARRAY_SIZE(bufmgr_gem->cache_bucket));
3098 DRMINITLISTHEAD(&bufmgr_gem->cache_bucket[i].head);
3099 bufmgr_gem->cache_bucket[i].size = size;
3100 bufmgr_gem->num_buckets++;
3104 init_cache_buckets(drm_intel_bufmgr_gem *bufmgr_gem)
3106 unsigned long size, cache_max_size = 64 * 1024 * 1024;
3108 /* OK, so power of two buckets was too wasteful of memory.
3109 * Give 3 other sizes between each power of two, to hopefully
3110 * cover things accurately enough. (The alternative is
3111 * probably to just go for exact matching of sizes, and assume
3112 * that for things like composited window resize the tiled
3113 * width/height alignment and rounding of sizes to pages will
3114 * get us useful cache hit rates anyway)
3116 add_bucket(bufmgr_gem, 4096);
3117 add_bucket(bufmgr_gem, 4096 * 2);
3118 add_bucket(bufmgr_gem, 4096 * 3);
3120 /* Initialize the linked lists for BO reuse cache. */
3121 for (size = 4 * 4096; size <= cache_max_size; size *= 2) {
3122 add_bucket(bufmgr_gem, size);
3124 add_bucket(bufmgr_gem, size + size * 1 / 4);
3125 add_bucket(bufmgr_gem, size + size * 2 / 4);
3126 add_bucket(bufmgr_gem, size + size * 3 / 4);
3131 drm_intel_bufmgr_gem_set_vma_cache_size(drm_intel_bufmgr *bufmgr, int limit)
3133 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
3135 bufmgr_gem->vma_max = limit;
3137 drm_intel_gem_bo_purge_vma_cache(bufmgr_gem);
3141 * Get the PCI ID for the device. This can be overridden by setting the
3142 * INTEL_DEVID_OVERRIDE environment variable to the desired ID.
3145 get_pci_device_id(drm_intel_bufmgr_gem *bufmgr_gem)
3147 char *devid_override;
3150 drm_i915_getparam_t gp;
3152 if (geteuid() == getuid()) {
3153 devid_override = getenv("INTEL_DEVID_OVERRIDE");
3154 if (devid_override) {
3155 bufmgr_gem->no_exec = true;
3156 return strtod(devid_override, NULL);
3161 gp.param = I915_PARAM_CHIPSET_ID;
3163 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3165 fprintf(stderr, "get chip id failed: %d [%d]\n", ret, errno);
3166 fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value);
3172 drm_intel_bufmgr_gem_get_devid(drm_intel_bufmgr *bufmgr)
3174 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
3176 return bufmgr_gem->pci_device;
3180 * Sets the AUB filename.
3182 * This function has to be called before drm_intel_bufmgr_gem_set_aub_dump()
3183 * for it to have any effect.
3186 drm_intel_bufmgr_gem_set_aub_filename(drm_intel_bufmgr *bufmgr,
3187 const char *filename)
3189 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
3191 free(bufmgr_gem->aub_filename);
3193 bufmgr_gem->aub_filename = strdup(filename);
3197 * Sets up AUB dumping.
3199 * This is a trace file format that can be used with the simulator.
3200 * Packets are emitted in a format somewhat like GPU command packets.
3201 * You can set up a GTT and upload your objects into the referenced
3202 * space, then send off batchbuffers and get BMPs out the other end.
3205 drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable)
3207 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
3208 int entry = 0x200003;
3210 int gtt_size = 0x10000;
3211 const char *filename;
3214 if (bufmgr_gem->aub_file) {
3215 fclose(bufmgr_gem->aub_file);
3216 bufmgr_gem->aub_file = NULL;
3221 if (geteuid() != getuid())
3224 if (bufmgr_gem->aub_filename)
3225 filename = bufmgr_gem->aub_filename;
3227 filename = "intel.aub";
3228 bufmgr_gem->aub_file = fopen(filename, "w+");
3229 if (!bufmgr_gem->aub_file)
3232 /* Start allocating objects from just after the GTT. */
3233 bufmgr_gem->aub_offset = gtt_size;
3235 /* Start with a (required) version packet. */
3236 aub_out(bufmgr_gem, CMD_AUB_HEADER | (13 - 2));
3238 (4 << AUB_HEADER_MAJOR_SHIFT) |
3239 (0 << AUB_HEADER_MINOR_SHIFT));
3240 for (i = 0; i < 8; i++) {
3241 aub_out(bufmgr_gem, 0); /* app name */
3243 aub_out(bufmgr_gem, 0); /* timestamp */
3244 aub_out(bufmgr_gem, 0); /* timestamp */
3245 aub_out(bufmgr_gem, 0); /* comment len */
3247 /* Set up the GTT. The max we can handle is 256M */
3248 aub_out(bufmgr_gem, CMD_AUB_TRACE_HEADER_BLOCK | ((bufmgr_gem->gen >= 8 ? 6 : 5) - 2));
3249 /* Need to use GTT_ENTRY type for recent emulator */
3250 aub_out(bufmgr_gem, AUB_TRACE_MEMTYPE_GTT_ENTRY | 0 | AUB_TRACE_OP_DATA_WRITE);
3251 aub_out(bufmgr_gem, 0); /* subtype */
3252 aub_out(bufmgr_gem, 0); /* offset */
3253 aub_out(bufmgr_gem, gtt_size); /* size */
3254 if (bufmgr_gem->gen >= 8)
3255 aub_out(bufmgr_gem, 0);
3256 for (i = 0x000; i < gtt_size; i += 4, entry += 0x1000) {
3257 aub_out(bufmgr_gem, entry);
3261 drm_public drm_intel_context *
3262 drm_intel_gem_context_create(drm_intel_bufmgr *bufmgr)
3264 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
3265 struct drm_i915_gem_context_create create;
3266 drm_intel_context *context = NULL;
3269 context = calloc(1, sizeof(*context));
3274 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_CONTEXT_CREATE, &create);
3276 DBG("DRM_IOCTL_I915_GEM_CONTEXT_CREATE failed: %s\n",
3282 context->ctx_id = create.ctx_id;
3283 context->bufmgr = bufmgr;
3289 drm_intel_gem_context_destroy(drm_intel_context *ctx)
3291 drm_intel_bufmgr_gem *bufmgr_gem;
3292 struct drm_i915_gem_context_destroy destroy;
3300 bufmgr_gem = (drm_intel_bufmgr_gem *)ctx->bufmgr;
3301 destroy.ctx_id = ctx->ctx_id;
3302 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_CONTEXT_DESTROY,
3305 fprintf(stderr, "DRM_IOCTL_I915_GEM_CONTEXT_DESTROY failed: %s\n",
3312 drm_intel_get_reset_stats(drm_intel_context *ctx,
3313 uint32_t *reset_count,
3317 drm_intel_bufmgr_gem *bufmgr_gem;
3318 struct drm_i915_reset_stats stats;
3326 bufmgr_gem = (drm_intel_bufmgr_gem *)ctx->bufmgr;
3327 stats.ctx_id = ctx->ctx_id;
3328 ret = drmIoctl(bufmgr_gem->fd,
3329 DRM_IOCTL_I915_GET_RESET_STATS,
3332 if (reset_count != NULL)
3333 *reset_count = stats.reset_count;
3336 *active = stats.batch_active;
3338 if (pending != NULL)
3339 *pending = stats.batch_pending;
3346 drm_intel_reg_read(drm_intel_bufmgr *bufmgr,
3350 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
3351 struct drm_i915_reg_read reg_read;
3355 reg_read.offset = offset;
3357 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_REG_READ, ®_read);
3359 *result = reg_read.val;
3364 drm_intel_get_subslice_total(int fd, unsigned int *subslice_total)
3366 drm_i915_getparam_t gp;
3370 gp.value = (int*)subslice_total;
3371 gp.param = I915_PARAM_SUBSLICE_TOTAL;
3372 ret = drmIoctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
3380 drm_intel_get_eu_total(int fd, unsigned int *eu_total)
3382 drm_i915_getparam_t gp;
3386 gp.value = (int*)eu_total;
3387 gp.param = I915_PARAM_EU_TOTAL;
3388 ret = drmIoctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
3396 * Annotate the given bo for use in aub dumping.
3398 * \param annotations is an array of drm_intel_aub_annotation objects
3399 * describing the type of data in various sections of the bo. Each
3400 * element of the array specifies the type and subtype of a section of
3401 * the bo, and the past-the-end offset of that section. The elements
3402 * of \c annotations must be sorted so that ending_offset is
3405 * \param count is the number of elements in the \c annotations array.
3406 * If \c count is zero, then \c annotations will not be dereferenced.
3408 * Annotations are copied into a private data structure, so caller may
3409 * re-use the memory pointed to by \c annotations after the call
3412 * Annotations are stored for the lifetime of the bo; to reset to the
3413 * default state (no annotations), call this function with a \c count
3417 drm_intel_bufmgr_gem_set_aub_annotations(drm_intel_bo *bo,
3418 drm_intel_aub_annotation *annotations,
3421 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
3422 unsigned size = sizeof(*annotations) * count;
3423 drm_intel_aub_annotation *new_annotations =
3424 count > 0 ? realloc(bo_gem->aub_annotations, size) : NULL;
3425 if (new_annotations == NULL) {
3426 free(bo_gem->aub_annotations);
3427 bo_gem->aub_annotations = NULL;
3428 bo_gem->aub_annotation_count = 0;
3431 memcpy(new_annotations, annotations, size);
3432 bo_gem->aub_annotations = new_annotations;
3433 bo_gem->aub_annotation_count = count;
3436 static pthread_mutex_t bufmgr_list_mutex = PTHREAD_MUTEX_INITIALIZER;
3437 static drmMMListHead bufmgr_list = { &bufmgr_list, &bufmgr_list };
3439 static drm_intel_bufmgr_gem *
3440 drm_intel_bufmgr_gem_find(int fd)
3442 drm_intel_bufmgr_gem *bufmgr_gem;
3444 DRMLISTFOREACHENTRY(bufmgr_gem, &bufmgr_list, managers) {
3445 if (bufmgr_gem->fd == fd) {
3446 atomic_inc(&bufmgr_gem->refcount);
3455 drm_intel_bufmgr_gem_unref(drm_intel_bufmgr *bufmgr)
3457 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
3459 if (atomic_add_unless(&bufmgr_gem->refcount, -1, 1)) {
3460 pthread_mutex_lock(&bufmgr_list_mutex);
3462 if (atomic_dec_and_test(&bufmgr_gem->refcount)) {
3463 DRMLISTDEL(&bufmgr_gem->managers);
3464 drm_intel_bufmgr_gem_destroy(bufmgr);
3467 pthread_mutex_unlock(&bufmgr_list_mutex);
3472 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
3473 * and manage map buffer objections.
3475 * \param fd File descriptor of the opened DRM device.
3477 drm_public drm_intel_bufmgr *
3478 drm_intel_bufmgr_gem_init(int fd, int batch_size)
3480 drm_intel_bufmgr_gem *bufmgr_gem;
3481 struct drm_i915_gem_get_aperture aperture;
3482 drm_i915_getparam_t gp;
3486 pthread_mutex_lock(&bufmgr_list_mutex);
3488 bufmgr_gem = drm_intel_bufmgr_gem_find(fd);
3492 bufmgr_gem = calloc(1, sizeof(*bufmgr_gem));
3493 if (bufmgr_gem == NULL)
3496 bufmgr_gem->fd = fd;
3497 atomic_set(&bufmgr_gem->refcount, 1);
3499 if (pthread_mutex_init(&bufmgr_gem->lock, NULL) != 0) {
3506 ret = drmIoctl(bufmgr_gem->fd,
3507 DRM_IOCTL_I915_GEM_GET_APERTURE,
3511 bufmgr_gem->gtt_size = aperture.aper_available_size;
3513 fprintf(stderr, "DRM_IOCTL_I915_GEM_APERTURE failed: %s\n",
3515 bufmgr_gem->gtt_size = 128 * 1024 * 1024;
3516 fprintf(stderr, "Assuming %dkB available aperture size.\n"
3517 "May lead to reduced performance or incorrect "
3519 (int)bufmgr_gem->gtt_size / 1024);
3522 bufmgr_gem->pci_device = get_pci_device_id(bufmgr_gem);
3524 if (IS_GEN2(bufmgr_gem->pci_device))
3525 bufmgr_gem->gen = 2;
3526 else if (IS_GEN3(bufmgr_gem->pci_device))
3527 bufmgr_gem->gen = 3;
3528 else if (IS_GEN4(bufmgr_gem->pci_device))
3529 bufmgr_gem->gen = 4;
3530 else if (IS_GEN5(bufmgr_gem->pci_device))
3531 bufmgr_gem->gen = 5;
3532 else if (IS_GEN6(bufmgr_gem->pci_device))
3533 bufmgr_gem->gen = 6;
3534 else if (IS_GEN7(bufmgr_gem->pci_device))
3535 bufmgr_gem->gen = 7;
3536 else if (IS_GEN8(bufmgr_gem->pci_device))
3537 bufmgr_gem->gen = 8;
3538 else if (IS_GEN9(bufmgr_gem->pci_device))
3539 bufmgr_gem->gen = 9;
3546 if (IS_GEN3(bufmgr_gem->pci_device) &&
3547 bufmgr_gem->gtt_size > 256*1024*1024) {
3548 /* The unmappable part of gtt on gen 3 (i.e. above 256MB) can't
3549 * be used for tiled blits. To simplify the accounting, just
3550 * substract the unmappable part (fixed to 256MB on all known
3551 * gen3 devices) if the kernel advertises it. */
3552 bufmgr_gem->gtt_size -= 256*1024*1024;
3558 gp.param = I915_PARAM_HAS_EXECBUF2;
3559 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3563 gp.param = I915_PARAM_HAS_BSD;
3564 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3565 bufmgr_gem->has_bsd = ret == 0;
3567 gp.param = I915_PARAM_HAS_BLT;
3568 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3569 bufmgr_gem->has_blt = ret == 0;
3571 gp.param = I915_PARAM_HAS_RELAXED_FENCING;
3572 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3573 bufmgr_gem->has_relaxed_fencing = ret == 0;
3575 bufmgr_gem->bufmgr.bo_alloc_userptr = check_bo_alloc_userptr;
3577 gp.param = I915_PARAM_HAS_WAIT_TIMEOUT;
3578 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3579 bufmgr_gem->has_wait_timeout = ret == 0;
3581 gp.param = I915_PARAM_HAS_LLC;
3582 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3584 /* Kernel does not supports HAS_LLC query, fallback to GPU
3585 * generation detection and assume that we have LLC on GEN6/7
3587 bufmgr_gem->has_llc = (IS_GEN6(bufmgr_gem->pci_device) |
3588 IS_GEN7(bufmgr_gem->pci_device));
3590 bufmgr_gem->has_llc = *gp.value;
3592 gp.param = I915_PARAM_HAS_VEBOX;
3593 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3594 bufmgr_gem->has_vebox = (ret == 0) & (*gp.value > 0);
3596 if (bufmgr_gem->gen < 4) {
3597 gp.param = I915_PARAM_NUM_FENCES_AVAIL;
3598 gp.value = &bufmgr_gem->available_fences;
3599 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3601 fprintf(stderr, "get fences failed: %d [%d]\n", ret,
3603 fprintf(stderr, "param: %d, val: %d\n", gp.param,
3605 bufmgr_gem->available_fences = 0;
3607 /* XXX The kernel reports the total number of fences,
3608 * including any that may be pinned.
3610 * We presume that there will be at least one pinned
3611 * fence for the scanout buffer, but there may be more
3612 * than one scanout and the user may be manually
3613 * pinning buffers. Let's move to execbuffer2 and
3614 * thereby forget the insanity of using fences...
3616 bufmgr_gem->available_fences -= 2;
3617 if (bufmgr_gem->available_fences < 0)
3618 bufmgr_gem->available_fences = 0;
3622 /* Let's go with one relocation per every 2 dwords (but round down a bit
3623 * since a power of two will mean an extra page allocation for the reloc
3626 * Every 4 was too few for the blender benchmark.
3628 bufmgr_gem->max_relocs = batch_size / sizeof(uint32_t) / 2 - 2;
3630 bufmgr_gem->bufmgr.bo_alloc = drm_intel_gem_bo_alloc;
3631 bufmgr_gem->bufmgr.bo_alloc_for_render =
3632 drm_intel_gem_bo_alloc_for_render;
3633 bufmgr_gem->bufmgr.bo_alloc_tiled = drm_intel_gem_bo_alloc_tiled;
3634 bufmgr_gem->bufmgr.bo_reference = drm_intel_gem_bo_reference;
3635 bufmgr_gem->bufmgr.bo_unreference = drm_intel_gem_bo_unreference;
3636 bufmgr_gem->bufmgr.bo_map = drm_intel_gem_bo_map;
3637 bufmgr_gem->bufmgr.bo_unmap = drm_intel_gem_bo_unmap;
3638 bufmgr_gem->bufmgr.bo_subdata = drm_intel_gem_bo_subdata;
3639 bufmgr_gem->bufmgr.bo_get_subdata = drm_intel_gem_bo_get_subdata;
3640 bufmgr_gem->bufmgr.bo_wait_rendering = drm_intel_gem_bo_wait_rendering;
3641 bufmgr_gem->bufmgr.bo_emit_reloc = drm_intel_gem_bo_emit_reloc;
3642 bufmgr_gem->bufmgr.bo_emit_reloc_fence = drm_intel_gem_bo_emit_reloc_fence;
3643 bufmgr_gem->bufmgr.bo_pin = drm_intel_gem_bo_pin;
3644 bufmgr_gem->bufmgr.bo_unpin = drm_intel_gem_bo_unpin;
3645 bufmgr_gem->bufmgr.bo_get_tiling = drm_intel_gem_bo_get_tiling;
3646 bufmgr_gem->bufmgr.bo_set_tiling = drm_intel_gem_bo_set_tiling;
3647 bufmgr_gem->bufmgr.bo_flink = drm_intel_gem_bo_flink;
3648 /* Use the new one if available */
3650 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec2;
3651 bufmgr_gem->bufmgr.bo_mrb_exec = drm_intel_gem_bo_mrb_exec2;
3653 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec;
3654 bufmgr_gem->bufmgr.bo_busy = drm_intel_gem_bo_busy;
3655 bufmgr_gem->bufmgr.bo_madvise = drm_intel_gem_bo_madvise;
3656 bufmgr_gem->bufmgr.destroy = drm_intel_bufmgr_gem_unref;
3657 bufmgr_gem->bufmgr.debug = 0;
3658 bufmgr_gem->bufmgr.check_aperture_space =
3659 drm_intel_gem_check_aperture_space;
3660 bufmgr_gem->bufmgr.bo_disable_reuse = drm_intel_gem_bo_disable_reuse;
3661 bufmgr_gem->bufmgr.bo_is_reusable = drm_intel_gem_bo_is_reusable;
3662 bufmgr_gem->bufmgr.get_pipe_from_crtc_id =
3663 drm_intel_gem_get_pipe_from_crtc_id;
3664 bufmgr_gem->bufmgr.bo_references = drm_intel_gem_bo_references;
3666 DRMINITLISTHEAD(&bufmgr_gem->named);
3667 init_cache_buckets(bufmgr_gem);
3669 DRMINITLISTHEAD(&bufmgr_gem->vma_cache);
3670 bufmgr_gem->vma_max = -1; /* unlimited by default */
3672 DRMLISTADD(&bufmgr_gem->managers, &bufmgr_list);
3675 pthread_mutex_unlock(&bufmgr_list_mutex);
3677 return bufmgr_gem != NULL ? &bufmgr_gem->bufmgr : NULL;