1 /**************************************************************************
3 * Copyright © 2007 Red Hat Inc.
4 * Copyright © 2007 Intel Corporation
5 * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
29 **************************************************************************/
31 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
32 * Keith Whitwell <keithw-at-tungstengraphics-dot-com>
33 * Eric Anholt <eric@anholt.net>
34 * Dave Airlie <airlied@linux.ie>
42 #include <xf86atomic.h>
50 #include <sys/ioctl.h>
53 #include <sys/types.h>
56 #include "libdrm_lists.h"
57 #include "intel_bufmgr.h"
58 #include "intel_bufmgr_priv.h"
59 #include "intel_chipset.h"
64 #define DBG(...) do { \
65 if (bufmgr_gem->bufmgr.debug) \
66 fprintf(stderr, __VA_ARGS__); \
69 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
71 typedef struct _drm_intel_bo_gem drm_intel_bo_gem;
73 struct drm_intel_gem_bo_bucket {
78 typedef struct _drm_intel_bufmgr_gem {
79 drm_intel_bufmgr bufmgr;
87 struct drm_i915_gem_exec_object *exec_objects;
88 struct drm_i915_gem_exec_object2 *exec2_objects;
89 drm_intel_bo **exec_bos;
93 /** Array of lists of cached gem objects of power-of-two sizes */
94 struct drm_intel_gem_bo_bucket cache_bucket[14 * 4];
101 int available_fences;
104 unsigned int has_bsd : 1;
105 unsigned int has_blt : 1;
106 unsigned int has_relaxed_fencing : 1;
107 unsigned int bo_reuse : 1;
109 } drm_intel_bufmgr_gem;
111 #define DRM_INTEL_RELOC_FENCE (1<<0)
113 typedef struct _drm_intel_reloc_target_info {
116 } drm_intel_reloc_target;
118 struct _drm_intel_bo_gem {
126 * Kenel-assigned global name for this object
128 unsigned int global_name;
129 drmMMListHead name_list;
132 * Index of the buffer within the validation list while preparing a
133 * batchbuffer execution.
138 * Current tiling mode
140 uint32_t tiling_mode;
141 uint32_t swizzle_mode;
142 unsigned long stride;
146 /** Array passed to the DRM containing relocation information. */
147 struct drm_i915_gem_relocation_entry *relocs;
149 * Array of info structs corresponding to relocs[i].target_handle etc
151 drm_intel_reloc_target *reloc_target_info;
152 /** Number of entries in relocs */
154 /** Mapped address for the buffer, saved across map/unmap cycles */
156 /** GTT virtual address for the buffer, saved across map/unmap cycles */
163 * Boolean of whether this BO and its children have been included in
164 * the current drm_intel_bufmgr_check_aperture_space() total.
166 char included_in_check_aperture;
169 * Boolean of whether this buffer has been used as a relocation
170 * target and had its size accounted for, and thus can't have any
171 * further relocations added to it.
173 char used_as_reloc_target;
176 * Boolean of whether we have encountered an error whilst building the relocation tree.
181 * Boolean of whether this buffer can be re-used
186 * Size in bytes of this buffer and its relocation descendents.
188 * Used to avoid costly tree walking in
189 * drm_intel_bufmgr_check_aperture in the common case.
194 * Number of potential fence registers required by this buffer and its
197 int reloc_tree_fences;
201 drm_intel_gem_estimate_batch_space(drm_intel_bo ** bo_array, int count);
204 drm_intel_gem_compute_batch_space(drm_intel_bo ** bo_array, int count);
207 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
208 uint32_t * swizzle_mode);
211 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
212 uint32_t tiling_mode,
215 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
218 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo);
220 static void drm_intel_gem_bo_free(drm_intel_bo *bo);
223 drm_intel_gem_bo_tile_size(drm_intel_bufmgr_gem *bufmgr_gem, unsigned long size,
224 uint32_t *tiling_mode)
226 unsigned long min_size, max_size;
229 if (*tiling_mode == I915_TILING_NONE)
232 /* 965+ just need multiples of page size for tiling */
233 if (bufmgr_gem->gen >= 4)
234 return ROUND_UP_TO(size, 4096);
236 /* Older chips need powers of two, of at least 512k or 1M */
237 if (bufmgr_gem->gen == 3) {
238 min_size = 1024*1024;
239 max_size = 128*1024*1024;
242 max_size = 64*1024*1024;
245 if (size > max_size) {
246 *tiling_mode = I915_TILING_NONE;
250 /* Do we need to allocate every page for the fence? */
251 if (bufmgr_gem->has_relaxed_fencing)
252 return ROUND_UP_TO(size, 4096);
254 for (i = min_size; i < size; i <<= 1)
261 * Round a given pitch up to the minimum required for X tiling on a
262 * given chip. We use 512 as the minimum to allow for a later tiling
266 drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem,
267 unsigned long pitch, uint32_t *tiling_mode)
269 unsigned long tile_width;
272 /* If untiled, then just align it so that we can do rendering
273 * to it with the 3D engine.
275 if (*tiling_mode == I915_TILING_NONE)
276 return ALIGN(pitch, 64);
278 if (*tiling_mode == I915_TILING_X)
283 /* 965 is flexible */
284 if (bufmgr_gem->gen >= 4)
285 return ROUND_UP_TO(pitch, tile_width);
287 /* The older hardware has a maximum pitch of 8192 with tiled
288 * surfaces, so fallback to untiled if it's too large.
291 *tiling_mode = I915_TILING_NONE;
292 return ALIGN(pitch, 64);
295 /* Pre-965 needs power of two tile width */
296 for (i = tile_width; i < pitch; i <<= 1)
302 static struct drm_intel_gem_bo_bucket *
303 drm_intel_gem_bo_bucket_for_size(drm_intel_bufmgr_gem *bufmgr_gem,
308 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
309 struct drm_intel_gem_bo_bucket *bucket =
310 &bufmgr_gem->cache_bucket[i];
311 if (bucket->size >= size) {
320 drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem *bufmgr_gem)
324 for (i = 0; i < bufmgr_gem->exec_count; i++) {
325 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
326 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
328 if (bo_gem->relocs == NULL) {
329 DBG("%2d: %d (%s)\n", i, bo_gem->gem_handle,
334 for (j = 0; j < bo_gem->reloc_count; j++) {
335 drm_intel_bo *target_bo = bo_gem->reloc_target_info[j].bo;
336 drm_intel_bo_gem *target_gem =
337 (drm_intel_bo_gem *) target_bo;
339 DBG("%2d: %d (%s)@0x%08llx -> "
340 "%d (%s)@0x%08lx + 0x%08x\n",
342 bo_gem->gem_handle, bo_gem->name,
343 (unsigned long long)bo_gem->relocs[j].offset,
344 target_gem->gem_handle,
347 bo_gem->relocs[j].delta);
353 drm_intel_gem_bo_reference(drm_intel_bo *bo)
355 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
357 atomic_inc(&bo_gem->refcount);
361 * Adds the given buffer to the list of buffers to be validated (moved into the
362 * appropriate memory type) with the next batch submission.
364 * If a buffer is validated multiple times in a batch submission, it ends up
365 * with the intersection of the memory type flags and the union of the
369 drm_intel_add_validate_buffer(drm_intel_bo *bo)
371 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
372 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
375 if (bo_gem->validate_index != -1)
378 /* Extend the array of validation entries as necessary. */
379 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
380 int new_size = bufmgr_gem->exec_size * 2;
385 bufmgr_gem->exec_objects =
386 realloc(bufmgr_gem->exec_objects,
387 sizeof(*bufmgr_gem->exec_objects) * new_size);
388 bufmgr_gem->exec_bos =
389 realloc(bufmgr_gem->exec_bos,
390 sizeof(*bufmgr_gem->exec_bos) * new_size);
391 bufmgr_gem->exec_size = new_size;
394 index = bufmgr_gem->exec_count;
395 bo_gem->validate_index = index;
396 /* Fill in array entry */
397 bufmgr_gem->exec_objects[index].handle = bo_gem->gem_handle;
398 bufmgr_gem->exec_objects[index].relocation_count = bo_gem->reloc_count;
399 bufmgr_gem->exec_objects[index].relocs_ptr = (uintptr_t) bo_gem->relocs;
400 bufmgr_gem->exec_objects[index].alignment = 0;
401 bufmgr_gem->exec_objects[index].offset = 0;
402 bufmgr_gem->exec_bos[index] = bo;
403 bufmgr_gem->exec_count++;
407 drm_intel_add_validate_buffer2(drm_intel_bo *bo, int need_fence)
409 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
410 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
413 if (bo_gem->validate_index != -1) {
415 bufmgr_gem->exec2_objects[bo_gem->validate_index].flags |=
416 EXEC_OBJECT_NEEDS_FENCE;
420 /* Extend the array of validation entries as necessary. */
421 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
422 int new_size = bufmgr_gem->exec_size * 2;
427 bufmgr_gem->exec2_objects =
428 realloc(bufmgr_gem->exec2_objects,
429 sizeof(*bufmgr_gem->exec2_objects) * new_size);
430 bufmgr_gem->exec_bos =
431 realloc(bufmgr_gem->exec_bos,
432 sizeof(*bufmgr_gem->exec_bos) * new_size);
433 bufmgr_gem->exec_size = new_size;
436 index = bufmgr_gem->exec_count;
437 bo_gem->validate_index = index;
438 /* Fill in array entry */
439 bufmgr_gem->exec2_objects[index].handle = bo_gem->gem_handle;
440 bufmgr_gem->exec2_objects[index].relocation_count = bo_gem->reloc_count;
441 bufmgr_gem->exec2_objects[index].relocs_ptr = (uintptr_t)bo_gem->relocs;
442 bufmgr_gem->exec2_objects[index].alignment = 0;
443 bufmgr_gem->exec2_objects[index].offset = 0;
444 bufmgr_gem->exec_bos[index] = bo;
445 bufmgr_gem->exec2_objects[index].flags = 0;
446 bufmgr_gem->exec2_objects[index].rsvd1 = 0;
447 bufmgr_gem->exec2_objects[index].rsvd2 = 0;
449 bufmgr_gem->exec2_objects[index].flags |=
450 EXEC_OBJECT_NEEDS_FENCE;
452 bufmgr_gem->exec_count++;
455 #define RELOC_BUF_SIZE(x) ((I915_RELOC_HEADER + x * I915_RELOC0_STRIDE) * \
459 drm_intel_bo_gem_set_in_aperture_size(drm_intel_bufmgr_gem *bufmgr_gem,
460 drm_intel_bo_gem *bo_gem)
464 assert(!bo_gem->used_as_reloc_target);
466 /* The older chipsets are far-less flexible in terms of tiling,
467 * and require tiled buffer to be size aligned in the aperture.
468 * This means that in the worst possible case we will need a hole
469 * twice as large as the object in order for it to fit into the
470 * aperture. Optimal packing is for wimps.
472 size = bo_gem->bo.size;
473 if (bufmgr_gem->gen < 4 && bo_gem->tiling_mode != I915_TILING_NONE) {
476 if (bufmgr_gem->has_relaxed_fencing) {
477 if (bufmgr_gem->gen == 3)
478 min_size = 1024*1024;
482 while (min_size < size)
487 /* Account for worst-case alignment. */
491 bo_gem->reloc_tree_size = size;
495 drm_intel_setup_reloc_list(drm_intel_bo *bo)
497 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
498 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
499 unsigned int max_relocs = bufmgr_gem->max_relocs;
501 if (bo->size / 4 < max_relocs)
502 max_relocs = bo->size / 4;
504 bo_gem->relocs = malloc(max_relocs *
505 sizeof(struct drm_i915_gem_relocation_entry));
506 bo_gem->reloc_target_info = malloc(max_relocs *
507 sizeof(drm_intel_reloc_target));
508 if (bo_gem->relocs == NULL || bo_gem->reloc_target_info == NULL) {
509 bo_gem->has_error = 1;
511 free (bo_gem->relocs);
512 bo_gem->relocs = NULL;
514 free (bo_gem->reloc_target_info);
515 bo_gem->reloc_target_info = NULL;
524 drm_intel_gem_bo_busy(drm_intel_bo *bo)
526 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
527 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
528 struct drm_i915_gem_busy busy;
531 memset(&busy, 0, sizeof(busy));
532 busy.handle = bo_gem->gem_handle;
534 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_BUSY, &busy);
536 return (ret == 0 && busy.busy);
540 drm_intel_gem_bo_madvise_internal(drm_intel_bufmgr_gem *bufmgr_gem,
541 drm_intel_bo_gem *bo_gem, int state)
543 struct drm_i915_gem_madvise madv;
545 madv.handle = bo_gem->gem_handle;
548 drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MADVISE, &madv);
550 return madv.retained;
554 drm_intel_gem_bo_madvise(drm_intel_bo *bo, int madv)
556 return drm_intel_gem_bo_madvise_internal
557 ((drm_intel_bufmgr_gem *) bo->bufmgr,
558 (drm_intel_bo_gem *) bo,
562 /* drop the oldest entries that have been purged by the kernel */
564 drm_intel_gem_bo_cache_purge_bucket(drm_intel_bufmgr_gem *bufmgr_gem,
565 struct drm_intel_gem_bo_bucket *bucket)
567 while (!DRMLISTEMPTY(&bucket->head)) {
568 drm_intel_bo_gem *bo_gem;
570 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
571 bucket->head.next, head);
572 if (drm_intel_gem_bo_madvise_internal
573 (bufmgr_gem, bo_gem, I915_MADV_DONTNEED))
576 DRMLISTDEL(&bo_gem->head);
577 drm_intel_gem_bo_free(&bo_gem->bo);
581 static drm_intel_bo *
582 drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr,
586 uint32_t tiling_mode,
587 unsigned long stride)
589 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
590 drm_intel_bo_gem *bo_gem;
591 unsigned int page_size = getpagesize();
593 struct drm_intel_gem_bo_bucket *bucket;
594 int alloc_from_cache;
595 unsigned long bo_size;
598 if (flags & BO_ALLOC_FOR_RENDER)
601 /* Round the allocated size up to a power of two number of pages. */
602 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, size);
604 /* If we don't have caching at this size, don't actually round the
607 if (bucket == NULL) {
609 if (bo_size < page_size)
612 bo_size = bucket->size;
615 pthread_mutex_lock(&bufmgr_gem->lock);
616 /* Get a buffer out of the cache if available */
618 alloc_from_cache = 0;
619 if (bucket != NULL && !DRMLISTEMPTY(&bucket->head)) {
621 /* Allocate new render-target BOs from the tail (MRU)
622 * of the list, as it will likely be hot in the GPU
623 * cache and in the aperture for us.
625 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
626 bucket->head.prev, head);
627 DRMLISTDEL(&bo_gem->head);
628 alloc_from_cache = 1;
630 /* For non-render-target BOs (where we're probably
631 * going to map it first thing in order to fill it
632 * with data), check if the last BO in the cache is
633 * unbusy, and only reuse in that case. Otherwise,
634 * allocating a new buffer is probably faster than
635 * waiting for the GPU to finish.
637 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
638 bucket->head.next, head);
639 if (!drm_intel_gem_bo_busy(&bo_gem->bo)) {
640 alloc_from_cache = 1;
641 DRMLISTDEL(&bo_gem->head);
645 if (alloc_from_cache) {
646 if (!drm_intel_gem_bo_madvise_internal
647 (bufmgr_gem, bo_gem, I915_MADV_WILLNEED)) {
648 drm_intel_gem_bo_free(&bo_gem->bo);
649 drm_intel_gem_bo_cache_purge_bucket(bufmgr_gem,
654 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
657 drm_intel_gem_bo_free(&bo_gem->bo);
662 pthread_mutex_unlock(&bufmgr_gem->lock);
664 if (!alloc_from_cache) {
665 struct drm_i915_gem_create create;
667 bo_gem = calloc(1, sizeof(*bo_gem));
671 bo_gem->bo.size = bo_size;
672 memset(&create, 0, sizeof(create));
673 create.size = bo_size;
675 ret = drmIoctl(bufmgr_gem->fd,
676 DRM_IOCTL_I915_GEM_CREATE,
678 bo_gem->gem_handle = create.handle;
679 bo_gem->bo.handle = bo_gem->gem_handle;
684 bo_gem->bo.bufmgr = bufmgr;
686 bo_gem->tiling_mode = I915_TILING_NONE;
687 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
690 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
693 drm_intel_gem_bo_free(&bo_gem->bo);
697 DRMINITLISTHEAD(&bo_gem->name_list);
701 atomic_set(&bo_gem->refcount, 1);
702 bo_gem->validate_index = -1;
703 bo_gem->reloc_tree_fences = 0;
704 bo_gem->used_as_reloc_target = 0;
705 bo_gem->has_error = 0;
706 bo_gem->reusable = 1;
708 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
710 DBG("bo_create: buf %d (%s) %ldb\n",
711 bo_gem->gem_handle, bo_gem->name, size);
716 static drm_intel_bo *
717 drm_intel_gem_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
720 unsigned int alignment)
722 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size,
724 I915_TILING_NONE, 0);
727 static drm_intel_bo *
728 drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr,
731 unsigned int alignment)
733 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, 0,
734 I915_TILING_NONE, 0);
737 static drm_intel_bo *
738 drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
739 int x, int y, int cpp, uint32_t *tiling_mode,
740 unsigned long *pitch, unsigned long flags)
742 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
743 unsigned long size, stride;
747 unsigned long aligned_y;
749 tiling = *tiling_mode;
751 /* If we're tiled, our allocations are in 8 or 32-row blocks,
752 * so failure to align our height means that we won't allocate
755 * If we're untiled, we still have to align to 2 rows high
756 * because the data port accesses 2x2 blocks even if the
757 * bottom row isn't to be rendered, so failure to align means
758 * we could walk off the end of the GTT and fault. This is
759 * documented on 965, and may be the case on older chipsets
760 * too so we try to be careful.
763 if (tiling == I915_TILING_NONE)
764 aligned_y = ALIGN(y, 2);
765 else if (tiling == I915_TILING_X)
766 aligned_y = ALIGN(y, 8);
767 else if (tiling == I915_TILING_Y)
768 aligned_y = ALIGN(y, 32);
771 stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, tiling_mode);
772 size = stride * aligned_y;
773 size = drm_intel_gem_bo_tile_size(bufmgr_gem, size, tiling_mode);
774 } while (*tiling_mode != tiling);
777 if (tiling == I915_TILING_NONE)
780 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, flags,
785 * Returns a drm_intel_bo wrapping the given buffer object handle.
787 * This can be used when one application needs to pass a buffer object
791 drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
795 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
796 drm_intel_bo_gem *bo_gem;
798 struct drm_gem_open open_arg;
799 struct drm_i915_gem_get_tiling get_tiling;
802 /* At the moment most applications only have a few named bo.
803 * For instance, in a DRI client only the render buffers passed
804 * between X and the client are named. And since X returns the
805 * alternating names for the front/back buffer a linear search
806 * provides a sufficiently fast match.
808 for (list = bufmgr_gem->named.next;
809 list != &bufmgr_gem->named;
811 bo_gem = DRMLISTENTRY(drm_intel_bo_gem, list, name_list);
812 if (bo_gem->global_name == handle) {
813 drm_intel_gem_bo_reference(&bo_gem->bo);
818 bo_gem = calloc(1, sizeof(*bo_gem));
822 memset(&open_arg, 0, sizeof(open_arg));
823 open_arg.name = handle;
824 ret = drmIoctl(bufmgr_gem->fd,
828 DBG("Couldn't reference %s handle 0x%08x: %s\n",
829 name, handle, strerror(errno));
833 bo_gem->bo.size = open_arg.size;
834 bo_gem->bo.offset = 0;
835 bo_gem->bo.virtual = NULL;
836 bo_gem->bo.bufmgr = bufmgr;
838 atomic_set(&bo_gem->refcount, 1);
839 bo_gem->validate_index = -1;
840 bo_gem->gem_handle = open_arg.handle;
841 bo_gem->bo.handle = open_arg.handle;
842 bo_gem->global_name = handle;
843 bo_gem->reusable = 0;
845 memset(&get_tiling, 0, sizeof(get_tiling));
846 get_tiling.handle = bo_gem->gem_handle;
847 ret = drmIoctl(bufmgr_gem->fd,
848 DRM_IOCTL_I915_GEM_GET_TILING,
851 drm_intel_gem_bo_unreference(&bo_gem->bo);
854 bo_gem->tiling_mode = get_tiling.tiling_mode;
855 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
856 /* XXX stride is unknown */
857 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
859 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
860 DBG("bo_create_from_handle: %d (%s)\n", handle, bo_gem->name);
866 drm_intel_gem_bo_free(drm_intel_bo *bo)
868 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
869 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
870 struct drm_gem_close close;
873 if (bo_gem->mem_virtual)
874 munmap(bo_gem->mem_virtual, bo_gem->bo.size);
875 if (bo_gem->gtt_virtual)
876 munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
878 /* Close this object */
879 memset(&close, 0, sizeof(close));
880 close.handle = bo_gem->gem_handle;
881 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close);
883 DBG("DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
884 bo_gem->gem_handle, bo_gem->name, strerror(errno));
889 /** Frees all cached buffers significantly older than @time. */
891 drm_intel_gem_cleanup_bo_cache(drm_intel_bufmgr_gem *bufmgr_gem, time_t time)
895 if (bufmgr_gem->time == time)
898 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
899 struct drm_intel_gem_bo_bucket *bucket =
900 &bufmgr_gem->cache_bucket[i];
902 while (!DRMLISTEMPTY(&bucket->head)) {
903 drm_intel_bo_gem *bo_gem;
905 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
906 bucket->head.next, head);
907 if (time - bo_gem->free_time <= 1)
910 DRMLISTDEL(&bo_gem->head);
912 drm_intel_gem_bo_free(&bo_gem->bo);
916 bufmgr_gem->time = time;
920 drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time)
922 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
923 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
924 struct drm_intel_gem_bo_bucket *bucket;
927 /* Unreference all the target buffers */
928 for (i = 0; i < bo_gem->reloc_count; i++) {
929 if (bo_gem->reloc_target_info[i].bo != bo) {
930 drm_intel_gem_bo_unreference_locked_timed(bo_gem->
931 reloc_target_info[i].bo,
935 bo_gem->reloc_count = 0;
936 bo_gem->used_as_reloc_target = 0;
938 DBG("bo_unreference final: %d (%s)\n",
939 bo_gem->gem_handle, bo_gem->name);
941 /* release memory associated with this object */
942 if (bo_gem->reloc_target_info) {
943 free(bo_gem->reloc_target_info);
944 bo_gem->reloc_target_info = NULL;
946 if (bo_gem->relocs) {
947 free(bo_gem->relocs);
948 bo_gem->relocs = NULL;
951 DRMLISTDEL(&bo_gem->name_list);
953 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, bo->size);
954 /* Put the buffer into our internal cache for reuse if we can. */
955 if (bufmgr_gem->bo_reuse && bo_gem->reusable && bucket != NULL &&
956 drm_intel_gem_bo_madvise_internal(bufmgr_gem, bo_gem,
957 I915_MADV_DONTNEED)) {
958 bo_gem->free_time = time;
961 bo_gem->validate_index = -1;
963 DRMLISTADDTAIL(&bo_gem->head, &bucket->head);
965 drm_intel_gem_bo_free(bo);
969 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
972 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
974 assert(atomic_read(&bo_gem->refcount) > 0);
975 if (atomic_dec_and_test(&bo_gem->refcount))
976 drm_intel_gem_bo_unreference_final(bo, time);
979 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo)
981 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
983 assert(atomic_read(&bo_gem->refcount) > 0);
984 if (atomic_dec_and_test(&bo_gem->refcount)) {
985 drm_intel_bufmgr_gem *bufmgr_gem =
986 (drm_intel_bufmgr_gem *) bo->bufmgr;
987 struct timespec time;
989 clock_gettime(CLOCK_MONOTONIC, &time);
991 pthread_mutex_lock(&bufmgr_gem->lock);
992 drm_intel_gem_bo_unreference_final(bo, time.tv_sec);
993 drm_intel_gem_cleanup_bo_cache(bufmgr_gem, time.tv_sec);
994 pthread_mutex_unlock(&bufmgr_gem->lock);
998 static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable)
1000 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1001 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1002 struct drm_i915_gem_set_domain set_domain;
1005 pthread_mutex_lock(&bufmgr_gem->lock);
1007 /* Allow recursive mapping. Mesa may recursively map buffers with
1008 * nested display loops.
1010 if (!bo_gem->mem_virtual) {
1011 struct drm_i915_gem_mmap mmap_arg;
1013 DBG("bo_map: %d (%s)\n", bo_gem->gem_handle, bo_gem->name);
1015 memset(&mmap_arg, 0, sizeof(mmap_arg));
1016 mmap_arg.handle = bo_gem->gem_handle;
1017 mmap_arg.offset = 0;
1018 mmap_arg.size = bo->size;
1019 ret = drmIoctl(bufmgr_gem->fd,
1020 DRM_IOCTL_I915_GEM_MMAP,
1024 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1025 __FILE__, __LINE__, bo_gem->gem_handle,
1026 bo_gem->name, strerror(errno));
1027 pthread_mutex_unlock(&bufmgr_gem->lock);
1030 bo_gem->mem_virtual = (void *)(uintptr_t) mmap_arg.addr_ptr;
1032 DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1033 bo_gem->mem_virtual);
1034 bo->virtual = bo_gem->mem_virtual;
1036 set_domain.handle = bo_gem->gem_handle;
1037 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
1039 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
1041 set_domain.write_domain = 0;
1042 ret = drmIoctl(bufmgr_gem->fd,
1043 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1046 DBG("%s:%d: Error setting to CPU domain %d: %s\n",
1047 __FILE__, __LINE__, bo_gem->gem_handle,
1051 pthread_mutex_unlock(&bufmgr_gem->lock);
1056 int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
1058 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1059 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1060 struct drm_i915_gem_set_domain set_domain;
1063 pthread_mutex_lock(&bufmgr_gem->lock);
1065 /* Get a mapping of the buffer if we haven't before. */
1066 if (bo_gem->gtt_virtual == NULL) {
1067 struct drm_i915_gem_mmap_gtt mmap_arg;
1069 DBG("bo_map_gtt: mmap %d (%s)\n", bo_gem->gem_handle,
1072 memset(&mmap_arg, 0, sizeof(mmap_arg));
1073 mmap_arg.handle = bo_gem->gem_handle;
1075 /* Get the fake offset back... */
1076 ret = drmIoctl(bufmgr_gem->fd,
1077 DRM_IOCTL_I915_GEM_MMAP_GTT,
1081 DBG("%s:%d: Error preparing buffer map %d (%s): %s .\n",
1083 bo_gem->gem_handle, bo_gem->name,
1085 pthread_mutex_unlock(&bufmgr_gem->lock);
1090 bo_gem->gtt_virtual = mmap(0, bo->size, PROT_READ | PROT_WRITE,
1091 MAP_SHARED, bufmgr_gem->fd,
1093 if (bo_gem->gtt_virtual == MAP_FAILED) {
1094 bo_gem->gtt_virtual = NULL;
1096 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1098 bo_gem->gem_handle, bo_gem->name,
1100 pthread_mutex_unlock(&bufmgr_gem->lock);
1105 bo->virtual = bo_gem->gtt_virtual;
1107 DBG("bo_map_gtt: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1108 bo_gem->gtt_virtual);
1110 /* Now move it to the GTT domain so that the CPU caches are flushed */
1111 set_domain.handle = bo_gem->gem_handle;
1112 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1113 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
1114 ret = drmIoctl(bufmgr_gem->fd,
1115 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1118 DBG("%s:%d: Error setting domain %d: %s\n",
1119 __FILE__, __LINE__, bo_gem->gem_handle,
1123 pthread_mutex_unlock(&bufmgr_gem->lock);
1128 int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo)
1130 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1136 pthread_mutex_lock(&bufmgr_gem->lock);
1138 pthread_mutex_unlock(&bufmgr_gem->lock);
1143 static int drm_intel_gem_bo_unmap(drm_intel_bo *bo)
1145 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1146 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1147 struct drm_i915_gem_sw_finish sw_finish;
1153 pthread_mutex_lock(&bufmgr_gem->lock);
1155 /* Cause a flush to happen if the buffer's pinned for scanout, so the
1156 * results show up in a timely manner.
1158 sw_finish.handle = bo_gem->gem_handle;
1159 ret = drmIoctl(bufmgr_gem->fd,
1160 DRM_IOCTL_I915_GEM_SW_FINISH,
1162 ret = ret == -1 ? -errno : 0;
1165 pthread_mutex_unlock(&bufmgr_gem->lock);
1171 drm_intel_gem_bo_subdata(drm_intel_bo *bo, unsigned long offset,
1172 unsigned long size, const void *data)
1174 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1175 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1176 struct drm_i915_gem_pwrite pwrite;
1179 memset(&pwrite, 0, sizeof(pwrite));
1180 pwrite.handle = bo_gem->gem_handle;
1181 pwrite.offset = offset;
1183 pwrite.data_ptr = (uint64_t) (uintptr_t) data;
1184 ret = drmIoctl(bufmgr_gem->fd,
1185 DRM_IOCTL_I915_GEM_PWRITE,
1189 DBG("%s:%d: Error writing data to buffer %d: (%d %d) %s .\n",
1190 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1191 (int)size, strerror(errno));
1198 drm_intel_gem_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id)
1200 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1201 struct drm_i915_get_pipe_from_crtc_id get_pipe_from_crtc_id;
1204 get_pipe_from_crtc_id.crtc_id = crtc_id;
1205 ret = drmIoctl(bufmgr_gem->fd,
1206 DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID,
1207 &get_pipe_from_crtc_id);
1209 /* We return -1 here to signal that we don't
1210 * know which pipe is associated with this crtc.
1211 * This lets the caller know that this information
1212 * isn't available; using the wrong pipe for
1213 * vblank waiting can cause the chipset to lock up
1218 return get_pipe_from_crtc_id.pipe;
1222 drm_intel_gem_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
1223 unsigned long size, void *data)
1225 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1226 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1227 struct drm_i915_gem_pread pread;
1230 memset(&pread, 0, sizeof(pread));
1231 pread.handle = bo_gem->gem_handle;
1232 pread.offset = offset;
1234 pread.data_ptr = (uint64_t) (uintptr_t) data;
1235 ret = drmIoctl(bufmgr_gem->fd,
1236 DRM_IOCTL_I915_GEM_PREAD,
1240 DBG("%s:%d: Error reading data from buffer %d: (%d %d) %s .\n",
1241 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1242 (int)size, strerror(errno));
1248 /** Waits for all GPU rendering with the object to have completed. */
1250 drm_intel_gem_bo_wait_rendering(drm_intel_bo *bo)
1252 drm_intel_gem_bo_start_gtt_access(bo, 1);
1256 * Sets the object to the GTT read and possibly write domain, used by the X
1257 * 2D driver in the absence of kernel support to do drm_intel_gem_bo_map_gtt().
1259 * In combination with drm_intel_gem_bo_pin() and manual fence management, we
1260 * can do tiled pixmaps this way.
1263 drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable)
1265 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1266 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1267 struct drm_i915_gem_set_domain set_domain;
1270 set_domain.handle = bo_gem->gem_handle;
1271 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1272 set_domain.write_domain = write_enable ? I915_GEM_DOMAIN_GTT : 0;
1273 ret = drmIoctl(bufmgr_gem->fd,
1274 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1277 DBG("%s:%d: Error setting memory domains %d (%08x %08x): %s .\n",
1278 __FILE__, __LINE__, bo_gem->gem_handle,
1279 set_domain.read_domains, set_domain.write_domain,
1285 drm_intel_bufmgr_gem_destroy(drm_intel_bufmgr *bufmgr)
1287 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1290 free(bufmgr_gem->exec2_objects);
1291 free(bufmgr_gem->exec_objects);
1292 free(bufmgr_gem->exec_bos);
1294 pthread_mutex_destroy(&bufmgr_gem->lock);
1296 /* Free any cached buffer objects we were going to reuse */
1297 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
1298 struct drm_intel_gem_bo_bucket *bucket =
1299 &bufmgr_gem->cache_bucket[i];
1300 drm_intel_bo_gem *bo_gem;
1302 while (!DRMLISTEMPTY(&bucket->head)) {
1303 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1304 bucket->head.next, head);
1305 DRMLISTDEL(&bo_gem->head);
1307 drm_intel_gem_bo_free(&bo_gem->bo);
1315 * Adds the target buffer to the validation list and adds the relocation
1316 * to the reloc_buffer's relocation list.
1318 * The relocation entry at the given offset must already contain the
1319 * precomputed relocation value, because the kernel will optimize out
1320 * the relocation entry write when the buffer hasn't moved from the
1321 * last known offset in target_bo.
1324 do_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1325 drm_intel_bo *target_bo, uint32_t target_offset,
1326 uint32_t read_domains, uint32_t write_domain,
1329 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1330 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1331 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
1334 if (bo_gem->has_error)
1337 if (target_bo_gem->has_error) {
1338 bo_gem->has_error = 1;
1342 /* We never use HW fences for rendering on 965+ */
1343 if (bufmgr_gem->gen >= 4)
1346 fenced_command = need_fence;
1347 if (target_bo_gem->tiling_mode == I915_TILING_NONE)
1350 /* Create a new relocation list if needed */
1351 if (bo_gem->relocs == NULL && drm_intel_setup_reloc_list(bo))
1354 /* Check overflow */
1355 assert(bo_gem->reloc_count < bufmgr_gem->max_relocs);
1358 assert(offset <= bo->size - 4);
1359 assert((write_domain & (write_domain - 1)) == 0);
1361 /* Make sure that we're not adding a reloc to something whose size has
1362 * already been accounted for.
1364 assert(!bo_gem->used_as_reloc_target);
1365 if (target_bo_gem != bo_gem) {
1366 target_bo_gem->used_as_reloc_target = 1;
1367 bo_gem->reloc_tree_size += target_bo_gem->reloc_tree_size;
1369 /* An object needing a fence is a tiled buffer, so it won't have
1370 * relocs to other buffers.
1373 target_bo_gem->reloc_tree_fences = 1;
1374 bo_gem->reloc_tree_fences += target_bo_gem->reloc_tree_fences;
1376 bo_gem->relocs[bo_gem->reloc_count].offset = offset;
1377 bo_gem->relocs[bo_gem->reloc_count].delta = target_offset;
1378 bo_gem->relocs[bo_gem->reloc_count].target_handle =
1379 target_bo_gem->gem_handle;
1380 bo_gem->relocs[bo_gem->reloc_count].read_domains = read_domains;
1381 bo_gem->relocs[bo_gem->reloc_count].write_domain = write_domain;
1382 bo_gem->relocs[bo_gem->reloc_count].presumed_offset = target_bo->offset;
1384 bo_gem->reloc_target_info[bo_gem->reloc_count].bo = target_bo;
1385 if (target_bo != bo)
1386 drm_intel_gem_bo_reference(target_bo);
1388 bo_gem->reloc_target_info[bo_gem->reloc_count].flags =
1389 DRM_INTEL_RELOC_FENCE;
1391 bo_gem->reloc_target_info[bo_gem->reloc_count].flags = 0;
1393 bo_gem->reloc_count++;
1399 drm_intel_gem_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1400 drm_intel_bo *target_bo, uint32_t target_offset,
1401 uint32_t read_domains, uint32_t write_domain)
1403 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1405 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1406 read_domains, write_domain,
1407 !bufmgr_gem->fenced_relocs);
1411 drm_intel_gem_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
1412 drm_intel_bo *target_bo,
1413 uint32_t target_offset,
1414 uint32_t read_domains, uint32_t write_domain)
1416 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1417 read_domains, write_domain, 1);
1421 * Walk the tree of relocations rooted at BO and accumulate the list of
1422 * validations to be performed and update the relocation buffers with
1423 * index values into the validation list.
1426 drm_intel_gem_bo_process_reloc(drm_intel_bo *bo)
1428 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1431 if (bo_gem->relocs == NULL)
1434 for (i = 0; i < bo_gem->reloc_count; i++) {
1435 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1437 if (target_bo == bo)
1440 /* Continue walking the tree depth-first. */
1441 drm_intel_gem_bo_process_reloc(target_bo);
1443 /* Add the target to the validate list */
1444 drm_intel_add_validate_buffer(target_bo);
1449 drm_intel_gem_bo_process_reloc2(drm_intel_bo *bo)
1451 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1454 if (bo_gem->relocs == NULL)
1457 for (i = 0; i < bo_gem->reloc_count; i++) {
1458 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1461 if (target_bo == bo)
1464 /* Continue walking the tree depth-first. */
1465 drm_intel_gem_bo_process_reloc2(target_bo);
1467 need_fence = (bo_gem->reloc_target_info[i].flags &
1468 DRM_INTEL_RELOC_FENCE);
1470 /* Add the target to the validate list */
1471 drm_intel_add_validate_buffer2(target_bo, need_fence);
1477 drm_intel_update_buffer_offsets(drm_intel_bufmgr_gem *bufmgr_gem)
1481 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1482 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1483 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1485 /* Update the buffer offset */
1486 if (bufmgr_gem->exec_objects[i].offset != bo->offset) {
1487 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1488 bo_gem->gem_handle, bo_gem->name, bo->offset,
1489 (unsigned long long)bufmgr_gem->exec_objects[i].
1491 bo->offset = bufmgr_gem->exec_objects[i].offset;
1497 drm_intel_update_buffer_offsets2 (drm_intel_bufmgr_gem *bufmgr_gem)
1501 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1502 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1503 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1505 /* Update the buffer offset */
1506 if (bufmgr_gem->exec2_objects[i].offset != bo->offset) {
1507 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1508 bo_gem->gem_handle, bo_gem->name, bo->offset,
1509 (unsigned long long)bufmgr_gem->exec2_objects[i].offset);
1510 bo->offset = bufmgr_gem->exec2_objects[i].offset;
1516 drm_intel_gem_bo_exec(drm_intel_bo *bo, int used,
1517 drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
1519 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1520 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1521 struct drm_i915_gem_execbuffer execbuf;
1524 if (bo_gem->has_error)
1527 pthread_mutex_lock(&bufmgr_gem->lock);
1528 /* Update indices and set up the validate list. */
1529 drm_intel_gem_bo_process_reloc(bo);
1531 /* Add the batch buffer to the validation list. There are no
1532 * relocations pointing to it.
1534 drm_intel_add_validate_buffer(bo);
1536 execbuf.buffers_ptr = (uintptr_t) bufmgr_gem->exec_objects;
1537 execbuf.buffer_count = bufmgr_gem->exec_count;
1538 execbuf.batch_start_offset = 0;
1539 execbuf.batch_len = used;
1540 execbuf.cliprects_ptr = (uintptr_t) cliprects;
1541 execbuf.num_cliprects = num_cliprects;
1545 ret = drmIoctl(bufmgr_gem->fd,
1546 DRM_IOCTL_I915_GEM_EXECBUFFER,
1550 if (errno == ENOSPC) {
1551 DBG("Execbuffer fails to pin. "
1552 "Estimate: %u. Actual: %u. Available: %u\n",
1553 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
1556 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
1559 (unsigned int)bufmgr_gem->gtt_size);
1562 drm_intel_update_buffer_offsets(bufmgr_gem);
1564 if (bufmgr_gem->bufmgr.debug)
1565 drm_intel_gem_dump_validation_list(bufmgr_gem);
1567 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1568 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1569 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1571 /* Disconnect the buffer from the validate list */
1572 bo_gem->validate_index = -1;
1573 bufmgr_gem->exec_bos[i] = NULL;
1575 bufmgr_gem->exec_count = 0;
1576 pthread_mutex_unlock(&bufmgr_gem->lock);
1582 drm_intel_gem_bo_mrb_exec2(drm_intel_bo *bo, int used,
1583 drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
1586 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1587 struct drm_i915_gem_execbuffer2 execbuf;
1590 switch (flags & 0x7) {
1594 if (!bufmgr_gem->has_blt)
1598 if (!bufmgr_gem->has_bsd)
1601 case I915_EXEC_RENDER:
1602 case I915_EXEC_DEFAULT:
1606 pthread_mutex_lock(&bufmgr_gem->lock);
1607 /* Update indices and set up the validate list. */
1608 drm_intel_gem_bo_process_reloc2(bo);
1610 /* Add the batch buffer to the validation list. There are no relocations
1613 drm_intel_add_validate_buffer2(bo, 0);
1615 execbuf.buffers_ptr = (uintptr_t)bufmgr_gem->exec2_objects;
1616 execbuf.buffer_count = bufmgr_gem->exec_count;
1617 execbuf.batch_start_offset = 0;
1618 execbuf.batch_len = used;
1619 execbuf.cliprects_ptr = (uintptr_t)cliprects;
1620 execbuf.num_cliprects = num_cliprects;
1623 execbuf.flags = flags;
1627 ret = drmIoctl(bufmgr_gem->fd,
1628 DRM_IOCTL_I915_GEM_EXECBUFFER2,
1632 if (ret == -ENOSPC) {
1633 DBG("Execbuffer fails to pin. "
1634 "Estimate: %u. Actual: %u. Available: %u\n",
1635 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
1636 bufmgr_gem->exec_count),
1637 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
1638 bufmgr_gem->exec_count),
1639 (unsigned int) bufmgr_gem->gtt_size);
1642 drm_intel_update_buffer_offsets2(bufmgr_gem);
1644 if (bufmgr_gem->bufmgr.debug)
1645 drm_intel_gem_dump_validation_list(bufmgr_gem);
1647 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1648 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1649 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1651 /* Disconnect the buffer from the validate list */
1652 bo_gem->validate_index = -1;
1653 bufmgr_gem->exec_bos[i] = NULL;
1655 bufmgr_gem->exec_count = 0;
1656 pthread_mutex_unlock(&bufmgr_gem->lock);
1662 drm_intel_gem_bo_exec2(drm_intel_bo *bo, int used,
1663 drm_clip_rect_t *cliprects, int num_cliprects,
1666 return drm_intel_gem_bo_mrb_exec2(bo, used,
1667 cliprects, num_cliprects, DR4,
1672 drm_intel_gem_bo_pin(drm_intel_bo *bo, uint32_t alignment)
1674 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1675 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1676 struct drm_i915_gem_pin pin;
1679 memset(&pin, 0, sizeof(pin));
1680 pin.handle = bo_gem->gem_handle;
1681 pin.alignment = alignment;
1683 ret = drmIoctl(bufmgr_gem->fd,
1684 DRM_IOCTL_I915_GEM_PIN,
1689 bo->offset = pin.offset;
1694 drm_intel_gem_bo_unpin(drm_intel_bo *bo)
1696 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1697 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1698 struct drm_i915_gem_unpin unpin;
1701 memset(&unpin, 0, sizeof(unpin));
1702 unpin.handle = bo_gem->gem_handle;
1704 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_UNPIN, &unpin);
1712 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
1713 uint32_t tiling_mode,
1716 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1717 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1718 struct drm_i915_gem_set_tiling set_tiling;
1721 if (bo_gem->global_name == 0 &&
1722 tiling_mode == bo_gem->tiling_mode &&
1723 stride == bo_gem->stride)
1726 memset(&set_tiling, 0, sizeof(set_tiling));
1728 /* set_tiling is slightly broken and overwrites the
1729 * input on the error path, so we have to open code
1732 set_tiling.handle = bo_gem->gem_handle;
1733 set_tiling.tiling_mode = tiling_mode;
1734 set_tiling.stride = stride;
1736 ret = ioctl(bufmgr_gem->fd,
1737 DRM_IOCTL_I915_GEM_SET_TILING,
1739 } while (ret == -1 && (errno == EINTR || errno == EAGAIN));
1743 bo_gem->tiling_mode = set_tiling.tiling_mode;
1744 bo_gem->swizzle_mode = set_tiling.swizzle_mode;
1745 bo_gem->stride = set_tiling.stride;
1750 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1753 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1754 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1757 /* Linear buffers have no stride. By ensuring that we only ever use
1758 * stride 0 with linear buffers, we simplify our code.
1760 if (*tiling_mode == I915_TILING_NONE)
1763 ret = drm_intel_gem_bo_set_tiling_internal(bo, *tiling_mode, stride);
1765 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
1767 *tiling_mode = bo_gem->tiling_mode;
1772 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1773 uint32_t * swizzle_mode)
1775 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1777 *tiling_mode = bo_gem->tiling_mode;
1778 *swizzle_mode = bo_gem->swizzle_mode;
1783 drm_intel_gem_bo_flink(drm_intel_bo *bo, uint32_t * name)
1785 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1786 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1787 struct drm_gem_flink flink;
1790 if (!bo_gem->global_name) {
1791 memset(&flink, 0, sizeof(flink));
1792 flink.handle = bo_gem->gem_handle;
1794 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_FLINK, &flink);
1797 bo_gem->global_name = flink.name;
1798 bo_gem->reusable = 0;
1800 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
1803 *name = bo_gem->global_name;
1808 * Enables unlimited caching of buffer objects for reuse.
1810 * This is potentially very memory expensive, as the cache at each bucket
1811 * size is only bounded by how many buffers of that size we've managed to have
1812 * in flight at once.
1815 drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr)
1817 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1819 bufmgr_gem->bo_reuse = 1;
1823 * Enable use of fenced reloc type.
1825 * New code should enable this to avoid unnecessary fence register
1826 * allocation. If this option is not enabled, all relocs will have fence
1827 * register allocated.
1830 drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr)
1832 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
1834 if (bufmgr_gem->bufmgr.bo_exec == drm_intel_gem_bo_exec2)
1835 bufmgr_gem->fenced_relocs = 1;
1839 * Return the additional aperture space required by the tree of buffer objects
1843 drm_intel_gem_bo_get_aperture_space(drm_intel_bo *bo)
1845 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1849 if (bo == NULL || bo_gem->included_in_check_aperture)
1853 bo_gem->included_in_check_aperture = 1;
1855 for (i = 0; i < bo_gem->reloc_count; i++)
1857 drm_intel_gem_bo_get_aperture_space(bo_gem->
1858 reloc_target_info[i].bo);
1864 * Count the number of buffers in this list that need a fence reg
1866 * If the count is greater than the number of available regs, we'll have
1867 * to ask the caller to resubmit a batch with fewer tiled buffers.
1869 * This function over-counts if the same buffer is used multiple times.
1872 drm_intel_gem_total_fences(drm_intel_bo ** bo_array, int count)
1875 unsigned int total = 0;
1877 for (i = 0; i < count; i++) {
1878 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
1883 total += bo_gem->reloc_tree_fences;
1889 * Clear the flag set by drm_intel_gem_bo_get_aperture_space() so we're ready
1890 * for the next drm_intel_bufmgr_check_aperture_space() call.
1893 drm_intel_gem_bo_clear_aperture_space_flag(drm_intel_bo *bo)
1895 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1898 if (bo == NULL || !bo_gem->included_in_check_aperture)
1901 bo_gem->included_in_check_aperture = 0;
1903 for (i = 0; i < bo_gem->reloc_count; i++)
1904 drm_intel_gem_bo_clear_aperture_space_flag(bo_gem->
1905 reloc_target_info[i].bo);
1909 * Return a conservative estimate for the amount of aperture required
1910 * for a collection of buffers. This may double-count some buffers.
1913 drm_intel_gem_estimate_batch_space(drm_intel_bo **bo_array, int count)
1916 unsigned int total = 0;
1918 for (i = 0; i < count; i++) {
1919 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
1921 total += bo_gem->reloc_tree_size;
1927 * Return the amount of aperture needed for a collection of buffers.
1928 * This avoids double counting any buffers, at the cost of looking
1929 * at every buffer in the set.
1932 drm_intel_gem_compute_batch_space(drm_intel_bo **bo_array, int count)
1935 unsigned int total = 0;
1937 for (i = 0; i < count; i++) {
1938 total += drm_intel_gem_bo_get_aperture_space(bo_array[i]);
1939 /* For the first buffer object in the array, we get an
1940 * accurate count back for its reloc_tree size (since nothing
1941 * had been flagged as being counted yet). We can save that
1942 * value out as a more conservative reloc_tree_size that
1943 * avoids double-counting target buffers. Since the first
1944 * buffer happens to usually be the batch buffer in our
1945 * callers, this can pull us back from doing the tree
1946 * walk on every new batch emit.
1949 drm_intel_bo_gem *bo_gem =
1950 (drm_intel_bo_gem *) bo_array[i];
1951 bo_gem->reloc_tree_size = total;
1955 for (i = 0; i < count; i++)
1956 drm_intel_gem_bo_clear_aperture_space_flag(bo_array[i]);
1961 * Return -1 if the batchbuffer should be flushed before attempting to
1962 * emit rendering referencing the buffers pointed to by bo_array.
1964 * This is required because if we try to emit a batchbuffer with relocations
1965 * to a tree of buffers that won't simultaneously fit in the aperture,
1966 * the rendering will return an error at a point where the software is not
1967 * prepared to recover from it.
1969 * However, we also want to emit the batchbuffer significantly before we reach
1970 * the limit, as a series of batchbuffers each of which references buffers
1971 * covering almost all of the aperture means that at each emit we end up
1972 * waiting to evict a buffer from the last rendering, and we get synchronous
1973 * performance. By emitting smaller batchbuffers, we eat some CPU overhead to
1974 * get better parallelism.
1977 drm_intel_gem_check_aperture_space(drm_intel_bo **bo_array, int count)
1979 drm_intel_bufmgr_gem *bufmgr_gem =
1980 (drm_intel_bufmgr_gem *) bo_array[0]->bufmgr;
1981 unsigned int total = 0;
1982 unsigned int threshold = bufmgr_gem->gtt_size * 3 / 4;
1985 /* Check for fence reg constraints if necessary */
1986 if (bufmgr_gem->available_fences) {
1987 total_fences = drm_intel_gem_total_fences(bo_array, count);
1988 if (total_fences > bufmgr_gem->available_fences)
1992 total = drm_intel_gem_estimate_batch_space(bo_array, count);
1994 if (total > threshold)
1995 total = drm_intel_gem_compute_batch_space(bo_array, count);
1997 if (total > threshold) {
1998 DBG("check_space: overflowed available aperture, "
2000 total / 1024, (int)bufmgr_gem->gtt_size / 1024);
2003 DBG("drm_check_space: total %dkb vs bufgr %dkb\n", total / 1024,
2004 (int)bufmgr_gem->gtt_size / 1024);
2010 * Disable buffer reuse for objects which are shared with the kernel
2011 * as scanout buffers
2014 drm_intel_gem_bo_disable_reuse(drm_intel_bo *bo)
2016 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2018 bo_gem->reusable = 0;
2023 drm_intel_gem_bo_is_reusable(drm_intel_bo *bo)
2025 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2027 return bo_gem->reusable;
2031 _drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
2033 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2036 for (i = 0; i < bo_gem->reloc_count; i++) {
2037 if (bo_gem->reloc_target_info[i].bo == target_bo)
2039 if (bo == bo_gem->reloc_target_info[i].bo)
2041 if (_drm_intel_gem_bo_references(bo_gem->reloc_target_info[i].bo,
2049 /** Return true if target_bo is referenced by bo's relocation tree. */
2051 drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
2053 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
2055 if (bo == NULL || target_bo == NULL)
2057 if (target_bo_gem->used_as_reloc_target)
2058 return _drm_intel_gem_bo_references(bo, target_bo);
2063 add_bucket(drm_intel_bufmgr_gem *bufmgr_gem, int size)
2065 unsigned int i = bufmgr_gem->num_buckets;
2067 assert(i < ARRAY_SIZE(bufmgr_gem->cache_bucket));
2069 DRMINITLISTHEAD(&bufmgr_gem->cache_bucket[i].head);
2070 bufmgr_gem->cache_bucket[i].size = size;
2071 bufmgr_gem->num_buckets++;
2075 init_cache_buckets(drm_intel_bufmgr_gem *bufmgr_gem)
2077 unsigned long size, cache_max_size = 64 * 1024 * 1024;
2079 /* OK, so power of two buckets was too wasteful of memory.
2080 * Give 3 other sizes between each power of two, to hopefully
2081 * cover things accurately enough. (The alternative is
2082 * probably to just go for exact matching of sizes, and assume
2083 * that for things like composited window resize the tiled
2084 * width/height alignment and rounding of sizes to pages will
2085 * get us useful cache hit rates anyway)
2087 add_bucket(bufmgr_gem, 4096);
2088 add_bucket(bufmgr_gem, 4096 * 2);
2089 add_bucket(bufmgr_gem, 4096 * 3);
2091 /* Initialize the linked lists for BO reuse cache. */
2092 for (size = 4 * 4096; size <= cache_max_size; size *= 2) {
2093 add_bucket(bufmgr_gem, size);
2095 add_bucket(bufmgr_gem, size + size * 1 / 4);
2096 add_bucket(bufmgr_gem, size + size * 2 / 4);
2097 add_bucket(bufmgr_gem, size + size * 3 / 4);
2102 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
2103 * and manage map buffer objections.
2105 * \param fd File descriptor of the opened DRM device.
2108 drm_intel_bufmgr_gem_init(int fd, int batch_size)
2110 drm_intel_bufmgr_gem *bufmgr_gem;
2111 struct drm_i915_gem_get_aperture aperture;
2112 drm_i915_getparam_t gp;
2116 bufmgr_gem = calloc(1, sizeof(*bufmgr_gem));
2117 if (bufmgr_gem == NULL)
2120 bufmgr_gem->fd = fd;
2122 if (pthread_mutex_init(&bufmgr_gem->lock, NULL) != 0) {
2127 ret = drmIoctl(bufmgr_gem->fd,
2128 DRM_IOCTL_I915_GEM_GET_APERTURE,
2132 bufmgr_gem->gtt_size = aperture.aper_available_size;
2134 fprintf(stderr, "DRM_IOCTL_I915_GEM_APERTURE failed: %s\n",
2136 bufmgr_gem->gtt_size = 128 * 1024 * 1024;
2137 fprintf(stderr, "Assuming %dkB available aperture size.\n"
2138 "May lead to reduced performance or incorrect "
2140 (int)bufmgr_gem->gtt_size / 1024);
2143 gp.param = I915_PARAM_CHIPSET_ID;
2144 gp.value = &bufmgr_gem->pci_device;
2145 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2147 fprintf(stderr, "get chip id failed: %d [%d]\n", ret, errno);
2148 fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value);
2151 if (IS_GEN2(bufmgr_gem))
2152 bufmgr_gem->gen = 2;
2153 else if (IS_GEN3(bufmgr_gem))
2154 bufmgr_gem->gen = 3;
2155 else if (IS_GEN4(bufmgr_gem))
2156 bufmgr_gem->gen = 4;
2158 bufmgr_gem->gen = 6;
2160 gp.param = I915_PARAM_HAS_EXECBUF2;
2161 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2165 gp.param = I915_PARAM_HAS_BSD;
2166 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2167 bufmgr_gem->has_bsd = ret == 0;
2169 gp.param = I915_PARAM_HAS_BLT;
2170 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2171 bufmgr_gem->has_blt = ret == 0;
2173 gp.param = I915_PARAM_HAS_RELAXED_FENCING;
2174 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2175 bufmgr_gem->has_relaxed_fencing = ret == 0;
2177 if (bufmgr_gem->gen < 4) {
2178 gp.param = I915_PARAM_NUM_FENCES_AVAIL;
2179 gp.value = &bufmgr_gem->available_fences;
2180 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2182 fprintf(stderr, "get fences failed: %d [%d]\n", ret,
2184 fprintf(stderr, "param: %d, val: %d\n", gp.param,
2186 bufmgr_gem->available_fences = 0;
2188 /* XXX The kernel reports the total number of fences,
2189 * including any that may be pinned.
2191 * We presume that there will be at least one pinned
2192 * fence for the scanout buffer, but there may be more
2193 * than one scanout and the user may be manually
2194 * pinning buffers. Let's move to execbuffer2 and
2195 * thereby forget the insanity of using fences...
2197 bufmgr_gem->available_fences -= 2;
2198 if (bufmgr_gem->available_fences < 0)
2199 bufmgr_gem->available_fences = 0;
2203 /* Let's go with one relocation per every 2 dwords (but round down a bit
2204 * since a power of two will mean an extra page allocation for the reloc
2207 * Every 4 was too few for the blender benchmark.
2209 bufmgr_gem->max_relocs = batch_size / sizeof(uint32_t) / 2 - 2;
2211 bufmgr_gem->bufmgr.bo_alloc = drm_intel_gem_bo_alloc;
2212 bufmgr_gem->bufmgr.bo_alloc_for_render =
2213 drm_intel_gem_bo_alloc_for_render;
2214 bufmgr_gem->bufmgr.bo_alloc_tiled = drm_intel_gem_bo_alloc_tiled;
2215 bufmgr_gem->bufmgr.bo_reference = drm_intel_gem_bo_reference;
2216 bufmgr_gem->bufmgr.bo_unreference = drm_intel_gem_bo_unreference;
2217 bufmgr_gem->bufmgr.bo_map = drm_intel_gem_bo_map;
2218 bufmgr_gem->bufmgr.bo_unmap = drm_intel_gem_bo_unmap;
2219 bufmgr_gem->bufmgr.bo_subdata = drm_intel_gem_bo_subdata;
2220 bufmgr_gem->bufmgr.bo_get_subdata = drm_intel_gem_bo_get_subdata;
2221 bufmgr_gem->bufmgr.bo_wait_rendering = drm_intel_gem_bo_wait_rendering;
2222 bufmgr_gem->bufmgr.bo_emit_reloc = drm_intel_gem_bo_emit_reloc;
2223 bufmgr_gem->bufmgr.bo_emit_reloc_fence = drm_intel_gem_bo_emit_reloc_fence;
2224 bufmgr_gem->bufmgr.bo_pin = drm_intel_gem_bo_pin;
2225 bufmgr_gem->bufmgr.bo_unpin = drm_intel_gem_bo_unpin;
2226 bufmgr_gem->bufmgr.bo_get_tiling = drm_intel_gem_bo_get_tiling;
2227 bufmgr_gem->bufmgr.bo_set_tiling = drm_intel_gem_bo_set_tiling;
2228 bufmgr_gem->bufmgr.bo_flink = drm_intel_gem_bo_flink;
2229 /* Use the new one if available */
2231 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec2;
2232 bufmgr_gem->bufmgr.bo_mrb_exec = drm_intel_gem_bo_mrb_exec2;
2234 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec;
2235 bufmgr_gem->bufmgr.bo_busy = drm_intel_gem_bo_busy;
2236 bufmgr_gem->bufmgr.bo_madvise = drm_intel_gem_bo_madvise;
2237 bufmgr_gem->bufmgr.destroy = drm_intel_bufmgr_gem_destroy;
2238 bufmgr_gem->bufmgr.debug = 0;
2239 bufmgr_gem->bufmgr.check_aperture_space =
2240 drm_intel_gem_check_aperture_space;
2241 bufmgr_gem->bufmgr.bo_disable_reuse = drm_intel_gem_bo_disable_reuse;
2242 bufmgr_gem->bufmgr.bo_is_reusable = drm_intel_gem_bo_is_reusable;
2243 bufmgr_gem->bufmgr.get_pipe_from_crtc_id =
2244 drm_intel_gem_get_pipe_from_crtc_id;
2245 bufmgr_gem->bufmgr.bo_references = drm_intel_gem_bo_references;
2247 DRMINITLISTHEAD(&bufmgr_gem->named);
2248 init_cache_buckets(bufmgr_gem);
2250 return &bufmgr_gem->bufmgr;