1 /**************************************************************************
3 * Copyright © 2007 Red Hat Inc.
4 * Copyright © 2007-2012 Intel Corporation
5 * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
29 **************************************************************************/
31 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
32 * Keith Whitwell <keithw-at-tungstengraphics-dot-com>
33 * Eric Anholt <eric@anholt.net>
34 * Dave Airlie <airlied@linux.ie>
42 #include <xf86atomic.h>
50 #include <sys/ioctl.h>
52 #include <sys/types.h>
57 #define ETIME ETIMEDOUT
59 #include "libdrm_macros.h"
60 #include "libdrm_lists.h"
61 #include "intel_bufmgr.h"
62 #include "intel_bufmgr_priv.h"
63 #include "intel_chipset.h"
76 #define memclear(s) memset(&s, 0, sizeof(s))
78 #define DBG(...) do { \
79 if (bufmgr_gem->bufmgr.debug) \
80 fprintf(stderr, __VA_ARGS__); \
83 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
84 #define MAX2(A, B) ((A) > (B) ? (A) : (B))
86 typedef struct _drm_intel_bo_gem drm_intel_bo_gem;
88 struct drm_intel_gem_bo_bucket {
93 typedef struct _drm_intel_bufmgr_gem {
94 drm_intel_bufmgr bufmgr;
102 pthread_mutex_t lock;
104 struct drm_i915_gem_exec_object *exec_objects;
105 struct drm_i915_gem_exec_object2 *exec2_objects;
106 drm_intel_bo **exec_bos;
110 /** Array of lists of cached gem objects of power-of-two sizes */
111 struct drm_intel_gem_bo_bucket cache_bucket[14 * 4];
115 drmMMListHead managers;
118 drmMMListHead vma_cache;
119 int vma_count, vma_open, vma_max;
122 int available_fences;
125 unsigned int has_bsd : 1;
126 unsigned int has_blt : 1;
127 unsigned int has_relaxed_fencing : 1;
128 unsigned int has_llc : 1;
129 unsigned int has_wait_timeout : 1;
130 unsigned int bo_reuse : 1;
131 unsigned int no_exec : 1;
132 unsigned int has_vebox : 1;
140 } drm_intel_bufmgr_gem;
142 #define DRM_INTEL_RELOC_FENCE (1<<0)
144 typedef struct _drm_intel_reloc_target_info {
147 } drm_intel_reloc_target;
149 struct _drm_intel_bo_gem {
157 * Kenel-assigned global name for this object
159 * List contains both flink named and prime fd'd objects
161 unsigned int global_name;
162 drmMMListHead name_list;
165 * Index of the buffer within the validation list while preparing a
166 * batchbuffer execution.
171 * Current tiling mode
173 uint32_t tiling_mode;
174 uint32_t swizzle_mode;
175 unsigned long stride;
179 /** Array passed to the DRM containing relocation information. */
180 struct drm_i915_gem_relocation_entry *relocs;
182 * Array of info structs corresponding to relocs[i].target_handle etc
184 drm_intel_reloc_target *reloc_target_info;
185 /** Number of entries in relocs */
187 /** Mapped address for the buffer, saved across map/unmap cycles */
189 /** GTT virtual address for the buffer, saved across map/unmap cycles */
192 * Virtual address of the buffer allocated by user, used for userptr
197 drmMMListHead vma_list;
203 * Boolean of whether this BO and its children have been included in
204 * the current drm_intel_bufmgr_check_aperture_space() total.
206 bool included_in_check_aperture;
209 * Boolean of whether this buffer has been used as a relocation
210 * target and had its size accounted for, and thus can't have any
211 * further relocations added to it.
213 bool used_as_reloc_target;
216 * Boolean of whether we have encountered an error whilst building the relocation tree.
221 * Boolean of whether this buffer can be re-used
226 * Boolean of whether the GPU is definitely not accessing the buffer.
228 * This is only valid when reusable, since non-reusable
229 * buffers are those that have been shared wth other
230 * processes, so we don't know their state.
235 * Boolean of whether this buffer was allocated with userptr
240 * Size in bytes of this buffer and its relocation descendents.
242 * Used to avoid costly tree walking in
243 * drm_intel_bufmgr_check_aperture in the common case.
248 * Number of potential fence registers required by this buffer and its
251 int reloc_tree_fences;
253 /** Flags that we may need to do the SW_FINSIH ioctl on unmap. */
254 bool mapped_cpu_write;
258 drm_intel_gem_estimate_batch_space(drm_intel_bo ** bo_array, int count);
261 drm_intel_gem_compute_batch_space(drm_intel_bo ** bo_array, int count);
264 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
265 uint32_t * swizzle_mode);
268 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
269 uint32_t tiling_mode,
272 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
275 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo);
277 static void drm_intel_gem_bo_free(drm_intel_bo *bo);
279 static inline drm_intel_bo_gem *to_bo_gem(drm_intel_bo *bo)
281 return (drm_intel_bo_gem *)bo;
285 drm_intel_gem_bo_tile_size(drm_intel_bufmgr_gem *bufmgr_gem, unsigned long size,
286 uint32_t *tiling_mode)
288 unsigned long min_size, max_size;
291 if (*tiling_mode == I915_TILING_NONE)
294 /* 965+ just need multiples of page size for tiling */
295 if (bufmgr_gem->gen >= 4)
296 return ROUND_UP_TO(size, 4096);
298 /* Older chips need powers of two, of at least 512k or 1M */
299 if (bufmgr_gem->gen == 3) {
300 min_size = 1024*1024;
301 max_size = 128*1024*1024;
304 max_size = 64*1024*1024;
307 if (size > max_size) {
308 *tiling_mode = I915_TILING_NONE;
312 /* Do we need to allocate every page for the fence? */
313 if (bufmgr_gem->has_relaxed_fencing)
314 return ROUND_UP_TO(size, 4096);
316 for (i = min_size; i < size; i <<= 1)
323 * Round a given pitch up to the minimum required for X tiling on a
324 * given chip. We use 512 as the minimum to allow for a later tiling
328 drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem,
329 unsigned long pitch, uint32_t *tiling_mode)
331 unsigned long tile_width;
334 /* If untiled, then just align it so that we can do rendering
335 * to it with the 3D engine.
337 if (*tiling_mode == I915_TILING_NONE)
338 return ALIGN(pitch, 64);
340 if (*tiling_mode == I915_TILING_X
341 || (IS_915(bufmgr_gem->pci_device)
342 && *tiling_mode == I915_TILING_Y))
347 /* 965 is flexible */
348 if (bufmgr_gem->gen >= 4)
349 return ROUND_UP_TO(pitch, tile_width);
351 /* The older hardware has a maximum pitch of 8192 with tiled
352 * surfaces, so fallback to untiled if it's too large.
355 *tiling_mode = I915_TILING_NONE;
356 return ALIGN(pitch, 64);
359 /* Pre-965 needs power of two tile width */
360 for (i = tile_width; i < pitch; i <<= 1)
366 static struct drm_intel_gem_bo_bucket *
367 drm_intel_gem_bo_bucket_for_size(drm_intel_bufmgr_gem *bufmgr_gem,
372 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
373 struct drm_intel_gem_bo_bucket *bucket =
374 &bufmgr_gem->cache_bucket[i];
375 if (bucket->size >= size) {
384 drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem *bufmgr_gem)
388 for (i = 0; i < bufmgr_gem->exec_count; i++) {
389 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
390 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
392 if (bo_gem->relocs == NULL) {
393 DBG("%2d: %d (%s)\n", i, bo_gem->gem_handle,
398 for (j = 0; j < bo_gem->reloc_count; j++) {
399 drm_intel_bo *target_bo = bo_gem->reloc_target_info[j].bo;
400 drm_intel_bo_gem *target_gem =
401 (drm_intel_bo_gem *) target_bo;
403 DBG("%2d: %d (%s)@0x%08llx -> "
404 "%d (%s)@0x%08lx + 0x%08x\n",
406 bo_gem->gem_handle, bo_gem->name,
407 (unsigned long long)bo_gem->relocs[j].offset,
408 target_gem->gem_handle,
411 bo_gem->relocs[j].delta);
417 drm_intel_gem_bo_reference(drm_intel_bo *bo)
419 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
421 atomic_inc(&bo_gem->refcount);
425 * Adds the given buffer to the list of buffers to be validated (moved into the
426 * appropriate memory type) with the next batch submission.
428 * If a buffer is validated multiple times in a batch submission, it ends up
429 * with the intersection of the memory type flags and the union of the
433 drm_intel_add_validate_buffer(drm_intel_bo *bo)
435 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
436 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
439 if (bo_gem->validate_index != -1)
442 /* Extend the array of validation entries as necessary. */
443 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
444 int new_size = bufmgr_gem->exec_size * 2;
449 bufmgr_gem->exec_objects =
450 realloc(bufmgr_gem->exec_objects,
451 sizeof(*bufmgr_gem->exec_objects) * new_size);
452 bufmgr_gem->exec_bos =
453 realloc(bufmgr_gem->exec_bos,
454 sizeof(*bufmgr_gem->exec_bos) * new_size);
455 bufmgr_gem->exec_size = new_size;
458 index = bufmgr_gem->exec_count;
459 bo_gem->validate_index = index;
460 /* Fill in array entry */
461 bufmgr_gem->exec_objects[index].handle = bo_gem->gem_handle;
462 bufmgr_gem->exec_objects[index].relocation_count = bo_gem->reloc_count;
463 bufmgr_gem->exec_objects[index].relocs_ptr = (uintptr_t) bo_gem->relocs;
464 bufmgr_gem->exec_objects[index].alignment = bo->align;
465 bufmgr_gem->exec_objects[index].offset = 0;
466 bufmgr_gem->exec_bos[index] = bo;
467 bufmgr_gem->exec_count++;
471 drm_intel_add_validate_buffer2(drm_intel_bo *bo, int need_fence)
473 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
474 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
477 if (bo_gem->validate_index != -1) {
479 bufmgr_gem->exec2_objects[bo_gem->validate_index].flags |=
480 EXEC_OBJECT_NEEDS_FENCE;
484 /* Extend the array of validation entries as necessary. */
485 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
486 int new_size = bufmgr_gem->exec_size * 2;
491 bufmgr_gem->exec2_objects =
492 realloc(bufmgr_gem->exec2_objects,
493 sizeof(*bufmgr_gem->exec2_objects) * new_size);
494 bufmgr_gem->exec_bos =
495 realloc(bufmgr_gem->exec_bos,
496 sizeof(*bufmgr_gem->exec_bos) * new_size);
497 bufmgr_gem->exec_size = new_size;
500 index = bufmgr_gem->exec_count;
501 bo_gem->validate_index = index;
502 /* Fill in array entry */
503 bufmgr_gem->exec2_objects[index].handle = bo_gem->gem_handle;
504 bufmgr_gem->exec2_objects[index].relocation_count = bo_gem->reloc_count;
505 bufmgr_gem->exec2_objects[index].relocs_ptr = (uintptr_t)bo_gem->relocs;
506 bufmgr_gem->exec2_objects[index].alignment = bo->align;
507 bufmgr_gem->exec2_objects[index].offset = 0;
508 bufmgr_gem->exec_bos[index] = bo;
509 bufmgr_gem->exec2_objects[index].flags = 0;
510 bufmgr_gem->exec2_objects[index].rsvd1 = 0;
511 bufmgr_gem->exec2_objects[index].rsvd2 = 0;
513 bufmgr_gem->exec2_objects[index].flags |=
514 EXEC_OBJECT_NEEDS_FENCE;
516 bufmgr_gem->exec_count++;
519 #define RELOC_BUF_SIZE(x) ((I915_RELOC_HEADER + x * I915_RELOC0_STRIDE) * \
523 drm_intel_bo_gem_set_in_aperture_size(drm_intel_bufmgr_gem *bufmgr_gem,
524 drm_intel_bo_gem *bo_gem,
525 unsigned int alignment)
529 assert(!bo_gem->used_as_reloc_target);
531 /* The older chipsets are far-less flexible in terms of tiling,
532 * and require tiled buffer to be size aligned in the aperture.
533 * This means that in the worst possible case we will need a hole
534 * twice as large as the object in order for it to fit into the
535 * aperture. Optimal packing is for wimps.
537 size = bo_gem->bo.size;
538 if (bufmgr_gem->gen < 4 && bo_gem->tiling_mode != I915_TILING_NONE) {
539 unsigned int min_size;
541 if (bufmgr_gem->has_relaxed_fencing) {
542 if (bufmgr_gem->gen == 3)
543 min_size = 1024*1024;
547 while (min_size < size)
552 /* Account for worst-case alignment. */
553 alignment = MAX2(alignment, min_size);
556 bo_gem->reloc_tree_size = size + alignment;
560 drm_intel_setup_reloc_list(drm_intel_bo *bo)
562 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
563 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
564 unsigned int max_relocs = bufmgr_gem->max_relocs;
566 if (bo->size / 4 < max_relocs)
567 max_relocs = bo->size / 4;
569 bo_gem->relocs = malloc(max_relocs *
570 sizeof(struct drm_i915_gem_relocation_entry));
571 bo_gem->reloc_target_info = malloc(max_relocs *
572 sizeof(drm_intel_reloc_target));
573 if (bo_gem->relocs == NULL || bo_gem->reloc_target_info == NULL) {
574 bo_gem->has_error = true;
576 free (bo_gem->relocs);
577 bo_gem->relocs = NULL;
579 free (bo_gem->reloc_target_info);
580 bo_gem->reloc_target_info = NULL;
589 drm_intel_gem_bo_busy(drm_intel_bo *bo)
591 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
592 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
593 struct drm_i915_gem_busy busy;
596 if (bo_gem->reusable && bo_gem->idle)
600 busy.handle = bo_gem->gem_handle;
602 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_BUSY, &busy);
604 bo_gem->idle = !busy.busy;
609 return (ret == 0 && busy.busy);
613 drm_intel_gem_bo_madvise_internal(drm_intel_bufmgr_gem *bufmgr_gem,
614 drm_intel_bo_gem *bo_gem, int state)
616 struct drm_i915_gem_madvise madv;
619 madv.handle = bo_gem->gem_handle;
622 drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MADVISE, &madv);
624 return madv.retained;
628 drm_intel_gem_bo_madvise(drm_intel_bo *bo, int madv)
630 return drm_intel_gem_bo_madvise_internal
631 ((drm_intel_bufmgr_gem *) bo->bufmgr,
632 (drm_intel_bo_gem *) bo,
636 /* drop the oldest entries that have been purged by the kernel */
638 drm_intel_gem_bo_cache_purge_bucket(drm_intel_bufmgr_gem *bufmgr_gem,
639 struct drm_intel_gem_bo_bucket *bucket)
641 while (!DRMLISTEMPTY(&bucket->head)) {
642 drm_intel_bo_gem *bo_gem;
644 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
645 bucket->head.next, head);
646 if (drm_intel_gem_bo_madvise_internal
647 (bufmgr_gem, bo_gem, I915_MADV_DONTNEED))
650 DRMLISTDEL(&bo_gem->head);
651 drm_intel_gem_bo_free(&bo_gem->bo);
655 static drm_intel_bo *
656 drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr,
660 uint32_t tiling_mode,
661 unsigned long stride,
662 unsigned int alignment)
664 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
665 drm_intel_bo_gem *bo_gem;
666 unsigned int page_size = getpagesize();
668 struct drm_intel_gem_bo_bucket *bucket;
669 bool alloc_from_cache;
670 unsigned long bo_size;
671 bool for_render = false;
673 if (flags & BO_ALLOC_FOR_RENDER)
676 /* Round the allocated size up to a power of two number of pages. */
677 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, size);
679 /* If we don't have caching at this size, don't actually round the
682 if (bucket == NULL) {
684 if (bo_size < page_size)
687 bo_size = bucket->size;
690 pthread_mutex_lock(&bufmgr_gem->lock);
691 /* Get a buffer out of the cache if available */
693 alloc_from_cache = false;
694 if (bucket != NULL && !DRMLISTEMPTY(&bucket->head)) {
696 /* Allocate new render-target BOs from the tail (MRU)
697 * of the list, as it will likely be hot in the GPU
698 * cache and in the aperture for us.
700 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
701 bucket->head.prev, head);
702 DRMLISTDEL(&bo_gem->head);
703 alloc_from_cache = true;
704 bo_gem->bo.align = alignment;
706 assert(alignment == 0);
707 /* For non-render-target BOs (where we're probably
708 * going to map it first thing in order to fill it
709 * with data), check if the last BO in the cache is
710 * unbusy, and only reuse in that case. Otherwise,
711 * allocating a new buffer is probably faster than
712 * waiting for the GPU to finish.
714 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
715 bucket->head.next, head);
716 if (!drm_intel_gem_bo_busy(&bo_gem->bo)) {
717 alloc_from_cache = true;
718 DRMLISTDEL(&bo_gem->head);
722 if (alloc_from_cache) {
723 if (!drm_intel_gem_bo_madvise_internal
724 (bufmgr_gem, bo_gem, I915_MADV_WILLNEED)) {
725 drm_intel_gem_bo_free(&bo_gem->bo);
726 drm_intel_gem_bo_cache_purge_bucket(bufmgr_gem,
731 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
734 drm_intel_gem_bo_free(&bo_gem->bo);
739 pthread_mutex_unlock(&bufmgr_gem->lock);
741 if (!alloc_from_cache) {
742 struct drm_i915_gem_create create;
744 bo_gem = calloc(1, sizeof(*bo_gem));
748 bo_gem->bo.size = bo_size;
751 create.size = bo_size;
753 ret = drmIoctl(bufmgr_gem->fd,
754 DRM_IOCTL_I915_GEM_CREATE,
756 bo_gem->gem_handle = create.handle;
757 bo_gem->bo.handle = bo_gem->gem_handle;
762 bo_gem->bo.bufmgr = bufmgr;
763 bo_gem->bo.align = alignment;
765 bo_gem->tiling_mode = I915_TILING_NONE;
766 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
769 /* drm_intel_gem_bo_free calls DRMLISTDEL() for an uninitialized
770 list (vma_list), so better set the list head here */
771 DRMINITLISTHEAD(&bo_gem->name_list);
772 DRMINITLISTHEAD(&bo_gem->vma_list);
773 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
776 drm_intel_gem_bo_free(&bo_gem->bo);
782 atomic_set(&bo_gem->refcount, 1);
783 bo_gem->validate_index = -1;
784 bo_gem->reloc_tree_fences = 0;
785 bo_gem->used_as_reloc_target = false;
786 bo_gem->has_error = false;
787 bo_gem->reusable = true;
789 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem, alignment);
791 DBG("bo_create: buf %d (%s) %ldb\n",
792 bo_gem->gem_handle, bo_gem->name, size);
797 static drm_intel_bo *
798 drm_intel_gem_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
801 unsigned int alignment)
803 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size,
809 static drm_intel_bo *
810 drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr,
813 unsigned int alignment)
815 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, 0,
816 I915_TILING_NONE, 0, 0);
819 static drm_intel_bo *
820 drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
821 int x, int y, int cpp, uint32_t *tiling_mode,
822 unsigned long *pitch, unsigned long flags)
824 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
825 unsigned long size, stride;
829 unsigned long aligned_y, height_alignment;
831 tiling = *tiling_mode;
833 /* If we're tiled, our allocations are in 8 or 32-row blocks,
834 * so failure to align our height means that we won't allocate
837 * If we're untiled, we still have to align to 2 rows high
838 * because the data port accesses 2x2 blocks even if the
839 * bottom row isn't to be rendered, so failure to align means
840 * we could walk off the end of the GTT and fault. This is
841 * documented on 965, and may be the case on older chipsets
842 * too so we try to be careful.
845 height_alignment = 2;
847 if ((bufmgr_gem->gen == 2) && tiling != I915_TILING_NONE)
848 height_alignment = 16;
849 else if (tiling == I915_TILING_X
850 || (IS_915(bufmgr_gem->pci_device)
851 && tiling == I915_TILING_Y))
852 height_alignment = 8;
853 else if (tiling == I915_TILING_Y)
854 height_alignment = 32;
855 aligned_y = ALIGN(y, height_alignment);
858 stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, tiling_mode);
859 size = stride * aligned_y;
860 size = drm_intel_gem_bo_tile_size(bufmgr_gem, size, tiling_mode);
861 } while (*tiling_mode != tiling);
864 if (tiling == I915_TILING_NONE)
867 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, flags,
871 static drm_intel_bo *
872 drm_intel_gem_bo_alloc_userptr(drm_intel_bufmgr *bufmgr,
875 uint32_t tiling_mode,
880 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
881 drm_intel_bo_gem *bo_gem;
883 struct drm_i915_gem_userptr userptr;
885 /* Tiling with userptr surfaces is not supported
886 * on all hardware so refuse it for time being.
888 if (tiling_mode != I915_TILING_NONE)
891 bo_gem = calloc(1, sizeof(*bo_gem));
895 bo_gem->bo.size = size;
898 userptr.user_ptr = (__u64)((unsigned long)addr);
899 userptr.user_size = size;
900 userptr.flags = flags;
902 ret = drmIoctl(bufmgr_gem->fd,
903 DRM_IOCTL_I915_GEM_USERPTR,
906 DBG("bo_create_userptr: "
907 "ioctl failed with user ptr %p size 0x%lx, "
908 "user flags 0x%lx\n", addr, size, flags);
913 bo_gem->gem_handle = userptr.handle;
914 bo_gem->bo.handle = bo_gem->gem_handle;
915 bo_gem->bo.bufmgr = bufmgr;
916 bo_gem->is_userptr = true;
917 bo_gem->bo.virtual = addr;
918 /* Save the address provided by user */
919 bo_gem->user_virtual = addr;
920 bo_gem->tiling_mode = I915_TILING_NONE;
921 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
924 DRMINITLISTHEAD(&bo_gem->name_list);
925 DRMINITLISTHEAD(&bo_gem->vma_list);
928 atomic_set(&bo_gem->refcount, 1);
929 bo_gem->validate_index = -1;
930 bo_gem->reloc_tree_fences = 0;
931 bo_gem->used_as_reloc_target = false;
932 bo_gem->has_error = false;
933 bo_gem->reusable = false;
935 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem, 0);
937 DBG("bo_create_userptr: "
938 "ptr %p buf %d (%s) size %ldb, stride 0x%x, tile mode %d\n",
939 addr, bo_gem->gem_handle, bo_gem->name,
940 size, stride, tiling_mode);
946 has_userptr(drm_intel_bufmgr_gem *bufmgr_gem)
951 struct drm_i915_gem_userptr userptr;
953 pgsz = sysconf(_SC_PAGESIZE);
956 ret = posix_memalign(&ptr, pgsz, pgsz);
958 DBG("Failed to get a page (%ld) for userptr detection!\n",
964 userptr.user_ptr = (__u64)(unsigned long)ptr;
965 userptr.user_size = pgsz;
968 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_USERPTR, &userptr);
970 if (errno == ENODEV && userptr.flags == 0) {
971 userptr.flags = I915_USERPTR_UNSYNCHRONIZED;
978 /* We don't release the userptr bo here as we want to keep the
979 * kernel mm tracking alive for our lifetime. The first time we
980 * create a userptr object the kernel has to install a mmu_notifer
981 * which is a heavyweight operation (e.g. it requires taking all
982 * mm_locks and stop_machine()).
985 bufmgr_gem->userptr_active.ptr = ptr;
986 bufmgr_gem->userptr_active.handle = userptr.handle;
991 static drm_intel_bo *
992 check_bo_alloc_userptr(drm_intel_bufmgr *bufmgr,
995 uint32_t tiling_mode,
1000 if (has_userptr((drm_intel_bufmgr_gem *)bufmgr))
1001 bufmgr->bo_alloc_userptr = drm_intel_gem_bo_alloc_userptr;
1003 bufmgr->bo_alloc_userptr = NULL;
1005 return drm_intel_bo_alloc_userptr(bufmgr, name, addr,
1006 tiling_mode, stride, size, flags);
1010 * Returns a drm_intel_bo wrapping the given buffer object handle.
1012 * This can be used when one application needs to pass a buffer object
1016 drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
1018 unsigned int handle)
1020 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1021 drm_intel_bo_gem *bo_gem;
1023 struct drm_gem_open open_arg;
1024 struct drm_i915_gem_get_tiling get_tiling;
1025 drmMMListHead *list;
1027 /* At the moment most applications only have a few named bo.
1028 * For instance, in a DRI client only the render buffers passed
1029 * between X and the client are named. And since X returns the
1030 * alternating names for the front/back buffer a linear search
1031 * provides a sufficiently fast match.
1033 pthread_mutex_lock(&bufmgr_gem->lock);
1034 for (list = bufmgr_gem->named.next;
1035 list != &bufmgr_gem->named;
1036 list = list->next) {
1037 bo_gem = DRMLISTENTRY(drm_intel_bo_gem, list, name_list);
1038 if (bo_gem->global_name == handle) {
1039 drm_intel_gem_bo_reference(&bo_gem->bo);
1040 pthread_mutex_unlock(&bufmgr_gem->lock);
1046 open_arg.name = handle;
1047 ret = drmIoctl(bufmgr_gem->fd,
1051 DBG("Couldn't reference %s handle 0x%08x: %s\n",
1052 name, handle, strerror(errno));
1053 pthread_mutex_unlock(&bufmgr_gem->lock);
1056 /* Now see if someone has used a prime handle to get this
1057 * object from the kernel before by looking through the list
1058 * again for a matching gem_handle
1060 for (list = bufmgr_gem->named.next;
1061 list != &bufmgr_gem->named;
1062 list = list->next) {
1063 bo_gem = DRMLISTENTRY(drm_intel_bo_gem, list, name_list);
1064 if (bo_gem->gem_handle == open_arg.handle) {
1065 drm_intel_gem_bo_reference(&bo_gem->bo);
1066 pthread_mutex_unlock(&bufmgr_gem->lock);
1071 bo_gem = calloc(1, sizeof(*bo_gem));
1073 pthread_mutex_unlock(&bufmgr_gem->lock);
1077 bo_gem->bo.size = open_arg.size;
1078 bo_gem->bo.offset = 0;
1079 bo_gem->bo.offset64 = 0;
1080 bo_gem->bo.virtual = NULL;
1081 bo_gem->bo.bufmgr = bufmgr;
1082 bo_gem->name = name;
1083 atomic_set(&bo_gem->refcount, 1);
1084 bo_gem->validate_index = -1;
1085 bo_gem->gem_handle = open_arg.handle;
1086 bo_gem->bo.handle = open_arg.handle;
1087 bo_gem->global_name = handle;
1088 bo_gem->reusable = false;
1090 memclear(get_tiling);
1091 get_tiling.handle = bo_gem->gem_handle;
1092 ret = drmIoctl(bufmgr_gem->fd,
1093 DRM_IOCTL_I915_GEM_GET_TILING,
1096 drm_intel_gem_bo_unreference(&bo_gem->bo);
1097 pthread_mutex_unlock(&bufmgr_gem->lock);
1100 bo_gem->tiling_mode = get_tiling.tiling_mode;
1101 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
1102 /* XXX stride is unknown */
1103 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem, 0);
1105 DRMINITLISTHEAD(&bo_gem->vma_list);
1106 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
1107 pthread_mutex_unlock(&bufmgr_gem->lock);
1108 DBG("bo_create_from_handle: %d (%s)\n", handle, bo_gem->name);
1114 drm_intel_gem_bo_free(drm_intel_bo *bo)
1116 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1117 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1118 struct drm_gem_close close;
1121 DRMLISTDEL(&bo_gem->vma_list);
1122 if (bo_gem->mem_virtual) {
1123 VG(VALGRIND_FREELIKE_BLOCK(bo_gem->mem_virtual, 0));
1124 drm_munmap(bo_gem->mem_virtual, bo_gem->bo.size);
1125 bufmgr_gem->vma_count--;
1127 if (bo_gem->gtt_virtual) {
1128 drm_munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
1129 bufmgr_gem->vma_count--;
1132 /* Close this object */
1134 close.handle = bo_gem->gem_handle;
1135 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close);
1137 DBG("DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
1138 bo_gem->gem_handle, bo_gem->name, strerror(errno));
1144 drm_intel_gem_bo_mark_mmaps_incoherent(drm_intel_bo *bo)
1147 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1149 if (bo_gem->mem_virtual)
1150 VALGRIND_MAKE_MEM_NOACCESS(bo_gem->mem_virtual, bo->size);
1152 if (bo_gem->gtt_virtual)
1153 VALGRIND_MAKE_MEM_NOACCESS(bo_gem->gtt_virtual, bo->size);
1157 /** Frees all cached buffers significantly older than @time. */
1159 drm_intel_gem_cleanup_bo_cache(drm_intel_bufmgr_gem *bufmgr_gem, time_t time)
1163 if (bufmgr_gem->time == time)
1166 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
1167 struct drm_intel_gem_bo_bucket *bucket =
1168 &bufmgr_gem->cache_bucket[i];
1170 while (!DRMLISTEMPTY(&bucket->head)) {
1171 drm_intel_bo_gem *bo_gem;
1173 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1174 bucket->head.next, head);
1175 if (time - bo_gem->free_time <= 1)
1178 DRMLISTDEL(&bo_gem->head);
1180 drm_intel_gem_bo_free(&bo_gem->bo);
1184 bufmgr_gem->time = time;
1187 static void drm_intel_gem_bo_purge_vma_cache(drm_intel_bufmgr_gem *bufmgr_gem)
1191 DBG("%s: cached=%d, open=%d, limit=%d\n", __FUNCTION__,
1192 bufmgr_gem->vma_count, bufmgr_gem->vma_open, bufmgr_gem->vma_max);
1194 if (bufmgr_gem->vma_max < 0)
1197 /* We may need to evict a few entries in order to create new mmaps */
1198 limit = bufmgr_gem->vma_max - 2*bufmgr_gem->vma_open;
1202 while (bufmgr_gem->vma_count > limit) {
1203 drm_intel_bo_gem *bo_gem;
1205 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1206 bufmgr_gem->vma_cache.next,
1208 assert(bo_gem->map_count == 0);
1209 DRMLISTDELINIT(&bo_gem->vma_list);
1211 if (bo_gem->mem_virtual) {
1212 drm_munmap(bo_gem->mem_virtual, bo_gem->bo.size);
1213 bo_gem->mem_virtual = NULL;
1214 bufmgr_gem->vma_count--;
1216 if (bo_gem->gtt_virtual) {
1217 drm_munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
1218 bo_gem->gtt_virtual = NULL;
1219 bufmgr_gem->vma_count--;
1224 static void drm_intel_gem_bo_close_vma(drm_intel_bufmgr_gem *bufmgr_gem,
1225 drm_intel_bo_gem *bo_gem)
1227 bufmgr_gem->vma_open--;
1228 DRMLISTADDTAIL(&bo_gem->vma_list, &bufmgr_gem->vma_cache);
1229 if (bo_gem->mem_virtual)
1230 bufmgr_gem->vma_count++;
1231 if (bo_gem->gtt_virtual)
1232 bufmgr_gem->vma_count++;
1233 drm_intel_gem_bo_purge_vma_cache(bufmgr_gem);
1236 static void drm_intel_gem_bo_open_vma(drm_intel_bufmgr_gem *bufmgr_gem,
1237 drm_intel_bo_gem *bo_gem)
1239 bufmgr_gem->vma_open++;
1240 DRMLISTDEL(&bo_gem->vma_list);
1241 if (bo_gem->mem_virtual)
1242 bufmgr_gem->vma_count--;
1243 if (bo_gem->gtt_virtual)
1244 bufmgr_gem->vma_count--;
1245 drm_intel_gem_bo_purge_vma_cache(bufmgr_gem);
1249 drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time)
1251 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1252 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1253 struct drm_intel_gem_bo_bucket *bucket;
1256 /* Unreference all the target buffers */
1257 for (i = 0; i < bo_gem->reloc_count; i++) {
1258 if (bo_gem->reloc_target_info[i].bo != bo) {
1259 drm_intel_gem_bo_unreference_locked_timed(bo_gem->
1260 reloc_target_info[i].bo,
1264 bo_gem->reloc_count = 0;
1265 bo_gem->used_as_reloc_target = false;
1267 DBG("bo_unreference final: %d (%s)\n",
1268 bo_gem->gem_handle, bo_gem->name);
1270 /* release memory associated with this object */
1271 if (bo_gem->reloc_target_info) {
1272 free(bo_gem->reloc_target_info);
1273 bo_gem->reloc_target_info = NULL;
1275 if (bo_gem->relocs) {
1276 free(bo_gem->relocs);
1277 bo_gem->relocs = NULL;
1280 /* Clear any left-over mappings */
1281 if (bo_gem->map_count) {
1282 DBG("bo freed with non-zero map-count %d\n", bo_gem->map_count);
1283 bo_gem->map_count = 0;
1284 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1285 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1288 DRMLISTDEL(&bo_gem->name_list);
1290 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, bo->size);
1291 /* Put the buffer into our internal cache for reuse if we can. */
1292 if (bufmgr_gem->bo_reuse && bo_gem->reusable && bucket != NULL &&
1293 drm_intel_gem_bo_madvise_internal(bufmgr_gem, bo_gem,
1294 I915_MADV_DONTNEED)) {
1295 bo_gem->free_time = time;
1297 bo_gem->name = NULL;
1298 bo_gem->validate_index = -1;
1300 DRMLISTADDTAIL(&bo_gem->head, &bucket->head);
1302 drm_intel_gem_bo_free(bo);
1306 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
1309 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1311 assert(atomic_read(&bo_gem->refcount) > 0);
1312 if (atomic_dec_and_test(&bo_gem->refcount))
1313 drm_intel_gem_bo_unreference_final(bo, time);
1316 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo)
1318 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1320 assert(atomic_read(&bo_gem->refcount) > 0);
1322 if (atomic_add_unless(&bo_gem->refcount, -1, 1)) {
1323 drm_intel_bufmgr_gem *bufmgr_gem =
1324 (drm_intel_bufmgr_gem *) bo->bufmgr;
1325 struct timespec time;
1327 clock_gettime(CLOCK_MONOTONIC, &time);
1329 pthread_mutex_lock(&bufmgr_gem->lock);
1331 if (atomic_dec_and_test(&bo_gem->refcount)) {
1332 drm_intel_gem_bo_unreference_final(bo, time.tv_sec);
1333 drm_intel_gem_cleanup_bo_cache(bufmgr_gem, time.tv_sec);
1336 pthread_mutex_unlock(&bufmgr_gem->lock);
1340 static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable)
1342 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1343 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1344 struct drm_i915_gem_set_domain set_domain;
1347 if (bo_gem->is_userptr) {
1348 /* Return the same user ptr */
1349 bo->virtual = bo_gem->user_virtual;
1353 pthread_mutex_lock(&bufmgr_gem->lock);
1355 if (bo_gem->map_count++ == 0)
1356 drm_intel_gem_bo_open_vma(bufmgr_gem, bo_gem);
1358 if (!bo_gem->mem_virtual) {
1359 struct drm_i915_gem_mmap mmap_arg;
1361 DBG("bo_map: %d (%s), map_count=%d\n",
1362 bo_gem->gem_handle, bo_gem->name, bo_gem->map_count);
1365 mmap_arg.handle = bo_gem->gem_handle;
1366 mmap_arg.size = bo->size;
1367 ret = drmIoctl(bufmgr_gem->fd,
1368 DRM_IOCTL_I915_GEM_MMAP,
1372 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1373 __FILE__, __LINE__, bo_gem->gem_handle,
1374 bo_gem->name, strerror(errno));
1375 if (--bo_gem->map_count == 0)
1376 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1377 pthread_mutex_unlock(&bufmgr_gem->lock);
1380 VG(VALGRIND_MALLOCLIKE_BLOCK(mmap_arg.addr_ptr, mmap_arg.size, 0, 1));
1381 bo_gem->mem_virtual = (void *)(uintptr_t) mmap_arg.addr_ptr;
1383 DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1384 bo_gem->mem_virtual);
1385 bo->virtual = bo_gem->mem_virtual;
1387 memclear(set_domain);
1388 set_domain.handle = bo_gem->gem_handle;
1389 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
1391 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
1393 set_domain.write_domain = 0;
1394 ret = drmIoctl(bufmgr_gem->fd,
1395 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1398 DBG("%s:%d: Error setting to CPU domain %d: %s\n",
1399 __FILE__, __LINE__, bo_gem->gem_handle,
1404 bo_gem->mapped_cpu_write = true;
1406 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1407 VG(VALGRIND_MAKE_MEM_DEFINED(bo_gem->mem_virtual, bo->size));
1408 pthread_mutex_unlock(&bufmgr_gem->lock);
1414 map_gtt(drm_intel_bo *bo)
1416 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1417 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1420 if (bo_gem->is_userptr)
1423 if (bo_gem->map_count++ == 0)
1424 drm_intel_gem_bo_open_vma(bufmgr_gem, bo_gem);
1426 /* Get a mapping of the buffer if we haven't before. */
1427 if (bo_gem->gtt_virtual == NULL) {
1428 struct drm_i915_gem_mmap_gtt mmap_arg;
1430 DBG("bo_map_gtt: mmap %d (%s), map_count=%d\n",
1431 bo_gem->gem_handle, bo_gem->name, bo_gem->map_count);
1434 mmap_arg.handle = bo_gem->gem_handle;
1436 /* Get the fake offset back... */
1437 ret = drmIoctl(bufmgr_gem->fd,
1438 DRM_IOCTL_I915_GEM_MMAP_GTT,
1442 DBG("%s:%d: Error preparing buffer map %d (%s): %s .\n",
1444 bo_gem->gem_handle, bo_gem->name,
1446 if (--bo_gem->map_count == 0)
1447 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1452 bo_gem->gtt_virtual = drm_mmap(0, bo->size, PROT_READ | PROT_WRITE,
1453 MAP_SHARED, bufmgr_gem->fd,
1455 if (bo_gem->gtt_virtual == MAP_FAILED) {
1456 bo_gem->gtt_virtual = NULL;
1458 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1460 bo_gem->gem_handle, bo_gem->name,
1462 if (--bo_gem->map_count == 0)
1463 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1468 bo->virtual = bo_gem->gtt_virtual;
1470 DBG("bo_map_gtt: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1471 bo_gem->gtt_virtual);
1477 drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
1479 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1480 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1481 struct drm_i915_gem_set_domain set_domain;
1484 pthread_mutex_lock(&bufmgr_gem->lock);
1488 pthread_mutex_unlock(&bufmgr_gem->lock);
1492 /* Now move it to the GTT domain so that the GPU and CPU
1493 * caches are flushed and the GPU isn't actively using the
1496 * The pagefault handler does this domain change for us when
1497 * it has unbound the BO from the GTT, but it's up to us to
1498 * tell it when we're about to use things if we had done
1499 * rendering and it still happens to be bound to the GTT.
1501 memclear(set_domain);
1502 set_domain.handle = bo_gem->gem_handle;
1503 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1504 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
1505 ret = drmIoctl(bufmgr_gem->fd,
1506 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1509 DBG("%s:%d: Error setting domain %d: %s\n",
1510 __FILE__, __LINE__, bo_gem->gem_handle,
1514 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1515 VG(VALGRIND_MAKE_MEM_DEFINED(bo_gem->gtt_virtual, bo->size));
1516 pthread_mutex_unlock(&bufmgr_gem->lock);
1522 * Performs a mapping of the buffer object like the normal GTT
1523 * mapping, but avoids waiting for the GPU to be done reading from or
1524 * rendering to the buffer.
1526 * This is used in the implementation of GL_ARB_map_buffer_range: The
1527 * user asks to create a buffer, then does a mapping, fills some
1528 * space, runs a drawing command, then asks to map it again without
1529 * synchronizing because it guarantees that it won't write over the
1530 * data that the GPU is busy using (or, more specifically, that if it
1531 * does write over the data, it acknowledges that rendering is
1536 drm_intel_gem_bo_map_unsynchronized(drm_intel_bo *bo)
1538 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1539 #ifdef HAVE_VALGRIND
1540 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1544 /* If the CPU cache isn't coherent with the GTT, then use a
1545 * regular synchronized mapping. The problem is that we don't
1546 * track where the buffer was last used on the CPU side in
1547 * terms of drm_intel_bo_map vs drm_intel_gem_bo_map_gtt, so
1548 * we would potentially corrupt the buffer even when the user
1549 * does reasonable things.
1551 if (!bufmgr_gem->has_llc)
1552 return drm_intel_gem_bo_map_gtt(bo);
1554 pthread_mutex_lock(&bufmgr_gem->lock);
1558 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1559 VG(VALGRIND_MAKE_MEM_DEFINED(bo_gem->gtt_virtual, bo->size));
1562 pthread_mutex_unlock(&bufmgr_gem->lock);
1567 static int drm_intel_gem_bo_unmap(drm_intel_bo *bo)
1569 drm_intel_bufmgr_gem *bufmgr_gem;
1570 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1576 if (bo_gem->is_userptr)
1579 bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1581 pthread_mutex_lock(&bufmgr_gem->lock);
1583 if (bo_gem->map_count <= 0) {
1584 DBG("attempted to unmap an unmapped bo\n");
1585 pthread_mutex_unlock(&bufmgr_gem->lock);
1586 /* Preserve the old behaviour of just treating this as a
1587 * no-op rather than reporting the error.
1592 if (bo_gem->mapped_cpu_write) {
1593 struct drm_i915_gem_sw_finish sw_finish;
1595 /* Cause a flush to happen if the buffer's pinned for
1596 * scanout, so the results show up in a timely manner.
1597 * Unlike GTT set domains, this only does work if the
1598 * buffer should be scanout-related.
1600 memclear(sw_finish);
1601 sw_finish.handle = bo_gem->gem_handle;
1602 ret = drmIoctl(bufmgr_gem->fd,
1603 DRM_IOCTL_I915_GEM_SW_FINISH,
1605 ret = ret == -1 ? -errno : 0;
1607 bo_gem->mapped_cpu_write = false;
1610 /* We need to unmap after every innovation as we cannot track
1611 * an open vma for every bo as that will exhaasut the system
1612 * limits and cause later failures.
1614 if (--bo_gem->map_count == 0) {
1615 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1616 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1619 pthread_mutex_unlock(&bufmgr_gem->lock);
1625 drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo)
1627 return drm_intel_gem_bo_unmap(bo);
1631 drm_intel_gem_bo_subdata(drm_intel_bo *bo, unsigned long offset,
1632 unsigned long size, const void *data)
1634 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1635 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1636 struct drm_i915_gem_pwrite pwrite;
1639 if (bo_gem->is_userptr)
1643 pwrite.handle = bo_gem->gem_handle;
1644 pwrite.offset = offset;
1646 pwrite.data_ptr = (uint64_t) (uintptr_t) data;
1647 ret = drmIoctl(bufmgr_gem->fd,
1648 DRM_IOCTL_I915_GEM_PWRITE,
1652 DBG("%s:%d: Error writing data to buffer %d: (%d %d) %s .\n",
1653 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1654 (int)size, strerror(errno));
1661 drm_intel_gem_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id)
1663 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1664 struct drm_i915_get_pipe_from_crtc_id get_pipe_from_crtc_id;
1667 memclear(get_pipe_from_crtc_id);
1668 get_pipe_from_crtc_id.crtc_id = crtc_id;
1669 ret = drmIoctl(bufmgr_gem->fd,
1670 DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID,
1671 &get_pipe_from_crtc_id);
1673 /* We return -1 here to signal that we don't
1674 * know which pipe is associated with this crtc.
1675 * This lets the caller know that this information
1676 * isn't available; using the wrong pipe for
1677 * vblank waiting can cause the chipset to lock up
1682 return get_pipe_from_crtc_id.pipe;
1686 drm_intel_gem_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
1687 unsigned long size, void *data)
1689 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1690 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1691 struct drm_i915_gem_pread pread;
1694 if (bo_gem->is_userptr)
1698 pread.handle = bo_gem->gem_handle;
1699 pread.offset = offset;
1701 pread.data_ptr = (uint64_t) (uintptr_t) data;
1702 ret = drmIoctl(bufmgr_gem->fd,
1703 DRM_IOCTL_I915_GEM_PREAD,
1707 DBG("%s:%d: Error reading data from buffer %d: (%d %d) %s .\n",
1708 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1709 (int)size, strerror(errno));
1715 /** Waits for all GPU rendering with the object to have completed. */
1717 drm_intel_gem_bo_wait_rendering(drm_intel_bo *bo)
1719 drm_intel_gem_bo_start_gtt_access(bo, 1);
1723 * Waits on a BO for the given amount of time.
1725 * @bo: buffer object to wait for
1726 * @timeout_ns: amount of time to wait in nanoseconds.
1727 * If value is less than 0, an infinite wait will occur.
1729 * Returns 0 if the wait was successful ie. the last batch referencing the
1730 * object has completed within the allotted time. Otherwise some negative return
1731 * value describes the error. Of particular interest is -ETIME when the wait has
1732 * failed to yield the desired result.
1734 * Similar to drm_intel_gem_bo_wait_rendering except a timeout parameter allows
1735 * the operation to give up after a certain amount of time. Another subtle
1736 * difference is the internal locking semantics are different (this variant does
1737 * not hold the lock for the duration of the wait). This makes the wait subject
1738 * to a larger userspace race window.
1740 * The implementation shall wait until the object is no longer actively
1741 * referenced within a batch buffer at the time of the call. The wait will
1742 * not guarantee that the buffer is re-issued via another thread, or an flinked
1743 * handle. Userspace must make sure this race does not occur if such precision
1746 * Note that some kernels have broken the inifite wait for negative values
1747 * promise, upgrade to latest stable kernels if this is the case.
1750 drm_intel_gem_bo_wait(drm_intel_bo *bo, int64_t timeout_ns)
1752 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1753 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1754 struct drm_i915_gem_wait wait;
1757 if (!bufmgr_gem->has_wait_timeout) {
1758 DBG("%s:%d: Timed wait is not supported. Falling back to "
1759 "infinite wait\n", __FILE__, __LINE__);
1761 drm_intel_gem_bo_wait_rendering(bo);
1764 return drm_intel_gem_bo_busy(bo) ? -ETIME : 0;
1769 wait.bo_handle = bo_gem->gem_handle;
1770 wait.timeout_ns = timeout_ns;
1771 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_WAIT, &wait);
1779 * Sets the object to the GTT read and possibly write domain, used by the X
1780 * 2D driver in the absence of kernel support to do drm_intel_gem_bo_map_gtt().
1782 * In combination with drm_intel_gem_bo_pin() and manual fence management, we
1783 * can do tiled pixmaps this way.
1786 drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable)
1788 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1789 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1790 struct drm_i915_gem_set_domain set_domain;
1793 memclear(set_domain);
1794 set_domain.handle = bo_gem->gem_handle;
1795 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1796 set_domain.write_domain = write_enable ? I915_GEM_DOMAIN_GTT : 0;
1797 ret = drmIoctl(bufmgr_gem->fd,
1798 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1801 DBG("%s:%d: Error setting memory domains %d (%08x %08x): %s .\n",
1802 __FILE__, __LINE__, bo_gem->gem_handle,
1803 set_domain.read_domains, set_domain.write_domain,
1809 drm_intel_bufmgr_gem_destroy(drm_intel_bufmgr *bufmgr)
1811 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1812 struct drm_gem_close close_bo;
1815 free(bufmgr_gem->exec2_objects);
1816 free(bufmgr_gem->exec_objects);
1817 free(bufmgr_gem->exec_bos);
1819 pthread_mutex_destroy(&bufmgr_gem->lock);
1821 /* Free any cached buffer objects we were going to reuse */
1822 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
1823 struct drm_intel_gem_bo_bucket *bucket =
1824 &bufmgr_gem->cache_bucket[i];
1825 drm_intel_bo_gem *bo_gem;
1827 while (!DRMLISTEMPTY(&bucket->head)) {
1828 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1829 bucket->head.next, head);
1830 DRMLISTDEL(&bo_gem->head);
1832 drm_intel_gem_bo_free(&bo_gem->bo);
1836 /* Release userptr bo kept hanging around for optimisation. */
1837 if (bufmgr_gem->userptr_active.ptr) {
1839 close_bo.handle = bufmgr_gem->userptr_active.handle;
1840 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close_bo);
1841 free(bufmgr_gem->userptr_active.ptr);
1844 "Failed to release test userptr object! (%d) "
1845 "i915 kernel driver may not be sane!\n", errno);
1852 * Adds the target buffer to the validation list and adds the relocation
1853 * to the reloc_buffer's relocation list.
1855 * The relocation entry at the given offset must already contain the
1856 * precomputed relocation value, because the kernel will optimize out
1857 * the relocation entry write when the buffer hasn't moved from the
1858 * last known offset in target_bo.
1861 do_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1862 drm_intel_bo *target_bo, uint32_t target_offset,
1863 uint32_t read_domains, uint32_t write_domain,
1866 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1867 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1868 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
1869 bool fenced_command;
1871 if (bo_gem->has_error)
1874 if (target_bo_gem->has_error) {
1875 bo_gem->has_error = true;
1879 /* We never use HW fences for rendering on 965+ */
1880 if (bufmgr_gem->gen >= 4)
1883 fenced_command = need_fence;
1884 if (target_bo_gem->tiling_mode == I915_TILING_NONE)
1887 /* Create a new relocation list if needed */
1888 if (bo_gem->relocs == NULL && drm_intel_setup_reloc_list(bo))
1891 /* Check overflow */
1892 assert(bo_gem->reloc_count < bufmgr_gem->max_relocs);
1895 assert(offset <= bo->size - 4);
1896 assert((write_domain & (write_domain - 1)) == 0);
1898 /* An object needing a fence is a tiled buffer, so it won't have
1899 * relocs to other buffers.
1902 assert(target_bo_gem->reloc_count == 0);
1903 target_bo_gem->reloc_tree_fences = 1;
1906 /* Make sure that we're not adding a reloc to something whose size has
1907 * already been accounted for.
1909 assert(!bo_gem->used_as_reloc_target);
1910 if (target_bo_gem != bo_gem) {
1911 target_bo_gem->used_as_reloc_target = true;
1912 bo_gem->reloc_tree_size += target_bo_gem->reloc_tree_size;
1913 bo_gem->reloc_tree_fences += target_bo_gem->reloc_tree_fences;
1916 bo_gem->relocs[bo_gem->reloc_count].offset = offset;
1917 bo_gem->relocs[bo_gem->reloc_count].delta = target_offset;
1918 bo_gem->relocs[bo_gem->reloc_count].target_handle =
1919 target_bo_gem->gem_handle;
1920 bo_gem->relocs[bo_gem->reloc_count].read_domains = read_domains;
1921 bo_gem->relocs[bo_gem->reloc_count].write_domain = write_domain;
1922 bo_gem->relocs[bo_gem->reloc_count].presumed_offset = target_bo->offset64;
1924 bo_gem->reloc_target_info[bo_gem->reloc_count].bo = target_bo;
1925 if (target_bo != bo)
1926 drm_intel_gem_bo_reference(target_bo);
1928 bo_gem->reloc_target_info[bo_gem->reloc_count].flags =
1929 DRM_INTEL_RELOC_FENCE;
1931 bo_gem->reloc_target_info[bo_gem->reloc_count].flags = 0;
1933 bo_gem->reloc_count++;
1939 drm_intel_gem_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1940 drm_intel_bo *target_bo, uint32_t target_offset,
1941 uint32_t read_domains, uint32_t write_domain)
1943 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1945 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1946 read_domains, write_domain,
1947 !bufmgr_gem->fenced_relocs);
1951 drm_intel_gem_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
1952 drm_intel_bo *target_bo,
1953 uint32_t target_offset,
1954 uint32_t read_domains, uint32_t write_domain)
1956 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1957 read_domains, write_domain, true);
1961 drm_intel_gem_bo_get_reloc_count(drm_intel_bo *bo)
1963 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1965 return bo_gem->reloc_count;
1969 * Removes existing relocation entries in the BO after "start".
1971 * This allows a user to avoid a two-step process for state setup with
1972 * counting up all the buffer objects and doing a
1973 * drm_intel_bufmgr_check_aperture_space() before emitting any of the
1974 * relocations for the state setup. Instead, save the state of the
1975 * batchbuffer including drm_intel_gem_get_reloc_count(), emit all the
1976 * state, and then check if it still fits in the aperture.
1978 * Any further drm_intel_bufmgr_check_aperture_space() queries
1979 * involving this buffer in the tree are undefined after this call.
1982 drm_intel_gem_bo_clear_relocs(drm_intel_bo *bo, int start)
1984 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1985 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1987 struct timespec time;
1989 clock_gettime(CLOCK_MONOTONIC, &time);
1991 assert(bo_gem->reloc_count >= start);
1993 /* Unreference the cleared target buffers */
1994 pthread_mutex_lock(&bufmgr_gem->lock);
1996 for (i = start; i < bo_gem->reloc_count; i++) {
1997 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) bo_gem->reloc_target_info[i].bo;
1998 if (&target_bo_gem->bo != bo) {
1999 bo_gem->reloc_tree_fences -= target_bo_gem->reloc_tree_fences;
2000 drm_intel_gem_bo_unreference_locked_timed(&target_bo_gem->bo,
2004 bo_gem->reloc_count = start;
2006 pthread_mutex_unlock(&bufmgr_gem->lock);
2011 * Walk the tree of relocations rooted at BO and accumulate the list of
2012 * validations to be performed and update the relocation buffers with
2013 * index values into the validation list.
2016 drm_intel_gem_bo_process_reloc(drm_intel_bo *bo)
2018 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2021 if (bo_gem->relocs == NULL)
2024 for (i = 0; i < bo_gem->reloc_count; i++) {
2025 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
2027 if (target_bo == bo)
2030 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
2032 /* Continue walking the tree depth-first. */
2033 drm_intel_gem_bo_process_reloc(target_bo);
2035 /* Add the target to the validate list */
2036 drm_intel_add_validate_buffer(target_bo);
2041 drm_intel_gem_bo_process_reloc2(drm_intel_bo *bo)
2043 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
2046 if (bo_gem->relocs == NULL)
2049 for (i = 0; i < bo_gem->reloc_count; i++) {
2050 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
2053 if (target_bo == bo)
2056 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
2058 /* Continue walking the tree depth-first. */
2059 drm_intel_gem_bo_process_reloc2(target_bo);
2061 need_fence = (bo_gem->reloc_target_info[i].flags &
2062 DRM_INTEL_RELOC_FENCE);
2064 /* Add the target to the validate list */
2065 drm_intel_add_validate_buffer2(target_bo, need_fence);
2071 drm_intel_update_buffer_offsets(drm_intel_bufmgr_gem *bufmgr_gem)
2075 for (i = 0; i < bufmgr_gem->exec_count; i++) {
2076 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
2077 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2079 /* Update the buffer offset */
2080 if (bufmgr_gem->exec_objects[i].offset != bo->offset64) {
2081 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
2082 bo_gem->gem_handle, bo_gem->name, bo->offset64,
2083 (unsigned long long)bufmgr_gem->exec_objects[i].
2085 bo->offset64 = bufmgr_gem->exec_objects[i].offset;
2086 bo->offset = bufmgr_gem->exec_objects[i].offset;
2092 drm_intel_update_buffer_offsets2 (drm_intel_bufmgr_gem *bufmgr_gem)
2096 for (i = 0; i < bufmgr_gem->exec_count; i++) {
2097 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
2098 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
2100 /* Update the buffer offset */
2101 if (bufmgr_gem->exec2_objects[i].offset != bo->offset64) {
2102 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
2103 bo_gem->gem_handle, bo_gem->name, bo->offset64,
2104 (unsigned long long)bufmgr_gem->exec2_objects[i].offset);
2105 bo->offset64 = bufmgr_gem->exec2_objects[i].offset;
2106 bo->offset = bufmgr_gem->exec2_objects[i].offset;
2112 drm_intel_gem_bo_aub_dump_bmp(drm_intel_bo *bo,
2113 int x1, int y1, int width, int height,
2114 enum aub_dump_bmp_format format,
2115 int pitch, int offset)
2120 drm_intel_gem_bo_exec(drm_intel_bo *bo, int used,
2121 drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
2123 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2124 struct drm_i915_gem_execbuffer execbuf;
2127 if (to_bo_gem(bo)->has_error)
2130 pthread_mutex_lock(&bufmgr_gem->lock);
2131 /* Update indices and set up the validate list. */
2132 drm_intel_gem_bo_process_reloc(bo);
2134 /* Add the batch buffer to the validation list. There are no
2135 * relocations pointing to it.
2137 drm_intel_add_validate_buffer(bo);
2140 execbuf.buffers_ptr = (uintptr_t) bufmgr_gem->exec_objects;
2141 execbuf.buffer_count = bufmgr_gem->exec_count;
2142 execbuf.batch_start_offset = 0;
2143 execbuf.batch_len = used;
2144 execbuf.cliprects_ptr = (uintptr_t) cliprects;
2145 execbuf.num_cliprects = num_cliprects;
2149 ret = drmIoctl(bufmgr_gem->fd,
2150 DRM_IOCTL_I915_GEM_EXECBUFFER,
2154 if (errno == ENOSPC) {
2155 DBG("Execbuffer fails to pin. "
2156 "Estimate: %u. Actual: %u. Available: %u\n",
2157 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
2160 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
2163 (unsigned int)bufmgr_gem->gtt_size);
2166 drm_intel_update_buffer_offsets(bufmgr_gem);
2168 if (bufmgr_gem->bufmgr.debug)
2169 drm_intel_gem_dump_validation_list(bufmgr_gem);
2171 for (i = 0; i < bufmgr_gem->exec_count; i++) {
2172 drm_intel_bo_gem *bo_gem = to_bo_gem(bufmgr_gem->exec_bos[i]);
2174 bo_gem->idle = false;
2176 /* Disconnect the buffer from the validate list */
2177 bo_gem->validate_index = -1;
2178 bufmgr_gem->exec_bos[i] = NULL;
2180 bufmgr_gem->exec_count = 0;
2181 pthread_mutex_unlock(&bufmgr_gem->lock);
2187 do_exec2(drm_intel_bo *bo, int used, drm_intel_context *ctx,
2188 drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
2191 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
2192 struct drm_i915_gem_execbuffer2 execbuf;
2196 if (to_bo_gem(bo)->has_error)
2199 switch (flags & 0x7) {
2203 if (!bufmgr_gem->has_blt)
2207 if (!bufmgr_gem->has_bsd)
2210 case I915_EXEC_VEBOX:
2211 if (!bufmgr_gem->has_vebox)
2214 case I915_EXEC_RENDER:
2215 case I915_EXEC_DEFAULT:
2219 pthread_mutex_lock(&bufmgr_gem->lock);
2220 /* Update indices and set up the validate list. */
2221 drm_intel_gem_bo_process_reloc2(bo);
2223 /* Add the batch buffer to the validation list. There are no relocations
2226 drm_intel_add_validate_buffer2(bo, 0);
2229 execbuf.buffers_ptr = (uintptr_t)bufmgr_gem->exec2_objects;
2230 execbuf.buffer_count = bufmgr_gem->exec_count;
2231 execbuf.batch_start_offset = 0;
2232 execbuf.batch_len = used;
2233 execbuf.cliprects_ptr = (uintptr_t)cliprects;
2234 execbuf.num_cliprects = num_cliprects;
2237 execbuf.flags = flags;
2239 i915_execbuffer2_set_context_id(execbuf, 0);
2241 i915_execbuffer2_set_context_id(execbuf, ctx->ctx_id);
2244 if (bufmgr_gem->no_exec)
2245 goto skip_execution;
2247 ret = drmIoctl(bufmgr_gem->fd,
2248 DRM_IOCTL_I915_GEM_EXECBUFFER2,
2252 if (ret == -ENOSPC) {
2253 DBG("Execbuffer fails to pin. "
2254 "Estimate: %u. Actual: %u. Available: %u\n",
2255 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
2256 bufmgr_gem->exec_count),
2257 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
2258 bufmgr_gem->exec_count),
2259 (unsigned int) bufmgr_gem->gtt_size);
2262 drm_intel_update_buffer_offsets2(bufmgr_gem);
2265 if (bufmgr_gem->bufmgr.debug)
2266 drm_intel_gem_dump_validation_list(bufmgr_gem);
2268 for (i = 0; i < bufmgr_gem->exec_count; i++) {
2269 drm_intel_bo_gem *bo_gem = to_bo_gem(bufmgr_gem->exec_bos[i]);
2271 bo_gem->idle = false;
2273 /* Disconnect the buffer from the validate list */
2274 bo_gem->validate_index = -1;
2275 bufmgr_gem->exec_bos[i] = NULL;
2277 bufmgr_gem->exec_count = 0;
2278 pthread_mutex_unlock(&bufmgr_gem->lock);
2284 drm_intel_gem_bo_exec2(drm_intel_bo *bo, int used,
2285 drm_clip_rect_t *cliprects, int num_cliprects,
2288 return do_exec2(bo, used, NULL, cliprects, num_cliprects, DR4,
2293 drm_intel_gem_bo_mrb_exec2(drm_intel_bo *bo, int used,
2294 drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
2297 return do_exec2(bo, used, NULL, cliprects, num_cliprects, DR4,
2302 drm_intel_gem_bo_context_exec(drm_intel_bo *bo, drm_intel_context *ctx,
2303 int used, unsigned int flags)
2305 return do_exec2(bo, used, ctx, NULL, 0, 0, flags);
2309 drm_intel_gem_bo_pin(drm_intel_bo *bo, uint32_t alignment)
2311 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2312 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2313 struct drm_i915_gem_pin pin;
2317 pin.handle = bo_gem->gem_handle;
2318 pin.alignment = alignment;
2320 ret = drmIoctl(bufmgr_gem->fd,
2321 DRM_IOCTL_I915_GEM_PIN,
2326 bo->offset64 = pin.offset;
2327 bo->offset = pin.offset;
2332 drm_intel_gem_bo_unpin(drm_intel_bo *bo)
2334 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2335 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2336 struct drm_i915_gem_unpin unpin;
2340 unpin.handle = bo_gem->gem_handle;
2342 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_UNPIN, &unpin);
2350 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
2351 uint32_t tiling_mode,
2354 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2355 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2356 struct drm_i915_gem_set_tiling set_tiling;
2359 if (bo_gem->global_name == 0 &&
2360 tiling_mode == bo_gem->tiling_mode &&
2361 stride == bo_gem->stride)
2364 memset(&set_tiling, 0, sizeof(set_tiling));
2366 /* set_tiling is slightly broken and overwrites the
2367 * input on the error path, so we have to open code
2370 set_tiling.handle = bo_gem->gem_handle;
2371 set_tiling.tiling_mode = tiling_mode;
2372 set_tiling.stride = stride;
2374 ret = ioctl(bufmgr_gem->fd,
2375 DRM_IOCTL_I915_GEM_SET_TILING,
2377 } while (ret == -1 && (errno == EINTR || errno == EAGAIN));
2381 bo_gem->tiling_mode = set_tiling.tiling_mode;
2382 bo_gem->swizzle_mode = set_tiling.swizzle_mode;
2383 bo_gem->stride = set_tiling.stride;
2388 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
2391 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2392 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2395 /* Tiling with userptr surfaces is not supported
2396 * on all hardware so refuse it for time being.
2398 if (bo_gem->is_userptr)
2401 /* Linear buffers have no stride. By ensuring that we only ever use
2402 * stride 0 with linear buffers, we simplify our code.
2404 if (*tiling_mode == I915_TILING_NONE)
2407 ret = drm_intel_gem_bo_set_tiling_internal(bo, *tiling_mode, stride);
2409 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem, 0);
2411 *tiling_mode = bo_gem->tiling_mode;
2416 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
2417 uint32_t * swizzle_mode)
2419 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2421 *tiling_mode = bo_gem->tiling_mode;
2422 *swizzle_mode = bo_gem->swizzle_mode;
2427 drm_intel_bo_gem_create_from_prime(drm_intel_bufmgr *bufmgr, int prime_fd, int size)
2429 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
2432 drm_intel_bo_gem *bo_gem;
2433 struct drm_i915_gem_get_tiling get_tiling;
2434 drmMMListHead *list;
2436 pthread_mutex_lock(&bufmgr_gem->lock);
2437 ret = drmPrimeFDToHandle(bufmgr_gem->fd, prime_fd, &handle);
2439 DBG("create_from_prime: failed to obtain handle from fd: %s\n", strerror(errno));
2440 pthread_mutex_unlock(&bufmgr_gem->lock);
2445 * See if the kernel has already returned this buffer to us. Just as
2446 * for named buffers, we must not create two bo's pointing at the same
2449 for (list = bufmgr_gem->named.next;
2450 list != &bufmgr_gem->named;
2451 list = list->next) {
2452 bo_gem = DRMLISTENTRY(drm_intel_bo_gem, list, name_list);
2453 if (bo_gem->gem_handle == handle) {
2454 drm_intel_gem_bo_reference(&bo_gem->bo);
2455 pthread_mutex_unlock(&bufmgr_gem->lock);
2460 bo_gem = calloc(1, sizeof(*bo_gem));
2462 pthread_mutex_unlock(&bufmgr_gem->lock);
2465 /* Determine size of bo. The fd-to-handle ioctl really should
2466 * return the size, but it doesn't. If we have kernel 3.12 or
2467 * later, we can lseek on the prime fd to get the size. Older
2468 * kernels will just fail, in which case we fall back to the
2469 * provided (estimated or guess size). */
2470 ret = lseek(prime_fd, 0, SEEK_END);
2472 bo_gem->bo.size = ret;
2474 bo_gem->bo.size = size;
2476 bo_gem->bo.handle = handle;
2477 bo_gem->bo.bufmgr = bufmgr;
2479 bo_gem->gem_handle = handle;
2481 atomic_set(&bo_gem->refcount, 1);
2483 bo_gem->name = "prime";
2484 bo_gem->validate_index = -1;
2485 bo_gem->reloc_tree_fences = 0;
2486 bo_gem->used_as_reloc_target = false;
2487 bo_gem->has_error = false;
2488 bo_gem->reusable = false;
2490 DRMINITLISTHEAD(&bo_gem->vma_list);
2491 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
2492 pthread_mutex_unlock(&bufmgr_gem->lock);
2494 memclear(get_tiling);
2495 get_tiling.handle = bo_gem->gem_handle;
2496 ret = drmIoctl(bufmgr_gem->fd,
2497 DRM_IOCTL_I915_GEM_GET_TILING,
2500 DBG("create_from_prime: failed to get tiling: %s\n", strerror(errno));
2501 drm_intel_gem_bo_unreference(&bo_gem->bo);
2504 bo_gem->tiling_mode = get_tiling.tiling_mode;
2505 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
2506 /* XXX stride is unknown */
2507 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem, 0);
2513 drm_intel_bo_gem_export_to_prime(drm_intel_bo *bo, int *prime_fd)
2515 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2516 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2518 pthread_mutex_lock(&bufmgr_gem->lock);
2519 if (DRMLISTEMPTY(&bo_gem->name_list))
2520 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
2521 pthread_mutex_unlock(&bufmgr_gem->lock);
2523 if (drmPrimeHandleToFD(bufmgr_gem->fd, bo_gem->gem_handle,
2524 DRM_CLOEXEC, prime_fd) != 0)
2527 bo_gem->reusable = false;
2533 drm_intel_gem_bo_flink(drm_intel_bo *bo, uint32_t * name)
2535 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2536 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2539 if (!bo_gem->global_name) {
2540 struct drm_gem_flink flink;
2543 flink.handle = bo_gem->gem_handle;
2545 pthread_mutex_lock(&bufmgr_gem->lock);
2547 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_FLINK, &flink);
2549 pthread_mutex_unlock(&bufmgr_gem->lock);
2553 bo_gem->global_name = flink.name;
2554 bo_gem->reusable = false;
2556 if (DRMLISTEMPTY(&bo_gem->name_list))
2557 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
2558 pthread_mutex_unlock(&bufmgr_gem->lock);
2561 *name = bo_gem->global_name;
2566 * Enables unlimited caching of buffer objects for reuse.
2568 * This is potentially very memory expensive, as the cache at each bucket
2569 * size is only bounded by how many buffers of that size we've managed to have
2570 * in flight at once.
2573 drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr)
2575 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
2577 bufmgr_gem->bo_reuse = true;
2581 * Enable use of fenced reloc type.
2583 * New code should enable this to avoid unnecessary fence register
2584 * allocation. If this option is not enabled, all relocs will have fence
2585 * register allocated.
2588 drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr)
2590 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
2592 if (bufmgr_gem->bufmgr.bo_exec == drm_intel_gem_bo_exec2)
2593 bufmgr_gem->fenced_relocs = true;
2597 * Return the additional aperture space required by the tree of buffer objects
2601 drm_intel_gem_bo_get_aperture_space(drm_intel_bo *bo)
2603 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2607 if (bo == NULL || bo_gem->included_in_check_aperture)
2611 bo_gem->included_in_check_aperture = true;
2613 for (i = 0; i < bo_gem->reloc_count; i++)
2615 drm_intel_gem_bo_get_aperture_space(bo_gem->
2616 reloc_target_info[i].bo);
2622 * Count the number of buffers in this list that need a fence reg
2624 * If the count is greater than the number of available regs, we'll have
2625 * to ask the caller to resubmit a batch with fewer tiled buffers.
2627 * This function over-counts if the same buffer is used multiple times.
2630 drm_intel_gem_total_fences(drm_intel_bo ** bo_array, int count)
2633 unsigned int total = 0;
2635 for (i = 0; i < count; i++) {
2636 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
2641 total += bo_gem->reloc_tree_fences;
2647 * Clear the flag set by drm_intel_gem_bo_get_aperture_space() so we're ready
2648 * for the next drm_intel_bufmgr_check_aperture_space() call.
2651 drm_intel_gem_bo_clear_aperture_space_flag(drm_intel_bo *bo)
2653 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2656 if (bo == NULL || !bo_gem->included_in_check_aperture)
2659 bo_gem->included_in_check_aperture = false;
2661 for (i = 0; i < bo_gem->reloc_count; i++)
2662 drm_intel_gem_bo_clear_aperture_space_flag(bo_gem->
2663 reloc_target_info[i].bo);
2667 * Return a conservative estimate for the amount of aperture required
2668 * for a collection of buffers. This may double-count some buffers.
2671 drm_intel_gem_estimate_batch_space(drm_intel_bo **bo_array, int count)
2674 unsigned int total = 0;
2676 for (i = 0; i < count; i++) {
2677 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
2679 total += bo_gem->reloc_tree_size;
2685 * Return the amount of aperture needed for a collection of buffers.
2686 * This avoids double counting any buffers, at the cost of looking
2687 * at every buffer in the set.
2690 drm_intel_gem_compute_batch_space(drm_intel_bo **bo_array, int count)
2693 unsigned int total = 0;
2695 for (i = 0; i < count; i++) {
2696 total += drm_intel_gem_bo_get_aperture_space(bo_array[i]);
2697 /* For the first buffer object in the array, we get an
2698 * accurate count back for its reloc_tree size (since nothing
2699 * had been flagged as being counted yet). We can save that
2700 * value out as a more conservative reloc_tree_size that
2701 * avoids double-counting target buffers. Since the first
2702 * buffer happens to usually be the batch buffer in our
2703 * callers, this can pull us back from doing the tree
2704 * walk on every new batch emit.
2707 drm_intel_bo_gem *bo_gem =
2708 (drm_intel_bo_gem *) bo_array[i];
2709 bo_gem->reloc_tree_size = total;
2713 for (i = 0; i < count; i++)
2714 drm_intel_gem_bo_clear_aperture_space_flag(bo_array[i]);
2719 * Return -1 if the batchbuffer should be flushed before attempting to
2720 * emit rendering referencing the buffers pointed to by bo_array.
2722 * This is required because if we try to emit a batchbuffer with relocations
2723 * to a tree of buffers that won't simultaneously fit in the aperture,
2724 * the rendering will return an error at a point where the software is not
2725 * prepared to recover from it.
2727 * However, we also want to emit the batchbuffer significantly before we reach
2728 * the limit, as a series of batchbuffers each of which references buffers
2729 * covering almost all of the aperture means that at each emit we end up
2730 * waiting to evict a buffer from the last rendering, and we get synchronous
2731 * performance. By emitting smaller batchbuffers, we eat some CPU overhead to
2732 * get better parallelism.
2735 drm_intel_gem_check_aperture_space(drm_intel_bo **bo_array, int count)
2737 drm_intel_bufmgr_gem *bufmgr_gem =
2738 (drm_intel_bufmgr_gem *) bo_array[0]->bufmgr;
2739 unsigned int total = 0;
2740 unsigned int threshold = bufmgr_gem->gtt_size * 3 / 4;
2743 /* Check for fence reg constraints if necessary */
2744 if (bufmgr_gem->available_fences) {
2745 total_fences = drm_intel_gem_total_fences(bo_array, count);
2746 if (total_fences > bufmgr_gem->available_fences)
2750 total = drm_intel_gem_estimate_batch_space(bo_array, count);
2752 if (total > threshold)
2753 total = drm_intel_gem_compute_batch_space(bo_array, count);
2755 if (total > threshold) {
2756 DBG("check_space: overflowed available aperture, "
2758 total / 1024, (int)bufmgr_gem->gtt_size / 1024);
2761 DBG("drm_check_space: total %dkb vs bufgr %dkb\n", total / 1024,
2762 (int)bufmgr_gem->gtt_size / 1024);
2768 * Disable buffer reuse for objects which are shared with the kernel
2769 * as scanout buffers
2772 drm_intel_gem_bo_disable_reuse(drm_intel_bo *bo)
2774 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2776 bo_gem->reusable = false;
2781 drm_intel_gem_bo_is_reusable(drm_intel_bo *bo)
2783 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2785 return bo_gem->reusable;
2789 _drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
2791 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2794 for (i = 0; i < bo_gem->reloc_count; i++) {
2795 if (bo_gem->reloc_target_info[i].bo == target_bo)
2797 if (bo == bo_gem->reloc_target_info[i].bo)
2799 if (_drm_intel_gem_bo_references(bo_gem->reloc_target_info[i].bo,
2807 /** Return true if target_bo is referenced by bo's relocation tree. */
2809 drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
2811 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
2813 if (bo == NULL || target_bo == NULL)
2815 if (target_bo_gem->used_as_reloc_target)
2816 return _drm_intel_gem_bo_references(bo, target_bo);
2821 add_bucket(drm_intel_bufmgr_gem *bufmgr_gem, int size)
2823 unsigned int i = bufmgr_gem->num_buckets;
2825 assert(i < ARRAY_SIZE(bufmgr_gem->cache_bucket));
2827 DRMINITLISTHEAD(&bufmgr_gem->cache_bucket[i].head);
2828 bufmgr_gem->cache_bucket[i].size = size;
2829 bufmgr_gem->num_buckets++;
2833 init_cache_buckets(drm_intel_bufmgr_gem *bufmgr_gem)
2835 unsigned long size, cache_max_size = 64 * 1024 * 1024;
2837 /* OK, so power of two buckets was too wasteful of memory.
2838 * Give 3 other sizes between each power of two, to hopefully
2839 * cover things accurately enough. (The alternative is
2840 * probably to just go for exact matching of sizes, and assume
2841 * that for things like composited window resize the tiled
2842 * width/height alignment and rounding of sizes to pages will
2843 * get us useful cache hit rates anyway)
2845 add_bucket(bufmgr_gem, 4096);
2846 add_bucket(bufmgr_gem, 4096 * 2);
2847 add_bucket(bufmgr_gem, 4096 * 3);
2849 /* Initialize the linked lists for BO reuse cache. */
2850 for (size = 4 * 4096; size <= cache_max_size; size *= 2) {
2851 add_bucket(bufmgr_gem, size);
2853 add_bucket(bufmgr_gem, size + size * 1 / 4);
2854 add_bucket(bufmgr_gem, size + size * 2 / 4);
2855 add_bucket(bufmgr_gem, size + size * 3 / 4);
2860 drm_intel_bufmgr_gem_set_vma_cache_size(drm_intel_bufmgr *bufmgr, int limit)
2862 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
2864 bufmgr_gem->vma_max = limit;
2866 drm_intel_gem_bo_purge_vma_cache(bufmgr_gem);
2870 * Get the PCI ID for the device. This can be overridden by setting the
2871 * INTEL_DEVID_OVERRIDE environment variable to the desired ID.
2874 get_pci_device_id(drm_intel_bufmgr_gem *bufmgr_gem)
2876 char *devid_override;
2879 drm_i915_getparam_t gp;
2881 if (geteuid() == getuid()) {
2882 devid_override = getenv("INTEL_DEVID_OVERRIDE");
2883 if (devid_override) {
2884 bufmgr_gem->no_exec = true;
2885 return strtod(devid_override, NULL);
2890 gp.param = I915_PARAM_CHIPSET_ID;
2892 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2894 fprintf(stderr, "get chip id failed: %d [%d]\n", ret, errno);
2895 fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value);
2901 drm_intel_bufmgr_gem_get_devid(drm_intel_bufmgr *bufmgr)
2903 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
2905 return bufmgr_gem->pci_device;
2909 * Sets the AUB filename.
2911 * This function has to be called before drm_intel_bufmgr_gem_set_aub_dump()
2912 * for it to have any effect.
2915 drm_intel_bufmgr_gem_set_aub_filename(drm_intel_bufmgr *bufmgr,
2916 const char *filename)
2921 * Sets up AUB dumping.
2923 * This is a trace file format that can be used with the simulator.
2924 * Packets are emitted in a format somewhat like GPU command packets.
2925 * You can set up a GTT and upload your objects into the referenced
2926 * space, then send off batchbuffers and get BMPs out the other end.
2929 drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable)
2931 fprintf(stderr, "libdrm aub dumping is deprecated.\n\n"
2932 "Use intel_aubdump from intel-gpu-tools instead. Install intel-gpu-tools,\n"
2933 "then run (for example)\n\n"
2934 "\t$ intel_aubdump --output=trace.aub glxgears -geometry 500x500\n\n"
2935 "See the intel_aubdump man page for more details.\n");
2939 drm_intel_gem_context_create(drm_intel_bufmgr *bufmgr)
2941 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
2942 struct drm_i915_gem_context_create create;
2943 drm_intel_context *context = NULL;
2946 context = calloc(1, sizeof(*context));
2951 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_CONTEXT_CREATE, &create);
2953 DBG("DRM_IOCTL_I915_GEM_CONTEXT_CREATE failed: %s\n",
2959 context->ctx_id = create.ctx_id;
2960 context->bufmgr = bufmgr;
2966 drm_intel_gem_context_destroy(drm_intel_context *ctx)
2968 drm_intel_bufmgr_gem *bufmgr_gem;
2969 struct drm_i915_gem_context_destroy destroy;
2977 bufmgr_gem = (drm_intel_bufmgr_gem *)ctx->bufmgr;
2978 destroy.ctx_id = ctx->ctx_id;
2979 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_CONTEXT_DESTROY,
2982 fprintf(stderr, "DRM_IOCTL_I915_GEM_CONTEXT_DESTROY failed: %s\n",
2989 drm_intel_get_reset_stats(drm_intel_context *ctx,
2990 uint32_t *reset_count,
2994 drm_intel_bufmgr_gem *bufmgr_gem;
2995 struct drm_i915_reset_stats stats;
3003 bufmgr_gem = (drm_intel_bufmgr_gem *)ctx->bufmgr;
3004 stats.ctx_id = ctx->ctx_id;
3005 ret = drmIoctl(bufmgr_gem->fd,
3006 DRM_IOCTL_I915_GET_RESET_STATS,
3009 if (reset_count != NULL)
3010 *reset_count = stats.reset_count;
3013 *active = stats.batch_active;
3015 if (pending != NULL)
3016 *pending = stats.batch_pending;
3023 drm_intel_reg_read(drm_intel_bufmgr *bufmgr,
3027 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
3028 struct drm_i915_reg_read reg_read;
3032 reg_read.offset = offset;
3034 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_REG_READ, ®_read);
3036 *result = reg_read.val;
3041 drm_intel_get_subslice_total(int fd, unsigned int *subslice_total)
3043 drm_i915_getparam_t gp;
3047 gp.value = (int*)subslice_total;
3048 gp.param = I915_PARAM_SUBSLICE_TOTAL;
3049 ret = drmIoctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
3057 drm_intel_get_eu_total(int fd, unsigned int *eu_total)
3059 drm_i915_getparam_t gp;
3063 gp.value = (int*)eu_total;
3064 gp.param = I915_PARAM_EU_TOTAL;
3065 ret = drmIoctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
3073 * Annotate the given bo for use in aub dumping.
3075 * \param annotations is an array of drm_intel_aub_annotation objects
3076 * describing the type of data in various sections of the bo. Each
3077 * element of the array specifies the type and subtype of a section of
3078 * the bo, and the past-the-end offset of that section. The elements
3079 * of \c annotations must be sorted so that ending_offset is
3082 * \param count is the number of elements in the \c annotations array.
3083 * If \c count is zero, then \c annotations will not be dereferenced.
3085 * Annotations are copied into a private data structure, so caller may
3086 * re-use the memory pointed to by \c annotations after the call
3089 * Annotations are stored for the lifetime of the bo; to reset to the
3090 * default state (no annotations), call this function with a \c count
3094 drm_intel_bufmgr_gem_set_aub_annotations(drm_intel_bo *bo,
3095 drm_intel_aub_annotation *annotations,
3100 static pthread_mutex_t bufmgr_list_mutex = PTHREAD_MUTEX_INITIALIZER;
3101 static drmMMListHead bufmgr_list = { &bufmgr_list, &bufmgr_list };
3103 static drm_intel_bufmgr_gem *
3104 drm_intel_bufmgr_gem_find(int fd)
3106 drm_intel_bufmgr_gem *bufmgr_gem;
3108 DRMLISTFOREACHENTRY(bufmgr_gem, &bufmgr_list, managers) {
3109 if (bufmgr_gem->fd == fd) {
3110 atomic_inc(&bufmgr_gem->refcount);
3119 drm_intel_bufmgr_gem_unref(drm_intel_bufmgr *bufmgr)
3121 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
3123 if (atomic_add_unless(&bufmgr_gem->refcount, -1, 1)) {
3124 pthread_mutex_lock(&bufmgr_list_mutex);
3126 if (atomic_dec_and_test(&bufmgr_gem->refcount)) {
3127 DRMLISTDEL(&bufmgr_gem->managers);
3128 drm_intel_bufmgr_gem_destroy(bufmgr);
3131 pthread_mutex_unlock(&bufmgr_list_mutex);
3136 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
3137 * and manage map buffer objections.
3139 * \param fd File descriptor of the opened DRM device.
3142 drm_intel_bufmgr_gem_init(int fd, int batch_size)
3144 drm_intel_bufmgr_gem *bufmgr_gem;
3145 struct drm_i915_gem_get_aperture aperture;
3146 drm_i915_getparam_t gp;
3150 pthread_mutex_lock(&bufmgr_list_mutex);
3152 bufmgr_gem = drm_intel_bufmgr_gem_find(fd);
3156 bufmgr_gem = calloc(1, sizeof(*bufmgr_gem));
3157 if (bufmgr_gem == NULL)
3160 bufmgr_gem->fd = fd;
3161 atomic_set(&bufmgr_gem->refcount, 1);
3163 if (pthread_mutex_init(&bufmgr_gem->lock, NULL) != 0) {
3170 ret = drmIoctl(bufmgr_gem->fd,
3171 DRM_IOCTL_I915_GEM_GET_APERTURE,
3175 bufmgr_gem->gtt_size = aperture.aper_available_size;
3177 fprintf(stderr, "DRM_IOCTL_I915_GEM_APERTURE failed: %s\n",
3179 bufmgr_gem->gtt_size = 128 * 1024 * 1024;
3180 fprintf(stderr, "Assuming %dkB available aperture size.\n"
3181 "May lead to reduced performance or incorrect "
3183 (int)bufmgr_gem->gtt_size / 1024);
3186 bufmgr_gem->pci_device = get_pci_device_id(bufmgr_gem);
3188 if (IS_GEN2(bufmgr_gem->pci_device))
3189 bufmgr_gem->gen = 2;
3190 else if (IS_GEN3(bufmgr_gem->pci_device))
3191 bufmgr_gem->gen = 3;
3192 else if (IS_GEN4(bufmgr_gem->pci_device))
3193 bufmgr_gem->gen = 4;
3194 else if (IS_GEN5(bufmgr_gem->pci_device))
3195 bufmgr_gem->gen = 5;
3196 else if (IS_GEN6(bufmgr_gem->pci_device))
3197 bufmgr_gem->gen = 6;
3198 else if (IS_GEN7(bufmgr_gem->pci_device))
3199 bufmgr_gem->gen = 7;
3200 else if (IS_GEN8(bufmgr_gem->pci_device))
3201 bufmgr_gem->gen = 8;
3202 else if (IS_GEN9(bufmgr_gem->pci_device))
3203 bufmgr_gem->gen = 9;
3210 if (IS_GEN3(bufmgr_gem->pci_device) &&
3211 bufmgr_gem->gtt_size > 256*1024*1024) {
3212 /* The unmappable part of gtt on gen 3 (i.e. above 256MB) can't
3213 * be used for tiled blits. To simplify the accounting, just
3214 * substract the unmappable part (fixed to 256MB on all known
3215 * gen3 devices) if the kernel advertises it. */
3216 bufmgr_gem->gtt_size -= 256*1024*1024;
3222 gp.param = I915_PARAM_HAS_EXECBUF2;
3223 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3227 gp.param = I915_PARAM_HAS_BSD;
3228 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3229 bufmgr_gem->has_bsd = ret == 0;
3231 gp.param = I915_PARAM_HAS_BLT;
3232 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3233 bufmgr_gem->has_blt = ret == 0;
3235 gp.param = I915_PARAM_HAS_RELAXED_FENCING;
3236 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3237 bufmgr_gem->has_relaxed_fencing = ret == 0;
3239 bufmgr_gem->bufmgr.bo_alloc_userptr = check_bo_alloc_userptr;
3241 gp.param = I915_PARAM_HAS_WAIT_TIMEOUT;
3242 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3243 bufmgr_gem->has_wait_timeout = ret == 0;
3245 gp.param = I915_PARAM_HAS_LLC;
3246 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3248 /* Kernel does not supports HAS_LLC query, fallback to GPU
3249 * generation detection and assume that we have LLC on GEN6/7
3251 bufmgr_gem->has_llc = (IS_GEN6(bufmgr_gem->pci_device) |
3252 IS_GEN7(bufmgr_gem->pci_device));
3254 bufmgr_gem->has_llc = *gp.value;
3256 gp.param = I915_PARAM_HAS_VEBOX;
3257 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3258 bufmgr_gem->has_vebox = (ret == 0) & (*gp.value > 0);
3260 if (bufmgr_gem->gen < 4) {
3261 gp.param = I915_PARAM_NUM_FENCES_AVAIL;
3262 gp.value = &bufmgr_gem->available_fences;
3263 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3265 fprintf(stderr, "get fences failed: %d [%d]\n", ret,
3267 fprintf(stderr, "param: %d, val: %d\n", gp.param,
3269 bufmgr_gem->available_fences = 0;
3271 /* XXX The kernel reports the total number of fences,
3272 * including any that may be pinned.
3274 * We presume that there will be at least one pinned
3275 * fence for the scanout buffer, but there may be more
3276 * than one scanout and the user may be manually
3277 * pinning buffers. Let's move to execbuffer2 and
3278 * thereby forget the insanity of using fences...
3280 bufmgr_gem->available_fences -= 2;
3281 if (bufmgr_gem->available_fences < 0)
3282 bufmgr_gem->available_fences = 0;
3286 /* Let's go with one relocation per every 2 dwords (but round down a bit
3287 * since a power of two will mean an extra page allocation for the reloc
3290 * Every 4 was too few for the blender benchmark.
3292 bufmgr_gem->max_relocs = batch_size / sizeof(uint32_t) / 2 - 2;
3294 bufmgr_gem->bufmgr.bo_alloc = drm_intel_gem_bo_alloc;
3295 bufmgr_gem->bufmgr.bo_alloc_for_render =
3296 drm_intel_gem_bo_alloc_for_render;
3297 bufmgr_gem->bufmgr.bo_alloc_tiled = drm_intel_gem_bo_alloc_tiled;
3298 bufmgr_gem->bufmgr.bo_reference = drm_intel_gem_bo_reference;
3299 bufmgr_gem->bufmgr.bo_unreference = drm_intel_gem_bo_unreference;
3300 bufmgr_gem->bufmgr.bo_map = drm_intel_gem_bo_map;
3301 bufmgr_gem->bufmgr.bo_unmap = drm_intel_gem_bo_unmap;
3302 bufmgr_gem->bufmgr.bo_subdata = drm_intel_gem_bo_subdata;
3303 bufmgr_gem->bufmgr.bo_get_subdata = drm_intel_gem_bo_get_subdata;
3304 bufmgr_gem->bufmgr.bo_wait_rendering = drm_intel_gem_bo_wait_rendering;
3305 bufmgr_gem->bufmgr.bo_emit_reloc = drm_intel_gem_bo_emit_reloc;
3306 bufmgr_gem->bufmgr.bo_emit_reloc_fence = drm_intel_gem_bo_emit_reloc_fence;
3307 bufmgr_gem->bufmgr.bo_pin = drm_intel_gem_bo_pin;
3308 bufmgr_gem->bufmgr.bo_unpin = drm_intel_gem_bo_unpin;
3309 bufmgr_gem->bufmgr.bo_get_tiling = drm_intel_gem_bo_get_tiling;
3310 bufmgr_gem->bufmgr.bo_set_tiling = drm_intel_gem_bo_set_tiling;
3311 bufmgr_gem->bufmgr.bo_flink = drm_intel_gem_bo_flink;
3312 /* Use the new one if available */
3314 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec2;
3315 bufmgr_gem->bufmgr.bo_mrb_exec = drm_intel_gem_bo_mrb_exec2;
3317 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec;
3318 bufmgr_gem->bufmgr.bo_busy = drm_intel_gem_bo_busy;
3319 bufmgr_gem->bufmgr.bo_madvise = drm_intel_gem_bo_madvise;
3320 bufmgr_gem->bufmgr.destroy = drm_intel_bufmgr_gem_unref;
3321 bufmgr_gem->bufmgr.debug = 0;
3322 bufmgr_gem->bufmgr.check_aperture_space =
3323 drm_intel_gem_check_aperture_space;
3324 bufmgr_gem->bufmgr.bo_disable_reuse = drm_intel_gem_bo_disable_reuse;
3325 bufmgr_gem->bufmgr.bo_is_reusable = drm_intel_gem_bo_is_reusable;
3326 bufmgr_gem->bufmgr.get_pipe_from_crtc_id =
3327 drm_intel_gem_get_pipe_from_crtc_id;
3328 bufmgr_gem->bufmgr.bo_references = drm_intel_gem_bo_references;
3330 DRMINITLISTHEAD(&bufmgr_gem->named);
3331 init_cache_buckets(bufmgr_gem);
3333 DRMINITLISTHEAD(&bufmgr_gem->vma_cache);
3334 bufmgr_gem->vma_max = -1; /* unlimited by default */
3336 DRMLISTADD(&bufmgr_gem->managers, &bufmgr_list);
3339 pthread_mutex_unlock(&bufmgr_list_mutex);
3341 return bufmgr_gem != NULL ? &bufmgr_gem->bufmgr : NULL;