1 /**************************************************************************
3 * Copyright © 2007 Red Hat Inc.
4 * Copyright © 2007 Intel Corporation
5 * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
29 **************************************************************************/
31 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
32 * Keith Whitwell <keithw-at-tungstengraphics-dot-com>
33 * Eric Anholt <eric@anholt.net>
34 * Dave Airlie <airlied@linux.ie>
42 #include <xf86atomic.h>
50 #include <sys/ioctl.h>
53 #include <sys/types.h>
56 #include "libdrm_lists.h"
57 #include "intel_bufmgr.h"
58 #include "intel_bufmgr_priv.h"
59 #include "intel_chipset.h"
64 #define DBG(...) do { \
65 if (bufmgr_gem->bufmgr.debug) \
66 fprintf(stderr, __VA_ARGS__); \
69 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
71 typedef struct _drm_intel_bo_gem drm_intel_bo_gem;
73 struct drm_intel_gem_bo_bucket {
78 typedef struct _drm_intel_bufmgr_gem {
79 drm_intel_bufmgr bufmgr;
87 struct drm_i915_gem_exec_object *exec_objects;
88 struct drm_i915_gem_exec_object2 *exec2_objects;
89 drm_intel_bo **exec_bos;
93 /** Array of lists of cached gem objects of power-of-two sizes */
94 struct drm_intel_gem_bo_bucket cache_bucket[14 * 4];
106 } drm_intel_bufmgr_gem;
108 #define DRM_INTEL_RELOC_FENCE (1<<0)
110 typedef struct _drm_intel_reloc_target_info {
113 } drm_intel_reloc_target;
115 struct _drm_intel_bo_gem {
123 * Kenel-assigned global name for this object
125 unsigned int global_name;
128 * Index of the buffer within the validation list while preparing a
129 * batchbuffer execution.
134 * Current tiling mode
136 uint32_t tiling_mode;
137 uint32_t swizzle_mode;
138 unsigned long stride;
142 /** Array passed to the DRM containing relocation information. */
143 struct drm_i915_gem_relocation_entry *relocs;
145 * Array of info structs corresponding to relocs[i].target_handle etc
147 drm_intel_reloc_target *reloc_target_info;
148 /** Number of entries in relocs */
150 /** Mapped address for the buffer, saved across map/unmap cycles */
152 /** GTT virtual address for the buffer, saved across map/unmap cycles */
159 * Boolean of whether this BO and its children have been included in
160 * the current drm_intel_bufmgr_check_aperture_space() total.
162 char included_in_check_aperture;
165 * Boolean of whether this buffer has been used as a relocation
166 * target and had its size accounted for, and thus can't have any
167 * further relocations added to it.
169 char used_as_reloc_target;
172 * Boolean of whether we have encountered an error whilst building the relocation tree.
177 * Boolean of whether this buffer can be re-used
182 * Size in bytes of this buffer and its relocation descendents.
184 * Used to avoid costly tree walking in
185 * drm_intel_bufmgr_check_aperture in the common case.
190 * Number of potential fence registers required by this buffer and its
193 int reloc_tree_fences;
197 drm_intel_gem_estimate_batch_space(drm_intel_bo ** bo_array, int count);
200 drm_intel_gem_compute_batch_space(drm_intel_bo ** bo_array, int count);
203 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
204 uint32_t * swizzle_mode);
207 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
208 uint32_t tiling_mode,
211 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
214 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo);
216 static void drm_intel_gem_bo_free(drm_intel_bo *bo);
219 drm_intel_gem_bo_tile_size(drm_intel_bufmgr_gem *bufmgr_gem, unsigned long size,
220 uint32_t *tiling_mode)
222 unsigned long min_size, max_size;
225 if (*tiling_mode == I915_TILING_NONE)
228 /* 965+ just need multiples of page size for tiling */
229 if (bufmgr_gem->gen >= 4)
230 return ROUND_UP_TO(size, 4096);
232 /* Older chips need powers of two, of at least 512k or 1M */
233 if (bufmgr_gem->gen == 3) {
234 min_size = 1024*1024;
235 max_size = 128*1024*1024;
238 max_size = 64*1024*1024;
241 if (size > max_size) {
242 *tiling_mode = I915_TILING_NONE;
246 for (i = min_size; i < size; i <<= 1)
253 * Round a given pitch up to the minimum required for X tiling on a
254 * given chip. We use 512 as the minimum to allow for a later tiling
258 drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem,
259 unsigned long pitch, uint32_t *tiling_mode)
261 unsigned long tile_width;
264 /* If untiled, then just align it so that we can do rendering
265 * to it with the 3D engine.
267 if (*tiling_mode == I915_TILING_NONE)
268 return ALIGN(pitch, 64);
270 if (*tiling_mode == I915_TILING_X)
275 /* 965 is flexible */
276 if (bufmgr_gem->gen >= 4)
277 return ROUND_UP_TO(pitch, tile_width);
279 /* The older hardware has a maximum pitch of 8192 with tiled
280 * surfaces, so fallback to untiled if it's too large.
283 *tiling_mode = I915_TILING_NONE;
284 return ALIGN(pitch, 64);
287 /* Pre-965 needs power of two tile width */
288 for (i = tile_width; i < pitch; i <<= 1)
294 static struct drm_intel_gem_bo_bucket *
295 drm_intel_gem_bo_bucket_for_size(drm_intel_bufmgr_gem *bufmgr_gem,
300 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
301 struct drm_intel_gem_bo_bucket *bucket =
302 &bufmgr_gem->cache_bucket[i];
303 if (bucket->size >= size) {
312 drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem *bufmgr_gem)
316 for (i = 0; i < bufmgr_gem->exec_count; i++) {
317 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
318 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
320 if (bo_gem->relocs == NULL) {
321 DBG("%2d: %d (%s)\n", i, bo_gem->gem_handle,
326 for (j = 0; j < bo_gem->reloc_count; j++) {
327 drm_intel_bo *target_bo = bo_gem->reloc_target_info[j].bo;
328 drm_intel_bo_gem *target_gem =
329 (drm_intel_bo_gem *) target_bo;
331 DBG("%2d: %d (%s)@0x%08llx -> "
332 "%d (%s)@0x%08lx + 0x%08x\n",
334 bo_gem->gem_handle, bo_gem->name,
335 (unsigned long long)bo_gem->relocs[j].offset,
336 target_gem->gem_handle,
339 bo_gem->relocs[j].delta);
345 drm_intel_gem_bo_reference(drm_intel_bo *bo)
347 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
349 assert(atomic_read(&bo_gem->refcount) > 0);
350 atomic_inc(&bo_gem->refcount);
354 * Adds the given buffer to the list of buffers to be validated (moved into the
355 * appropriate memory type) with the next batch submission.
357 * If a buffer is validated multiple times in a batch submission, it ends up
358 * with the intersection of the memory type flags and the union of the
362 drm_intel_add_validate_buffer(drm_intel_bo *bo)
364 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
365 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
368 if (bo_gem->validate_index != -1)
371 /* Extend the array of validation entries as necessary. */
372 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
373 int new_size = bufmgr_gem->exec_size * 2;
378 bufmgr_gem->exec_objects =
379 realloc(bufmgr_gem->exec_objects,
380 sizeof(*bufmgr_gem->exec_objects) * new_size);
381 bufmgr_gem->exec_bos =
382 realloc(bufmgr_gem->exec_bos,
383 sizeof(*bufmgr_gem->exec_bos) * new_size);
384 bufmgr_gem->exec_size = new_size;
387 index = bufmgr_gem->exec_count;
388 bo_gem->validate_index = index;
389 /* Fill in array entry */
390 bufmgr_gem->exec_objects[index].handle = bo_gem->gem_handle;
391 bufmgr_gem->exec_objects[index].relocation_count = bo_gem->reloc_count;
392 bufmgr_gem->exec_objects[index].relocs_ptr = (uintptr_t) bo_gem->relocs;
393 bufmgr_gem->exec_objects[index].alignment = 0;
394 bufmgr_gem->exec_objects[index].offset = 0;
395 bufmgr_gem->exec_bos[index] = bo;
396 bufmgr_gem->exec_count++;
400 drm_intel_add_validate_buffer2(drm_intel_bo *bo, int need_fence)
402 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
403 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
406 if (bo_gem->validate_index != -1) {
408 bufmgr_gem->exec2_objects[bo_gem->validate_index].flags |=
409 EXEC_OBJECT_NEEDS_FENCE;
413 /* Extend the array of validation entries as necessary. */
414 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
415 int new_size = bufmgr_gem->exec_size * 2;
420 bufmgr_gem->exec2_objects =
421 realloc(bufmgr_gem->exec2_objects,
422 sizeof(*bufmgr_gem->exec2_objects) * new_size);
423 bufmgr_gem->exec_bos =
424 realloc(bufmgr_gem->exec_bos,
425 sizeof(*bufmgr_gem->exec_bos) * new_size);
426 bufmgr_gem->exec_size = new_size;
429 index = bufmgr_gem->exec_count;
430 bo_gem->validate_index = index;
431 /* Fill in array entry */
432 bufmgr_gem->exec2_objects[index].handle = bo_gem->gem_handle;
433 bufmgr_gem->exec2_objects[index].relocation_count = bo_gem->reloc_count;
434 bufmgr_gem->exec2_objects[index].relocs_ptr = (uintptr_t)bo_gem->relocs;
435 bufmgr_gem->exec2_objects[index].alignment = 0;
436 bufmgr_gem->exec2_objects[index].offset = 0;
437 bufmgr_gem->exec_bos[index] = bo;
438 bufmgr_gem->exec2_objects[index].flags = 0;
439 bufmgr_gem->exec2_objects[index].rsvd1 = 0;
440 bufmgr_gem->exec2_objects[index].rsvd2 = 0;
442 bufmgr_gem->exec2_objects[index].flags |=
443 EXEC_OBJECT_NEEDS_FENCE;
445 bufmgr_gem->exec_count++;
448 #define RELOC_BUF_SIZE(x) ((I915_RELOC_HEADER + x * I915_RELOC0_STRIDE) * \
452 drm_intel_bo_gem_set_in_aperture_size(drm_intel_bufmgr_gem *bufmgr_gem,
453 drm_intel_bo_gem *bo_gem)
457 assert(!bo_gem->used_as_reloc_target);
459 /* The older chipsets are far-less flexible in terms of tiling,
460 * and require tiled buffer to be size aligned in the aperture.
461 * This means that in the worst possible case we will need a hole
462 * twice as large as the object in order for it to fit into the
463 * aperture. Optimal packing is for wimps.
465 size = bo_gem->bo.size;
466 if (bufmgr_gem->gen < 4 && bo_gem->tiling_mode != I915_TILING_NONE)
469 bo_gem->reloc_tree_size = size;
473 drm_intel_setup_reloc_list(drm_intel_bo *bo)
475 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
476 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
477 unsigned int max_relocs = bufmgr_gem->max_relocs;
479 if (bo->size / 4 < max_relocs)
480 max_relocs = bo->size / 4;
482 bo_gem->relocs = malloc(max_relocs *
483 sizeof(struct drm_i915_gem_relocation_entry));
484 bo_gem->reloc_target_info = malloc(max_relocs *
485 sizeof(drm_intel_reloc_target));
486 if (bo_gem->relocs == NULL || bo_gem->reloc_target_info == NULL) {
487 bo_gem->has_error = 1;
489 free (bo_gem->relocs);
490 bo_gem->relocs = NULL;
492 free (bo_gem->reloc_target_info);
493 bo_gem->reloc_target_info = NULL;
502 drm_intel_gem_bo_busy(drm_intel_bo *bo)
504 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
505 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
506 struct drm_i915_gem_busy busy;
509 memset(&busy, 0, sizeof(busy));
510 busy.handle = bo_gem->gem_handle;
512 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_BUSY, &busy);
514 return (ret == 0 && busy.busy);
518 drm_intel_gem_bo_madvise_internal(drm_intel_bufmgr_gem *bufmgr_gem,
519 drm_intel_bo_gem *bo_gem, int state)
521 struct drm_i915_gem_madvise madv;
523 madv.handle = bo_gem->gem_handle;
526 drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MADVISE, &madv);
528 return madv.retained;
532 drm_intel_gem_bo_madvise(drm_intel_bo *bo, int madv)
534 return drm_intel_gem_bo_madvise_internal
535 ((drm_intel_bufmgr_gem *) bo->bufmgr,
536 (drm_intel_bo_gem *) bo,
540 /* drop the oldest entries that have been purged by the kernel */
542 drm_intel_gem_bo_cache_purge_bucket(drm_intel_bufmgr_gem *bufmgr_gem,
543 struct drm_intel_gem_bo_bucket *bucket)
545 while (!DRMLISTEMPTY(&bucket->head)) {
546 drm_intel_bo_gem *bo_gem;
548 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
549 bucket->head.next, head);
550 if (drm_intel_gem_bo_madvise_internal
551 (bufmgr_gem, bo_gem, I915_MADV_DONTNEED))
554 DRMLISTDEL(&bo_gem->head);
555 drm_intel_gem_bo_free(&bo_gem->bo);
559 static drm_intel_bo *
560 drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr,
564 uint32_t tiling_mode,
565 unsigned long stride)
567 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
568 drm_intel_bo_gem *bo_gem;
569 unsigned int page_size = getpagesize();
571 struct drm_intel_gem_bo_bucket *bucket;
572 int alloc_from_cache;
573 unsigned long bo_size;
576 if (flags & BO_ALLOC_FOR_RENDER)
579 /* Round the allocated size up to a power of two number of pages. */
580 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, size);
582 /* If we don't have caching at this size, don't actually round the
585 if (bucket == NULL) {
587 if (bo_size < page_size)
590 bo_size = bucket->size;
593 pthread_mutex_lock(&bufmgr_gem->lock);
594 /* Get a buffer out of the cache if available */
596 alloc_from_cache = 0;
597 if (bucket != NULL && !DRMLISTEMPTY(&bucket->head)) {
599 /* Allocate new render-target BOs from the tail (MRU)
600 * of the list, as it will likely be hot in the GPU
601 * cache and in the aperture for us.
603 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
604 bucket->head.prev, head);
605 DRMLISTDEL(&bo_gem->head);
606 alloc_from_cache = 1;
608 /* For non-render-target BOs (where we're probably
609 * going to map it first thing in order to fill it
610 * with data), check if the last BO in the cache is
611 * unbusy, and only reuse in that case. Otherwise,
612 * allocating a new buffer is probably faster than
613 * waiting for the GPU to finish.
615 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
616 bucket->head.next, head);
617 if (!drm_intel_gem_bo_busy(&bo_gem->bo)) {
618 alloc_from_cache = 1;
619 DRMLISTDEL(&bo_gem->head);
623 if (alloc_from_cache) {
624 if (!drm_intel_gem_bo_madvise_internal
625 (bufmgr_gem, bo_gem, I915_MADV_WILLNEED)) {
626 drm_intel_gem_bo_free(&bo_gem->bo);
627 drm_intel_gem_bo_cache_purge_bucket(bufmgr_gem,
632 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
635 drm_intel_gem_bo_free(&bo_gem->bo);
640 pthread_mutex_unlock(&bufmgr_gem->lock);
642 if (!alloc_from_cache) {
643 struct drm_i915_gem_create create;
645 bo_gem = calloc(1, sizeof(*bo_gem));
649 bo_gem->bo.size = bo_size;
650 memset(&create, 0, sizeof(create));
651 create.size = bo_size;
653 ret = drmIoctl(bufmgr_gem->fd,
654 DRM_IOCTL_I915_GEM_CREATE,
656 bo_gem->gem_handle = create.handle;
657 bo_gem->bo.handle = bo_gem->gem_handle;
662 bo_gem->bo.bufmgr = bufmgr;
664 bo_gem->tiling_mode = I915_TILING_NONE;
665 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
668 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
671 drm_intel_gem_bo_free(&bo_gem->bo);
677 atomic_set(&bo_gem->refcount, 1);
678 bo_gem->validate_index = -1;
679 bo_gem->reloc_tree_fences = 0;
680 bo_gem->used_as_reloc_target = 0;
681 bo_gem->has_error = 0;
682 bo_gem->reusable = 1;
684 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
686 DBG("bo_create: buf %d (%s) %ldb\n",
687 bo_gem->gem_handle, bo_gem->name, size);
692 static drm_intel_bo *
693 drm_intel_gem_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
696 unsigned int alignment)
698 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size,
700 I915_TILING_NONE, 0);
703 static drm_intel_bo *
704 drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr,
707 unsigned int alignment)
709 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, 0,
710 I915_TILING_NONE, 0);
713 static drm_intel_bo *
714 drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
715 int x, int y, int cpp, uint32_t *tiling_mode,
716 unsigned long *pitch, unsigned long flags)
718 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
719 unsigned long size, stride;
723 unsigned long aligned_y;
725 tiling = *tiling_mode;
727 /* If we're tiled, our allocations are in 8 or 32-row blocks,
728 * so failure to align our height means that we won't allocate
731 * If we're untiled, we still have to align to 2 rows high
732 * because the data port accesses 2x2 blocks even if the
733 * bottom row isn't to be rendered, so failure to align means
734 * we could walk off the end of the GTT and fault. This is
735 * documented on 965, and may be the case on older chipsets
736 * too so we try to be careful.
739 if (tiling == I915_TILING_NONE)
740 aligned_y = ALIGN(y, 2);
741 else if (tiling == I915_TILING_X)
742 aligned_y = ALIGN(y, 8);
743 else if (tiling == I915_TILING_Y)
744 aligned_y = ALIGN(y, 32);
747 stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, tiling_mode);
748 size = stride * aligned_y;
749 size = drm_intel_gem_bo_tile_size(bufmgr_gem, size, tiling_mode);
750 } while (*tiling_mode != tiling);
753 if (tiling == I915_TILING_NONE)
756 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, flags,
761 * Returns a drm_intel_bo wrapping the given buffer object handle.
763 * This can be used when one application needs to pass a buffer object
767 drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
771 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
772 drm_intel_bo_gem *bo_gem;
774 struct drm_gem_open open_arg;
775 struct drm_i915_gem_get_tiling get_tiling;
777 bo_gem = calloc(1, sizeof(*bo_gem));
781 memset(&open_arg, 0, sizeof(open_arg));
782 open_arg.name = handle;
783 ret = drmIoctl(bufmgr_gem->fd,
787 DBG("Couldn't reference %s handle 0x%08x: %s\n",
788 name, handle, strerror(errno));
792 bo_gem->bo.size = open_arg.size;
793 bo_gem->bo.offset = 0;
794 bo_gem->bo.virtual = NULL;
795 bo_gem->bo.bufmgr = bufmgr;
797 atomic_set(&bo_gem->refcount, 1);
798 bo_gem->validate_index = -1;
799 bo_gem->gem_handle = open_arg.handle;
800 bo_gem->global_name = handle;
801 bo_gem->reusable = 0;
803 memset(&get_tiling, 0, sizeof(get_tiling));
804 get_tiling.handle = bo_gem->gem_handle;
805 ret = drmIoctl(bufmgr_gem->fd,
806 DRM_IOCTL_I915_GEM_GET_TILING,
809 drm_intel_gem_bo_unreference(&bo_gem->bo);
812 bo_gem->tiling_mode = get_tiling.tiling_mode;
813 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
814 /* XXX stride is unknown */
815 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
817 DBG("bo_create_from_handle: %d (%s)\n", handle, bo_gem->name);
823 drm_intel_gem_bo_free(drm_intel_bo *bo)
825 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
826 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
827 struct drm_gem_close close;
830 if (bo_gem->mem_virtual)
831 munmap(bo_gem->mem_virtual, bo_gem->bo.size);
832 if (bo_gem->gtt_virtual)
833 munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
835 /* Close this object */
836 memset(&close, 0, sizeof(close));
837 close.handle = bo_gem->gem_handle;
838 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close);
840 DBG("DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
841 bo_gem->gem_handle, bo_gem->name, strerror(errno));
846 /** Frees all cached buffers significantly older than @time. */
848 drm_intel_gem_cleanup_bo_cache(drm_intel_bufmgr_gem *bufmgr_gem, time_t time)
852 if (bufmgr_gem->time == time)
855 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
856 struct drm_intel_gem_bo_bucket *bucket =
857 &bufmgr_gem->cache_bucket[i];
859 while (!DRMLISTEMPTY(&bucket->head)) {
860 drm_intel_bo_gem *bo_gem;
862 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
863 bucket->head.next, head);
864 if (time - bo_gem->free_time <= 1)
867 DRMLISTDEL(&bo_gem->head);
869 drm_intel_gem_bo_free(&bo_gem->bo);
873 bufmgr_gem->time = time;
877 drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time)
879 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
880 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
881 struct drm_intel_gem_bo_bucket *bucket;
884 /* Unreference all the target buffers */
885 for (i = 0; i < bo_gem->reloc_count; i++) {
886 if (bo_gem->reloc_target_info[i].bo != bo) {
887 drm_intel_gem_bo_unreference_locked_timed(bo_gem->
888 reloc_target_info[i].bo,
892 bo_gem->reloc_count = 0;
893 bo_gem->used_as_reloc_target = 0;
895 DBG("bo_unreference final: %d (%s)\n",
896 bo_gem->gem_handle, bo_gem->name);
898 /* release memory associated with this object */
899 if (bo_gem->reloc_target_info) {
900 free(bo_gem->reloc_target_info);
901 bo_gem->reloc_target_info = NULL;
903 if (bo_gem->relocs) {
904 free(bo_gem->relocs);
905 bo_gem->relocs = NULL;
908 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, bo->size);
909 /* Put the buffer into our internal cache for reuse if we can. */
910 if (bufmgr_gem->bo_reuse && bo_gem->reusable && bucket != NULL &&
911 drm_intel_gem_bo_madvise_internal(bufmgr_gem, bo_gem,
912 I915_MADV_DONTNEED)) {
913 bo_gem->free_time = time;
916 bo_gem->validate_index = -1;
918 DRMLISTADDTAIL(&bo_gem->head, &bucket->head);
920 drm_intel_gem_bo_free(bo);
924 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
927 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
929 assert(atomic_read(&bo_gem->refcount) > 0);
930 if (atomic_dec_and_test(&bo_gem->refcount))
931 drm_intel_gem_bo_unreference_final(bo, time);
934 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo)
936 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
938 assert(atomic_read(&bo_gem->refcount) > 0);
939 if (atomic_dec_and_test(&bo_gem->refcount)) {
940 drm_intel_bufmgr_gem *bufmgr_gem =
941 (drm_intel_bufmgr_gem *) bo->bufmgr;
942 struct timespec time;
944 clock_gettime(CLOCK_MONOTONIC, &time);
946 pthread_mutex_lock(&bufmgr_gem->lock);
947 drm_intel_gem_bo_unreference_final(bo, time.tv_sec);
948 drm_intel_gem_cleanup_bo_cache(bufmgr_gem, time.tv_sec);
949 pthread_mutex_unlock(&bufmgr_gem->lock);
953 static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable)
955 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
956 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
957 struct drm_i915_gem_set_domain set_domain;
960 pthread_mutex_lock(&bufmgr_gem->lock);
962 /* Allow recursive mapping. Mesa may recursively map buffers with
963 * nested display loops.
965 if (!bo_gem->mem_virtual) {
966 struct drm_i915_gem_mmap mmap_arg;
968 DBG("bo_map: %d (%s)\n", bo_gem->gem_handle, bo_gem->name);
970 memset(&mmap_arg, 0, sizeof(mmap_arg));
971 mmap_arg.handle = bo_gem->gem_handle;
973 mmap_arg.size = bo->size;
974 ret = drmIoctl(bufmgr_gem->fd,
975 DRM_IOCTL_I915_GEM_MMAP,
979 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
980 __FILE__, __LINE__, bo_gem->gem_handle,
981 bo_gem->name, strerror(errno));
982 pthread_mutex_unlock(&bufmgr_gem->lock);
985 bo_gem->mem_virtual = (void *)(uintptr_t) mmap_arg.addr_ptr;
987 DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
988 bo_gem->mem_virtual);
989 bo->virtual = bo_gem->mem_virtual;
991 set_domain.handle = bo_gem->gem_handle;
992 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
994 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
996 set_domain.write_domain = 0;
997 ret = drmIoctl(bufmgr_gem->fd,
998 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1001 DBG("%s:%d: Error setting to CPU domain %d: %s\n",
1002 __FILE__, __LINE__, bo_gem->gem_handle,
1006 pthread_mutex_unlock(&bufmgr_gem->lock);
1011 int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
1013 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1014 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1015 struct drm_i915_gem_set_domain set_domain;
1018 pthread_mutex_lock(&bufmgr_gem->lock);
1020 /* Get a mapping of the buffer if we haven't before. */
1021 if (bo_gem->gtt_virtual == NULL) {
1022 struct drm_i915_gem_mmap_gtt mmap_arg;
1024 DBG("bo_map_gtt: mmap %d (%s)\n", bo_gem->gem_handle,
1027 memset(&mmap_arg, 0, sizeof(mmap_arg));
1028 mmap_arg.handle = bo_gem->gem_handle;
1030 /* Get the fake offset back... */
1031 ret = drmIoctl(bufmgr_gem->fd,
1032 DRM_IOCTL_I915_GEM_MMAP_GTT,
1036 DBG("%s:%d: Error preparing buffer map %d (%s): %s .\n",
1038 bo_gem->gem_handle, bo_gem->name,
1040 pthread_mutex_unlock(&bufmgr_gem->lock);
1045 bo_gem->gtt_virtual = mmap(0, bo->size, PROT_READ | PROT_WRITE,
1046 MAP_SHARED, bufmgr_gem->fd,
1048 if (bo_gem->gtt_virtual == MAP_FAILED) {
1049 bo_gem->gtt_virtual = NULL;
1051 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1053 bo_gem->gem_handle, bo_gem->name,
1055 pthread_mutex_unlock(&bufmgr_gem->lock);
1060 bo->virtual = bo_gem->gtt_virtual;
1062 DBG("bo_map_gtt: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1063 bo_gem->gtt_virtual);
1065 /* Now move it to the GTT domain so that the CPU caches are flushed */
1066 set_domain.handle = bo_gem->gem_handle;
1067 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1068 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
1069 ret = drmIoctl(bufmgr_gem->fd,
1070 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1073 DBG("%s:%d: Error setting domain %d: %s\n",
1074 __FILE__, __LINE__, bo_gem->gem_handle,
1078 pthread_mutex_unlock(&bufmgr_gem->lock);
1083 int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo)
1085 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1086 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1092 assert(bo_gem->gtt_virtual != NULL);
1094 pthread_mutex_lock(&bufmgr_gem->lock);
1096 pthread_mutex_unlock(&bufmgr_gem->lock);
1101 static int drm_intel_gem_bo_unmap(drm_intel_bo *bo)
1103 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1104 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1105 struct drm_i915_gem_sw_finish sw_finish;
1111 assert(bo_gem->mem_virtual != NULL);
1113 pthread_mutex_lock(&bufmgr_gem->lock);
1115 /* Cause a flush to happen if the buffer's pinned for scanout, so the
1116 * results show up in a timely manner.
1118 sw_finish.handle = bo_gem->gem_handle;
1119 ret = drmIoctl(bufmgr_gem->fd,
1120 DRM_IOCTL_I915_GEM_SW_FINISH,
1122 ret = ret == -1 ? -errno : 0;
1125 pthread_mutex_unlock(&bufmgr_gem->lock);
1131 drm_intel_gem_bo_subdata(drm_intel_bo *bo, unsigned long offset,
1132 unsigned long size, const void *data)
1134 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1135 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1136 struct drm_i915_gem_pwrite pwrite;
1139 memset(&pwrite, 0, sizeof(pwrite));
1140 pwrite.handle = bo_gem->gem_handle;
1141 pwrite.offset = offset;
1143 pwrite.data_ptr = (uint64_t) (uintptr_t) data;
1144 ret = drmIoctl(bufmgr_gem->fd,
1145 DRM_IOCTL_I915_GEM_PWRITE,
1149 DBG("%s:%d: Error writing data to buffer %d: (%d %d) %s .\n",
1150 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1151 (int)size, strerror(errno));
1158 drm_intel_gem_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id)
1160 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1161 struct drm_i915_get_pipe_from_crtc_id get_pipe_from_crtc_id;
1164 get_pipe_from_crtc_id.crtc_id = crtc_id;
1165 ret = drmIoctl(bufmgr_gem->fd,
1166 DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID,
1167 &get_pipe_from_crtc_id);
1169 /* We return -1 here to signal that we don't
1170 * know which pipe is associated with this crtc.
1171 * This lets the caller know that this information
1172 * isn't available; using the wrong pipe for
1173 * vblank waiting can cause the chipset to lock up
1178 return get_pipe_from_crtc_id.pipe;
1182 drm_intel_gem_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
1183 unsigned long size, void *data)
1185 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1186 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1187 struct drm_i915_gem_pread pread;
1190 memset(&pread, 0, sizeof(pread));
1191 pread.handle = bo_gem->gem_handle;
1192 pread.offset = offset;
1194 pread.data_ptr = (uint64_t) (uintptr_t) data;
1195 ret = drmIoctl(bufmgr_gem->fd,
1196 DRM_IOCTL_I915_GEM_PREAD,
1200 DBG("%s:%d: Error reading data from buffer %d: (%d %d) %s .\n",
1201 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1202 (int)size, strerror(errno));
1208 /** Waits for all GPU rendering to the object to have completed. */
1210 drm_intel_gem_bo_wait_rendering(drm_intel_bo *bo)
1212 drm_intel_gem_bo_start_gtt_access(bo, 0);
1216 * Sets the object to the GTT read and possibly write domain, used by the X
1217 * 2D driver in the absence of kernel support to do drm_intel_gem_bo_map_gtt().
1219 * In combination with drm_intel_gem_bo_pin() and manual fence management, we
1220 * can do tiled pixmaps this way.
1223 drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable)
1225 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1226 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1227 struct drm_i915_gem_set_domain set_domain;
1230 set_domain.handle = bo_gem->gem_handle;
1231 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1232 set_domain.write_domain = write_enable ? I915_GEM_DOMAIN_GTT : 0;
1233 ret = drmIoctl(bufmgr_gem->fd,
1234 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1237 DBG("%s:%d: Error setting memory domains %d (%08x %08x): %s .\n",
1238 __FILE__, __LINE__, bo_gem->gem_handle,
1239 set_domain.read_domains, set_domain.write_domain,
1245 drm_intel_bufmgr_gem_destroy(drm_intel_bufmgr *bufmgr)
1247 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1250 free(bufmgr_gem->exec2_objects);
1251 free(bufmgr_gem->exec_objects);
1252 free(bufmgr_gem->exec_bos);
1254 pthread_mutex_destroy(&bufmgr_gem->lock);
1256 /* Free any cached buffer objects we were going to reuse */
1257 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
1258 struct drm_intel_gem_bo_bucket *bucket =
1259 &bufmgr_gem->cache_bucket[i];
1260 drm_intel_bo_gem *bo_gem;
1262 while (!DRMLISTEMPTY(&bucket->head)) {
1263 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1264 bucket->head.next, head);
1265 DRMLISTDEL(&bo_gem->head);
1267 drm_intel_gem_bo_free(&bo_gem->bo);
1275 * Adds the target buffer to the validation list and adds the relocation
1276 * to the reloc_buffer's relocation list.
1278 * The relocation entry at the given offset must already contain the
1279 * precomputed relocation value, because the kernel will optimize out
1280 * the relocation entry write when the buffer hasn't moved from the
1281 * last known offset in target_bo.
1284 do_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1285 drm_intel_bo *target_bo, uint32_t target_offset,
1286 uint32_t read_domains, uint32_t write_domain,
1289 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1290 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1291 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
1293 if (bo_gem->has_error)
1296 if (target_bo_gem->has_error) {
1297 bo_gem->has_error = 1;
1301 if (target_bo_gem->tiling_mode == I915_TILING_NONE)
1304 /* We never use HW fences for rendering on 965+ */
1305 if (bufmgr_gem->gen >= 4)
1308 /* Create a new relocation list if needed */
1309 if (bo_gem->relocs == NULL && drm_intel_setup_reloc_list(bo))
1312 /* Check overflow */
1313 assert(bo_gem->reloc_count < bufmgr_gem->max_relocs);
1316 assert(offset <= bo->size - 4);
1317 assert((write_domain & (write_domain - 1)) == 0);
1319 /* Make sure that we're not adding a reloc to something whose size has
1320 * already been accounted for.
1322 assert(!bo_gem->used_as_reloc_target);
1323 if (target_bo_gem != bo_gem) {
1324 target_bo_gem->used_as_reloc_target = 1;
1325 bo_gem->reloc_tree_size += target_bo_gem->reloc_tree_size;
1327 /* An object needing a fence is a tiled buffer, so it won't have
1328 * relocs to other buffers.
1331 target_bo_gem->reloc_tree_fences = 1;
1332 bo_gem->reloc_tree_fences += target_bo_gem->reloc_tree_fences;
1334 /* Flag the target to disallow further relocations in it. */
1336 bo_gem->relocs[bo_gem->reloc_count].offset = offset;
1337 bo_gem->relocs[bo_gem->reloc_count].delta = target_offset;
1338 bo_gem->relocs[bo_gem->reloc_count].target_handle =
1339 target_bo_gem->gem_handle;
1340 bo_gem->relocs[bo_gem->reloc_count].read_domains = read_domains;
1341 bo_gem->relocs[bo_gem->reloc_count].write_domain = write_domain;
1342 bo_gem->relocs[bo_gem->reloc_count].presumed_offset = target_bo->offset;
1344 bo_gem->reloc_target_info[bo_gem->reloc_count].bo = target_bo;
1345 if (target_bo != bo)
1346 drm_intel_gem_bo_reference(target_bo);
1348 bo_gem->reloc_target_info[bo_gem->reloc_count].flags =
1349 DRM_INTEL_RELOC_FENCE;
1351 bo_gem->reloc_target_info[bo_gem->reloc_count].flags = 0;
1353 bo_gem->reloc_count++;
1359 drm_intel_gem_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1360 drm_intel_bo *target_bo, uint32_t target_offset,
1361 uint32_t read_domains, uint32_t write_domain)
1363 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1365 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1366 read_domains, write_domain,
1367 !bufmgr_gem->fenced_relocs);
1371 drm_intel_gem_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
1372 drm_intel_bo *target_bo,
1373 uint32_t target_offset,
1374 uint32_t read_domains, uint32_t write_domain)
1376 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1377 read_domains, write_domain, 1);
1381 * Walk the tree of relocations rooted at BO and accumulate the list of
1382 * validations to be performed and update the relocation buffers with
1383 * index values into the validation list.
1386 drm_intel_gem_bo_process_reloc(drm_intel_bo *bo)
1388 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1391 if (bo_gem->relocs == NULL)
1394 for (i = 0; i < bo_gem->reloc_count; i++) {
1395 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1397 if (target_bo == bo)
1400 /* Continue walking the tree depth-first. */
1401 drm_intel_gem_bo_process_reloc(target_bo);
1403 /* Add the target to the validate list */
1404 drm_intel_add_validate_buffer(target_bo);
1409 drm_intel_gem_bo_process_reloc2(drm_intel_bo *bo)
1411 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1414 if (bo_gem->relocs == NULL)
1417 for (i = 0; i < bo_gem->reloc_count; i++) {
1418 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1421 if (target_bo == bo)
1424 /* Continue walking the tree depth-first. */
1425 drm_intel_gem_bo_process_reloc2(target_bo);
1427 need_fence = (bo_gem->reloc_target_info[i].flags &
1428 DRM_INTEL_RELOC_FENCE);
1430 /* Add the target to the validate list */
1431 drm_intel_add_validate_buffer2(target_bo, need_fence);
1437 drm_intel_update_buffer_offsets(drm_intel_bufmgr_gem *bufmgr_gem)
1441 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1442 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1443 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1445 /* Update the buffer offset */
1446 if (bufmgr_gem->exec_objects[i].offset != bo->offset) {
1447 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1448 bo_gem->gem_handle, bo_gem->name, bo->offset,
1449 (unsigned long long)bufmgr_gem->exec_objects[i].
1451 bo->offset = bufmgr_gem->exec_objects[i].offset;
1457 drm_intel_update_buffer_offsets2 (drm_intel_bufmgr_gem *bufmgr_gem)
1461 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1462 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1463 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1465 /* Update the buffer offset */
1466 if (bufmgr_gem->exec2_objects[i].offset != bo->offset) {
1467 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1468 bo_gem->gem_handle, bo_gem->name, bo->offset,
1469 (unsigned long long)bufmgr_gem->exec2_objects[i].offset);
1470 bo->offset = bufmgr_gem->exec2_objects[i].offset;
1476 drm_intel_gem_bo_exec(drm_intel_bo *bo, int used,
1477 drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
1479 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1480 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1481 struct drm_i915_gem_execbuffer execbuf;
1484 if (bo_gem->has_error)
1487 pthread_mutex_lock(&bufmgr_gem->lock);
1488 /* Update indices and set up the validate list. */
1489 drm_intel_gem_bo_process_reloc(bo);
1491 /* Add the batch buffer to the validation list. There are no
1492 * relocations pointing to it.
1494 drm_intel_add_validate_buffer(bo);
1496 execbuf.buffers_ptr = (uintptr_t) bufmgr_gem->exec_objects;
1497 execbuf.buffer_count = bufmgr_gem->exec_count;
1498 execbuf.batch_start_offset = 0;
1499 execbuf.batch_len = used;
1500 execbuf.cliprects_ptr = (uintptr_t) cliprects;
1501 execbuf.num_cliprects = num_cliprects;
1505 ret = drmIoctl(bufmgr_gem->fd,
1506 DRM_IOCTL_I915_GEM_EXECBUFFER,
1510 if (errno == ENOSPC) {
1511 DBG("Execbuffer fails to pin. "
1512 "Estimate: %u. Actual: %u. Available: %u\n",
1513 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
1516 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
1519 (unsigned int)bufmgr_gem->gtt_size);
1522 drm_intel_update_buffer_offsets(bufmgr_gem);
1524 if (bufmgr_gem->bufmgr.debug)
1525 drm_intel_gem_dump_validation_list(bufmgr_gem);
1527 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1528 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1529 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1531 /* Disconnect the buffer from the validate list */
1532 bo_gem->validate_index = -1;
1533 bufmgr_gem->exec_bos[i] = NULL;
1535 bufmgr_gem->exec_count = 0;
1536 pthread_mutex_unlock(&bufmgr_gem->lock);
1542 drm_intel_gem_bo_mrb_exec2(drm_intel_bo *bo, int used,
1543 drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
1546 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1547 struct drm_i915_gem_execbuffer2 execbuf;
1550 switch (ring_flag) {
1554 if (!bufmgr_gem->has_blt)
1558 if (!bufmgr_gem->has_bsd)
1561 case I915_EXEC_RENDER:
1562 case I915_EXEC_DEFAULT:
1566 pthread_mutex_lock(&bufmgr_gem->lock);
1567 /* Update indices and set up the validate list. */
1568 drm_intel_gem_bo_process_reloc2(bo);
1570 /* Add the batch buffer to the validation list. There are no relocations
1573 drm_intel_add_validate_buffer2(bo, 0);
1575 execbuf.buffers_ptr = (uintptr_t)bufmgr_gem->exec2_objects;
1576 execbuf.buffer_count = bufmgr_gem->exec_count;
1577 execbuf.batch_start_offset = 0;
1578 execbuf.batch_len = used;
1579 execbuf.cliprects_ptr = (uintptr_t)cliprects;
1580 execbuf.num_cliprects = num_cliprects;
1583 execbuf.flags = ring_flag;
1587 ret = drmIoctl(bufmgr_gem->fd,
1588 DRM_IOCTL_I915_GEM_EXECBUFFER2,
1592 if (ret == -ENOSPC) {
1593 DBG("Execbuffer fails to pin. "
1594 "Estimate: %u. Actual: %u. Available: %u\n",
1595 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
1596 bufmgr_gem->exec_count),
1597 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
1598 bufmgr_gem->exec_count),
1599 (unsigned int) bufmgr_gem->gtt_size);
1602 drm_intel_update_buffer_offsets2(bufmgr_gem);
1604 if (bufmgr_gem->bufmgr.debug)
1605 drm_intel_gem_dump_validation_list(bufmgr_gem);
1607 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1608 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1609 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1611 /* Disconnect the buffer from the validate list */
1612 bo_gem->validate_index = -1;
1613 bufmgr_gem->exec_bos[i] = NULL;
1615 bufmgr_gem->exec_count = 0;
1616 pthread_mutex_unlock(&bufmgr_gem->lock);
1622 drm_intel_gem_bo_exec2(drm_intel_bo *bo, int used,
1623 drm_clip_rect_t *cliprects, int num_cliprects,
1626 return drm_intel_gem_bo_mrb_exec2(bo, used,
1627 cliprects, num_cliprects, DR4,
1632 drm_intel_gem_bo_pin(drm_intel_bo *bo, uint32_t alignment)
1634 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1635 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1636 struct drm_i915_gem_pin pin;
1639 memset(&pin, 0, sizeof(pin));
1640 pin.handle = bo_gem->gem_handle;
1641 pin.alignment = alignment;
1643 ret = drmIoctl(bufmgr_gem->fd,
1644 DRM_IOCTL_I915_GEM_PIN,
1649 bo->offset = pin.offset;
1654 drm_intel_gem_bo_unpin(drm_intel_bo *bo)
1656 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1657 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1658 struct drm_i915_gem_unpin unpin;
1661 memset(&unpin, 0, sizeof(unpin));
1662 unpin.handle = bo_gem->gem_handle;
1664 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_UNPIN, &unpin);
1672 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
1673 uint32_t tiling_mode,
1676 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1677 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1678 struct drm_i915_gem_set_tiling set_tiling;
1681 if (bo_gem->global_name == 0 &&
1682 tiling_mode == bo_gem->tiling_mode &&
1683 stride == bo_gem->stride)
1686 memset(&set_tiling, 0, sizeof(set_tiling));
1688 /* set_tiling is slightly broken and overwrites the
1689 * input on the error path, so we have to open code
1692 set_tiling.handle = bo_gem->gem_handle;
1693 set_tiling.tiling_mode = tiling_mode;
1694 set_tiling.stride = stride;
1696 ret = ioctl(bufmgr_gem->fd,
1697 DRM_IOCTL_I915_GEM_SET_TILING,
1699 } while (ret == -1 && (errno == EINTR || errno == EAGAIN));
1703 bo_gem->tiling_mode = set_tiling.tiling_mode;
1704 bo_gem->swizzle_mode = set_tiling.swizzle_mode;
1705 bo_gem->stride = set_tiling.stride;
1710 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1713 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1714 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1717 /* Linear buffers have no stride. By ensuring that we only ever use
1718 * stride 0 with linear buffers, we simplify our code.
1720 if (*tiling_mode == I915_TILING_NONE)
1723 ret = drm_intel_gem_bo_set_tiling_internal(bo, *tiling_mode, stride);
1725 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
1727 *tiling_mode = bo_gem->tiling_mode;
1732 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1733 uint32_t * swizzle_mode)
1735 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1737 *tiling_mode = bo_gem->tiling_mode;
1738 *swizzle_mode = bo_gem->swizzle_mode;
1743 drm_intel_gem_bo_flink(drm_intel_bo *bo, uint32_t * name)
1745 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1746 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1747 struct drm_gem_flink flink;
1750 if (!bo_gem->global_name) {
1751 memset(&flink, 0, sizeof(flink));
1752 flink.handle = bo_gem->gem_handle;
1754 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_FLINK, &flink);
1757 bo_gem->global_name = flink.name;
1758 bo_gem->reusable = 0;
1761 *name = bo_gem->global_name;
1766 * Enables unlimited caching of buffer objects for reuse.
1768 * This is potentially very memory expensive, as the cache at each bucket
1769 * size is only bounded by how many buffers of that size we've managed to have
1770 * in flight at once.
1773 drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr)
1775 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1777 bufmgr_gem->bo_reuse = 1;
1781 * Enable use of fenced reloc type.
1783 * New code should enable this to avoid unnecessary fence register
1784 * allocation. If this option is not enabled, all relocs will have fence
1785 * register allocated.
1788 drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr)
1790 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
1792 if (bufmgr_gem->bufmgr.bo_exec == drm_intel_gem_bo_exec2)
1793 bufmgr_gem->fenced_relocs = 1;
1797 * Return the additional aperture space required by the tree of buffer objects
1801 drm_intel_gem_bo_get_aperture_space(drm_intel_bo *bo)
1803 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1807 if (bo == NULL || bo_gem->included_in_check_aperture)
1811 bo_gem->included_in_check_aperture = 1;
1813 for (i = 0; i < bo_gem->reloc_count; i++)
1815 drm_intel_gem_bo_get_aperture_space(bo_gem->
1816 reloc_target_info[i].bo);
1822 * Count the number of buffers in this list that need a fence reg
1824 * If the count is greater than the number of available regs, we'll have
1825 * to ask the caller to resubmit a batch with fewer tiled buffers.
1827 * This function over-counts if the same buffer is used multiple times.
1830 drm_intel_gem_total_fences(drm_intel_bo ** bo_array, int count)
1833 unsigned int total = 0;
1835 for (i = 0; i < count; i++) {
1836 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
1841 total += bo_gem->reloc_tree_fences;
1847 * Clear the flag set by drm_intel_gem_bo_get_aperture_space() so we're ready
1848 * for the next drm_intel_bufmgr_check_aperture_space() call.
1851 drm_intel_gem_bo_clear_aperture_space_flag(drm_intel_bo *bo)
1853 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1856 if (bo == NULL || !bo_gem->included_in_check_aperture)
1859 bo_gem->included_in_check_aperture = 0;
1861 for (i = 0; i < bo_gem->reloc_count; i++)
1862 drm_intel_gem_bo_clear_aperture_space_flag(bo_gem->
1863 reloc_target_info[i].bo);
1867 * Return a conservative estimate for the amount of aperture required
1868 * for a collection of buffers. This may double-count some buffers.
1871 drm_intel_gem_estimate_batch_space(drm_intel_bo **bo_array, int count)
1874 unsigned int total = 0;
1876 for (i = 0; i < count; i++) {
1877 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
1879 total += bo_gem->reloc_tree_size;
1885 * Return the amount of aperture needed for a collection of buffers.
1886 * This avoids double counting any buffers, at the cost of looking
1887 * at every buffer in the set.
1890 drm_intel_gem_compute_batch_space(drm_intel_bo **bo_array, int count)
1893 unsigned int total = 0;
1895 for (i = 0; i < count; i++) {
1896 total += drm_intel_gem_bo_get_aperture_space(bo_array[i]);
1897 /* For the first buffer object in the array, we get an
1898 * accurate count back for its reloc_tree size (since nothing
1899 * had been flagged as being counted yet). We can save that
1900 * value out as a more conservative reloc_tree_size that
1901 * avoids double-counting target buffers. Since the first
1902 * buffer happens to usually be the batch buffer in our
1903 * callers, this can pull us back from doing the tree
1904 * walk on every new batch emit.
1907 drm_intel_bo_gem *bo_gem =
1908 (drm_intel_bo_gem *) bo_array[i];
1909 bo_gem->reloc_tree_size = total;
1913 for (i = 0; i < count; i++)
1914 drm_intel_gem_bo_clear_aperture_space_flag(bo_array[i]);
1919 * Return -1 if the batchbuffer should be flushed before attempting to
1920 * emit rendering referencing the buffers pointed to by bo_array.
1922 * This is required because if we try to emit a batchbuffer with relocations
1923 * to a tree of buffers that won't simultaneously fit in the aperture,
1924 * the rendering will return an error at a point where the software is not
1925 * prepared to recover from it.
1927 * However, we also want to emit the batchbuffer significantly before we reach
1928 * the limit, as a series of batchbuffers each of which references buffers
1929 * covering almost all of the aperture means that at each emit we end up
1930 * waiting to evict a buffer from the last rendering, and we get synchronous
1931 * performance. By emitting smaller batchbuffers, we eat some CPU overhead to
1932 * get better parallelism.
1935 drm_intel_gem_check_aperture_space(drm_intel_bo **bo_array, int count)
1937 drm_intel_bufmgr_gem *bufmgr_gem =
1938 (drm_intel_bufmgr_gem *) bo_array[0]->bufmgr;
1939 unsigned int total = 0;
1940 unsigned int threshold = bufmgr_gem->gtt_size * 3 / 4;
1943 /* Check for fence reg constraints if necessary */
1944 if (bufmgr_gem->available_fences) {
1945 total_fences = drm_intel_gem_total_fences(bo_array, count);
1946 if (total_fences > bufmgr_gem->available_fences)
1950 total = drm_intel_gem_estimate_batch_space(bo_array, count);
1952 if (total > threshold)
1953 total = drm_intel_gem_compute_batch_space(bo_array, count);
1955 if (total > threshold) {
1956 DBG("check_space: overflowed available aperture, "
1958 total / 1024, (int)bufmgr_gem->gtt_size / 1024);
1961 DBG("drm_check_space: total %dkb vs bufgr %dkb\n", total / 1024,
1962 (int)bufmgr_gem->gtt_size / 1024);
1968 * Disable buffer reuse for objects which are shared with the kernel
1969 * as scanout buffers
1972 drm_intel_gem_bo_disable_reuse(drm_intel_bo *bo)
1974 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1976 bo_gem->reusable = 0;
1981 drm_intel_gem_bo_is_reusable(drm_intel_bo *bo)
1983 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1985 return bo_gem->reusable;
1989 _drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
1991 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1994 for (i = 0; i < bo_gem->reloc_count; i++) {
1995 if (bo_gem->reloc_target_info[i].bo == target_bo)
1997 if (bo == bo_gem->reloc_target_info[i].bo)
1999 if (_drm_intel_gem_bo_references(bo_gem->reloc_target_info[i].bo,
2007 /** Return true if target_bo is referenced by bo's relocation tree. */
2009 drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
2011 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
2013 if (bo == NULL || target_bo == NULL)
2015 if (target_bo_gem->used_as_reloc_target)
2016 return _drm_intel_gem_bo_references(bo, target_bo);
2021 add_bucket(drm_intel_bufmgr_gem *bufmgr_gem, int size)
2023 unsigned int i = bufmgr_gem->num_buckets;
2025 assert(i < ARRAY_SIZE(bufmgr_gem->cache_bucket));
2027 DRMINITLISTHEAD(&bufmgr_gem->cache_bucket[i].head);
2028 bufmgr_gem->cache_bucket[i].size = size;
2029 bufmgr_gem->num_buckets++;
2033 init_cache_buckets(drm_intel_bufmgr_gem *bufmgr_gem)
2035 unsigned long size, cache_max_size = 64 * 1024 * 1024;
2037 /* OK, so power of two buckets was too wasteful of memory.
2038 * Give 3 other sizes between each power of two, to hopefully
2039 * cover things accurately enough. (The alternative is
2040 * probably to just go for exact matching of sizes, and assume
2041 * that for things like composited window resize the tiled
2042 * width/height alignment and rounding of sizes to pages will
2043 * get us useful cache hit rates anyway)
2045 add_bucket(bufmgr_gem, 4096);
2046 add_bucket(bufmgr_gem, 4096 * 2);
2047 add_bucket(bufmgr_gem, 4096 * 3);
2049 /* Initialize the linked lists for BO reuse cache. */
2050 for (size = 4 * 4096; size <= cache_max_size; size *= 2) {
2051 add_bucket(bufmgr_gem, size);
2053 add_bucket(bufmgr_gem, size + size * 1 / 4);
2054 add_bucket(bufmgr_gem, size + size * 2 / 4);
2055 add_bucket(bufmgr_gem, size + size * 3 / 4);
2060 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
2061 * and manage map buffer objections.
2063 * \param fd File descriptor of the opened DRM device.
2066 drm_intel_bufmgr_gem_init(int fd, int batch_size)
2068 drm_intel_bufmgr_gem *bufmgr_gem;
2069 struct drm_i915_gem_get_aperture aperture;
2070 drm_i915_getparam_t gp;
2074 bufmgr_gem = calloc(1, sizeof(*bufmgr_gem));
2075 if (bufmgr_gem == NULL)
2078 bufmgr_gem->fd = fd;
2080 if (pthread_mutex_init(&bufmgr_gem->lock, NULL) != 0) {
2085 ret = drmIoctl(bufmgr_gem->fd,
2086 DRM_IOCTL_I915_GEM_GET_APERTURE,
2090 bufmgr_gem->gtt_size = aperture.aper_available_size;
2092 fprintf(stderr, "DRM_IOCTL_I915_GEM_APERTURE failed: %s\n",
2094 bufmgr_gem->gtt_size = 128 * 1024 * 1024;
2095 fprintf(stderr, "Assuming %dkB available aperture size.\n"
2096 "May lead to reduced performance or incorrect "
2098 (int)bufmgr_gem->gtt_size / 1024);
2101 gp.param = I915_PARAM_CHIPSET_ID;
2102 gp.value = &bufmgr_gem->pci_device;
2103 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2105 fprintf(stderr, "get chip id failed: %d [%d]\n", ret, errno);
2106 fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value);
2109 if (IS_GEN2(bufmgr_gem))
2110 bufmgr_gem->gen = 2;
2111 else if (IS_GEN3(bufmgr_gem))
2112 bufmgr_gem->gen = 3;
2113 else if (IS_GEN4(bufmgr_gem))
2114 bufmgr_gem->gen = 4;
2116 bufmgr_gem->gen = 6;
2118 gp.param = I915_PARAM_HAS_EXECBUF2;
2119 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2123 gp.param = I915_PARAM_HAS_BSD;
2124 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2125 bufmgr_gem->has_bsd = ret == 0;
2127 gp.param = I915_PARAM_HAS_BLT;
2128 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2129 bufmgr_gem->has_blt = ret == 0;
2131 if (bufmgr_gem->gen < 4) {
2132 gp.param = I915_PARAM_NUM_FENCES_AVAIL;
2133 gp.value = &bufmgr_gem->available_fences;
2134 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2136 fprintf(stderr, "get fences failed: %d [%d]\n", ret,
2138 fprintf(stderr, "param: %d, val: %d\n", gp.param,
2140 bufmgr_gem->available_fences = 0;
2142 /* XXX The kernel reports the total number of fences,
2143 * including any that may be pinned.
2145 * We presume that there will be at least one pinned
2146 * fence for the scanout buffer, but there may be more
2147 * than one scanout and the user may be manually
2148 * pinning buffers. Let's move to execbuffer2 and
2149 * thereby forget the insanity of using fences...
2151 bufmgr_gem->available_fences -= 2;
2152 if (bufmgr_gem->available_fences < 0)
2153 bufmgr_gem->available_fences = 0;
2157 /* Let's go with one relocation per every 2 dwords (but round down a bit
2158 * since a power of two will mean an extra page allocation for the reloc
2161 * Every 4 was too few for the blender benchmark.
2163 bufmgr_gem->max_relocs = batch_size / sizeof(uint32_t) / 2 - 2;
2165 bufmgr_gem->bufmgr.bo_alloc = drm_intel_gem_bo_alloc;
2166 bufmgr_gem->bufmgr.bo_alloc_for_render =
2167 drm_intel_gem_bo_alloc_for_render;
2168 bufmgr_gem->bufmgr.bo_alloc_tiled = drm_intel_gem_bo_alloc_tiled;
2169 bufmgr_gem->bufmgr.bo_reference = drm_intel_gem_bo_reference;
2170 bufmgr_gem->bufmgr.bo_unreference = drm_intel_gem_bo_unreference;
2171 bufmgr_gem->bufmgr.bo_map = drm_intel_gem_bo_map;
2172 bufmgr_gem->bufmgr.bo_unmap = drm_intel_gem_bo_unmap;
2173 bufmgr_gem->bufmgr.bo_subdata = drm_intel_gem_bo_subdata;
2174 bufmgr_gem->bufmgr.bo_get_subdata = drm_intel_gem_bo_get_subdata;
2175 bufmgr_gem->bufmgr.bo_wait_rendering = drm_intel_gem_bo_wait_rendering;
2176 bufmgr_gem->bufmgr.bo_emit_reloc = drm_intel_gem_bo_emit_reloc;
2177 bufmgr_gem->bufmgr.bo_emit_reloc_fence = drm_intel_gem_bo_emit_reloc_fence;
2178 bufmgr_gem->bufmgr.bo_pin = drm_intel_gem_bo_pin;
2179 bufmgr_gem->bufmgr.bo_unpin = drm_intel_gem_bo_unpin;
2180 bufmgr_gem->bufmgr.bo_get_tiling = drm_intel_gem_bo_get_tiling;
2181 bufmgr_gem->bufmgr.bo_set_tiling = drm_intel_gem_bo_set_tiling;
2182 bufmgr_gem->bufmgr.bo_flink = drm_intel_gem_bo_flink;
2183 /* Use the new one if available */
2185 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec2;
2186 if (bufmgr_gem->has_bsd|bufmgr_gem->has_blt)
2187 bufmgr_gem->bufmgr.bo_mrb_exec = drm_intel_gem_bo_mrb_exec2;
2189 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec;
2190 bufmgr_gem->bufmgr.bo_busy = drm_intel_gem_bo_busy;
2191 bufmgr_gem->bufmgr.bo_madvise = drm_intel_gem_bo_madvise;
2192 bufmgr_gem->bufmgr.destroy = drm_intel_bufmgr_gem_destroy;
2193 bufmgr_gem->bufmgr.debug = 0;
2194 bufmgr_gem->bufmgr.check_aperture_space =
2195 drm_intel_gem_check_aperture_space;
2196 bufmgr_gem->bufmgr.bo_disable_reuse = drm_intel_gem_bo_disable_reuse;
2197 bufmgr_gem->bufmgr.bo_is_reusable = drm_intel_gem_bo_is_reusable;
2198 bufmgr_gem->bufmgr.get_pipe_from_crtc_id =
2199 drm_intel_gem_get_pipe_from_crtc_id;
2200 bufmgr_gem->bufmgr.bo_references = drm_intel_gem_bo_references;
2202 init_cache_buckets(bufmgr_gem);
2204 return &bufmgr_gem->bufmgr;