1 /**************************************************************************
3 * Copyright © 2007 Red Hat Inc.
4 * Copyright © 2007 Intel Corporation
5 * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
29 **************************************************************************/
31 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
32 * Keith Whitwell <keithw-at-tungstengraphics-dot-com>
33 * Eric Anholt <eric@anholt.net>
34 * Dave Airlie <airlied@linux.ie>
42 #include <xf86atomic.h>
50 #include <sys/ioctl.h>
53 #include <sys/types.h>
56 #include "libdrm_lists.h"
57 #include "intel_bufmgr.h"
58 #include "intel_bufmgr_priv.h"
59 #include "intel_chipset.h"
64 #define DBG(...) do { \
65 if (bufmgr_gem->bufmgr.debug) \
66 fprintf(stderr, __VA_ARGS__); \
69 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
71 typedef struct _drm_intel_bo_gem drm_intel_bo_gem;
73 struct drm_intel_gem_bo_bucket {
78 typedef struct _drm_intel_bufmgr_gem {
79 drm_intel_bufmgr bufmgr;
87 struct drm_i915_gem_exec_object *exec_objects;
88 struct drm_i915_gem_exec_object2 *exec2_objects;
89 drm_intel_bo **exec_bos;
93 /** Array of lists of cached gem objects of power-of-two sizes */
94 struct drm_intel_gem_bo_bucket cache_bucket[14 * 4];
102 unsigned int has_bsd : 1;
103 unsigned int has_blt : 1;
104 unsigned int has_relaxed_fencing : 1;
105 unsigned int bo_reuse : 1;
107 } drm_intel_bufmgr_gem;
109 #define DRM_INTEL_RELOC_FENCE (1<<0)
111 typedef struct _drm_intel_reloc_target_info {
114 } drm_intel_reloc_target;
116 struct _drm_intel_bo_gem {
124 * Kenel-assigned global name for this object
126 unsigned int global_name;
129 * Index of the buffer within the validation list while preparing a
130 * batchbuffer execution.
135 * Current tiling mode
137 uint32_t tiling_mode;
138 uint32_t swizzle_mode;
139 unsigned long stride;
143 /** Array passed to the DRM containing relocation information. */
144 struct drm_i915_gem_relocation_entry *relocs;
146 * Array of info structs corresponding to relocs[i].target_handle etc
148 drm_intel_reloc_target *reloc_target_info;
149 /** Number of entries in relocs */
151 /** Mapped address for the buffer, saved across map/unmap cycles */
153 /** GTT virtual address for the buffer, saved across map/unmap cycles */
160 * Boolean of whether this BO and its children have been included in
161 * the current drm_intel_bufmgr_check_aperture_space() total.
163 char included_in_check_aperture;
166 * Boolean of whether this buffer has been used as a relocation
167 * target and had its size accounted for, and thus can't have any
168 * further relocations added to it.
170 char used_as_reloc_target;
173 * Boolean of whether we have encountered an error whilst building the relocation tree.
178 * Boolean of whether this buffer can be re-used
183 * Size in bytes of this buffer and its relocation descendents.
185 * Used to avoid costly tree walking in
186 * drm_intel_bufmgr_check_aperture in the common case.
191 * Number of potential fence registers required by this buffer and its
194 int reloc_tree_fences;
198 drm_intel_gem_estimate_batch_space(drm_intel_bo ** bo_array, int count);
201 drm_intel_gem_compute_batch_space(drm_intel_bo ** bo_array, int count);
204 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
205 uint32_t * swizzle_mode);
208 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
209 uint32_t tiling_mode,
212 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
215 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo);
217 static void drm_intel_gem_bo_free(drm_intel_bo *bo);
220 drm_intel_gem_bo_tile_size(drm_intel_bufmgr_gem *bufmgr_gem, unsigned long size,
221 uint32_t *tiling_mode)
223 unsigned long min_size, max_size;
226 if (*tiling_mode == I915_TILING_NONE)
229 /* 965+ just need multiples of page size for tiling */
230 if (bufmgr_gem->gen >= 4)
231 return ROUND_UP_TO(size, 4096);
233 /* Older chips need powers of two, of at least 512k or 1M */
234 if (bufmgr_gem->gen == 3) {
235 min_size = 1024*1024;
236 max_size = 128*1024*1024;
239 max_size = 64*1024*1024;
242 if (size > max_size) {
243 *tiling_mode = I915_TILING_NONE;
247 /* Do we need to allocate every page for the fence? */
248 if (bufmgr_gem->has_relaxed_fencing)
249 return ROUND_UP_TO(size, 4096);
251 for (i = min_size; i < size; i <<= 1)
258 * Round a given pitch up to the minimum required for X tiling on a
259 * given chip. We use 512 as the minimum to allow for a later tiling
263 drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem,
264 unsigned long pitch, uint32_t *tiling_mode)
266 unsigned long tile_width;
269 /* If untiled, then just align it so that we can do rendering
270 * to it with the 3D engine.
272 if (*tiling_mode == I915_TILING_NONE)
273 return ALIGN(pitch, 64);
275 if (*tiling_mode == I915_TILING_X)
280 /* 965 is flexible */
281 if (bufmgr_gem->gen >= 4)
282 return ROUND_UP_TO(pitch, tile_width);
284 /* The older hardware has a maximum pitch of 8192 with tiled
285 * surfaces, so fallback to untiled if it's too large.
288 *tiling_mode = I915_TILING_NONE;
289 return ALIGN(pitch, 64);
292 /* Pre-965 needs power of two tile width */
293 for (i = tile_width; i < pitch; i <<= 1)
299 static struct drm_intel_gem_bo_bucket *
300 drm_intel_gem_bo_bucket_for_size(drm_intel_bufmgr_gem *bufmgr_gem,
305 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
306 struct drm_intel_gem_bo_bucket *bucket =
307 &bufmgr_gem->cache_bucket[i];
308 if (bucket->size >= size) {
317 drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem *bufmgr_gem)
321 for (i = 0; i < bufmgr_gem->exec_count; i++) {
322 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
323 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
325 if (bo_gem->relocs == NULL) {
326 DBG("%2d: %d (%s)\n", i, bo_gem->gem_handle,
331 for (j = 0; j < bo_gem->reloc_count; j++) {
332 drm_intel_bo *target_bo = bo_gem->reloc_target_info[j].bo;
333 drm_intel_bo_gem *target_gem =
334 (drm_intel_bo_gem *) target_bo;
336 DBG("%2d: %d (%s)@0x%08llx -> "
337 "%d (%s)@0x%08lx + 0x%08x\n",
339 bo_gem->gem_handle, bo_gem->name,
340 (unsigned long long)bo_gem->relocs[j].offset,
341 target_gem->gem_handle,
344 bo_gem->relocs[j].delta);
350 drm_intel_gem_bo_reference(drm_intel_bo *bo)
352 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
354 assert(atomic_read(&bo_gem->refcount) > 0);
355 atomic_inc(&bo_gem->refcount);
359 * Adds the given buffer to the list of buffers to be validated (moved into the
360 * appropriate memory type) with the next batch submission.
362 * If a buffer is validated multiple times in a batch submission, it ends up
363 * with the intersection of the memory type flags and the union of the
367 drm_intel_add_validate_buffer(drm_intel_bo *bo)
369 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
370 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
373 if (bo_gem->validate_index != -1)
376 /* Extend the array of validation entries as necessary. */
377 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
378 int new_size = bufmgr_gem->exec_size * 2;
383 bufmgr_gem->exec_objects =
384 realloc(bufmgr_gem->exec_objects,
385 sizeof(*bufmgr_gem->exec_objects) * new_size);
386 bufmgr_gem->exec_bos =
387 realloc(bufmgr_gem->exec_bos,
388 sizeof(*bufmgr_gem->exec_bos) * new_size);
389 bufmgr_gem->exec_size = new_size;
392 index = bufmgr_gem->exec_count;
393 bo_gem->validate_index = index;
394 /* Fill in array entry */
395 bufmgr_gem->exec_objects[index].handle = bo_gem->gem_handle;
396 bufmgr_gem->exec_objects[index].relocation_count = bo_gem->reloc_count;
397 bufmgr_gem->exec_objects[index].relocs_ptr = (uintptr_t) bo_gem->relocs;
398 bufmgr_gem->exec_objects[index].alignment = 0;
399 bufmgr_gem->exec_objects[index].offset = 0;
400 bufmgr_gem->exec_bos[index] = bo;
401 bufmgr_gem->exec_count++;
405 drm_intel_add_validate_buffer2(drm_intel_bo *bo, int need_fence)
407 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
408 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
411 if (bo_gem->validate_index != -1) {
413 bufmgr_gem->exec2_objects[bo_gem->validate_index].flags |=
414 EXEC_OBJECT_NEEDS_FENCE;
418 /* Extend the array of validation entries as necessary. */
419 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
420 int new_size = bufmgr_gem->exec_size * 2;
425 bufmgr_gem->exec2_objects =
426 realloc(bufmgr_gem->exec2_objects,
427 sizeof(*bufmgr_gem->exec2_objects) * new_size);
428 bufmgr_gem->exec_bos =
429 realloc(bufmgr_gem->exec_bos,
430 sizeof(*bufmgr_gem->exec_bos) * new_size);
431 bufmgr_gem->exec_size = new_size;
434 index = bufmgr_gem->exec_count;
435 bo_gem->validate_index = index;
436 /* Fill in array entry */
437 bufmgr_gem->exec2_objects[index].handle = bo_gem->gem_handle;
438 bufmgr_gem->exec2_objects[index].relocation_count = bo_gem->reloc_count;
439 bufmgr_gem->exec2_objects[index].relocs_ptr = (uintptr_t)bo_gem->relocs;
440 bufmgr_gem->exec2_objects[index].alignment = 0;
441 bufmgr_gem->exec2_objects[index].offset = 0;
442 bufmgr_gem->exec_bos[index] = bo;
443 bufmgr_gem->exec2_objects[index].flags = 0;
444 bufmgr_gem->exec2_objects[index].rsvd1 = 0;
445 bufmgr_gem->exec2_objects[index].rsvd2 = 0;
447 bufmgr_gem->exec2_objects[index].flags |=
448 EXEC_OBJECT_NEEDS_FENCE;
450 bufmgr_gem->exec_count++;
453 #define RELOC_BUF_SIZE(x) ((I915_RELOC_HEADER + x * I915_RELOC0_STRIDE) * \
457 drm_intel_bo_gem_set_in_aperture_size(drm_intel_bufmgr_gem *bufmgr_gem,
458 drm_intel_bo_gem *bo_gem)
462 assert(!bo_gem->used_as_reloc_target);
464 /* The older chipsets are far-less flexible in terms of tiling,
465 * and require tiled buffer to be size aligned in the aperture.
466 * This means that in the worst possible case we will need a hole
467 * twice as large as the object in order for it to fit into the
468 * aperture. Optimal packing is for wimps.
470 size = bo_gem->bo.size;
471 if (bufmgr_gem->gen < 4 && bo_gem->tiling_mode != I915_TILING_NONE)
474 bo_gem->reloc_tree_size = size;
478 drm_intel_setup_reloc_list(drm_intel_bo *bo)
480 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
481 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
482 unsigned int max_relocs = bufmgr_gem->max_relocs;
484 if (bo->size / 4 < max_relocs)
485 max_relocs = bo->size / 4;
487 bo_gem->relocs = malloc(max_relocs *
488 sizeof(struct drm_i915_gem_relocation_entry));
489 bo_gem->reloc_target_info = malloc(max_relocs *
490 sizeof(drm_intel_reloc_target));
491 if (bo_gem->relocs == NULL || bo_gem->reloc_target_info == NULL) {
492 bo_gem->has_error = 1;
494 free (bo_gem->relocs);
495 bo_gem->relocs = NULL;
497 free (bo_gem->reloc_target_info);
498 bo_gem->reloc_target_info = NULL;
507 drm_intel_gem_bo_busy(drm_intel_bo *bo)
509 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
510 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
511 struct drm_i915_gem_busy busy;
514 memset(&busy, 0, sizeof(busy));
515 busy.handle = bo_gem->gem_handle;
517 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_BUSY, &busy);
519 return (ret == 0 && busy.busy);
523 drm_intel_gem_bo_madvise_internal(drm_intel_bufmgr_gem *bufmgr_gem,
524 drm_intel_bo_gem *bo_gem, int state)
526 struct drm_i915_gem_madvise madv;
528 madv.handle = bo_gem->gem_handle;
531 drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MADVISE, &madv);
533 return madv.retained;
537 drm_intel_gem_bo_madvise(drm_intel_bo *bo, int madv)
539 return drm_intel_gem_bo_madvise_internal
540 ((drm_intel_bufmgr_gem *) bo->bufmgr,
541 (drm_intel_bo_gem *) bo,
545 /* drop the oldest entries that have been purged by the kernel */
547 drm_intel_gem_bo_cache_purge_bucket(drm_intel_bufmgr_gem *bufmgr_gem,
548 struct drm_intel_gem_bo_bucket *bucket)
550 while (!DRMLISTEMPTY(&bucket->head)) {
551 drm_intel_bo_gem *bo_gem;
553 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
554 bucket->head.next, head);
555 if (drm_intel_gem_bo_madvise_internal
556 (bufmgr_gem, bo_gem, I915_MADV_DONTNEED))
559 DRMLISTDEL(&bo_gem->head);
560 drm_intel_gem_bo_free(&bo_gem->bo);
564 static drm_intel_bo *
565 drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr,
569 uint32_t tiling_mode,
570 unsigned long stride)
572 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
573 drm_intel_bo_gem *bo_gem;
574 unsigned int page_size = getpagesize();
576 struct drm_intel_gem_bo_bucket *bucket;
577 int alloc_from_cache;
578 unsigned long bo_size;
581 if (flags & BO_ALLOC_FOR_RENDER)
584 /* Round the allocated size up to a power of two number of pages. */
585 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, size);
587 /* If we don't have caching at this size, don't actually round the
590 if (bucket == NULL) {
592 if (bo_size < page_size)
595 bo_size = bucket->size;
598 pthread_mutex_lock(&bufmgr_gem->lock);
599 /* Get a buffer out of the cache if available */
601 alloc_from_cache = 0;
602 if (bucket != NULL && !DRMLISTEMPTY(&bucket->head)) {
604 /* Allocate new render-target BOs from the tail (MRU)
605 * of the list, as it will likely be hot in the GPU
606 * cache and in the aperture for us.
608 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
609 bucket->head.prev, head);
610 DRMLISTDEL(&bo_gem->head);
611 alloc_from_cache = 1;
613 /* For non-render-target BOs (where we're probably
614 * going to map it first thing in order to fill it
615 * with data), check if the last BO in the cache is
616 * unbusy, and only reuse in that case. Otherwise,
617 * allocating a new buffer is probably faster than
618 * waiting for the GPU to finish.
620 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
621 bucket->head.next, head);
622 if (!drm_intel_gem_bo_busy(&bo_gem->bo)) {
623 alloc_from_cache = 1;
624 DRMLISTDEL(&bo_gem->head);
628 if (alloc_from_cache) {
629 if (!drm_intel_gem_bo_madvise_internal
630 (bufmgr_gem, bo_gem, I915_MADV_WILLNEED)) {
631 drm_intel_gem_bo_free(&bo_gem->bo);
632 drm_intel_gem_bo_cache_purge_bucket(bufmgr_gem,
637 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
640 drm_intel_gem_bo_free(&bo_gem->bo);
645 pthread_mutex_unlock(&bufmgr_gem->lock);
647 if (!alloc_from_cache) {
648 struct drm_i915_gem_create create;
650 bo_gem = calloc(1, sizeof(*bo_gem));
654 bo_gem->bo.size = bo_size;
655 memset(&create, 0, sizeof(create));
656 create.size = bo_size;
658 ret = drmIoctl(bufmgr_gem->fd,
659 DRM_IOCTL_I915_GEM_CREATE,
661 bo_gem->gem_handle = create.handle;
662 bo_gem->bo.handle = bo_gem->gem_handle;
667 bo_gem->bo.bufmgr = bufmgr;
669 bo_gem->tiling_mode = I915_TILING_NONE;
670 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
673 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
676 drm_intel_gem_bo_free(&bo_gem->bo);
682 atomic_set(&bo_gem->refcount, 1);
683 bo_gem->validate_index = -1;
684 bo_gem->reloc_tree_fences = 0;
685 bo_gem->used_as_reloc_target = 0;
686 bo_gem->has_error = 0;
687 bo_gem->reusable = 1;
689 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
691 DBG("bo_create: buf %d (%s) %ldb\n",
692 bo_gem->gem_handle, bo_gem->name, size);
697 static drm_intel_bo *
698 drm_intel_gem_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
701 unsigned int alignment)
703 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size,
705 I915_TILING_NONE, 0);
708 static drm_intel_bo *
709 drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr,
712 unsigned int alignment)
714 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, 0,
715 I915_TILING_NONE, 0);
718 static drm_intel_bo *
719 drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
720 int x, int y, int cpp, uint32_t *tiling_mode,
721 unsigned long *pitch, unsigned long flags)
723 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
724 unsigned long size, stride;
728 unsigned long aligned_y;
730 tiling = *tiling_mode;
732 /* If we're tiled, our allocations are in 8 or 32-row blocks,
733 * so failure to align our height means that we won't allocate
736 * If we're untiled, we still have to align to 2 rows high
737 * because the data port accesses 2x2 blocks even if the
738 * bottom row isn't to be rendered, so failure to align means
739 * we could walk off the end of the GTT and fault. This is
740 * documented on 965, and may be the case on older chipsets
741 * too so we try to be careful.
744 if (tiling == I915_TILING_NONE)
745 aligned_y = ALIGN(y, 2);
746 else if (tiling == I915_TILING_X)
747 aligned_y = ALIGN(y, 8);
748 else if (tiling == I915_TILING_Y)
749 aligned_y = ALIGN(y, 32);
752 stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, tiling_mode);
753 size = stride * aligned_y;
754 size = drm_intel_gem_bo_tile_size(bufmgr_gem, size, tiling_mode);
755 } while (*tiling_mode != tiling);
758 if (tiling == I915_TILING_NONE)
761 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, flags,
766 * Returns a drm_intel_bo wrapping the given buffer object handle.
768 * This can be used when one application needs to pass a buffer object
772 drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
776 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
777 drm_intel_bo_gem *bo_gem;
779 struct drm_gem_open open_arg;
780 struct drm_i915_gem_get_tiling get_tiling;
782 bo_gem = calloc(1, sizeof(*bo_gem));
786 memset(&open_arg, 0, sizeof(open_arg));
787 open_arg.name = handle;
788 ret = drmIoctl(bufmgr_gem->fd,
792 DBG("Couldn't reference %s handle 0x%08x: %s\n",
793 name, handle, strerror(errno));
797 bo_gem->bo.size = open_arg.size;
798 bo_gem->bo.offset = 0;
799 bo_gem->bo.virtual = NULL;
800 bo_gem->bo.bufmgr = bufmgr;
802 atomic_set(&bo_gem->refcount, 1);
803 bo_gem->validate_index = -1;
804 bo_gem->gem_handle = open_arg.handle;
805 bo_gem->global_name = handle;
806 bo_gem->reusable = 0;
808 memset(&get_tiling, 0, sizeof(get_tiling));
809 get_tiling.handle = bo_gem->gem_handle;
810 ret = drmIoctl(bufmgr_gem->fd,
811 DRM_IOCTL_I915_GEM_GET_TILING,
814 drm_intel_gem_bo_unreference(&bo_gem->bo);
817 bo_gem->tiling_mode = get_tiling.tiling_mode;
818 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
819 /* XXX stride is unknown */
820 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
822 DBG("bo_create_from_handle: %d (%s)\n", handle, bo_gem->name);
828 drm_intel_gem_bo_free(drm_intel_bo *bo)
830 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
831 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
832 struct drm_gem_close close;
835 if (bo_gem->mem_virtual)
836 munmap(bo_gem->mem_virtual, bo_gem->bo.size);
837 if (bo_gem->gtt_virtual)
838 munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
840 /* Close this object */
841 memset(&close, 0, sizeof(close));
842 close.handle = bo_gem->gem_handle;
843 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close);
845 DBG("DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
846 bo_gem->gem_handle, bo_gem->name, strerror(errno));
851 /** Frees all cached buffers significantly older than @time. */
853 drm_intel_gem_cleanup_bo_cache(drm_intel_bufmgr_gem *bufmgr_gem, time_t time)
857 if (bufmgr_gem->time == time)
860 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
861 struct drm_intel_gem_bo_bucket *bucket =
862 &bufmgr_gem->cache_bucket[i];
864 while (!DRMLISTEMPTY(&bucket->head)) {
865 drm_intel_bo_gem *bo_gem;
867 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
868 bucket->head.next, head);
869 if (time - bo_gem->free_time <= 1)
872 DRMLISTDEL(&bo_gem->head);
874 drm_intel_gem_bo_free(&bo_gem->bo);
878 bufmgr_gem->time = time;
882 drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time)
884 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
885 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
886 struct drm_intel_gem_bo_bucket *bucket;
889 /* Unreference all the target buffers */
890 for (i = 0; i < bo_gem->reloc_count; i++) {
891 if (bo_gem->reloc_target_info[i].bo != bo) {
892 drm_intel_gem_bo_unreference_locked_timed(bo_gem->
893 reloc_target_info[i].bo,
897 bo_gem->reloc_count = 0;
898 bo_gem->used_as_reloc_target = 0;
900 DBG("bo_unreference final: %d (%s)\n",
901 bo_gem->gem_handle, bo_gem->name);
903 /* release memory associated with this object */
904 if (bo_gem->reloc_target_info) {
905 free(bo_gem->reloc_target_info);
906 bo_gem->reloc_target_info = NULL;
908 if (bo_gem->relocs) {
909 free(bo_gem->relocs);
910 bo_gem->relocs = NULL;
913 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, bo->size);
914 /* Put the buffer into our internal cache for reuse if we can. */
915 if (bufmgr_gem->bo_reuse && bo_gem->reusable && bucket != NULL &&
916 drm_intel_gem_bo_madvise_internal(bufmgr_gem, bo_gem,
917 I915_MADV_DONTNEED)) {
918 bo_gem->free_time = time;
921 bo_gem->validate_index = -1;
923 DRMLISTADDTAIL(&bo_gem->head, &bucket->head);
925 drm_intel_gem_bo_free(bo);
929 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
932 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
934 assert(atomic_read(&bo_gem->refcount) > 0);
935 if (atomic_dec_and_test(&bo_gem->refcount))
936 drm_intel_gem_bo_unreference_final(bo, time);
939 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo)
941 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
943 assert(atomic_read(&bo_gem->refcount) > 0);
944 if (atomic_dec_and_test(&bo_gem->refcount)) {
945 drm_intel_bufmgr_gem *bufmgr_gem =
946 (drm_intel_bufmgr_gem *) bo->bufmgr;
947 struct timespec time;
949 clock_gettime(CLOCK_MONOTONIC, &time);
951 pthread_mutex_lock(&bufmgr_gem->lock);
952 drm_intel_gem_bo_unreference_final(bo, time.tv_sec);
953 drm_intel_gem_cleanup_bo_cache(bufmgr_gem, time.tv_sec);
954 pthread_mutex_unlock(&bufmgr_gem->lock);
958 static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable)
960 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
961 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
962 struct drm_i915_gem_set_domain set_domain;
965 pthread_mutex_lock(&bufmgr_gem->lock);
967 /* Allow recursive mapping. Mesa may recursively map buffers with
968 * nested display loops.
970 if (!bo_gem->mem_virtual) {
971 struct drm_i915_gem_mmap mmap_arg;
973 DBG("bo_map: %d (%s)\n", bo_gem->gem_handle, bo_gem->name);
975 memset(&mmap_arg, 0, sizeof(mmap_arg));
976 mmap_arg.handle = bo_gem->gem_handle;
978 mmap_arg.size = bo->size;
979 ret = drmIoctl(bufmgr_gem->fd,
980 DRM_IOCTL_I915_GEM_MMAP,
984 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
985 __FILE__, __LINE__, bo_gem->gem_handle,
986 bo_gem->name, strerror(errno));
987 pthread_mutex_unlock(&bufmgr_gem->lock);
990 bo_gem->mem_virtual = (void *)(uintptr_t) mmap_arg.addr_ptr;
992 DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
993 bo_gem->mem_virtual);
994 bo->virtual = bo_gem->mem_virtual;
996 set_domain.handle = bo_gem->gem_handle;
997 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
999 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
1001 set_domain.write_domain = 0;
1002 ret = drmIoctl(bufmgr_gem->fd,
1003 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1006 DBG("%s:%d: Error setting to CPU domain %d: %s\n",
1007 __FILE__, __LINE__, bo_gem->gem_handle,
1011 pthread_mutex_unlock(&bufmgr_gem->lock);
1016 int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
1018 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1019 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1020 struct drm_i915_gem_set_domain set_domain;
1023 pthread_mutex_lock(&bufmgr_gem->lock);
1025 /* Get a mapping of the buffer if we haven't before. */
1026 if (bo_gem->gtt_virtual == NULL) {
1027 struct drm_i915_gem_mmap_gtt mmap_arg;
1029 DBG("bo_map_gtt: mmap %d (%s)\n", bo_gem->gem_handle,
1032 memset(&mmap_arg, 0, sizeof(mmap_arg));
1033 mmap_arg.handle = bo_gem->gem_handle;
1035 /* Get the fake offset back... */
1036 ret = drmIoctl(bufmgr_gem->fd,
1037 DRM_IOCTL_I915_GEM_MMAP_GTT,
1041 DBG("%s:%d: Error preparing buffer map %d (%s): %s .\n",
1043 bo_gem->gem_handle, bo_gem->name,
1045 pthread_mutex_unlock(&bufmgr_gem->lock);
1050 bo_gem->gtt_virtual = mmap(0, bo->size, PROT_READ | PROT_WRITE,
1051 MAP_SHARED, bufmgr_gem->fd,
1053 if (bo_gem->gtt_virtual == MAP_FAILED) {
1054 bo_gem->gtt_virtual = NULL;
1056 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1058 bo_gem->gem_handle, bo_gem->name,
1060 pthread_mutex_unlock(&bufmgr_gem->lock);
1065 bo->virtual = bo_gem->gtt_virtual;
1067 DBG("bo_map_gtt: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1068 bo_gem->gtt_virtual);
1070 /* Now move it to the GTT domain so that the CPU caches are flushed */
1071 set_domain.handle = bo_gem->gem_handle;
1072 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1073 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
1074 ret = drmIoctl(bufmgr_gem->fd,
1075 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1078 DBG("%s:%d: Error setting domain %d: %s\n",
1079 __FILE__, __LINE__, bo_gem->gem_handle,
1083 pthread_mutex_unlock(&bufmgr_gem->lock);
1088 int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo)
1090 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1091 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1097 assert(bo_gem->gtt_virtual != NULL);
1099 pthread_mutex_lock(&bufmgr_gem->lock);
1101 pthread_mutex_unlock(&bufmgr_gem->lock);
1106 static int drm_intel_gem_bo_unmap(drm_intel_bo *bo)
1108 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1109 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1110 struct drm_i915_gem_sw_finish sw_finish;
1116 assert(bo_gem->mem_virtual != NULL);
1118 pthread_mutex_lock(&bufmgr_gem->lock);
1120 /* Cause a flush to happen if the buffer's pinned for scanout, so the
1121 * results show up in a timely manner.
1123 sw_finish.handle = bo_gem->gem_handle;
1124 ret = drmIoctl(bufmgr_gem->fd,
1125 DRM_IOCTL_I915_GEM_SW_FINISH,
1127 ret = ret == -1 ? -errno : 0;
1130 pthread_mutex_unlock(&bufmgr_gem->lock);
1136 drm_intel_gem_bo_subdata(drm_intel_bo *bo, unsigned long offset,
1137 unsigned long size, const void *data)
1139 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1140 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1141 struct drm_i915_gem_pwrite pwrite;
1144 memset(&pwrite, 0, sizeof(pwrite));
1145 pwrite.handle = bo_gem->gem_handle;
1146 pwrite.offset = offset;
1148 pwrite.data_ptr = (uint64_t) (uintptr_t) data;
1149 ret = drmIoctl(bufmgr_gem->fd,
1150 DRM_IOCTL_I915_GEM_PWRITE,
1154 DBG("%s:%d: Error writing data to buffer %d: (%d %d) %s .\n",
1155 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1156 (int)size, strerror(errno));
1163 drm_intel_gem_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id)
1165 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1166 struct drm_i915_get_pipe_from_crtc_id get_pipe_from_crtc_id;
1169 get_pipe_from_crtc_id.crtc_id = crtc_id;
1170 ret = drmIoctl(bufmgr_gem->fd,
1171 DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID,
1172 &get_pipe_from_crtc_id);
1174 /* We return -1 here to signal that we don't
1175 * know which pipe is associated with this crtc.
1176 * This lets the caller know that this information
1177 * isn't available; using the wrong pipe for
1178 * vblank waiting can cause the chipset to lock up
1183 return get_pipe_from_crtc_id.pipe;
1187 drm_intel_gem_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
1188 unsigned long size, void *data)
1190 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1191 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1192 struct drm_i915_gem_pread pread;
1195 memset(&pread, 0, sizeof(pread));
1196 pread.handle = bo_gem->gem_handle;
1197 pread.offset = offset;
1199 pread.data_ptr = (uint64_t) (uintptr_t) data;
1200 ret = drmIoctl(bufmgr_gem->fd,
1201 DRM_IOCTL_I915_GEM_PREAD,
1205 DBG("%s:%d: Error reading data from buffer %d: (%d %d) %s .\n",
1206 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1207 (int)size, strerror(errno));
1213 /** Waits for all GPU rendering to the object to have completed. */
1215 drm_intel_gem_bo_wait_rendering(drm_intel_bo *bo)
1217 drm_intel_gem_bo_start_gtt_access(bo, 0);
1221 * Sets the object to the GTT read and possibly write domain, used by the X
1222 * 2D driver in the absence of kernel support to do drm_intel_gem_bo_map_gtt().
1224 * In combination with drm_intel_gem_bo_pin() and manual fence management, we
1225 * can do tiled pixmaps this way.
1228 drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable)
1230 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1231 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1232 struct drm_i915_gem_set_domain set_domain;
1235 set_domain.handle = bo_gem->gem_handle;
1236 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1237 set_domain.write_domain = write_enable ? I915_GEM_DOMAIN_GTT : 0;
1238 ret = drmIoctl(bufmgr_gem->fd,
1239 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1242 DBG("%s:%d: Error setting memory domains %d (%08x %08x): %s .\n",
1243 __FILE__, __LINE__, bo_gem->gem_handle,
1244 set_domain.read_domains, set_domain.write_domain,
1250 drm_intel_bufmgr_gem_destroy(drm_intel_bufmgr *bufmgr)
1252 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1255 free(bufmgr_gem->exec2_objects);
1256 free(bufmgr_gem->exec_objects);
1257 free(bufmgr_gem->exec_bos);
1259 pthread_mutex_destroy(&bufmgr_gem->lock);
1261 /* Free any cached buffer objects we were going to reuse */
1262 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
1263 struct drm_intel_gem_bo_bucket *bucket =
1264 &bufmgr_gem->cache_bucket[i];
1265 drm_intel_bo_gem *bo_gem;
1267 while (!DRMLISTEMPTY(&bucket->head)) {
1268 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1269 bucket->head.next, head);
1270 DRMLISTDEL(&bo_gem->head);
1272 drm_intel_gem_bo_free(&bo_gem->bo);
1280 * Adds the target buffer to the validation list and adds the relocation
1281 * to the reloc_buffer's relocation list.
1283 * The relocation entry at the given offset must already contain the
1284 * precomputed relocation value, because the kernel will optimize out
1285 * the relocation entry write when the buffer hasn't moved from the
1286 * last known offset in target_bo.
1289 do_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1290 drm_intel_bo *target_bo, uint32_t target_offset,
1291 uint32_t read_domains, uint32_t write_domain,
1294 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1295 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1296 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
1298 if (bo_gem->has_error)
1301 if (target_bo_gem->has_error) {
1302 bo_gem->has_error = 1;
1306 if (target_bo_gem->tiling_mode == I915_TILING_NONE)
1309 /* We never use HW fences for rendering on 965+ */
1310 if (bufmgr_gem->gen >= 4)
1313 /* Create a new relocation list if needed */
1314 if (bo_gem->relocs == NULL && drm_intel_setup_reloc_list(bo))
1317 /* Check overflow */
1318 assert(bo_gem->reloc_count < bufmgr_gem->max_relocs);
1321 assert(offset <= bo->size - 4);
1322 assert((write_domain & (write_domain - 1)) == 0);
1324 /* Make sure that we're not adding a reloc to something whose size has
1325 * already been accounted for.
1327 assert(!bo_gem->used_as_reloc_target);
1328 if (target_bo_gem != bo_gem) {
1329 target_bo_gem->used_as_reloc_target = 1;
1330 bo_gem->reloc_tree_size += target_bo_gem->reloc_tree_size;
1332 /* An object needing a fence is a tiled buffer, so it won't have
1333 * relocs to other buffers.
1336 target_bo_gem->reloc_tree_fences = 1;
1337 bo_gem->reloc_tree_fences += target_bo_gem->reloc_tree_fences;
1339 bo_gem->relocs[bo_gem->reloc_count].offset = offset;
1340 bo_gem->relocs[bo_gem->reloc_count].delta = target_offset;
1341 bo_gem->relocs[bo_gem->reloc_count].target_handle =
1342 target_bo_gem->gem_handle;
1343 bo_gem->relocs[bo_gem->reloc_count].read_domains = read_domains;
1344 bo_gem->relocs[bo_gem->reloc_count].write_domain = write_domain;
1345 bo_gem->relocs[bo_gem->reloc_count].presumed_offset = target_bo->offset;
1347 bo_gem->reloc_target_info[bo_gem->reloc_count].bo = target_bo;
1348 if (target_bo != bo)
1349 drm_intel_gem_bo_reference(target_bo);
1351 bo_gem->reloc_target_info[bo_gem->reloc_count].flags =
1352 DRM_INTEL_RELOC_FENCE;
1354 bo_gem->reloc_target_info[bo_gem->reloc_count].flags = 0;
1356 bo_gem->reloc_count++;
1362 drm_intel_gem_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1363 drm_intel_bo *target_bo, uint32_t target_offset,
1364 uint32_t read_domains, uint32_t write_domain)
1366 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1368 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1369 read_domains, write_domain,
1370 !bufmgr_gem->fenced_relocs);
1374 drm_intel_gem_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
1375 drm_intel_bo *target_bo,
1376 uint32_t target_offset,
1377 uint32_t read_domains, uint32_t write_domain)
1379 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1380 read_domains, write_domain, 1);
1384 * Walk the tree of relocations rooted at BO and accumulate the list of
1385 * validations to be performed and update the relocation buffers with
1386 * index values into the validation list.
1389 drm_intel_gem_bo_process_reloc(drm_intel_bo *bo)
1391 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1394 if (bo_gem->relocs == NULL)
1397 for (i = 0; i < bo_gem->reloc_count; i++) {
1398 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1400 if (target_bo == bo)
1403 /* Continue walking the tree depth-first. */
1404 drm_intel_gem_bo_process_reloc(target_bo);
1406 /* Add the target to the validate list */
1407 drm_intel_add_validate_buffer(target_bo);
1412 drm_intel_gem_bo_process_reloc2(drm_intel_bo *bo)
1414 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1417 if (bo_gem->relocs == NULL)
1420 for (i = 0; i < bo_gem->reloc_count; i++) {
1421 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1424 if (target_bo == bo)
1427 /* Continue walking the tree depth-first. */
1428 drm_intel_gem_bo_process_reloc2(target_bo);
1430 need_fence = (bo_gem->reloc_target_info[i].flags &
1431 DRM_INTEL_RELOC_FENCE);
1433 /* Add the target to the validate list */
1434 drm_intel_add_validate_buffer2(target_bo, need_fence);
1440 drm_intel_update_buffer_offsets(drm_intel_bufmgr_gem *bufmgr_gem)
1444 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1445 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1446 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1448 /* Update the buffer offset */
1449 if (bufmgr_gem->exec_objects[i].offset != bo->offset) {
1450 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1451 bo_gem->gem_handle, bo_gem->name, bo->offset,
1452 (unsigned long long)bufmgr_gem->exec_objects[i].
1454 bo->offset = bufmgr_gem->exec_objects[i].offset;
1460 drm_intel_update_buffer_offsets2 (drm_intel_bufmgr_gem *bufmgr_gem)
1464 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1465 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1466 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1468 /* Update the buffer offset */
1469 if (bufmgr_gem->exec2_objects[i].offset != bo->offset) {
1470 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1471 bo_gem->gem_handle, bo_gem->name, bo->offset,
1472 (unsigned long long)bufmgr_gem->exec2_objects[i].offset);
1473 bo->offset = bufmgr_gem->exec2_objects[i].offset;
1479 drm_intel_gem_bo_exec(drm_intel_bo *bo, int used,
1480 drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
1482 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1483 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1484 struct drm_i915_gem_execbuffer execbuf;
1487 if (bo_gem->has_error)
1490 pthread_mutex_lock(&bufmgr_gem->lock);
1491 /* Update indices and set up the validate list. */
1492 drm_intel_gem_bo_process_reloc(bo);
1494 /* Add the batch buffer to the validation list. There are no
1495 * relocations pointing to it.
1497 drm_intel_add_validate_buffer(bo);
1499 execbuf.buffers_ptr = (uintptr_t) bufmgr_gem->exec_objects;
1500 execbuf.buffer_count = bufmgr_gem->exec_count;
1501 execbuf.batch_start_offset = 0;
1502 execbuf.batch_len = used;
1503 execbuf.cliprects_ptr = (uintptr_t) cliprects;
1504 execbuf.num_cliprects = num_cliprects;
1508 ret = drmIoctl(bufmgr_gem->fd,
1509 DRM_IOCTL_I915_GEM_EXECBUFFER,
1513 if (errno == ENOSPC) {
1514 DBG("Execbuffer fails to pin. "
1515 "Estimate: %u. Actual: %u. Available: %u\n",
1516 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
1519 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
1522 (unsigned int)bufmgr_gem->gtt_size);
1525 drm_intel_update_buffer_offsets(bufmgr_gem);
1527 if (bufmgr_gem->bufmgr.debug)
1528 drm_intel_gem_dump_validation_list(bufmgr_gem);
1530 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1531 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1532 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1534 /* Disconnect the buffer from the validate list */
1535 bo_gem->validate_index = -1;
1536 bufmgr_gem->exec_bos[i] = NULL;
1538 bufmgr_gem->exec_count = 0;
1539 pthread_mutex_unlock(&bufmgr_gem->lock);
1545 drm_intel_gem_bo_mrb_exec2(drm_intel_bo *bo, int used,
1546 drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
1549 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1550 struct drm_i915_gem_execbuffer2 execbuf;
1553 switch (ring_flag) {
1557 if (!bufmgr_gem->has_blt)
1561 if (!bufmgr_gem->has_bsd)
1564 case I915_EXEC_RENDER:
1565 case I915_EXEC_DEFAULT:
1569 pthread_mutex_lock(&bufmgr_gem->lock);
1570 /* Update indices and set up the validate list. */
1571 drm_intel_gem_bo_process_reloc2(bo);
1573 /* Add the batch buffer to the validation list. There are no relocations
1576 drm_intel_add_validate_buffer2(bo, 0);
1578 execbuf.buffers_ptr = (uintptr_t)bufmgr_gem->exec2_objects;
1579 execbuf.buffer_count = bufmgr_gem->exec_count;
1580 execbuf.batch_start_offset = 0;
1581 execbuf.batch_len = used;
1582 execbuf.cliprects_ptr = (uintptr_t)cliprects;
1583 execbuf.num_cliprects = num_cliprects;
1586 execbuf.flags = ring_flag;
1590 ret = drmIoctl(bufmgr_gem->fd,
1591 DRM_IOCTL_I915_GEM_EXECBUFFER2,
1595 if (ret == -ENOSPC) {
1596 DBG("Execbuffer fails to pin. "
1597 "Estimate: %u. Actual: %u. Available: %u\n",
1598 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
1599 bufmgr_gem->exec_count),
1600 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
1601 bufmgr_gem->exec_count),
1602 (unsigned int) bufmgr_gem->gtt_size);
1605 drm_intel_update_buffer_offsets2(bufmgr_gem);
1607 if (bufmgr_gem->bufmgr.debug)
1608 drm_intel_gem_dump_validation_list(bufmgr_gem);
1610 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1611 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1612 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1614 /* Disconnect the buffer from the validate list */
1615 bo_gem->validate_index = -1;
1616 bufmgr_gem->exec_bos[i] = NULL;
1618 bufmgr_gem->exec_count = 0;
1619 pthread_mutex_unlock(&bufmgr_gem->lock);
1625 drm_intel_gem_bo_exec2(drm_intel_bo *bo, int used,
1626 drm_clip_rect_t *cliprects, int num_cliprects,
1629 return drm_intel_gem_bo_mrb_exec2(bo, used,
1630 cliprects, num_cliprects, DR4,
1635 drm_intel_gem_bo_pin(drm_intel_bo *bo, uint32_t alignment)
1637 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1638 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1639 struct drm_i915_gem_pin pin;
1642 memset(&pin, 0, sizeof(pin));
1643 pin.handle = bo_gem->gem_handle;
1644 pin.alignment = alignment;
1646 ret = drmIoctl(bufmgr_gem->fd,
1647 DRM_IOCTL_I915_GEM_PIN,
1652 bo->offset = pin.offset;
1657 drm_intel_gem_bo_unpin(drm_intel_bo *bo)
1659 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1660 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1661 struct drm_i915_gem_unpin unpin;
1664 memset(&unpin, 0, sizeof(unpin));
1665 unpin.handle = bo_gem->gem_handle;
1667 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_UNPIN, &unpin);
1675 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
1676 uint32_t tiling_mode,
1679 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1680 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1681 struct drm_i915_gem_set_tiling set_tiling;
1684 if (bo_gem->global_name == 0 &&
1685 tiling_mode == bo_gem->tiling_mode &&
1686 stride == bo_gem->stride)
1689 memset(&set_tiling, 0, sizeof(set_tiling));
1691 /* set_tiling is slightly broken and overwrites the
1692 * input on the error path, so we have to open code
1695 set_tiling.handle = bo_gem->gem_handle;
1696 set_tiling.tiling_mode = tiling_mode;
1697 set_tiling.stride = stride;
1699 ret = ioctl(bufmgr_gem->fd,
1700 DRM_IOCTL_I915_GEM_SET_TILING,
1702 } while (ret == -1 && (errno == EINTR || errno == EAGAIN));
1706 bo_gem->tiling_mode = set_tiling.tiling_mode;
1707 bo_gem->swizzle_mode = set_tiling.swizzle_mode;
1708 bo_gem->stride = set_tiling.stride;
1713 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1716 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1717 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1720 /* Linear buffers have no stride. By ensuring that we only ever use
1721 * stride 0 with linear buffers, we simplify our code.
1723 if (*tiling_mode == I915_TILING_NONE)
1726 ret = drm_intel_gem_bo_set_tiling_internal(bo, *tiling_mode, stride);
1728 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
1730 *tiling_mode = bo_gem->tiling_mode;
1735 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1736 uint32_t * swizzle_mode)
1738 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1740 *tiling_mode = bo_gem->tiling_mode;
1741 *swizzle_mode = bo_gem->swizzle_mode;
1746 drm_intel_gem_bo_flink(drm_intel_bo *bo, uint32_t * name)
1748 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1749 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1750 struct drm_gem_flink flink;
1753 if (!bo_gem->global_name) {
1754 memset(&flink, 0, sizeof(flink));
1755 flink.handle = bo_gem->gem_handle;
1757 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_FLINK, &flink);
1760 bo_gem->global_name = flink.name;
1761 bo_gem->reusable = 0;
1764 *name = bo_gem->global_name;
1769 * Enables unlimited caching of buffer objects for reuse.
1771 * This is potentially very memory expensive, as the cache at each bucket
1772 * size is only bounded by how many buffers of that size we've managed to have
1773 * in flight at once.
1776 drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr)
1778 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1780 bufmgr_gem->bo_reuse = 1;
1784 * Enable use of fenced reloc type.
1786 * New code should enable this to avoid unnecessary fence register
1787 * allocation. If this option is not enabled, all relocs will have fence
1788 * register allocated.
1791 drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr)
1793 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
1795 if (bufmgr_gem->bufmgr.bo_exec == drm_intel_gem_bo_exec2)
1796 bufmgr_gem->fenced_relocs = 1;
1800 * Return the additional aperture space required by the tree of buffer objects
1804 drm_intel_gem_bo_get_aperture_space(drm_intel_bo *bo)
1806 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1810 if (bo == NULL || bo_gem->included_in_check_aperture)
1814 bo_gem->included_in_check_aperture = 1;
1816 for (i = 0; i < bo_gem->reloc_count; i++)
1818 drm_intel_gem_bo_get_aperture_space(bo_gem->
1819 reloc_target_info[i].bo);
1825 * Count the number of buffers in this list that need a fence reg
1827 * If the count is greater than the number of available regs, we'll have
1828 * to ask the caller to resubmit a batch with fewer tiled buffers.
1830 * This function over-counts if the same buffer is used multiple times.
1833 drm_intel_gem_total_fences(drm_intel_bo ** bo_array, int count)
1836 unsigned int total = 0;
1838 for (i = 0; i < count; i++) {
1839 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
1844 total += bo_gem->reloc_tree_fences;
1850 * Clear the flag set by drm_intel_gem_bo_get_aperture_space() so we're ready
1851 * for the next drm_intel_bufmgr_check_aperture_space() call.
1854 drm_intel_gem_bo_clear_aperture_space_flag(drm_intel_bo *bo)
1856 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1859 if (bo == NULL || !bo_gem->included_in_check_aperture)
1862 bo_gem->included_in_check_aperture = 0;
1864 for (i = 0; i < bo_gem->reloc_count; i++)
1865 drm_intel_gem_bo_clear_aperture_space_flag(bo_gem->
1866 reloc_target_info[i].bo);
1870 * Return a conservative estimate for the amount of aperture required
1871 * for a collection of buffers. This may double-count some buffers.
1874 drm_intel_gem_estimate_batch_space(drm_intel_bo **bo_array, int count)
1877 unsigned int total = 0;
1879 for (i = 0; i < count; i++) {
1880 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
1882 total += bo_gem->reloc_tree_size;
1888 * Return the amount of aperture needed for a collection of buffers.
1889 * This avoids double counting any buffers, at the cost of looking
1890 * at every buffer in the set.
1893 drm_intel_gem_compute_batch_space(drm_intel_bo **bo_array, int count)
1896 unsigned int total = 0;
1898 for (i = 0; i < count; i++) {
1899 total += drm_intel_gem_bo_get_aperture_space(bo_array[i]);
1900 /* For the first buffer object in the array, we get an
1901 * accurate count back for its reloc_tree size (since nothing
1902 * had been flagged as being counted yet). We can save that
1903 * value out as a more conservative reloc_tree_size that
1904 * avoids double-counting target buffers. Since the first
1905 * buffer happens to usually be the batch buffer in our
1906 * callers, this can pull us back from doing the tree
1907 * walk on every new batch emit.
1910 drm_intel_bo_gem *bo_gem =
1911 (drm_intel_bo_gem *) bo_array[i];
1912 bo_gem->reloc_tree_size = total;
1916 for (i = 0; i < count; i++)
1917 drm_intel_gem_bo_clear_aperture_space_flag(bo_array[i]);
1922 * Return -1 if the batchbuffer should be flushed before attempting to
1923 * emit rendering referencing the buffers pointed to by bo_array.
1925 * This is required because if we try to emit a batchbuffer with relocations
1926 * to a tree of buffers that won't simultaneously fit in the aperture,
1927 * the rendering will return an error at a point where the software is not
1928 * prepared to recover from it.
1930 * However, we also want to emit the batchbuffer significantly before we reach
1931 * the limit, as a series of batchbuffers each of which references buffers
1932 * covering almost all of the aperture means that at each emit we end up
1933 * waiting to evict a buffer from the last rendering, and we get synchronous
1934 * performance. By emitting smaller batchbuffers, we eat some CPU overhead to
1935 * get better parallelism.
1938 drm_intel_gem_check_aperture_space(drm_intel_bo **bo_array, int count)
1940 drm_intel_bufmgr_gem *bufmgr_gem =
1941 (drm_intel_bufmgr_gem *) bo_array[0]->bufmgr;
1942 unsigned int total = 0;
1943 unsigned int threshold = bufmgr_gem->gtt_size * 3 / 4;
1946 /* Check for fence reg constraints if necessary */
1947 if (bufmgr_gem->available_fences) {
1948 total_fences = drm_intel_gem_total_fences(bo_array, count);
1949 if (total_fences > bufmgr_gem->available_fences)
1953 total = drm_intel_gem_estimate_batch_space(bo_array, count);
1955 if (total > threshold)
1956 total = drm_intel_gem_compute_batch_space(bo_array, count);
1958 if (total > threshold) {
1959 DBG("check_space: overflowed available aperture, "
1961 total / 1024, (int)bufmgr_gem->gtt_size / 1024);
1964 DBG("drm_check_space: total %dkb vs bufgr %dkb\n", total / 1024,
1965 (int)bufmgr_gem->gtt_size / 1024);
1971 * Disable buffer reuse for objects which are shared with the kernel
1972 * as scanout buffers
1975 drm_intel_gem_bo_disable_reuse(drm_intel_bo *bo)
1977 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1979 bo_gem->reusable = 0;
1984 drm_intel_gem_bo_is_reusable(drm_intel_bo *bo)
1986 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1988 return bo_gem->reusable;
1992 _drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
1994 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1997 for (i = 0; i < bo_gem->reloc_count; i++) {
1998 if (bo_gem->reloc_target_info[i].bo == target_bo)
2000 if (bo == bo_gem->reloc_target_info[i].bo)
2002 if (_drm_intel_gem_bo_references(bo_gem->reloc_target_info[i].bo,
2010 /** Return true if target_bo is referenced by bo's relocation tree. */
2012 drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
2014 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
2016 if (bo == NULL || target_bo == NULL)
2018 if (target_bo_gem->used_as_reloc_target)
2019 return _drm_intel_gem_bo_references(bo, target_bo);
2024 add_bucket(drm_intel_bufmgr_gem *bufmgr_gem, int size)
2026 unsigned int i = bufmgr_gem->num_buckets;
2028 assert(i < ARRAY_SIZE(bufmgr_gem->cache_bucket));
2030 DRMINITLISTHEAD(&bufmgr_gem->cache_bucket[i].head);
2031 bufmgr_gem->cache_bucket[i].size = size;
2032 bufmgr_gem->num_buckets++;
2036 init_cache_buckets(drm_intel_bufmgr_gem *bufmgr_gem)
2038 unsigned long size, cache_max_size = 64 * 1024 * 1024;
2040 /* OK, so power of two buckets was too wasteful of memory.
2041 * Give 3 other sizes between each power of two, to hopefully
2042 * cover things accurately enough. (The alternative is
2043 * probably to just go for exact matching of sizes, and assume
2044 * that for things like composited window resize the tiled
2045 * width/height alignment and rounding of sizes to pages will
2046 * get us useful cache hit rates anyway)
2048 add_bucket(bufmgr_gem, 4096);
2049 add_bucket(bufmgr_gem, 4096 * 2);
2050 add_bucket(bufmgr_gem, 4096 * 3);
2052 /* Initialize the linked lists for BO reuse cache. */
2053 for (size = 4 * 4096; size <= cache_max_size; size *= 2) {
2054 add_bucket(bufmgr_gem, size);
2056 add_bucket(bufmgr_gem, size + size * 1 / 4);
2057 add_bucket(bufmgr_gem, size + size * 2 / 4);
2058 add_bucket(bufmgr_gem, size + size * 3 / 4);
2063 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
2064 * and manage map buffer objections.
2066 * \param fd File descriptor of the opened DRM device.
2069 drm_intel_bufmgr_gem_init(int fd, int batch_size)
2071 drm_intel_bufmgr_gem *bufmgr_gem;
2072 struct drm_i915_gem_get_aperture aperture;
2073 drm_i915_getparam_t gp;
2077 bufmgr_gem = calloc(1, sizeof(*bufmgr_gem));
2078 if (bufmgr_gem == NULL)
2081 bufmgr_gem->fd = fd;
2083 if (pthread_mutex_init(&bufmgr_gem->lock, NULL) != 0) {
2088 ret = drmIoctl(bufmgr_gem->fd,
2089 DRM_IOCTL_I915_GEM_GET_APERTURE,
2093 bufmgr_gem->gtt_size = aperture.aper_available_size;
2095 fprintf(stderr, "DRM_IOCTL_I915_GEM_APERTURE failed: %s\n",
2097 bufmgr_gem->gtt_size = 128 * 1024 * 1024;
2098 fprintf(stderr, "Assuming %dkB available aperture size.\n"
2099 "May lead to reduced performance or incorrect "
2101 (int)bufmgr_gem->gtt_size / 1024);
2104 gp.param = I915_PARAM_CHIPSET_ID;
2105 gp.value = &bufmgr_gem->pci_device;
2106 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2108 fprintf(stderr, "get chip id failed: %d [%d]\n", ret, errno);
2109 fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value);
2112 if (IS_GEN2(bufmgr_gem))
2113 bufmgr_gem->gen = 2;
2114 else if (IS_GEN3(bufmgr_gem))
2115 bufmgr_gem->gen = 3;
2116 else if (IS_GEN4(bufmgr_gem))
2117 bufmgr_gem->gen = 4;
2119 bufmgr_gem->gen = 6;
2121 gp.param = I915_PARAM_HAS_EXECBUF2;
2122 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2126 gp.param = I915_PARAM_HAS_BSD;
2127 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2128 bufmgr_gem->has_bsd = ret == 0;
2130 gp.param = I915_PARAM_HAS_BLT;
2131 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2132 bufmgr_gem->has_blt = ret == 0;
2134 gp.param = I915_PARAM_HAS_RELAXED_FENCING;
2135 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2136 bufmgr_gem->has_relaxed_fencing = ret == 0;
2138 if (bufmgr_gem->gen < 4) {
2139 gp.param = I915_PARAM_NUM_FENCES_AVAIL;
2140 gp.value = &bufmgr_gem->available_fences;
2141 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2143 fprintf(stderr, "get fences failed: %d [%d]\n", ret,
2145 fprintf(stderr, "param: %d, val: %d\n", gp.param,
2147 bufmgr_gem->available_fences = 0;
2149 /* XXX The kernel reports the total number of fences,
2150 * including any that may be pinned.
2152 * We presume that there will be at least one pinned
2153 * fence for the scanout buffer, but there may be more
2154 * than one scanout and the user may be manually
2155 * pinning buffers. Let's move to execbuffer2 and
2156 * thereby forget the insanity of using fences...
2158 bufmgr_gem->available_fences -= 2;
2159 if (bufmgr_gem->available_fences < 0)
2160 bufmgr_gem->available_fences = 0;
2164 /* Let's go with one relocation per every 2 dwords (but round down a bit
2165 * since a power of two will mean an extra page allocation for the reloc
2168 * Every 4 was too few for the blender benchmark.
2170 bufmgr_gem->max_relocs = batch_size / sizeof(uint32_t) / 2 - 2;
2172 bufmgr_gem->bufmgr.bo_alloc = drm_intel_gem_bo_alloc;
2173 bufmgr_gem->bufmgr.bo_alloc_for_render =
2174 drm_intel_gem_bo_alloc_for_render;
2175 bufmgr_gem->bufmgr.bo_alloc_tiled = drm_intel_gem_bo_alloc_tiled;
2176 bufmgr_gem->bufmgr.bo_reference = drm_intel_gem_bo_reference;
2177 bufmgr_gem->bufmgr.bo_unreference = drm_intel_gem_bo_unreference;
2178 bufmgr_gem->bufmgr.bo_map = drm_intel_gem_bo_map;
2179 bufmgr_gem->bufmgr.bo_unmap = drm_intel_gem_bo_unmap;
2180 bufmgr_gem->bufmgr.bo_subdata = drm_intel_gem_bo_subdata;
2181 bufmgr_gem->bufmgr.bo_get_subdata = drm_intel_gem_bo_get_subdata;
2182 bufmgr_gem->bufmgr.bo_wait_rendering = drm_intel_gem_bo_wait_rendering;
2183 bufmgr_gem->bufmgr.bo_emit_reloc = drm_intel_gem_bo_emit_reloc;
2184 bufmgr_gem->bufmgr.bo_emit_reloc_fence = drm_intel_gem_bo_emit_reloc_fence;
2185 bufmgr_gem->bufmgr.bo_pin = drm_intel_gem_bo_pin;
2186 bufmgr_gem->bufmgr.bo_unpin = drm_intel_gem_bo_unpin;
2187 bufmgr_gem->bufmgr.bo_get_tiling = drm_intel_gem_bo_get_tiling;
2188 bufmgr_gem->bufmgr.bo_set_tiling = drm_intel_gem_bo_set_tiling;
2189 bufmgr_gem->bufmgr.bo_flink = drm_intel_gem_bo_flink;
2190 /* Use the new one if available */
2192 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec2;
2193 if (bufmgr_gem->has_bsd|bufmgr_gem->has_blt)
2194 bufmgr_gem->bufmgr.bo_mrb_exec = drm_intel_gem_bo_mrb_exec2;
2196 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec;
2197 bufmgr_gem->bufmgr.bo_busy = drm_intel_gem_bo_busy;
2198 bufmgr_gem->bufmgr.bo_madvise = drm_intel_gem_bo_madvise;
2199 bufmgr_gem->bufmgr.destroy = drm_intel_bufmgr_gem_destroy;
2200 bufmgr_gem->bufmgr.debug = 0;
2201 bufmgr_gem->bufmgr.check_aperture_space =
2202 drm_intel_gem_check_aperture_space;
2203 bufmgr_gem->bufmgr.bo_disable_reuse = drm_intel_gem_bo_disable_reuse;
2204 bufmgr_gem->bufmgr.bo_is_reusable = drm_intel_gem_bo_is_reusable;
2205 bufmgr_gem->bufmgr.get_pipe_from_crtc_id =
2206 drm_intel_gem_get_pipe_from_crtc_id;
2207 bufmgr_gem->bufmgr.bo_references = drm_intel_gem_bo_references;
2209 init_cache_buckets(bufmgr_gem);
2211 return &bufmgr_gem->bufmgr;