1 /**************************************************************************
3 * Copyright © 2007 Red Hat Inc.
4 * Copyright © 2007 Intel Corporation
5 * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
29 **************************************************************************/
31 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
32 * Keith Whitwell <keithw-at-tungstengraphics-dot-com>
33 * Eric Anholt <eric@anholt.net>
34 * Dave Airlie <airlied@linux.ie>
42 #include <xf86atomic.h>
50 #include <sys/ioctl.h>
53 #include <sys/types.h>
57 #include "libdrm_lists.h"
58 #include "intel_bufmgr.h"
59 #include "intel_bufmgr_priv.h"
60 #include "intel_chipset.h"
65 #define DBG(...) do { \
66 if (bufmgr_gem->bufmgr.debug) \
67 fprintf(stderr, __VA_ARGS__); \
70 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
72 typedef struct _drm_intel_bo_gem drm_intel_bo_gem;
74 struct drm_intel_gem_bo_bucket {
79 typedef struct _drm_intel_bufmgr_gem {
80 drm_intel_bufmgr bufmgr;
88 struct drm_i915_gem_exec_object *exec_objects;
89 struct drm_i915_gem_exec_object2 *exec2_objects;
90 drm_intel_bo **exec_bos;
94 /** Array of lists of cached gem objects of power-of-two sizes */
95 struct drm_intel_gem_bo_bucket cache_bucket[14 * 4];
100 drmMMListHead vma_cache;
101 int vma_count, vma_max;
104 int available_fences;
107 unsigned int has_bsd : 1;
108 unsigned int has_blt : 1;
109 unsigned int has_relaxed_fencing : 1;
110 unsigned int bo_reuse : 1;
112 } drm_intel_bufmgr_gem;
114 #define DRM_INTEL_RELOC_FENCE (1<<0)
116 typedef struct _drm_intel_reloc_target_info {
119 } drm_intel_reloc_target;
121 struct _drm_intel_bo_gem {
129 * Kenel-assigned global name for this object
131 unsigned int global_name;
132 drmMMListHead name_list;
135 * Index of the buffer within the validation list while preparing a
136 * batchbuffer execution.
141 * Current tiling mode
143 uint32_t tiling_mode;
144 uint32_t swizzle_mode;
145 unsigned long stride;
149 /** Array passed to the DRM containing relocation information. */
150 struct drm_i915_gem_relocation_entry *relocs;
152 * Array of info structs corresponding to relocs[i].target_handle etc
154 drm_intel_reloc_target *reloc_target_info;
155 /** Number of entries in relocs */
157 /** Mapped address for the buffer, saved across map/unmap cycles */
159 /** GTT virtual address for the buffer, saved across map/unmap cycles */
162 drmMMListHead vma_list;
168 * Boolean of whether this BO and its children have been included in
169 * the current drm_intel_bufmgr_check_aperture_space() total.
171 bool included_in_check_aperture;
174 * Boolean of whether this buffer has been used as a relocation
175 * target and had its size accounted for, and thus can't have any
176 * further relocations added to it.
178 bool used_as_reloc_target;
181 * Boolean of whether we have encountered an error whilst building the relocation tree.
186 * Boolean of whether this buffer can be re-used
191 * Size in bytes of this buffer and its relocation descendents.
193 * Used to avoid costly tree walking in
194 * drm_intel_bufmgr_check_aperture in the common case.
199 * Number of potential fence registers required by this buffer and its
202 int reloc_tree_fences;
204 /** Flags that we may need to do the SW_FINSIH ioctl on unmap. */
205 bool mapped_cpu_write;
209 drm_intel_gem_estimate_batch_space(drm_intel_bo ** bo_array, int count);
212 drm_intel_gem_compute_batch_space(drm_intel_bo ** bo_array, int count);
215 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
216 uint32_t * swizzle_mode);
219 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
220 uint32_t tiling_mode,
223 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
226 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo);
228 static void drm_intel_gem_bo_free(drm_intel_bo *bo);
231 drm_intel_gem_bo_tile_size(drm_intel_bufmgr_gem *bufmgr_gem, unsigned long size,
232 uint32_t *tiling_mode)
234 unsigned long min_size, max_size;
237 if (*tiling_mode == I915_TILING_NONE)
240 /* 965+ just need multiples of page size for tiling */
241 if (bufmgr_gem->gen >= 4)
242 return ROUND_UP_TO(size, 4096);
244 /* Older chips need powers of two, of at least 512k or 1M */
245 if (bufmgr_gem->gen == 3) {
246 min_size = 1024*1024;
247 max_size = 128*1024*1024;
250 max_size = 64*1024*1024;
253 if (size > max_size) {
254 *tiling_mode = I915_TILING_NONE;
258 /* Do we need to allocate every page for the fence? */
259 if (bufmgr_gem->has_relaxed_fencing)
260 return ROUND_UP_TO(size, 4096);
262 for (i = min_size; i < size; i <<= 1)
269 * Round a given pitch up to the minimum required for X tiling on a
270 * given chip. We use 512 as the minimum to allow for a later tiling
274 drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem,
275 unsigned long pitch, uint32_t *tiling_mode)
277 unsigned long tile_width;
280 /* If untiled, then just align it so that we can do rendering
281 * to it with the 3D engine.
283 if (*tiling_mode == I915_TILING_NONE)
284 return ALIGN(pitch, 64);
286 if (*tiling_mode == I915_TILING_X
287 || (IS_915(bufmgr_gem) && *tiling_mode == I915_TILING_Y))
292 /* 965 is flexible */
293 if (bufmgr_gem->gen >= 4)
294 return ROUND_UP_TO(pitch, tile_width);
296 /* The older hardware has a maximum pitch of 8192 with tiled
297 * surfaces, so fallback to untiled if it's too large.
300 *tiling_mode = I915_TILING_NONE;
301 return ALIGN(pitch, 64);
304 /* Pre-965 needs power of two tile width */
305 for (i = tile_width; i < pitch; i <<= 1)
311 static struct drm_intel_gem_bo_bucket *
312 drm_intel_gem_bo_bucket_for_size(drm_intel_bufmgr_gem *bufmgr_gem,
317 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
318 struct drm_intel_gem_bo_bucket *bucket =
319 &bufmgr_gem->cache_bucket[i];
320 if (bucket->size >= size) {
329 drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem *bufmgr_gem)
333 for (i = 0; i < bufmgr_gem->exec_count; i++) {
334 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
335 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
337 if (bo_gem->relocs == NULL) {
338 DBG("%2d: %d (%s)\n", i, bo_gem->gem_handle,
343 for (j = 0; j < bo_gem->reloc_count; j++) {
344 drm_intel_bo *target_bo = bo_gem->reloc_target_info[j].bo;
345 drm_intel_bo_gem *target_gem =
346 (drm_intel_bo_gem *) target_bo;
348 DBG("%2d: %d (%s)@0x%08llx -> "
349 "%d (%s)@0x%08lx + 0x%08x\n",
351 bo_gem->gem_handle, bo_gem->name,
352 (unsigned long long)bo_gem->relocs[j].offset,
353 target_gem->gem_handle,
356 bo_gem->relocs[j].delta);
362 drm_intel_gem_bo_reference(drm_intel_bo *bo)
364 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
366 atomic_inc(&bo_gem->refcount);
370 * Adds the given buffer to the list of buffers to be validated (moved into the
371 * appropriate memory type) with the next batch submission.
373 * If a buffer is validated multiple times in a batch submission, it ends up
374 * with the intersection of the memory type flags and the union of the
378 drm_intel_add_validate_buffer(drm_intel_bo *bo)
380 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
381 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
384 if (bo_gem->validate_index != -1)
387 /* Extend the array of validation entries as necessary. */
388 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
389 int new_size = bufmgr_gem->exec_size * 2;
394 bufmgr_gem->exec_objects =
395 realloc(bufmgr_gem->exec_objects,
396 sizeof(*bufmgr_gem->exec_objects) * new_size);
397 bufmgr_gem->exec_bos =
398 realloc(bufmgr_gem->exec_bos,
399 sizeof(*bufmgr_gem->exec_bos) * new_size);
400 bufmgr_gem->exec_size = new_size;
403 index = bufmgr_gem->exec_count;
404 bo_gem->validate_index = index;
405 /* Fill in array entry */
406 bufmgr_gem->exec_objects[index].handle = bo_gem->gem_handle;
407 bufmgr_gem->exec_objects[index].relocation_count = bo_gem->reloc_count;
408 bufmgr_gem->exec_objects[index].relocs_ptr = (uintptr_t) bo_gem->relocs;
409 bufmgr_gem->exec_objects[index].alignment = 0;
410 bufmgr_gem->exec_objects[index].offset = 0;
411 bufmgr_gem->exec_bos[index] = bo;
412 bufmgr_gem->exec_count++;
416 drm_intel_add_validate_buffer2(drm_intel_bo *bo, int need_fence)
418 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
419 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
422 if (bo_gem->validate_index != -1) {
424 bufmgr_gem->exec2_objects[bo_gem->validate_index].flags |=
425 EXEC_OBJECT_NEEDS_FENCE;
429 /* Extend the array of validation entries as necessary. */
430 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
431 int new_size = bufmgr_gem->exec_size * 2;
436 bufmgr_gem->exec2_objects =
437 realloc(bufmgr_gem->exec2_objects,
438 sizeof(*bufmgr_gem->exec2_objects) * new_size);
439 bufmgr_gem->exec_bos =
440 realloc(bufmgr_gem->exec_bos,
441 sizeof(*bufmgr_gem->exec_bos) * new_size);
442 bufmgr_gem->exec_size = new_size;
445 index = bufmgr_gem->exec_count;
446 bo_gem->validate_index = index;
447 /* Fill in array entry */
448 bufmgr_gem->exec2_objects[index].handle = bo_gem->gem_handle;
449 bufmgr_gem->exec2_objects[index].relocation_count = bo_gem->reloc_count;
450 bufmgr_gem->exec2_objects[index].relocs_ptr = (uintptr_t)bo_gem->relocs;
451 bufmgr_gem->exec2_objects[index].alignment = 0;
452 bufmgr_gem->exec2_objects[index].offset = 0;
453 bufmgr_gem->exec_bos[index] = bo;
454 bufmgr_gem->exec2_objects[index].flags = 0;
455 bufmgr_gem->exec2_objects[index].rsvd1 = 0;
456 bufmgr_gem->exec2_objects[index].rsvd2 = 0;
458 bufmgr_gem->exec2_objects[index].flags |=
459 EXEC_OBJECT_NEEDS_FENCE;
461 bufmgr_gem->exec_count++;
464 #define RELOC_BUF_SIZE(x) ((I915_RELOC_HEADER + x * I915_RELOC0_STRIDE) * \
468 drm_intel_bo_gem_set_in_aperture_size(drm_intel_bufmgr_gem *bufmgr_gem,
469 drm_intel_bo_gem *bo_gem)
473 assert(!bo_gem->used_as_reloc_target);
475 /* The older chipsets are far-less flexible in terms of tiling,
476 * and require tiled buffer to be size aligned in the aperture.
477 * This means that in the worst possible case we will need a hole
478 * twice as large as the object in order for it to fit into the
479 * aperture. Optimal packing is for wimps.
481 size = bo_gem->bo.size;
482 if (bufmgr_gem->gen < 4 && bo_gem->tiling_mode != I915_TILING_NONE) {
485 if (bufmgr_gem->has_relaxed_fencing) {
486 if (bufmgr_gem->gen == 3)
487 min_size = 1024*1024;
491 while (min_size < size)
496 /* Account for worst-case alignment. */
500 bo_gem->reloc_tree_size = size;
504 drm_intel_setup_reloc_list(drm_intel_bo *bo)
506 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
507 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
508 unsigned int max_relocs = bufmgr_gem->max_relocs;
510 if (bo->size / 4 < max_relocs)
511 max_relocs = bo->size / 4;
513 bo_gem->relocs = malloc(max_relocs *
514 sizeof(struct drm_i915_gem_relocation_entry));
515 bo_gem->reloc_target_info = malloc(max_relocs *
516 sizeof(drm_intel_reloc_target));
517 if (bo_gem->relocs == NULL || bo_gem->reloc_target_info == NULL) {
518 bo_gem->has_error = true;
520 free (bo_gem->relocs);
521 bo_gem->relocs = NULL;
523 free (bo_gem->reloc_target_info);
524 bo_gem->reloc_target_info = NULL;
533 drm_intel_gem_bo_busy(drm_intel_bo *bo)
535 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
536 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
537 struct drm_i915_gem_busy busy;
540 memset(&busy, 0, sizeof(busy));
541 busy.handle = bo_gem->gem_handle;
543 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_BUSY, &busy);
545 return (ret == 0 && busy.busy);
549 drm_intel_gem_bo_madvise_internal(drm_intel_bufmgr_gem *bufmgr_gem,
550 drm_intel_bo_gem *bo_gem, int state)
552 struct drm_i915_gem_madvise madv;
554 madv.handle = bo_gem->gem_handle;
557 drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MADVISE, &madv);
559 return madv.retained;
563 drm_intel_gem_bo_madvise(drm_intel_bo *bo, int madv)
565 return drm_intel_gem_bo_madvise_internal
566 ((drm_intel_bufmgr_gem *) bo->bufmgr,
567 (drm_intel_bo_gem *) bo,
571 /* drop the oldest entries that have been purged by the kernel */
573 drm_intel_gem_bo_cache_purge_bucket(drm_intel_bufmgr_gem *bufmgr_gem,
574 struct drm_intel_gem_bo_bucket *bucket)
576 while (!DRMLISTEMPTY(&bucket->head)) {
577 drm_intel_bo_gem *bo_gem;
579 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
580 bucket->head.next, head);
581 if (drm_intel_gem_bo_madvise_internal
582 (bufmgr_gem, bo_gem, I915_MADV_DONTNEED))
585 DRMLISTDEL(&bo_gem->head);
586 drm_intel_gem_bo_free(&bo_gem->bo);
590 static drm_intel_bo *
591 drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr,
595 uint32_t tiling_mode,
596 unsigned long stride)
598 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
599 drm_intel_bo_gem *bo_gem;
600 unsigned int page_size = getpagesize();
602 struct drm_intel_gem_bo_bucket *bucket;
603 bool alloc_from_cache;
604 unsigned long bo_size;
605 bool for_render = false;
607 if (flags & BO_ALLOC_FOR_RENDER)
610 /* Round the allocated size up to a power of two number of pages. */
611 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, size);
613 /* If we don't have caching at this size, don't actually round the
616 if (bucket == NULL) {
618 if (bo_size < page_size)
621 bo_size = bucket->size;
624 pthread_mutex_lock(&bufmgr_gem->lock);
625 /* Get a buffer out of the cache if available */
627 alloc_from_cache = false;
628 if (bucket != NULL && !DRMLISTEMPTY(&bucket->head)) {
630 /* Allocate new render-target BOs from the tail (MRU)
631 * of the list, as it will likely be hot in the GPU
632 * cache and in the aperture for us.
634 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
635 bucket->head.prev, head);
636 DRMLISTDEL(&bo_gem->head);
637 alloc_from_cache = true;
639 /* For non-render-target BOs (where we're probably
640 * going to map it first thing in order to fill it
641 * with data), check if the last BO in the cache is
642 * unbusy, and only reuse in that case. Otherwise,
643 * allocating a new buffer is probably faster than
644 * waiting for the GPU to finish.
646 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
647 bucket->head.next, head);
648 if (!drm_intel_gem_bo_busy(&bo_gem->bo)) {
649 alloc_from_cache = true;
650 DRMLISTDEL(&bo_gem->head);
654 if (alloc_from_cache) {
655 if (!drm_intel_gem_bo_madvise_internal
656 (bufmgr_gem, bo_gem, I915_MADV_WILLNEED)) {
657 drm_intel_gem_bo_free(&bo_gem->bo);
658 drm_intel_gem_bo_cache_purge_bucket(bufmgr_gem,
663 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
666 drm_intel_gem_bo_free(&bo_gem->bo);
671 pthread_mutex_unlock(&bufmgr_gem->lock);
673 if (!alloc_from_cache) {
674 struct drm_i915_gem_create create;
676 bo_gem = calloc(1, sizeof(*bo_gem));
680 bo_gem->bo.size = bo_size;
681 memset(&create, 0, sizeof(create));
682 create.size = bo_size;
684 ret = drmIoctl(bufmgr_gem->fd,
685 DRM_IOCTL_I915_GEM_CREATE,
687 bo_gem->gem_handle = create.handle;
688 bo_gem->bo.handle = bo_gem->gem_handle;
693 bo_gem->bo.bufmgr = bufmgr;
695 bo_gem->tiling_mode = I915_TILING_NONE;
696 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
699 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
702 drm_intel_gem_bo_free(&bo_gem->bo);
706 DRMINITLISTHEAD(&bo_gem->name_list);
707 DRMINITLISTHEAD(&bo_gem->vma_list);
711 atomic_set(&bo_gem->refcount, 1);
712 bo_gem->validate_index = -1;
713 bo_gem->reloc_tree_fences = 0;
714 bo_gem->used_as_reloc_target = false;
715 bo_gem->has_error = false;
716 bo_gem->reusable = true;
718 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
720 DBG("bo_create: buf %d (%s) %ldb\n",
721 bo_gem->gem_handle, bo_gem->name, size);
726 static drm_intel_bo *
727 drm_intel_gem_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
730 unsigned int alignment)
732 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size,
734 I915_TILING_NONE, 0);
737 static drm_intel_bo *
738 drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr,
741 unsigned int alignment)
743 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, 0,
744 I915_TILING_NONE, 0);
747 static drm_intel_bo *
748 drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
749 int x, int y, int cpp, uint32_t *tiling_mode,
750 unsigned long *pitch, unsigned long flags)
752 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
753 unsigned long size, stride;
757 unsigned long aligned_y, height_alignment;
759 tiling = *tiling_mode;
761 /* If we're tiled, our allocations are in 8 or 32-row blocks,
762 * so failure to align our height means that we won't allocate
765 * If we're untiled, we still have to align to 2 rows high
766 * because the data port accesses 2x2 blocks even if the
767 * bottom row isn't to be rendered, so failure to align means
768 * we could walk off the end of the GTT and fault. This is
769 * documented on 965, and may be the case on older chipsets
770 * too so we try to be careful.
773 height_alignment = 2;
775 if (IS_GEN2(bufmgr_gem) && tiling != I915_TILING_NONE)
776 height_alignment = 16;
777 else if (tiling == I915_TILING_X
778 || (IS_915(bufmgr_gem) && tiling == I915_TILING_Y))
779 height_alignment = 8;
780 else if (tiling == I915_TILING_Y)
781 height_alignment = 32;
782 aligned_y = ALIGN(y, height_alignment);
785 stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, tiling_mode);
786 size = stride * aligned_y;
787 size = drm_intel_gem_bo_tile_size(bufmgr_gem, size, tiling_mode);
788 } while (*tiling_mode != tiling);
791 if (tiling == I915_TILING_NONE)
794 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, flags,
799 * Returns a drm_intel_bo wrapping the given buffer object handle.
801 * This can be used when one application needs to pass a buffer object
805 drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
809 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
810 drm_intel_bo_gem *bo_gem;
812 struct drm_gem_open open_arg;
813 struct drm_i915_gem_get_tiling get_tiling;
816 /* At the moment most applications only have a few named bo.
817 * For instance, in a DRI client only the render buffers passed
818 * between X and the client are named. And since X returns the
819 * alternating names for the front/back buffer a linear search
820 * provides a sufficiently fast match.
822 for (list = bufmgr_gem->named.next;
823 list != &bufmgr_gem->named;
825 bo_gem = DRMLISTENTRY(drm_intel_bo_gem, list, name_list);
826 if (bo_gem->global_name == handle) {
827 drm_intel_gem_bo_reference(&bo_gem->bo);
832 bo_gem = calloc(1, sizeof(*bo_gem));
836 memset(&open_arg, 0, sizeof(open_arg));
837 open_arg.name = handle;
838 ret = drmIoctl(bufmgr_gem->fd,
842 DBG("Couldn't reference %s handle 0x%08x: %s\n",
843 name, handle, strerror(errno));
847 bo_gem->bo.size = open_arg.size;
848 bo_gem->bo.offset = 0;
849 bo_gem->bo.virtual = NULL;
850 bo_gem->bo.bufmgr = bufmgr;
852 atomic_set(&bo_gem->refcount, 1);
853 bo_gem->validate_index = -1;
854 bo_gem->gem_handle = open_arg.handle;
855 bo_gem->bo.handle = open_arg.handle;
856 bo_gem->global_name = handle;
857 bo_gem->reusable = false;
859 memset(&get_tiling, 0, sizeof(get_tiling));
860 get_tiling.handle = bo_gem->gem_handle;
861 ret = drmIoctl(bufmgr_gem->fd,
862 DRM_IOCTL_I915_GEM_GET_TILING,
865 drm_intel_gem_bo_unreference(&bo_gem->bo);
868 bo_gem->tiling_mode = get_tiling.tiling_mode;
869 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
870 /* XXX stride is unknown */
871 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
873 DRMINITLISTHEAD(&bo_gem->vma_list);
874 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
875 DBG("bo_create_from_handle: %d (%s)\n", handle, bo_gem->name);
881 drm_intel_gem_bo_free(drm_intel_bo *bo)
883 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
884 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
885 struct drm_gem_close close;
888 DRMLISTDEL(&bo_gem->vma_list);
889 if (bo_gem->mem_virtual) {
890 munmap(bo_gem->mem_virtual, bo_gem->bo.size);
891 bufmgr_gem->vma_count--;
893 if (bo_gem->gtt_virtual) {
894 munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
895 bufmgr_gem->vma_count--;
898 /* Close this object */
899 memset(&close, 0, sizeof(close));
900 close.handle = bo_gem->gem_handle;
901 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close);
903 DBG("DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
904 bo_gem->gem_handle, bo_gem->name, strerror(errno));
909 /** Frees all cached buffers significantly older than @time. */
911 drm_intel_gem_cleanup_bo_cache(drm_intel_bufmgr_gem *bufmgr_gem, time_t time)
915 if (bufmgr_gem->time == time)
918 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
919 struct drm_intel_gem_bo_bucket *bucket =
920 &bufmgr_gem->cache_bucket[i];
922 while (!DRMLISTEMPTY(&bucket->head)) {
923 drm_intel_bo_gem *bo_gem;
925 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
926 bucket->head.next, head);
927 if (time - bo_gem->free_time <= 1)
930 DRMLISTDEL(&bo_gem->head);
932 drm_intel_gem_bo_free(&bo_gem->bo);
936 bufmgr_gem->time = time;
939 static void drm_intel_gem_bo_purge_vma_cache(drm_intel_bufmgr_gem *bufmgr_gem)
941 DBG("%s: count=%d, limit=%d\n", __FUNCTION__,
942 bufmgr_gem->vma_count, bufmgr_gem->vma_max);
944 if (bufmgr_gem->vma_max < 0)
947 while (bufmgr_gem->vma_count > bufmgr_gem->vma_max) {
948 drm_intel_bo_gem *bo_gem;
950 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
951 bufmgr_gem->vma_cache.next,
953 assert(bo_gem->map_count == 0);
954 DRMLISTDEL(&bo_gem->vma_list);
956 if (bo_gem->mem_virtual) {
957 munmap(bo_gem->mem_virtual, bo_gem->bo.size);
958 bo_gem->mem_virtual = NULL;
959 bufmgr_gem->vma_count--;
961 if (bo_gem->gtt_virtual) {
962 munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
963 bo_gem->gtt_virtual = NULL;
964 bufmgr_gem->vma_count--;
969 static void drm_intel_gem_bo_add_to_vma_cache(drm_intel_bufmgr_gem *bufmgr_gem,
970 drm_intel_bo_gem *bo_gem)
972 DRMLISTADDTAIL(&bo_gem->vma_list, &bufmgr_gem->vma_cache);
973 if (bo_gem->mem_virtual)
974 bufmgr_gem->vma_count++;
975 if (bo_gem->gtt_virtual)
976 bufmgr_gem->vma_count++;
977 drm_intel_gem_bo_purge_vma_cache(bufmgr_gem);
980 static void drm_intel_gem_bo_remove_from_vma_cache(drm_intel_bufmgr_gem *bufmgr_gem,
981 drm_intel_bo_gem *bo_gem)
983 DRMLISTDEL(&bo_gem->vma_list);
984 if (bo_gem->mem_virtual)
985 bufmgr_gem->vma_count--;
986 if (bo_gem->gtt_virtual)
987 bufmgr_gem->vma_count--;
991 drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time)
993 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
994 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
995 struct drm_intel_gem_bo_bucket *bucket;
998 /* Unreference all the target buffers */
999 for (i = 0; i < bo_gem->reloc_count; i++) {
1000 if (bo_gem->reloc_target_info[i].bo != bo) {
1001 drm_intel_gem_bo_unreference_locked_timed(bo_gem->
1002 reloc_target_info[i].bo,
1006 bo_gem->reloc_count = 0;
1007 bo_gem->used_as_reloc_target = false;
1009 DBG("bo_unreference final: %d (%s)\n",
1010 bo_gem->gem_handle, bo_gem->name);
1012 /* release memory associated with this object */
1013 if (bo_gem->reloc_target_info) {
1014 free(bo_gem->reloc_target_info);
1015 bo_gem->reloc_target_info = NULL;
1017 if (bo_gem->relocs) {
1018 free(bo_gem->relocs);
1019 bo_gem->relocs = NULL;
1022 /* Clear any left-over mappings */
1023 if (bo_gem->map_count) {
1024 DBG("bo freed with non-zero map-count %d\n", bo_gem->map_count);
1025 bo_gem->map_count = 0;
1028 DRMLISTDEL(&bo_gem->name_list);
1030 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, bo->size);
1031 /* Put the buffer into our internal cache for reuse if we can. */
1032 if (bufmgr_gem->bo_reuse && bo_gem->reusable && bucket != NULL &&
1033 drm_intel_gem_bo_madvise_internal(bufmgr_gem, bo_gem,
1034 I915_MADV_DONTNEED)) {
1035 bo_gem->free_time = time;
1037 bo_gem->name = NULL;
1038 bo_gem->validate_index = -1;
1040 if (bo_gem->mem_virtual || bo_gem->gtt_virtual)
1041 drm_intel_gem_bo_add_to_vma_cache(bufmgr_gem, bo_gem);
1043 DRMLISTADDTAIL(&bo_gem->head, &bucket->head);
1045 drm_intel_gem_bo_free(bo);
1049 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
1052 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1054 assert(atomic_read(&bo_gem->refcount) > 0);
1055 if (atomic_dec_and_test(&bo_gem->refcount))
1056 drm_intel_gem_bo_unreference_final(bo, time);
1059 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo)
1061 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1063 assert(atomic_read(&bo_gem->refcount) > 0);
1064 if (atomic_dec_and_test(&bo_gem->refcount)) {
1065 drm_intel_bufmgr_gem *bufmgr_gem =
1066 (drm_intel_bufmgr_gem *) bo->bufmgr;
1067 struct timespec time;
1069 clock_gettime(CLOCK_MONOTONIC, &time);
1071 pthread_mutex_lock(&bufmgr_gem->lock);
1072 drm_intel_gem_bo_unreference_final(bo, time.tv_sec);
1073 drm_intel_gem_cleanup_bo_cache(bufmgr_gem, time.tv_sec);
1074 pthread_mutex_unlock(&bufmgr_gem->lock);
1078 static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable)
1080 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1081 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1082 struct drm_i915_gem_set_domain set_domain;
1085 pthread_mutex_lock(&bufmgr_gem->lock);
1087 if (bo_gem->map_count++ == 0)
1088 drm_intel_gem_bo_remove_from_vma_cache(bufmgr_gem, bo_gem);
1090 if (!bo_gem->mem_virtual) {
1091 struct drm_i915_gem_mmap mmap_arg;
1093 DBG("bo_map: %d (%s)\n", bo_gem->gem_handle, bo_gem->name);
1094 assert(bo_gem->map_count == 1);
1096 memset(&mmap_arg, 0, sizeof(mmap_arg));
1097 mmap_arg.handle = bo_gem->gem_handle;
1098 mmap_arg.offset = 0;
1099 mmap_arg.size = bo->size;
1100 ret = drmIoctl(bufmgr_gem->fd,
1101 DRM_IOCTL_I915_GEM_MMAP,
1105 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1106 __FILE__, __LINE__, bo_gem->gem_handle,
1107 bo_gem->name, strerror(errno));
1108 if (--bo_gem->map_count == 0)
1109 drm_intel_gem_bo_add_to_vma_cache(bufmgr_gem, bo_gem);
1110 pthread_mutex_unlock(&bufmgr_gem->lock);
1113 bo_gem->mem_virtual = (void *)(uintptr_t) mmap_arg.addr_ptr;
1115 DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1116 bo_gem->mem_virtual);
1117 bo->virtual = bo_gem->mem_virtual;
1119 set_domain.handle = bo_gem->gem_handle;
1120 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
1122 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
1124 set_domain.write_domain = 0;
1125 ret = drmIoctl(bufmgr_gem->fd,
1126 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1129 DBG("%s:%d: Error setting to CPU domain %d: %s\n",
1130 __FILE__, __LINE__, bo_gem->gem_handle,
1135 bo_gem->mapped_cpu_write = true;
1137 pthread_mutex_unlock(&bufmgr_gem->lock);
1142 int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
1144 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1145 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1146 struct drm_i915_gem_set_domain set_domain;
1149 pthread_mutex_lock(&bufmgr_gem->lock);
1151 if (bo_gem->map_count++ == 0)
1152 drm_intel_gem_bo_remove_from_vma_cache(bufmgr_gem, bo_gem);
1154 /* Get a mapping of the buffer if we haven't before. */
1155 if (bo_gem->gtt_virtual == NULL) {
1156 struct drm_i915_gem_mmap_gtt mmap_arg;
1158 DBG("bo_map_gtt: mmap %d (%s)\n", bo_gem->gem_handle,
1160 assert(bo_gem->map_count == 1);
1162 memset(&mmap_arg, 0, sizeof(mmap_arg));
1163 mmap_arg.handle = bo_gem->gem_handle;
1165 /* Get the fake offset back... */
1166 ret = drmIoctl(bufmgr_gem->fd,
1167 DRM_IOCTL_I915_GEM_MMAP_GTT,
1171 DBG("%s:%d: Error preparing buffer map %d (%s): %s .\n",
1173 bo_gem->gem_handle, bo_gem->name,
1175 pthread_mutex_unlock(&bufmgr_gem->lock);
1180 bo_gem->gtt_virtual = mmap(0, bo->size, PROT_READ | PROT_WRITE,
1181 MAP_SHARED, bufmgr_gem->fd,
1183 if (bo_gem->gtt_virtual == MAP_FAILED) {
1184 bo_gem->gtt_virtual = NULL;
1186 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1188 bo_gem->gem_handle, bo_gem->name,
1190 if (--bo_gem->map_count == 0)
1191 drm_intel_gem_bo_add_to_vma_cache(bufmgr_gem, bo_gem);
1192 pthread_mutex_unlock(&bufmgr_gem->lock);
1197 bo->virtual = bo_gem->gtt_virtual;
1199 DBG("bo_map_gtt: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1200 bo_gem->gtt_virtual);
1202 /* Now move it to the GTT domain so that the CPU caches are flushed */
1203 set_domain.handle = bo_gem->gem_handle;
1204 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1205 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
1206 ret = drmIoctl(bufmgr_gem->fd,
1207 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1210 DBG("%s:%d: Error setting domain %d: %s\n",
1211 __FILE__, __LINE__, bo_gem->gem_handle,
1215 pthread_mutex_unlock(&bufmgr_gem->lock);
1220 static int drm_intel_gem_bo_unmap(drm_intel_bo *bo)
1222 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1223 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1224 struct drm_i915_gem_sw_finish sw_finish;
1230 pthread_mutex_lock(&bufmgr_gem->lock);
1232 assert(bo_gem->map_count > 0);
1234 if (bo_gem->mapped_cpu_write) {
1235 /* Cause a flush to happen if the buffer's pinned for
1236 * scanout, so the results show up in a timely manner.
1237 * Unlike GTT set domains, this only does work if the
1238 * buffer should be scanout-related.
1240 sw_finish.handle = bo_gem->gem_handle;
1241 ret = drmIoctl(bufmgr_gem->fd,
1242 DRM_IOCTL_I915_GEM_SW_FINISH,
1244 ret = ret == -1 ? -errno : 0;
1246 bo_gem->mapped_cpu_write = false;
1249 /* We need to unmap after every innovation as we cannot track
1250 * an open vma for every bo as that will exhaasut the system
1251 * limits and cause later failures.
1253 if (--bo_gem->map_count == 0) {
1254 drm_intel_gem_bo_add_to_vma_cache(bufmgr_gem, bo_gem);
1257 pthread_mutex_unlock(&bufmgr_gem->lock);
1262 int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo)
1264 return drm_intel_gem_bo_unmap(bo);
1268 drm_intel_gem_bo_subdata(drm_intel_bo *bo, unsigned long offset,
1269 unsigned long size, const void *data)
1271 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1272 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1273 struct drm_i915_gem_pwrite pwrite;
1276 memset(&pwrite, 0, sizeof(pwrite));
1277 pwrite.handle = bo_gem->gem_handle;
1278 pwrite.offset = offset;
1280 pwrite.data_ptr = (uint64_t) (uintptr_t) data;
1281 ret = drmIoctl(bufmgr_gem->fd,
1282 DRM_IOCTL_I915_GEM_PWRITE,
1286 DBG("%s:%d: Error writing data to buffer %d: (%d %d) %s .\n",
1287 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1288 (int)size, strerror(errno));
1295 drm_intel_gem_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id)
1297 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1298 struct drm_i915_get_pipe_from_crtc_id get_pipe_from_crtc_id;
1301 get_pipe_from_crtc_id.crtc_id = crtc_id;
1302 ret = drmIoctl(bufmgr_gem->fd,
1303 DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID,
1304 &get_pipe_from_crtc_id);
1306 /* We return -1 here to signal that we don't
1307 * know which pipe is associated with this crtc.
1308 * This lets the caller know that this information
1309 * isn't available; using the wrong pipe for
1310 * vblank waiting can cause the chipset to lock up
1315 return get_pipe_from_crtc_id.pipe;
1319 drm_intel_gem_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
1320 unsigned long size, void *data)
1322 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1323 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1324 struct drm_i915_gem_pread pread;
1327 memset(&pread, 0, sizeof(pread));
1328 pread.handle = bo_gem->gem_handle;
1329 pread.offset = offset;
1331 pread.data_ptr = (uint64_t) (uintptr_t) data;
1332 ret = drmIoctl(bufmgr_gem->fd,
1333 DRM_IOCTL_I915_GEM_PREAD,
1337 DBG("%s:%d: Error reading data from buffer %d: (%d %d) %s .\n",
1338 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1339 (int)size, strerror(errno));
1345 /** Waits for all GPU rendering with the object to have completed. */
1347 drm_intel_gem_bo_wait_rendering(drm_intel_bo *bo)
1349 drm_intel_gem_bo_start_gtt_access(bo, 1);
1353 * Sets the object to the GTT read and possibly write domain, used by the X
1354 * 2D driver in the absence of kernel support to do drm_intel_gem_bo_map_gtt().
1356 * In combination with drm_intel_gem_bo_pin() and manual fence management, we
1357 * can do tiled pixmaps this way.
1360 drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable)
1362 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1363 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1364 struct drm_i915_gem_set_domain set_domain;
1367 set_domain.handle = bo_gem->gem_handle;
1368 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1369 set_domain.write_domain = write_enable ? I915_GEM_DOMAIN_GTT : 0;
1370 ret = drmIoctl(bufmgr_gem->fd,
1371 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1374 DBG("%s:%d: Error setting memory domains %d (%08x %08x): %s .\n",
1375 __FILE__, __LINE__, bo_gem->gem_handle,
1376 set_domain.read_domains, set_domain.write_domain,
1382 drm_intel_bufmgr_gem_destroy(drm_intel_bufmgr *bufmgr)
1384 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1387 free(bufmgr_gem->exec2_objects);
1388 free(bufmgr_gem->exec_objects);
1389 free(bufmgr_gem->exec_bos);
1391 pthread_mutex_destroy(&bufmgr_gem->lock);
1393 /* Free any cached buffer objects we were going to reuse */
1394 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
1395 struct drm_intel_gem_bo_bucket *bucket =
1396 &bufmgr_gem->cache_bucket[i];
1397 drm_intel_bo_gem *bo_gem;
1399 while (!DRMLISTEMPTY(&bucket->head)) {
1400 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1401 bucket->head.next, head);
1402 DRMLISTDEL(&bo_gem->head);
1404 drm_intel_gem_bo_free(&bo_gem->bo);
1412 * Adds the target buffer to the validation list and adds the relocation
1413 * to the reloc_buffer's relocation list.
1415 * The relocation entry at the given offset must already contain the
1416 * precomputed relocation value, because the kernel will optimize out
1417 * the relocation entry write when the buffer hasn't moved from the
1418 * last known offset in target_bo.
1421 do_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1422 drm_intel_bo *target_bo, uint32_t target_offset,
1423 uint32_t read_domains, uint32_t write_domain,
1426 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1427 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1428 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
1429 bool fenced_command;
1431 if (bo_gem->has_error)
1434 if (target_bo_gem->has_error) {
1435 bo_gem->has_error = true;
1439 /* We never use HW fences for rendering on 965+ */
1440 if (bufmgr_gem->gen >= 4)
1443 fenced_command = need_fence;
1444 if (target_bo_gem->tiling_mode == I915_TILING_NONE)
1447 /* Create a new relocation list if needed */
1448 if (bo_gem->relocs == NULL && drm_intel_setup_reloc_list(bo))
1451 /* Check overflow */
1452 assert(bo_gem->reloc_count < bufmgr_gem->max_relocs);
1455 assert(offset <= bo->size - 4);
1456 assert((write_domain & (write_domain - 1)) == 0);
1458 /* Make sure that we're not adding a reloc to something whose size has
1459 * already been accounted for.
1461 assert(!bo_gem->used_as_reloc_target);
1462 if (target_bo_gem != bo_gem) {
1463 target_bo_gem->used_as_reloc_target = true;
1464 bo_gem->reloc_tree_size += target_bo_gem->reloc_tree_size;
1466 /* An object needing a fence is a tiled buffer, so it won't have
1467 * relocs to other buffers.
1470 target_bo_gem->reloc_tree_fences = 1;
1471 bo_gem->reloc_tree_fences += target_bo_gem->reloc_tree_fences;
1473 bo_gem->relocs[bo_gem->reloc_count].offset = offset;
1474 bo_gem->relocs[bo_gem->reloc_count].delta = target_offset;
1475 bo_gem->relocs[bo_gem->reloc_count].target_handle =
1476 target_bo_gem->gem_handle;
1477 bo_gem->relocs[bo_gem->reloc_count].read_domains = read_domains;
1478 bo_gem->relocs[bo_gem->reloc_count].write_domain = write_domain;
1479 bo_gem->relocs[bo_gem->reloc_count].presumed_offset = target_bo->offset;
1481 bo_gem->reloc_target_info[bo_gem->reloc_count].bo = target_bo;
1482 if (target_bo != bo)
1483 drm_intel_gem_bo_reference(target_bo);
1485 bo_gem->reloc_target_info[bo_gem->reloc_count].flags =
1486 DRM_INTEL_RELOC_FENCE;
1488 bo_gem->reloc_target_info[bo_gem->reloc_count].flags = 0;
1490 bo_gem->reloc_count++;
1496 drm_intel_gem_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1497 drm_intel_bo *target_bo, uint32_t target_offset,
1498 uint32_t read_domains, uint32_t write_domain)
1500 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1502 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1503 read_domains, write_domain,
1504 !bufmgr_gem->fenced_relocs);
1508 drm_intel_gem_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
1509 drm_intel_bo *target_bo,
1510 uint32_t target_offset,
1511 uint32_t read_domains, uint32_t write_domain)
1513 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1514 read_domains, write_domain, true);
1518 drm_intel_gem_bo_get_reloc_count(drm_intel_bo *bo)
1520 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1522 return bo_gem->reloc_count;
1526 * Removes existing relocation entries in the BO after "start".
1528 * This allows a user to avoid a two-step process for state setup with
1529 * counting up all the buffer objects and doing a
1530 * drm_intel_bufmgr_check_aperture_space() before emitting any of the
1531 * relocations for the state setup. Instead, save the state of the
1532 * batchbuffer including drm_intel_gem_get_reloc_count(), emit all the
1533 * state, and then check if it still fits in the aperture.
1535 * Any further drm_intel_bufmgr_check_aperture_space() queries
1536 * involving this buffer in the tree are undefined after this call.
1539 drm_intel_gem_bo_clear_relocs(drm_intel_bo *bo, int start)
1541 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1543 struct timespec time;
1545 clock_gettime(CLOCK_MONOTONIC, &time);
1547 assert(bo_gem->reloc_count >= start);
1548 /* Unreference the cleared target buffers */
1549 for (i = start; i < bo_gem->reloc_count; i++) {
1550 if (bo_gem->reloc_target_info[i].bo != bo) {
1551 drm_intel_gem_bo_unreference_locked_timed(bo_gem->
1552 reloc_target_info[i].bo,
1556 bo_gem->reloc_count = start;
1560 * Walk the tree of relocations rooted at BO and accumulate the list of
1561 * validations to be performed and update the relocation buffers with
1562 * index values into the validation list.
1565 drm_intel_gem_bo_process_reloc(drm_intel_bo *bo)
1567 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1570 if (bo_gem->relocs == NULL)
1573 for (i = 0; i < bo_gem->reloc_count; i++) {
1574 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1576 if (target_bo == bo)
1579 /* Continue walking the tree depth-first. */
1580 drm_intel_gem_bo_process_reloc(target_bo);
1582 /* Add the target to the validate list */
1583 drm_intel_add_validate_buffer(target_bo);
1588 drm_intel_gem_bo_process_reloc2(drm_intel_bo *bo)
1590 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1593 if (bo_gem->relocs == NULL)
1596 for (i = 0; i < bo_gem->reloc_count; i++) {
1597 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1600 if (target_bo == bo)
1603 /* Continue walking the tree depth-first. */
1604 drm_intel_gem_bo_process_reloc2(target_bo);
1606 need_fence = (bo_gem->reloc_target_info[i].flags &
1607 DRM_INTEL_RELOC_FENCE);
1609 /* Add the target to the validate list */
1610 drm_intel_add_validate_buffer2(target_bo, need_fence);
1616 drm_intel_update_buffer_offsets(drm_intel_bufmgr_gem *bufmgr_gem)
1620 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1621 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1622 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1624 /* Update the buffer offset */
1625 if (bufmgr_gem->exec_objects[i].offset != bo->offset) {
1626 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1627 bo_gem->gem_handle, bo_gem->name, bo->offset,
1628 (unsigned long long)bufmgr_gem->exec_objects[i].
1630 bo->offset = bufmgr_gem->exec_objects[i].offset;
1636 drm_intel_update_buffer_offsets2 (drm_intel_bufmgr_gem *bufmgr_gem)
1640 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1641 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1642 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1644 /* Update the buffer offset */
1645 if (bufmgr_gem->exec2_objects[i].offset != bo->offset) {
1646 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1647 bo_gem->gem_handle, bo_gem->name, bo->offset,
1648 (unsigned long long)bufmgr_gem->exec2_objects[i].offset);
1649 bo->offset = bufmgr_gem->exec2_objects[i].offset;
1655 drm_intel_gem_bo_exec(drm_intel_bo *bo, int used,
1656 drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
1658 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1659 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1660 struct drm_i915_gem_execbuffer execbuf;
1663 if (bo_gem->has_error)
1666 pthread_mutex_lock(&bufmgr_gem->lock);
1667 /* Update indices and set up the validate list. */
1668 drm_intel_gem_bo_process_reloc(bo);
1670 /* Add the batch buffer to the validation list. There are no
1671 * relocations pointing to it.
1673 drm_intel_add_validate_buffer(bo);
1675 execbuf.buffers_ptr = (uintptr_t) bufmgr_gem->exec_objects;
1676 execbuf.buffer_count = bufmgr_gem->exec_count;
1677 execbuf.batch_start_offset = 0;
1678 execbuf.batch_len = used;
1679 execbuf.cliprects_ptr = (uintptr_t) cliprects;
1680 execbuf.num_cliprects = num_cliprects;
1684 ret = drmIoctl(bufmgr_gem->fd,
1685 DRM_IOCTL_I915_GEM_EXECBUFFER,
1689 if (errno == ENOSPC) {
1690 DBG("Execbuffer fails to pin. "
1691 "Estimate: %u. Actual: %u. Available: %u\n",
1692 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
1695 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
1698 (unsigned int)bufmgr_gem->gtt_size);
1701 drm_intel_update_buffer_offsets(bufmgr_gem);
1703 if (bufmgr_gem->bufmgr.debug)
1704 drm_intel_gem_dump_validation_list(bufmgr_gem);
1706 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1707 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1708 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1710 /* Disconnect the buffer from the validate list */
1711 bo_gem->validate_index = -1;
1712 bufmgr_gem->exec_bos[i] = NULL;
1714 bufmgr_gem->exec_count = 0;
1715 pthread_mutex_unlock(&bufmgr_gem->lock);
1721 drm_intel_gem_bo_mrb_exec2(drm_intel_bo *bo, int used,
1722 drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
1725 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1726 struct drm_i915_gem_execbuffer2 execbuf;
1729 switch (flags & 0x7) {
1733 if (!bufmgr_gem->has_blt)
1737 if (!bufmgr_gem->has_bsd)
1740 case I915_EXEC_RENDER:
1741 case I915_EXEC_DEFAULT:
1745 pthread_mutex_lock(&bufmgr_gem->lock);
1746 /* Update indices and set up the validate list. */
1747 drm_intel_gem_bo_process_reloc2(bo);
1749 /* Add the batch buffer to the validation list. There are no relocations
1752 drm_intel_add_validate_buffer2(bo, 0);
1754 execbuf.buffers_ptr = (uintptr_t)bufmgr_gem->exec2_objects;
1755 execbuf.buffer_count = bufmgr_gem->exec_count;
1756 execbuf.batch_start_offset = 0;
1757 execbuf.batch_len = used;
1758 execbuf.cliprects_ptr = (uintptr_t)cliprects;
1759 execbuf.num_cliprects = num_cliprects;
1762 execbuf.flags = flags;
1766 ret = drmIoctl(bufmgr_gem->fd,
1767 DRM_IOCTL_I915_GEM_EXECBUFFER2,
1771 if (ret == -ENOSPC) {
1772 DBG("Execbuffer fails to pin. "
1773 "Estimate: %u. Actual: %u. Available: %u\n",
1774 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
1775 bufmgr_gem->exec_count),
1776 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
1777 bufmgr_gem->exec_count),
1778 (unsigned int) bufmgr_gem->gtt_size);
1781 drm_intel_update_buffer_offsets2(bufmgr_gem);
1783 if (bufmgr_gem->bufmgr.debug)
1784 drm_intel_gem_dump_validation_list(bufmgr_gem);
1786 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1787 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1788 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1790 /* Disconnect the buffer from the validate list */
1791 bo_gem->validate_index = -1;
1792 bufmgr_gem->exec_bos[i] = NULL;
1794 bufmgr_gem->exec_count = 0;
1795 pthread_mutex_unlock(&bufmgr_gem->lock);
1801 drm_intel_gem_bo_exec2(drm_intel_bo *bo, int used,
1802 drm_clip_rect_t *cliprects, int num_cliprects,
1805 return drm_intel_gem_bo_mrb_exec2(bo, used,
1806 cliprects, num_cliprects, DR4,
1811 drm_intel_gem_bo_pin(drm_intel_bo *bo, uint32_t alignment)
1813 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1814 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1815 struct drm_i915_gem_pin pin;
1818 memset(&pin, 0, sizeof(pin));
1819 pin.handle = bo_gem->gem_handle;
1820 pin.alignment = alignment;
1822 ret = drmIoctl(bufmgr_gem->fd,
1823 DRM_IOCTL_I915_GEM_PIN,
1828 bo->offset = pin.offset;
1833 drm_intel_gem_bo_unpin(drm_intel_bo *bo)
1835 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1836 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1837 struct drm_i915_gem_unpin unpin;
1840 memset(&unpin, 0, sizeof(unpin));
1841 unpin.handle = bo_gem->gem_handle;
1843 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_UNPIN, &unpin);
1851 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
1852 uint32_t tiling_mode,
1855 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1856 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1857 struct drm_i915_gem_set_tiling set_tiling;
1860 if (bo_gem->global_name == 0 &&
1861 tiling_mode == bo_gem->tiling_mode &&
1862 stride == bo_gem->stride)
1865 memset(&set_tiling, 0, sizeof(set_tiling));
1867 /* set_tiling is slightly broken and overwrites the
1868 * input on the error path, so we have to open code
1871 set_tiling.handle = bo_gem->gem_handle;
1872 set_tiling.tiling_mode = tiling_mode;
1873 set_tiling.stride = stride;
1875 ret = ioctl(bufmgr_gem->fd,
1876 DRM_IOCTL_I915_GEM_SET_TILING,
1878 } while (ret == -1 && (errno == EINTR || errno == EAGAIN));
1882 bo_gem->tiling_mode = set_tiling.tiling_mode;
1883 bo_gem->swizzle_mode = set_tiling.swizzle_mode;
1884 bo_gem->stride = set_tiling.stride;
1889 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1892 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1893 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1896 /* Linear buffers have no stride. By ensuring that we only ever use
1897 * stride 0 with linear buffers, we simplify our code.
1899 if (*tiling_mode == I915_TILING_NONE)
1902 ret = drm_intel_gem_bo_set_tiling_internal(bo, *tiling_mode, stride);
1904 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
1906 *tiling_mode = bo_gem->tiling_mode;
1911 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1912 uint32_t * swizzle_mode)
1914 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1916 *tiling_mode = bo_gem->tiling_mode;
1917 *swizzle_mode = bo_gem->swizzle_mode;
1922 drm_intel_gem_bo_flink(drm_intel_bo *bo, uint32_t * name)
1924 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1925 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1926 struct drm_gem_flink flink;
1929 if (!bo_gem->global_name) {
1930 memset(&flink, 0, sizeof(flink));
1931 flink.handle = bo_gem->gem_handle;
1933 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_FLINK, &flink);
1936 bo_gem->global_name = flink.name;
1937 bo_gem->reusable = false;
1939 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
1942 *name = bo_gem->global_name;
1947 * Enables unlimited caching of buffer objects for reuse.
1949 * This is potentially very memory expensive, as the cache at each bucket
1950 * size is only bounded by how many buffers of that size we've managed to have
1951 * in flight at once.
1954 drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr)
1956 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1958 bufmgr_gem->bo_reuse = true;
1962 * Enable use of fenced reloc type.
1964 * New code should enable this to avoid unnecessary fence register
1965 * allocation. If this option is not enabled, all relocs will have fence
1966 * register allocated.
1969 drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr)
1971 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
1973 if (bufmgr_gem->bufmgr.bo_exec == drm_intel_gem_bo_exec2)
1974 bufmgr_gem->fenced_relocs = true;
1978 * Return the additional aperture space required by the tree of buffer objects
1982 drm_intel_gem_bo_get_aperture_space(drm_intel_bo *bo)
1984 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1988 if (bo == NULL || bo_gem->included_in_check_aperture)
1992 bo_gem->included_in_check_aperture = true;
1994 for (i = 0; i < bo_gem->reloc_count; i++)
1996 drm_intel_gem_bo_get_aperture_space(bo_gem->
1997 reloc_target_info[i].bo);
2003 * Count the number of buffers in this list that need a fence reg
2005 * If the count is greater than the number of available regs, we'll have
2006 * to ask the caller to resubmit a batch with fewer tiled buffers.
2008 * This function over-counts if the same buffer is used multiple times.
2011 drm_intel_gem_total_fences(drm_intel_bo ** bo_array, int count)
2014 unsigned int total = 0;
2016 for (i = 0; i < count; i++) {
2017 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
2022 total += bo_gem->reloc_tree_fences;
2028 * Clear the flag set by drm_intel_gem_bo_get_aperture_space() so we're ready
2029 * for the next drm_intel_bufmgr_check_aperture_space() call.
2032 drm_intel_gem_bo_clear_aperture_space_flag(drm_intel_bo *bo)
2034 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2037 if (bo == NULL || !bo_gem->included_in_check_aperture)
2040 bo_gem->included_in_check_aperture = false;
2042 for (i = 0; i < bo_gem->reloc_count; i++)
2043 drm_intel_gem_bo_clear_aperture_space_flag(bo_gem->
2044 reloc_target_info[i].bo);
2048 * Return a conservative estimate for the amount of aperture required
2049 * for a collection of buffers. This may double-count some buffers.
2052 drm_intel_gem_estimate_batch_space(drm_intel_bo **bo_array, int count)
2055 unsigned int total = 0;
2057 for (i = 0; i < count; i++) {
2058 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
2060 total += bo_gem->reloc_tree_size;
2066 * Return the amount of aperture needed for a collection of buffers.
2067 * This avoids double counting any buffers, at the cost of looking
2068 * at every buffer in the set.
2071 drm_intel_gem_compute_batch_space(drm_intel_bo **bo_array, int count)
2074 unsigned int total = 0;
2076 for (i = 0; i < count; i++) {
2077 total += drm_intel_gem_bo_get_aperture_space(bo_array[i]);
2078 /* For the first buffer object in the array, we get an
2079 * accurate count back for its reloc_tree size (since nothing
2080 * had been flagged as being counted yet). We can save that
2081 * value out as a more conservative reloc_tree_size that
2082 * avoids double-counting target buffers. Since the first
2083 * buffer happens to usually be the batch buffer in our
2084 * callers, this can pull us back from doing the tree
2085 * walk on every new batch emit.
2088 drm_intel_bo_gem *bo_gem =
2089 (drm_intel_bo_gem *) bo_array[i];
2090 bo_gem->reloc_tree_size = total;
2094 for (i = 0; i < count; i++)
2095 drm_intel_gem_bo_clear_aperture_space_flag(bo_array[i]);
2100 * Return -1 if the batchbuffer should be flushed before attempting to
2101 * emit rendering referencing the buffers pointed to by bo_array.
2103 * This is required because if we try to emit a batchbuffer with relocations
2104 * to a tree of buffers that won't simultaneously fit in the aperture,
2105 * the rendering will return an error at a point where the software is not
2106 * prepared to recover from it.
2108 * However, we also want to emit the batchbuffer significantly before we reach
2109 * the limit, as a series of batchbuffers each of which references buffers
2110 * covering almost all of the aperture means that at each emit we end up
2111 * waiting to evict a buffer from the last rendering, and we get synchronous
2112 * performance. By emitting smaller batchbuffers, we eat some CPU overhead to
2113 * get better parallelism.
2116 drm_intel_gem_check_aperture_space(drm_intel_bo **bo_array, int count)
2118 drm_intel_bufmgr_gem *bufmgr_gem =
2119 (drm_intel_bufmgr_gem *) bo_array[0]->bufmgr;
2120 unsigned int total = 0;
2121 unsigned int threshold = bufmgr_gem->gtt_size * 3 / 4;
2124 /* Check for fence reg constraints if necessary */
2125 if (bufmgr_gem->available_fences) {
2126 total_fences = drm_intel_gem_total_fences(bo_array, count);
2127 if (total_fences > bufmgr_gem->available_fences)
2131 total = drm_intel_gem_estimate_batch_space(bo_array, count);
2133 if (total > threshold)
2134 total = drm_intel_gem_compute_batch_space(bo_array, count);
2136 if (total > threshold) {
2137 DBG("check_space: overflowed available aperture, "
2139 total / 1024, (int)bufmgr_gem->gtt_size / 1024);
2142 DBG("drm_check_space: total %dkb vs bufgr %dkb\n", total / 1024,
2143 (int)bufmgr_gem->gtt_size / 1024);
2149 * Disable buffer reuse for objects which are shared with the kernel
2150 * as scanout buffers
2153 drm_intel_gem_bo_disable_reuse(drm_intel_bo *bo)
2155 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2157 bo_gem->reusable = false;
2162 drm_intel_gem_bo_is_reusable(drm_intel_bo *bo)
2164 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2166 return bo_gem->reusable;
2170 _drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
2172 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2175 for (i = 0; i < bo_gem->reloc_count; i++) {
2176 if (bo_gem->reloc_target_info[i].bo == target_bo)
2178 if (bo == bo_gem->reloc_target_info[i].bo)
2180 if (_drm_intel_gem_bo_references(bo_gem->reloc_target_info[i].bo,
2188 /** Return true if target_bo is referenced by bo's relocation tree. */
2190 drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
2192 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
2194 if (bo == NULL || target_bo == NULL)
2196 if (target_bo_gem->used_as_reloc_target)
2197 return _drm_intel_gem_bo_references(bo, target_bo);
2202 add_bucket(drm_intel_bufmgr_gem *bufmgr_gem, int size)
2204 unsigned int i = bufmgr_gem->num_buckets;
2206 assert(i < ARRAY_SIZE(bufmgr_gem->cache_bucket));
2208 DRMINITLISTHEAD(&bufmgr_gem->cache_bucket[i].head);
2209 bufmgr_gem->cache_bucket[i].size = size;
2210 bufmgr_gem->num_buckets++;
2214 init_cache_buckets(drm_intel_bufmgr_gem *bufmgr_gem)
2216 unsigned long size, cache_max_size = 64 * 1024 * 1024;
2218 /* OK, so power of two buckets was too wasteful of memory.
2219 * Give 3 other sizes between each power of two, to hopefully
2220 * cover things accurately enough. (The alternative is
2221 * probably to just go for exact matching of sizes, and assume
2222 * that for things like composited window resize the tiled
2223 * width/height alignment and rounding of sizes to pages will
2224 * get us useful cache hit rates anyway)
2226 add_bucket(bufmgr_gem, 4096);
2227 add_bucket(bufmgr_gem, 4096 * 2);
2228 add_bucket(bufmgr_gem, 4096 * 3);
2230 /* Initialize the linked lists for BO reuse cache. */
2231 for (size = 4 * 4096; size <= cache_max_size; size *= 2) {
2232 add_bucket(bufmgr_gem, size);
2234 add_bucket(bufmgr_gem, size + size * 1 / 4);
2235 add_bucket(bufmgr_gem, size + size * 2 / 4);
2236 add_bucket(bufmgr_gem, size + size * 3 / 4);
2241 drm_intel_bufmgr_gem_set_vma_cache_size(drm_intel_bufmgr *bufmgr, int limit)
2243 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
2245 bufmgr_gem->vma_max = limit;
2247 drm_intel_gem_bo_purge_vma_cache(bufmgr_gem);
2251 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
2252 * and manage map buffer objections.
2254 * \param fd File descriptor of the opened DRM device.
2257 drm_intel_bufmgr_gem_init(int fd, int batch_size)
2259 drm_intel_bufmgr_gem *bufmgr_gem;
2260 struct drm_i915_gem_get_aperture aperture;
2261 drm_i915_getparam_t gp;
2265 bufmgr_gem = calloc(1, sizeof(*bufmgr_gem));
2266 if (bufmgr_gem == NULL)
2269 bufmgr_gem->fd = fd;
2271 if (pthread_mutex_init(&bufmgr_gem->lock, NULL) != 0) {
2276 ret = drmIoctl(bufmgr_gem->fd,
2277 DRM_IOCTL_I915_GEM_GET_APERTURE,
2281 bufmgr_gem->gtt_size = aperture.aper_available_size;
2283 fprintf(stderr, "DRM_IOCTL_I915_GEM_APERTURE failed: %s\n",
2285 bufmgr_gem->gtt_size = 128 * 1024 * 1024;
2286 fprintf(stderr, "Assuming %dkB available aperture size.\n"
2287 "May lead to reduced performance or incorrect "
2289 (int)bufmgr_gem->gtt_size / 1024);
2292 gp.param = I915_PARAM_CHIPSET_ID;
2293 gp.value = &bufmgr_gem->pci_device;
2294 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2296 fprintf(stderr, "get chip id failed: %d [%d]\n", ret, errno);
2297 fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value);
2300 if (IS_GEN2(bufmgr_gem))
2301 bufmgr_gem->gen = 2;
2302 else if (IS_GEN3(bufmgr_gem))
2303 bufmgr_gem->gen = 3;
2304 else if (IS_GEN4(bufmgr_gem))
2305 bufmgr_gem->gen = 4;
2307 bufmgr_gem->gen = 6;
2309 if (IS_GEN3(bufmgr_gem) && bufmgr_gem->gtt_size > 256*1024*1024) {
2310 /* The unmappable part of gtt on gen 3 (i.e. above 256MB) can't
2311 * be used for tiled blits. To simplify the accounting, just
2312 * substract the unmappable part (fixed to 256MB on all known
2313 * gen3 devices) if the kernel advertises it. */
2314 bufmgr_gem->gtt_size -= 256*1024*1024;
2319 gp.param = I915_PARAM_HAS_EXECBUF2;
2320 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2324 gp.param = I915_PARAM_HAS_BSD;
2325 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2326 bufmgr_gem->has_bsd = ret == 0;
2328 gp.param = I915_PARAM_HAS_BLT;
2329 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2330 bufmgr_gem->has_blt = ret == 0;
2332 gp.param = I915_PARAM_HAS_RELAXED_FENCING;
2333 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2334 bufmgr_gem->has_relaxed_fencing = ret == 0;
2336 if (bufmgr_gem->gen < 4) {
2337 gp.param = I915_PARAM_NUM_FENCES_AVAIL;
2338 gp.value = &bufmgr_gem->available_fences;
2339 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2341 fprintf(stderr, "get fences failed: %d [%d]\n", ret,
2343 fprintf(stderr, "param: %d, val: %d\n", gp.param,
2345 bufmgr_gem->available_fences = 0;
2347 /* XXX The kernel reports the total number of fences,
2348 * including any that may be pinned.
2350 * We presume that there will be at least one pinned
2351 * fence for the scanout buffer, but there may be more
2352 * than one scanout and the user may be manually
2353 * pinning buffers. Let's move to execbuffer2 and
2354 * thereby forget the insanity of using fences...
2356 bufmgr_gem->available_fences -= 2;
2357 if (bufmgr_gem->available_fences < 0)
2358 bufmgr_gem->available_fences = 0;
2362 /* Let's go with one relocation per every 2 dwords (but round down a bit
2363 * since a power of two will mean an extra page allocation for the reloc
2366 * Every 4 was too few for the blender benchmark.
2368 bufmgr_gem->max_relocs = batch_size / sizeof(uint32_t) / 2 - 2;
2370 bufmgr_gem->bufmgr.bo_alloc = drm_intel_gem_bo_alloc;
2371 bufmgr_gem->bufmgr.bo_alloc_for_render =
2372 drm_intel_gem_bo_alloc_for_render;
2373 bufmgr_gem->bufmgr.bo_alloc_tiled = drm_intel_gem_bo_alloc_tiled;
2374 bufmgr_gem->bufmgr.bo_reference = drm_intel_gem_bo_reference;
2375 bufmgr_gem->bufmgr.bo_unreference = drm_intel_gem_bo_unreference;
2376 bufmgr_gem->bufmgr.bo_map = drm_intel_gem_bo_map;
2377 bufmgr_gem->bufmgr.bo_unmap = drm_intel_gem_bo_unmap;
2378 bufmgr_gem->bufmgr.bo_subdata = drm_intel_gem_bo_subdata;
2379 bufmgr_gem->bufmgr.bo_get_subdata = drm_intel_gem_bo_get_subdata;
2380 bufmgr_gem->bufmgr.bo_wait_rendering = drm_intel_gem_bo_wait_rendering;
2381 bufmgr_gem->bufmgr.bo_emit_reloc = drm_intel_gem_bo_emit_reloc;
2382 bufmgr_gem->bufmgr.bo_emit_reloc_fence = drm_intel_gem_bo_emit_reloc_fence;
2383 bufmgr_gem->bufmgr.bo_pin = drm_intel_gem_bo_pin;
2384 bufmgr_gem->bufmgr.bo_unpin = drm_intel_gem_bo_unpin;
2385 bufmgr_gem->bufmgr.bo_get_tiling = drm_intel_gem_bo_get_tiling;
2386 bufmgr_gem->bufmgr.bo_set_tiling = drm_intel_gem_bo_set_tiling;
2387 bufmgr_gem->bufmgr.bo_flink = drm_intel_gem_bo_flink;
2388 /* Use the new one if available */
2390 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec2;
2391 bufmgr_gem->bufmgr.bo_mrb_exec = drm_intel_gem_bo_mrb_exec2;
2393 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec;
2394 bufmgr_gem->bufmgr.bo_busy = drm_intel_gem_bo_busy;
2395 bufmgr_gem->bufmgr.bo_madvise = drm_intel_gem_bo_madvise;
2396 bufmgr_gem->bufmgr.destroy = drm_intel_bufmgr_gem_destroy;
2397 bufmgr_gem->bufmgr.debug = 0;
2398 bufmgr_gem->bufmgr.check_aperture_space =
2399 drm_intel_gem_check_aperture_space;
2400 bufmgr_gem->bufmgr.bo_disable_reuse = drm_intel_gem_bo_disable_reuse;
2401 bufmgr_gem->bufmgr.bo_is_reusable = drm_intel_gem_bo_is_reusable;
2402 bufmgr_gem->bufmgr.get_pipe_from_crtc_id =
2403 drm_intel_gem_get_pipe_from_crtc_id;
2404 bufmgr_gem->bufmgr.bo_references = drm_intel_gem_bo_references;
2406 DRMINITLISTHEAD(&bufmgr_gem->named);
2407 init_cache_buckets(bufmgr_gem);
2409 DRMINITLISTHEAD(&bufmgr_gem->vma_cache);
2410 bufmgr_gem->vma_max = -1; /* unlimited by default */
2412 return &bufmgr_gem->bufmgr;