1 /**************************************************************************
3 * Copyright © 2007 Red Hat Inc.
4 * Copyright © 2007 Intel Corporation
5 * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
29 **************************************************************************/
31 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
32 * Keith Whitwell <keithw-at-tungstengraphics-dot-com>
33 * Eric Anholt <eric@anholt.net>
34 * Dave Airlie <airlied@linux.ie>
42 #include <xf86atomic.h>
50 #include <sys/ioctl.h>
53 #include <sys/types.h>
56 #include "libdrm_lists.h"
57 #include "intel_bufmgr.h"
58 #include "intel_bufmgr_priv.h"
59 #include "intel_chipset.h"
64 #define DBG(...) do { \
65 if (bufmgr_gem->bufmgr.debug) \
66 fprintf(stderr, __VA_ARGS__); \
69 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
71 typedef struct _drm_intel_bo_gem drm_intel_bo_gem;
73 struct drm_intel_gem_bo_bucket {
78 typedef struct _drm_intel_bufmgr_gem {
79 drm_intel_bufmgr bufmgr;
87 struct drm_i915_gem_exec_object *exec_objects;
88 struct drm_i915_gem_exec_object2 *exec2_objects;
89 drm_intel_bo **exec_bos;
93 /** Array of lists of cached gem objects of power-of-two sizes */
94 struct drm_intel_gem_bo_bucket cache_bucket[14 * 4];
103 } drm_intel_bufmgr_gem;
105 #define DRM_INTEL_RELOC_FENCE (1<<0)
107 typedef struct _drm_intel_reloc_target_info {
110 } drm_intel_reloc_target;
112 struct _drm_intel_bo_gem {
120 * Kenel-assigned global name for this object
122 unsigned int global_name;
125 * Index of the buffer within the validation list while preparing a
126 * batchbuffer execution.
131 * Current tiling mode
133 uint32_t tiling_mode;
134 uint32_t swizzle_mode;
135 unsigned long stride;
139 /** Array passed to the DRM containing relocation information. */
140 struct drm_i915_gem_relocation_entry *relocs;
142 * Array of info structs corresponding to relocs[i].target_handle etc
144 drm_intel_reloc_target *reloc_target_info;
145 /** Number of entries in relocs */
147 /** Mapped address for the buffer, saved across map/unmap cycles */
149 /** GTT virtual address for the buffer, saved across map/unmap cycles */
156 * Boolean of whether this BO and its children have been included in
157 * the current drm_intel_bufmgr_check_aperture_space() total.
159 char included_in_check_aperture;
162 * Boolean of whether this buffer has been used as a relocation
163 * target and had its size accounted for, and thus can't have any
164 * further relocations added to it.
166 char used_as_reloc_target;
169 * Boolean of whether we have encountered an error whilst building the relocation tree.
174 * Boolean of whether this buffer can be re-used
179 * Size in bytes of this buffer and its relocation descendents.
181 * Used to avoid costly tree walking in
182 * drm_intel_bufmgr_check_aperture in the common case.
187 * Number of potential fence registers required by this buffer and its
190 int reloc_tree_fences;
194 drm_intel_gem_estimate_batch_space(drm_intel_bo ** bo_array, int count);
197 drm_intel_gem_compute_batch_space(drm_intel_bo ** bo_array, int count);
200 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
201 uint32_t * swizzle_mode);
204 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
205 uint32_t tiling_mode,
208 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
211 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo);
213 static void drm_intel_gem_bo_free(drm_intel_bo *bo);
216 drm_intel_gem_bo_tile_size(drm_intel_bufmgr_gem *bufmgr_gem, unsigned long size,
217 uint32_t *tiling_mode)
219 unsigned long min_size, max_size;
222 if (*tiling_mode == I915_TILING_NONE)
225 /* 965+ just need multiples of page size for tiling */
226 if (bufmgr_gem->gen >= 4)
227 return ROUND_UP_TO(size, 4096);
229 /* Older chips need powers of two, of at least 512k or 1M */
230 if (bufmgr_gem->gen == 3) {
231 min_size = 1024*1024;
232 max_size = 128*1024*1024;
235 max_size = 64*1024*1024;
238 if (size > max_size) {
239 *tiling_mode = I915_TILING_NONE;
243 for (i = min_size; i < size; i <<= 1)
250 * Round a given pitch up to the minimum required for X tiling on a
251 * given chip. We use 512 as the minimum to allow for a later tiling
255 drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem,
256 unsigned long pitch, uint32_t tiling_mode)
258 unsigned long tile_width;
261 /* If untiled, then just align it so that we can do rendering
262 * to it with the 3D engine.
264 if (tiling_mode == I915_TILING_NONE)
265 return ALIGN(pitch, 64);
267 if (tiling_mode == I915_TILING_X)
272 /* 965 is flexible */
273 if (bufmgr_gem->gen >= 4)
274 return ROUND_UP_TO(pitch, tile_width);
276 /* Pre-965 needs power of two tile width */
277 for (i = tile_width; i < pitch; i <<= 1)
283 static struct drm_intel_gem_bo_bucket *
284 drm_intel_gem_bo_bucket_for_size(drm_intel_bufmgr_gem *bufmgr_gem,
289 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
290 struct drm_intel_gem_bo_bucket *bucket =
291 &bufmgr_gem->cache_bucket[i];
292 if (bucket->size >= size) {
301 drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem *bufmgr_gem)
305 for (i = 0; i < bufmgr_gem->exec_count; i++) {
306 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
307 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
309 if (bo_gem->relocs == NULL) {
310 DBG("%2d: %d (%s)\n", i, bo_gem->gem_handle,
315 for (j = 0; j < bo_gem->reloc_count; j++) {
316 drm_intel_bo *target_bo = bo_gem->reloc_target_info[j].bo;
317 drm_intel_bo_gem *target_gem =
318 (drm_intel_bo_gem *) target_bo;
320 DBG("%2d: %d (%s)@0x%08llx -> "
321 "%d (%s)@0x%08lx + 0x%08x\n",
323 bo_gem->gem_handle, bo_gem->name,
324 (unsigned long long)bo_gem->relocs[j].offset,
325 target_gem->gem_handle,
328 bo_gem->relocs[j].delta);
334 drm_intel_gem_bo_reference(drm_intel_bo *bo)
336 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
338 assert(atomic_read(&bo_gem->refcount) > 0);
339 atomic_inc(&bo_gem->refcount);
343 * Adds the given buffer to the list of buffers to be validated (moved into the
344 * appropriate memory type) with the next batch submission.
346 * If a buffer is validated multiple times in a batch submission, it ends up
347 * with the intersection of the memory type flags and the union of the
351 drm_intel_add_validate_buffer(drm_intel_bo *bo)
353 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
354 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
357 if (bo_gem->validate_index != -1)
360 /* Extend the array of validation entries as necessary. */
361 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
362 int new_size = bufmgr_gem->exec_size * 2;
367 bufmgr_gem->exec_objects =
368 realloc(bufmgr_gem->exec_objects,
369 sizeof(*bufmgr_gem->exec_objects) * new_size);
370 bufmgr_gem->exec_bos =
371 realloc(bufmgr_gem->exec_bos,
372 sizeof(*bufmgr_gem->exec_bos) * new_size);
373 bufmgr_gem->exec_size = new_size;
376 index = bufmgr_gem->exec_count;
377 bo_gem->validate_index = index;
378 /* Fill in array entry */
379 bufmgr_gem->exec_objects[index].handle = bo_gem->gem_handle;
380 bufmgr_gem->exec_objects[index].relocation_count = bo_gem->reloc_count;
381 bufmgr_gem->exec_objects[index].relocs_ptr = (uintptr_t) bo_gem->relocs;
382 bufmgr_gem->exec_objects[index].alignment = 0;
383 bufmgr_gem->exec_objects[index].offset = 0;
384 bufmgr_gem->exec_bos[index] = bo;
385 bufmgr_gem->exec_count++;
389 drm_intel_add_validate_buffer2(drm_intel_bo *bo, int need_fence)
391 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
392 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
395 if (bo_gem->validate_index != -1) {
397 bufmgr_gem->exec2_objects[bo_gem->validate_index].flags |=
398 EXEC_OBJECT_NEEDS_FENCE;
402 /* Extend the array of validation entries as necessary. */
403 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
404 int new_size = bufmgr_gem->exec_size * 2;
409 bufmgr_gem->exec2_objects =
410 realloc(bufmgr_gem->exec2_objects,
411 sizeof(*bufmgr_gem->exec2_objects) * new_size);
412 bufmgr_gem->exec_bos =
413 realloc(bufmgr_gem->exec_bos,
414 sizeof(*bufmgr_gem->exec_bos) * new_size);
415 bufmgr_gem->exec_size = new_size;
418 index = bufmgr_gem->exec_count;
419 bo_gem->validate_index = index;
420 /* Fill in array entry */
421 bufmgr_gem->exec2_objects[index].handle = bo_gem->gem_handle;
422 bufmgr_gem->exec2_objects[index].relocation_count = bo_gem->reloc_count;
423 bufmgr_gem->exec2_objects[index].relocs_ptr = (uintptr_t)bo_gem->relocs;
424 bufmgr_gem->exec2_objects[index].alignment = 0;
425 bufmgr_gem->exec2_objects[index].offset = 0;
426 bufmgr_gem->exec_bos[index] = bo;
427 bufmgr_gem->exec2_objects[index].flags = 0;
428 bufmgr_gem->exec2_objects[index].rsvd1 = 0;
429 bufmgr_gem->exec2_objects[index].rsvd2 = 0;
431 bufmgr_gem->exec2_objects[index].flags |=
432 EXEC_OBJECT_NEEDS_FENCE;
434 bufmgr_gem->exec_count++;
437 #define RELOC_BUF_SIZE(x) ((I915_RELOC_HEADER + x * I915_RELOC0_STRIDE) * \
441 drm_intel_bo_gem_set_in_aperture_size(drm_intel_bufmgr_gem *bufmgr_gem,
442 drm_intel_bo_gem *bo_gem)
446 assert(!bo_gem->used_as_reloc_target);
448 /* The older chipsets are far-less flexible in terms of tiling,
449 * and require tiled buffer to be size aligned in the aperture.
450 * This means that in the worst possible case we will need a hole
451 * twice as large as the object in order for it to fit into the
452 * aperture. Optimal packing is for wimps.
454 size = bo_gem->bo.size;
455 if (bufmgr_gem->gen < 4 && bo_gem->tiling_mode != I915_TILING_NONE)
458 bo_gem->reloc_tree_size = size;
462 drm_intel_setup_reloc_list(drm_intel_bo *bo)
464 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
465 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
466 unsigned int max_relocs = bufmgr_gem->max_relocs;
468 if (bo->size / 4 < max_relocs)
469 max_relocs = bo->size / 4;
471 bo_gem->relocs = malloc(max_relocs *
472 sizeof(struct drm_i915_gem_relocation_entry));
473 bo_gem->reloc_target_info = malloc(max_relocs *
474 sizeof(drm_intel_reloc_target));
475 if (bo_gem->relocs == NULL || bo_gem->reloc_target_info == NULL) {
476 bo_gem->has_error = 1;
478 free (bo_gem->relocs);
479 bo_gem->relocs = NULL;
481 free (bo_gem->reloc_target_info);
482 bo_gem->reloc_target_info = NULL;
491 drm_intel_gem_bo_busy(drm_intel_bo *bo)
493 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
494 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
495 struct drm_i915_gem_busy busy;
498 memset(&busy, 0, sizeof(busy));
499 busy.handle = bo_gem->gem_handle;
502 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_BUSY, &busy);
503 } while (ret == -1 && errno == EINTR);
505 return (ret == 0 && busy.busy);
509 drm_intel_gem_bo_madvise_internal(drm_intel_bufmgr_gem *bufmgr_gem,
510 drm_intel_bo_gem *bo_gem, int state)
512 struct drm_i915_gem_madvise madv;
514 madv.handle = bo_gem->gem_handle;
517 ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MADVISE, &madv);
519 return madv.retained;
523 drm_intel_gem_bo_madvise(drm_intel_bo *bo, int madv)
525 return drm_intel_gem_bo_madvise_internal
526 ((drm_intel_bufmgr_gem *) bo->bufmgr,
527 (drm_intel_bo_gem *) bo,
531 /* drop the oldest entries that have been purged by the kernel */
533 drm_intel_gem_bo_cache_purge_bucket(drm_intel_bufmgr_gem *bufmgr_gem,
534 struct drm_intel_gem_bo_bucket *bucket)
536 while (!DRMLISTEMPTY(&bucket->head)) {
537 drm_intel_bo_gem *bo_gem;
539 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
540 bucket->head.next, head);
541 if (drm_intel_gem_bo_madvise_internal
542 (bufmgr_gem, bo_gem, I915_MADV_DONTNEED))
545 DRMLISTDEL(&bo_gem->head);
546 drm_intel_gem_bo_free(&bo_gem->bo);
550 static drm_intel_bo *
551 drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr,
555 uint32_t tiling_mode,
556 unsigned long stride)
558 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
559 drm_intel_bo_gem *bo_gem;
560 unsigned int page_size = getpagesize();
562 struct drm_intel_gem_bo_bucket *bucket;
563 int alloc_from_cache;
564 unsigned long bo_size;
567 if (flags & BO_ALLOC_FOR_RENDER)
570 /* Round the allocated size up to a power of two number of pages. */
571 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, size);
573 /* If we don't have caching at this size, don't actually round the
576 if (bucket == NULL) {
578 if (bo_size < page_size)
581 bo_size = bucket->size;
584 pthread_mutex_lock(&bufmgr_gem->lock);
585 /* Get a buffer out of the cache if available */
587 alloc_from_cache = 0;
588 if (bucket != NULL && !DRMLISTEMPTY(&bucket->head)) {
590 /* Allocate new render-target BOs from the tail (MRU)
591 * of the list, as it will likely be hot in the GPU
592 * cache and in the aperture for us.
594 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
595 bucket->head.prev, head);
596 DRMLISTDEL(&bo_gem->head);
597 alloc_from_cache = 1;
599 /* For non-render-target BOs (where we're probably
600 * going to map it first thing in order to fill it
601 * with data), check if the last BO in the cache is
602 * unbusy, and only reuse in that case. Otherwise,
603 * allocating a new buffer is probably faster than
604 * waiting for the GPU to finish.
606 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
607 bucket->head.next, head);
608 if (!drm_intel_gem_bo_busy(&bo_gem->bo)) {
609 alloc_from_cache = 1;
610 DRMLISTDEL(&bo_gem->head);
614 if (alloc_from_cache) {
615 if (!drm_intel_gem_bo_madvise_internal
616 (bufmgr_gem, bo_gem, I915_MADV_WILLNEED)) {
617 drm_intel_gem_bo_free(&bo_gem->bo);
618 drm_intel_gem_bo_cache_purge_bucket(bufmgr_gem,
623 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
626 drm_intel_gem_bo_free(&bo_gem->bo);
631 pthread_mutex_unlock(&bufmgr_gem->lock);
633 if (!alloc_from_cache) {
634 struct drm_i915_gem_create create;
636 bo_gem = calloc(1, sizeof(*bo_gem));
640 bo_gem->bo.size = bo_size;
641 memset(&create, 0, sizeof(create));
642 create.size = bo_size;
645 ret = ioctl(bufmgr_gem->fd,
646 DRM_IOCTL_I915_GEM_CREATE,
648 } while (ret == -1 && errno == EINTR);
649 bo_gem->gem_handle = create.handle;
650 bo_gem->bo.handle = bo_gem->gem_handle;
655 bo_gem->bo.bufmgr = bufmgr;
657 bo_gem->tiling_mode = I915_TILING_NONE;
658 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
661 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
664 drm_intel_gem_bo_free(&bo_gem->bo);
670 atomic_set(&bo_gem->refcount, 1);
671 bo_gem->validate_index = -1;
672 bo_gem->reloc_tree_fences = 0;
673 bo_gem->used_as_reloc_target = 0;
674 bo_gem->has_error = 0;
675 bo_gem->reusable = 1;
677 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
679 DBG("bo_create: buf %d (%s) %ldb\n",
680 bo_gem->gem_handle, bo_gem->name, size);
685 static drm_intel_bo *
686 drm_intel_gem_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
689 unsigned int alignment)
691 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size,
693 I915_TILING_NONE, 0);
696 static drm_intel_bo *
697 drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr,
700 unsigned int alignment)
702 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, 0,
703 I915_TILING_NONE, 0);
706 static drm_intel_bo *
707 drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
708 int x, int y, int cpp, uint32_t *tiling_mode,
709 unsigned long *pitch, unsigned long flags)
711 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
713 unsigned long size, stride;
717 unsigned long aligned_y;
719 tiling = *tiling_mode;
721 /* If we're tiled, our allocations are in 8 or 32-row blocks,
722 * so failure to align our height means that we won't allocate
725 * If we're untiled, we still have to align to 2 rows high
726 * because the data port accesses 2x2 blocks even if the
727 * bottom row isn't to be rendered, so failure to align means
728 * we could walk off the end of the GTT and fault. This is
729 * documented on 965, and may be the case on older chipsets
730 * too so we try to be careful.
733 if (tiling == I915_TILING_NONE)
734 aligned_y = ALIGN(y, 2);
735 else if (tiling == I915_TILING_X)
736 aligned_y = ALIGN(y, 8);
737 else if (tiling == I915_TILING_Y)
738 aligned_y = ALIGN(y, 32);
741 stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, tiling);
742 size = stride * aligned_y;
743 size = drm_intel_gem_bo_tile_size(bufmgr_gem, size, tiling_mode);
744 } while (*tiling_mode != tiling);
746 bo = drm_intel_gem_bo_alloc_internal(bufmgr, name, size, flags,
747 *tiling_mode, stride);
756 * Returns a drm_intel_bo wrapping the given buffer object handle.
758 * This can be used when one application needs to pass a buffer object
762 drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
766 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
767 drm_intel_bo_gem *bo_gem;
769 struct drm_gem_open open_arg;
770 struct drm_i915_gem_get_tiling get_tiling;
772 bo_gem = calloc(1, sizeof(*bo_gem));
776 memset(&open_arg, 0, sizeof(open_arg));
777 open_arg.name = handle;
779 ret = ioctl(bufmgr_gem->fd,
782 } while (ret == -1 && errno == EINTR);
784 fprintf(stderr, "Couldn't reference %s handle 0x%08x: %s\n",
785 name, handle, strerror(errno));
789 bo_gem->bo.size = open_arg.size;
790 bo_gem->bo.offset = 0;
791 bo_gem->bo.virtual = NULL;
792 bo_gem->bo.bufmgr = bufmgr;
794 atomic_set(&bo_gem->refcount, 1);
795 bo_gem->validate_index = -1;
796 bo_gem->gem_handle = open_arg.handle;
797 bo_gem->global_name = handle;
798 bo_gem->reusable = 0;
800 memset(&get_tiling, 0, sizeof(get_tiling));
801 get_tiling.handle = bo_gem->gem_handle;
802 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_GET_TILING, &get_tiling);
804 drm_intel_gem_bo_unreference(&bo_gem->bo);
807 bo_gem->tiling_mode = get_tiling.tiling_mode;
808 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
809 /* XXX stride is unknown */
810 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
812 DBG("bo_create_from_handle: %d (%s)\n", handle, bo_gem->name);
818 drm_intel_gem_bo_free(drm_intel_bo *bo)
820 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
821 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
822 struct drm_gem_close close;
825 if (bo_gem->mem_virtual)
826 munmap(bo_gem->mem_virtual, bo_gem->bo.size);
827 if (bo_gem->gtt_virtual)
828 munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
830 /* Close this object */
831 memset(&close, 0, sizeof(close));
832 close.handle = bo_gem->gem_handle;
833 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close);
836 "DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
837 bo_gem->gem_handle, bo_gem->name, strerror(errno));
842 /** Frees all cached buffers significantly older than @time. */
844 drm_intel_gem_cleanup_bo_cache(drm_intel_bufmgr_gem *bufmgr_gem, time_t time)
848 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
849 struct drm_intel_gem_bo_bucket *bucket =
850 &bufmgr_gem->cache_bucket[i];
852 while (!DRMLISTEMPTY(&bucket->head)) {
853 drm_intel_bo_gem *bo_gem;
855 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
856 bucket->head.next, head);
857 if (time - bo_gem->free_time <= 1)
860 DRMLISTDEL(&bo_gem->head);
862 drm_intel_gem_bo_free(&bo_gem->bo);
868 drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time)
870 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
871 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
872 struct drm_intel_gem_bo_bucket *bucket;
875 /* Unreference all the target buffers */
876 for (i = 0; i < bo_gem->reloc_count; i++) {
877 if (bo_gem->reloc_target_info[i].bo != bo) {
878 drm_intel_gem_bo_unreference_locked_timed(bo_gem->
879 reloc_target_info[i].bo,
883 bo_gem->reloc_count = 0;
884 bo_gem->used_as_reloc_target = 0;
886 DBG("bo_unreference final: %d (%s)\n",
887 bo_gem->gem_handle, bo_gem->name);
889 /* release memory associated with this object */
890 if (bo_gem->reloc_target_info) {
891 free(bo_gem->reloc_target_info);
892 bo_gem->reloc_target_info = NULL;
894 if (bo_gem->relocs) {
895 free(bo_gem->relocs);
896 bo_gem->relocs = NULL;
899 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, bo->size);
900 /* Put the buffer into our internal cache for reuse if we can. */
901 if (bufmgr_gem->bo_reuse && bo_gem->reusable && bucket != NULL &&
902 drm_intel_gem_bo_madvise_internal(bufmgr_gem, bo_gem,
903 I915_MADV_DONTNEED)) {
904 bo_gem->free_time = time;
907 bo_gem->validate_index = -1;
909 DRMLISTADDTAIL(&bo_gem->head, &bucket->head);
911 drm_intel_gem_cleanup_bo_cache(bufmgr_gem, time);
913 drm_intel_gem_bo_free(bo);
917 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
920 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
922 assert(atomic_read(&bo_gem->refcount) > 0);
923 if (atomic_dec_and_test(&bo_gem->refcount))
924 drm_intel_gem_bo_unreference_final(bo, time);
927 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo)
929 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
931 assert(atomic_read(&bo_gem->refcount) > 0);
932 if (atomic_dec_and_test(&bo_gem->refcount)) {
933 drm_intel_bufmgr_gem *bufmgr_gem =
934 (drm_intel_bufmgr_gem *) bo->bufmgr;
935 struct timespec time;
937 clock_gettime(CLOCK_MONOTONIC, &time);
939 pthread_mutex_lock(&bufmgr_gem->lock);
940 drm_intel_gem_bo_unreference_final(bo, time.tv_sec);
941 pthread_mutex_unlock(&bufmgr_gem->lock);
945 static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable)
947 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
948 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
949 struct drm_i915_gem_set_domain set_domain;
952 pthread_mutex_lock(&bufmgr_gem->lock);
954 /* Allow recursive mapping. Mesa may recursively map buffers with
955 * nested display loops.
957 if (!bo_gem->mem_virtual) {
958 struct drm_i915_gem_mmap mmap_arg;
960 DBG("bo_map: %d (%s)\n", bo_gem->gem_handle, bo_gem->name);
962 memset(&mmap_arg, 0, sizeof(mmap_arg));
963 mmap_arg.handle = bo_gem->gem_handle;
965 mmap_arg.size = bo->size;
967 ret = ioctl(bufmgr_gem->fd,
968 DRM_IOCTL_I915_GEM_MMAP,
970 } while (ret == -1 && errno == EINTR);
974 "%s:%d: Error mapping buffer %d (%s): %s .\n",
975 __FILE__, __LINE__, bo_gem->gem_handle,
976 bo_gem->name, strerror(errno));
977 pthread_mutex_unlock(&bufmgr_gem->lock);
980 bo_gem->mem_virtual = (void *)(uintptr_t) mmap_arg.addr_ptr;
982 DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
983 bo_gem->mem_virtual);
984 bo->virtual = bo_gem->mem_virtual;
986 set_domain.handle = bo_gem->gem_handle;
987 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
989 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
991 set_domain.write_domain = 0;
993 ret = ioctl(bufmgr_gem->fd,
994 DRM_IOCTL_I915_GEM_SET_DOMAIN,
996 } while (ret == -1 && errno == EINTR);
999 fprintf(stderr, "%s:%d: Error setting to CPU domain %d: %s\n",
1000 __FILE__, __LINE__, bo_gem->gem_handle,
1002 pthread_mutex_unlock(&bufmgr_gem->lock);
1006 pthread_mutex_unlock(&bufmgr_gem->lock);
1011 int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
1013 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1014 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1015 struct drm_i915_gem_set_domain set_domain;
1018 pthread_mutex_lock(&bufmgr_gem->lock);
1020 /* Get a mapping of the buffer if we haven't before. */
1021 if (bo_gem->gtt_virtual == NULL) {
1022 struct drm_i915_gem_mmap_gtt mmap_arg;
1024 DBG("bo_map_gtt: mmap %d (%s)\n", bo_gem->gem_handle,
1027 memset(&mmap_arg, 0, sizeof(mmap_arg));
1028 mmap_arg.handle = bo_gem->gem_handle;
1030 /* Get the fake offset back... */
1032 ret = ioctl(bufmgr_gem->fd,
1033 DRM_IOCTL_I915_GEM_MMAP_GTT,
1035 } while (ret == -1 && errno == EINTR);
1039 "%s:%d: Error preparing buffer map %d (%s): %s .\n",
1041 bo_gem->gem_handle, bo_gem->name,
1043 pthread_mutex_unlock(&bufmgr_gem->lock);
1048 bo_gem->gtt_virtual = mmap(0, bo->size, PROT_READ | PROT_WRITE,
1049 MAP_SHARED, bufmgr_gem->fd,
1051 if (bo_gem->gtt_virtual == MAP_FAILED) {
1052 bo_gem->gtt_virtual = NULL;
1055 "%s:%d: Error mapping buffer %d (%s): %s .\n",
1057 bo_gem->gem_handle, bo_gem->name,
1059 pthread_mutex_unlock(&bufmgr_gem->lock);
1064 bo->virtual = bo_gem->gtt_virtual;
1066 DBG("bo_map_gtt: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1067 bo_gem->gtt_virtual);
1069 /* Now move it to the GTT domain so that the CPU caches are flushed */
1070 set_domain.handle = bo_gem->gem_handle;
1071 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1072 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
1074 ret = ioctl(bufmgr_gem->fd,
1075 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1077 } while (ret == -1 && errno == EINTR);
1081 fprintf(stderr, "%s:%d: Error setting domain %d: %s\n",
1082 __FILE__, __LINE__, bo_gem->gem_handle,
1086 pthread_mutex_unlock(&bufmgr_gem->lock);
1091 int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo)
1093 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1094 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1100 assert(bo_gem->gtt_virtual != NULL);
1102 pthread_mutex_lock(&bufmgr_gem->lock);
1104 pthread_mutex_unlock(&bufmgr_gem->lock);
1109 static int drm_intel_gem_bo_unmap(drm_intel_bo *bo)
1111 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1112 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1113 struct drm_i915_gem_sw_finish sw_finish;
1119 assert(bo_gem->mem_virtual != NULL);
1121 pthread_mutex_lock(&bufmgr_gem->lock);
1123 /* Cause a flush to happen if the buffer's pinned for scanout, so the
1124 * results show up in a timely manner.
1126 sw_finish.handle = bo_gem->gem_handle;
1128 ret = ioctl(bufmgr_gem->fd,
1129 DRM_IOCTL_I915_GEM_SW_FINISH,
1131 } while (ret == -1 && errno == EINTR);
1132 ret = ret == -1 ? -errno : 0;
1135 pthread_mutex_unlock(&bufmgr_gem->lock);
1141 drm_intel_gem_bo_subdata(drm_intel_bo *bo, unsigned long offset,
1142 unsigned long size, const void *data)
1144 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1145 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1146 struct drm_i915_gem_pwrite pwrite;
1149 memset(&pwrite, 0, sizeof(pwrite));
1150 pwrite.handle = bo_gem->gem_handle;
1151 pwrite.offset = offset;
1153 pwrite.data_ptr = (uint64_t) (uintptr_t) data;
1155 ret = ioctl(bufmgr_gem->fd,
1156 DRM_IOCTL_I915_GEM_PWRITE,
1158 } while (ret == -1 && errno == EINTR);
1162 "%s:%d: Error writing data to buffer %d: (%d %d) %s .\n",
1163 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1164 (int)size, strerror(errno));
1171 drm_intel_gem_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id)
1173 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1174 struct drm_i915_get_pipe_from_crtc_id get_pipe_from_crtc_id;
1177 get_pipe_from_crtc_id.crtc_id = crtc_id;
1178 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID,
1179 &get_pipe_from_crtc_id);
1181 /* We return -1 here to signal that we don't
1182 * know which pipe is associated with this crtc.
1183 * This lets the caller know that this information
1184 * isn't available; using the wrong pipe for
1185 * vblank waiting can cause the chipset to lock up
1190 return get_pipe_from_crtc_id.pipe;
1194 drm_intel_gem_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
1195 unsigned long size, void *data)
1197 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1198 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1199 struct drm_i915_gem_pread pread;
1202 memset(&pread, 0, sizeof(pread));
1203 pread.handle = bo_gem->gem_handle;
1204 pread.offset = offset;
1206 pread.data_ptr = (uint64_t) (uintptr_t) data;
1208 ret = ioctl(bufmgr_gem->fd,
1209 DRM_IOCTL_I915_GEM_PREAD,
1211 } while (ret == -1 && errno == EINTR);
1215 "%s:%d: Error reading data from buffer %d: (%d %d) %s .\n",
1216 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1217 (int)size, strerror(errno));
1223 /** Waits for all GPU rendering to the object to have completed. */
1225 drm_intel_gem_bo_wait_rendering(drm_intel_bo *bo)
1227 drm_intel_gem_bo_start_gtt_access(bo, 0);
1231 * Sets the object to the GTT read and possibly write domain, used by the X
1232 * 2D driver in the absence of kernel support to do drm_intel_gem_bo_map_gtt().
1234 * In combination with drm_intel_gem_bo_pin() and manual fence management, we
1235 * can do tiled pixmaps this way.
1238 drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable)
1240 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1241 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1242 struct drm_i915_gem_set_domain set_domain;
1245 set_domain.handle = bo_gem->gem_handle;
1246 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1247 set_domain.write_domain = write_enable ? I915_GEM_DOMAIN_GTT : 0;
1249 ret = ioctl(bufmgr_gem->fd,
1250 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1252 } while (ret == -1 && errno == EINTR);
1255 "%s:%d: Error setting memory domains %d (%08x %08x): %s .\n",
1256 __FILE__, __LINE__, bo_gem->gem_handle,
1257 set_domain.read_domains, set_domain.write_domain,
1263 drm_intel_bufmgr_gem_destroy(drm_intel_bufmgr *bufmgr)
1265 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1268 free(bufmgr_gem->exec2_objects);
1269 free(bufmgr_gem->exec_objects);
1270 free(bufmgr_gem->exec_bos);
1272 pthread_mutex_destroy(&bufmgr_gem->lock);
1274 /* Free any cached buffer objects we were going to reuse */
1275 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
1276 struct drm_intel_gem_bo_bucket *bucket =
1277 &bufmgr_gem->cache_bucket[i];
1278 drm_intel_bo_gem *bo_gem;
1280 while (!DRMLISTEMPTY(&bucket->head)) {
1281 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1282 bucket->head.next, head);
1283 DRMLISTDEL(&bo_gem->head);
1285 drm_intel_gem_bo_free(&bo_gem->bo);
1293 * Adds the target buffer to the validation list and adds the relocation
1294 * to the reloc_buffer's relocation list.
1296 * The relocation entry at the given offset must already contain the
1297 * precomputed relocation value, because the kernel will optimize out
1298 * the relocation entry write when the buffer hasn't moved from the
1299 * last known offset in target_bo.
1302 do_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1303 drm_intel_bo *target_bo, uint32_t target_offset,
1304 uint32_t read_domains, uint32_t write_domain,
1307 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1308 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1309 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
1311 if (bo_gem->has_error)
1314 if (target_bo_gem->has_error) {
1315 bo_gem->has_error = 1;
1319 if (target_bo_gem->tiling_mode == I915_TILING_NONE)
1322 /* We never use HW fences for rendering on 965+ */
1323 if (bufmgr_gem->gen >= 4)
1326 /* Create a new relocation list if needed */
1327 if (bo_gem->relocs == NULL && drm_intel_setup_reloc_list(bo))
1330 /* Check overflow */
1331 assert(bo_gem->reloc_count < bufmgr_gem->max_relocs);
1334 assert(offset <= bo->size - 4);
1335 assert((write_domain & (write_domain - 1)) == 0);
1337 /* Make sure that we're not adding a reloc to something whose size has
1338 * already been accounted for.
1340 assert(!bo_gem->used_as_reloc_target);
1341 if (target_bo_gem != bo_gem) {
1342 target_bo_gem->used_as_reloc_target = 1;
1343 bo_gem->reloc_tree_size += target_bo_gem->reloc_tree_size;
1345 /* An object needing a fence is a tiled buffer, so it won't have
1346 * relocs to other buffers.
1349 target_bo_gem->reloc_tree_fences = 1;
1350 bo_gem->reloc_tree_fences += target_bo_gem->reloc_tree_fences;
1352 /* Flag the target to disallow further relocations in it. */
1354 bo_gem->relocs[bo_gem->reloc_count].offset = offset;
1355 bo_gem->relocs[bo_gem->reloc_count].delta = target_offset;
1356 bo_gem->relocs[bo_gem->reloc_count].target_handle =
1357 target_bo_gem->gem_handle;
1358 bo_gem->relocs[bo_gem->reloc_count].read_domains = read_domains;
1359 bo_gem->relocs[bo_gem->reloc_count].write_domain = write_domain;
1360 bo_gem->relocs[bo_gem->reloc_count].presumed_offset = target_bo->offset;
1362 bo_gem->reloc_target_info[bo_gem->reloc_count].bo = target_bo;
1363 if (target_bo != bo)
1364 drm_intel_gem_bo_reference(target_bo);
1366 bo_gem->reloc_target_info[bo_gem->reloc_count].flags =
1367 DRM_INTEL_RELOC_FENCE;
1369 bo_gem->reloc_target_info[bo_gem->reloc_count].flags = 0;
1371 bo_gem->reloc_count++;
1377 drm_intel_gem_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1378 drm_intel_bo *target_bo, uint32_t target_offset,
1379 uint32_t read_domains, uint32_t write_domain)
1381 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1383 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1384 read_domains, write_domain,
1385 !bufmgr_gem->fenced_relocs);
1389 drm_intel_gem_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
1390 drm_intel_bo *target_bo,
1391 uint32_t target_offset,
1392 uint32_t read_domains, uint32_t write_domain)
1394 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1395 read_domains, write_domain, 1);
1399 * Walk the tree of relocations rooted at BO and accumulate the list of
1400 * validations to be performed and update the relocation buffers with
1401 * index values into the validation list.
1404 drm_intel_gem_bo_process_reloc(drm_intel_bo *bo)
1406 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1409 if (bo_gem->relocs == NULL)
1412 for (i = 0; i < bo_gem->reloc_count; i++) {
1413 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1415 if (target_bo == bo)
1418 /* Continue walking the tree depth-first. */
1419 drm_intel_gem_bo_process_reloc(target_bo);
1421 /* Add the target to the validate list */
1422 drm_intel_add_validate_buffer(target_bo);
1427 drm_intel_gem_bo_process_reloc2(drm_intel_bo *bo)
1429 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1432 if (bo_gem->relocs == NULL)
1435 for (i = 0; i < bo_gem->reloc_count; i++) {
1436 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1439 if (target_bo == bo)
1442 /* Continue walking the tree depth-first. */
1443 drm_intel_gem_bo_process_reloc2(target_bo);
1445 need_fence = (bo_gem->reloc_target_info[i].flags &
1446 DRM_INTEL_RELOC_FENCE);
1448 /* Add the target to the validate list */
1449 drm_intel_add_validate_buffer2(target_bo, need_fence);
1455 drm_intel_update_buffer_offsets(drm_intel_bufmgr_gem *bufmgr_gem)
1459 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1460 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1461 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1463 /* Update the buffer offset */
1464 if (bufmgr_gem->exec_objects[i].offset != bo->offset) {
1465 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1466 bo_gem->gem_handle, bo_gem->name, bo->offset,
1467 (unsigned long long)bufmgr_gem->exec_objects[i].
1469 bo->offset = bufmgr_gem->exec_objects[i].offset;
1475 drm_intel_update_buffer_offsets2 (drm_intel_bufmgr_gem *bufmgr_gem)
1479 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1480 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1481 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1483 /* Update the buffer offset */
1484 if (bufmgr_gem->exec2_objects[i].offset != bo->offset) {
1485 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1486 bo_gem->gem_handle, bo_gem->name, bo->offset,
1487 (unsigned long long)bufmgr_gem->exec2_objects[i].offset);
1488 bo->offset = bufmgr_gem->exec2_objects[i].offset;
1494 drm_intel_gem_bo_exec(drm_intel_bo *bo, int used,
1495 drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
1497 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1498 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1499 struct drm_i915_gem_execbuffer execbuf;
1502 if (bo_gem->has_error)
1505 pthread_mutex_lock(&bufmgr_gem->lock);
1506 /* Update indices and set up the validate list. */
1507 drm_intel_gem_bo_process_reloc(bo);
1509 /* Add the batch buffer to the validation list. There are no
1510 * relocations pointing to it.
1512 drm_intel_add_validate_buffer(bo);
1514 execbuf.buffers_ptr = (uintptr_t) bufmgr_gem->exec_objects;
1515 execbuf.buffer_count = bufmgr_gem->exec_count;
1516 execbuf.batch_start_offset = 0;
1517 execbuf.batch_len = used;
1518 execbuf.cliprects_ptr = (uintptr_t) cliprects;
1519 execbuf.num_cliprects = num_cliprects;
1524 ret = ioctl(bufmgr_gem->fd,
1525 DRM_IOCTL_I915_GEM_EXECBUFFER,
1527 } while (ret != 0 && errno == EINTR);
1531 if (errno == ENOSPC) {
1533 "Execbuffer fails to pin. "
1534 "Estimate: %u. Actual: %u. Available: %u\n",
1535 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
1538 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
1541 (unsigned int)bufmgr_gem->gtt_size);
1544 drm_intel_update_buffer_offsets(bufmgr_gem);
1546 if (bufmgr_gem->bufmgr.debug)
1547 drm_intel_gem_dump_validation_list(bufmgr_gem);
1549 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1550 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1551 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1553 /* Disconnect the buffer from the validate list */
1554 bo_gem->validate_index = -1;
1555 bufmgr_gem->exec_bos[i] = NULL;
1557 bufmgr_gem->exec_count = 0;
1558 pthread_mutex_unlock(&bufmgr_gem->lock);
1564 drm_intel_gem_bo_mrb_exec2(drm_intel_bo *bo, int used,
1565 drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
1568 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1569 struct drm_i915_gem_execbuffer2 execbuf;
1572 if ((ring_flag != I915_EXEC_RENDER) && (ring_flag != I915_EXEC_BSD))
1575 pthread_mutex_lock(&bufmgr_gem->lock);
1576 /* Update indices and set up the validate list. */
1577 drm_intel_gem_bo_process_reloc2(bo);
1579 /* Add the batch buffer to the validation list. There are no relocations
1582 drm_intel_add_validate_buffer2(bo, 0);
1584 execbuf.buffers_ptr = (uintptr_t)bufmgr_gem->exec2_objects;
1585 execbuf.buffer_count = bufmgr_gem->exec_count;
1586 execbuf.batch_start_offset = 0;
1587 execbuf.batch_len = used;
1588 execbuf.cliprects_ptr = (uintptr_t)cliprects;
1589 execbuf.num_cliprects = num_cliprects;
1592 execbuf.flags = ring_flag;
1597 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_EXECBUFFER2,
1599 } while (ret != 0 && errno == EINTR);
1603 if (ret == -ENOMEM) {
1605 "Execbuffer fails to pin. "
1606 "Estimate: %u. Actual: %u. Available: %u\n",
1607 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
1608 bufmgr_gem->exec_count),
1609 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
1610 bufmgr_gem->exec_count),
1611 (unsigned int) bufmgr_gem->gtt_size);
1614 drm_intel_update_buffer_offsets2(bufmgr_gem);
1616 if (bufmgr_gem->bufmgr.debug)
1617 drm_intel_gem_dump_validation_list(bufmgr_gem);
1619 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1620 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1621 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1623 /* Disconnect the buffer from the validate list */
1624 bo_gem->validate_index = -1;
1625 bufmgr_gem->exec_bos[i] = NULL;
1627 bufmgr_gem->exec_count = 0;
1628 pthread_mutex_unlock(&bufmgr_gem->lock);
1634 drm_intel_gem_bo_exec2(drm_intel_bo *bo, int used,
1635 drm_clip_rect_t *cliprects, int num_cliprects,
1638 return drm_intel_gem_bo_mrb_exec2(bo, used,
1639 cliprects, num_cliprects, DR4,
1644 drm_intel_gem_bo_pin(drm_intel_bo *bo, uint32_t alignment)
1646 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1647 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1648 struct drm_i915_gem_pin pin;
1651 memset(&pin, 0, sizeof(pin));
1652 pin.handle = bo_gem->gem_handle;
1653 pin.alignment = alignment;
1656 ret = ioctl(bufmgr_gem->fd,
1657 DRM_IOCTL_I915_GEM_PIN,
1659 } while (ret == -1 && errno == EINTR);
1664 bo->offset = pin.offset;
1669 drm_intel_gem_bo_unpin(drm_intel_bo *bo)
1671 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1672 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1673 struct drm_i915_gem_unpin unpin;
1676 memset(&unpin, 0, sizeof(unpin));
1677 unpin.handle = bo_gem->gem_handle;
1679 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_UNPIN, &unpin);
1687 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
1688 uint32_t tiling_mode,
1691 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1692 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1693 struct drm_i915_gem_set_tiling set_tiling;
1696 if (tiling_mode == bo_gem->tiling_mode &&
1697 stride == bo_gem->stride)
1700 memset(&set_tiling, 0, sizeof(set_tiling));
1702 set_tiling.handle = bo_gem->gem_handle;
1703 set_tiling.tiling_mode = tiling_mode;
1704 set_tiling.stride = stride;
1706 ret = ioctl(bufmgr_gem->fd,
1707 DRM_IOCTL_I915_GEM_SET_TILING,
1709 } while (ret == -1 && errno == EINTR);
1713 bo_gem->tiling_mode = set_tiling.tiling_mode;
1714 bo_gem->swizzle_mode = set_tiling.swizzle_mode;
1715 bo_gem->stride = stride;
1720 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1723 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1724 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1727 if (bo_gem->global_name == 0)
1730 ret = drm_intel_gem_bo_set_tiling_internal(bo, *tiling_mode, stride);
1732 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
1734 *tiling_mode = bo_gem->tiling_mode;
1739 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1740 uint32_t * swizzle_mode)
1742 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1744 *tiling_mode = bo_gem->tiling_mode;
1745 *swizzle_mode = bo_gem->swizzle_mode;
1750 drm_intel_gem_bo_flink(drm_intel_bo *bo, uint32_t * name)
1752 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1753 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1754 struct drm_gem_flink flink;
1757 if (!bo_gem->global_name) {
1758 memset(&flink, 0, sizeof(flink));
1759 flink.handle = bo_gem->gem_handle;
1761 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_FLINK, &flink);
1764 bo_gem->global_name = flink.name;
1765 bo_gem->reusable = 0;
1768 *name = bo_gem->global_name;
1773 * Enables unlimited caching of buffer objects for reuse.
1775 * This is potentially very memory expensive, as the cache at each bucket
1776 * size is only bounded by how many buffers of that size we've managed to have
1777 * in flight at once.
1780 drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr)
1782 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1784 bufmgr_gem->bo_reuse = 1;
1788 * Enable use of fenced reloc type.
1790 * New code should enable this to avoid unnecessary fence register
1791 * allocation. If this option is not enabled, all relocs will have fence
1792 * register allocated.
1795 drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr)
1797 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
1799 if (bufmgr_gem->bufmgr.bo_exec == drm_intel_gem_bo_exec2)
1800 bufmgr_gem->fenced_relocs = 1;
1804 * Return the additional aperture space required by the tree of buffer objects
1808 drm_intel_gem_bo_get_aperture_space(drm_intel_bo *bo)
1810 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1814 if (bo == NULL || bo_gem->included_in_check_aperture)
1818 bo_gem->included_in_check_aperture = 1;
1820 for (i = 0; i < bo_gem->reloc_count; i++)
1822 drm_intel_gem_bo_get_aperture_space(bo_gem->
1823 reloc_target_info[i].bo);
1829 * Count the number of buffers in this list that need a fence reg
1831 * If the count is greater than the number of available regs, we'll have
1832 * to ask the caller to resubmit a batch with fewer tiled buffers.
1834 * This function over-counts if the same buffer is used multiple times.
1837 drm_intel_gem_total_fences(drm_intel_bo ** bo_array, int count)
1840 unsigned int total = 0;
1842 for (i = 0; i < count; i++) {
1843 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
1848 total += bo_gem->reloc_tree_fences;
1854 * Clear the flag set by drm_intel_gem_bo_get_aperture_space() so we're ready
1855 * for the next drm_intel_bufmgr_check_aperture_space() call.
1858 drm_intel_gem_bo_clear_aperture_space_flag(drm_intel_bo *bo)
1860 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1863 if (bo == NULL || !bo_gem->included_in_check_aperture)
1866 bo_gem->included_in_check_aperture = 0;
1868 for (i = 0; i < bo_gem->reloc_count; i++)
1869 drm_intel_gem_bo_clear_aperture_space_flag(bo_gem->
1870 reloc_target_info[i].bo);
1874 * Return a conservative estimate for the amount of aperture required
1875 * for a collection of buffers. This may double-count some buffers.
1878 drm_intel_gem_estimate_batch_space(drm_intel_bo **bo_array, int count)
1881 unsigned int total = 0;
1883 for (i = 0; i < count; i++) {
1884 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
1886 total += bo_gem->reloc_tree_size;
1892 * Return the amount of aperture needed for a collection of buffers.
1893 * This avoids double counting any buffers, at the cost of looking
1894 * at every buffer in the set.
1897 drm_intel_gem_compute_batch_space(drm_intel_bo **bo_array, int count)
1900 unsigned int total = 0;
1902 for (i = 0; i < count; i++) {
1903 total += drm_intel_gem_bo_get_aperture_space(bo_array[i]);
1904 /* For the first buffer object in the array, we get an
1905 * accurate count back for its reloc_tree size (since nothing
1906 * had been flagged as being counted yet). We can save that
1907 * value out as a more conservative reloc_tree_size that
1908 * avoids double-counting target buffers. Since the first
1909 * buffer happens to usually be the batch buffer in our
1910 * callers, this can pull us back from doing the tree
1911 * walk on every new batch emit.
1914 drm_intel_bo_gem *bo_gem =
1915 (drm_intel_bo_gem *) bo_array[i];
1916 bo_gem->reloc_tree_size = total;
1920 for (i = 0; i < count; i++)
1921 drm_intel_gem_bo_clear_aperture_space_flag(bo_array[i]);
1926 * Return -1 if the batchbuffer should be flushed before attempting to
1927 * emit rendering referencing the buffers pointed to by bo_array.
1929 * This is required because if we try to emit a batchbuffer with relocations
1930 * to a tree of buffers that won't simultaneously fit in the aperture,
1931 * the rendering will return an error at a point where the software is not
1932 * prepared to recover from it.
1934 * However, we also want to emit the batchbuffer significantly before we reach
1935 * the limit, as a series of batchbuffers each of which references buffers
1936 * covering almost all of the aperture means that at each emit we end up
1937 * waiting to evict a buffer from the last rendering, and we get synchronous
1938 * performance. By emitting smaller batchbuffers, we eat some CPU overhead to
1939 * get better parallelism.
1942 drm_intel_gem_check_aperture_space(drm_intel_bo **bo_array, int count)
1944 drm_intel_bufmgr_gem *bufmgr_gem =
1945 (drm_intel_bufmgr_gem *) bo_array[0]->bufmgr;
1946 unsigned int total = 0;
1947 unsigned int threshold = bufmgr_gem->gtt_size * 3 / 4;
1950 /* Check for fence reg constraints if necessary */
1951 if (bufmgr_gem->available_fences) {
1952 total_fences = drm_intel_gem_total_fences(bo_array, count);
1953 if (total_fences > bufmgr_gem->available_fences)
1957 total = drm_intel_gem_estimate_batch_space(bo_array, count);
1959 if (total > threshold)
1960 total = drm_intel_gem_compute_batch_space(bo_array, count);
1962 if (total > threshold) {
1963 DBG("check_space: overflowed available aperture, "
1965 total / 1024, (int)bufmgr_gem->gtt_size / 1024);
1968 DBG("drm_check_space: total %dkb vs bufgr %dkb\n", total / 1024,
1969 (int)bufmgr_gem->gtt_size / 1024);
1975 * Disable buffer reuse for objects which are shared with the kernel
1976 * as scanout buffers
1979 drm_intel_gem_bo_disable_reuse(drm_intel_bo *bo)
1981 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1983 bo_gem->reusable = 0;
1988 drm_intel_gem_bo_is_reusable(drm_intel_bo *bo)
1990 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1992 return bo_gem->reusable;
1996 _drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
1998 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2001 for (i = 0; i < bo_gem->reloc_count; i++) {
2002 if (bo_gem->reloc_target_info[i].bo == target_bo)
2004 if (bo == bo_gem->reloc_target_info[i].bo)
2006 if (_drm_intel_gem_bo_references(bo_gem->reloc_target_info[i].bo,
2014 /** Return true if target_bo is referenced by bo's relocation tree. */
2016 drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
2018 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
2020 if (bo == NULL || target_bo == NULL)
2022 if (target_bo_gem->used_as_reloc_target)
2023 return _drm_intel_gem_bo_references(bo, target_bo);
2028 add_bucket(drm_intel_bufmgr_gem *bufmgr_gem, int size)
2030 unsigned int i = bufmgr_gem->num_buckets;
2032 assert(i < ARRAY_SIZE(bufmgr_gem->cache_bucket));
2034 DRMINITLISTHEAD(&bufmgr_gem->cache_bucket[i].head);
2035 bufmgr_gem->cache_bucket[i].size = size;
2036 bufmgr_gem->num_buckets++;
2040 init_cache_buckets(drm_intel_bufmgr_gem *bufmgr_gem)
2042 unsigned long size, cache_max_size = 64 * 1024 * 1024;
2044 /* OK, so power of two buckets was too wasteful of memory.
2045 * Give 3 other sizes between each power of two, to hopefully
2046 * cover things accurately enough. (The alternative is
2047 * probably to just go for exact matching of sizes, and assume
2048 * that for things like composited window resize the tiled
2049 * width/height alignment and rounding of sizes to pages will
2050 * get us useful cache hit rates anyway)
2052 add_bucket(bufmgr_gem, 4096);
2053 add_bucket(bufmgr_gem, 4096 * 2);
2054 add_bucket(bufmgr_gem, 4096 * 3);
2056 /* Initialize the linked lists for BO reuse cache. */
2057 for (size = 4 * 4096; size <= cache_max_size; size *= 2) {
2058 add_bucket(bufmgr_gem, size);
2060 add_bucket(bufmgr_gem, size + size * 1 / 4);
2061 add_bucket(bufmgr_gem, size + size * 2 / 4);
2062 add_bucket(bufmgr_gem, size + size * 3 / 4);
2067 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
2068 * and manage map buffer objections.
2070 * \param fd File descriptor of the opened DRM device.
2073 drm_intel_bufmgr_gem_init(int fd, int batch_size)
2075 drm_intel_bufmgr_gem *bufmgr_gem;
2076 struct drm_i915_gem_get_aperture aperture;
2077 drm_i915_getparam_t gp;
2079 int exec2 = 0, has_bsd = 0;
2081 bufmgr_gem = calloc(1, sizeof(*bufmgr_gem));
2082 if (bufmgr_gem == NULL)
2085 bufmgr_gem->fd = fd;
2087 if (pthread_mutex_init(&bufmgr_gem->lock, NULL) != 0) {
2092 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
2095 bufmgr_gem->gtt_size = aperture.aper_available_size;
2097 fprintf(stderr, "DRM_IOCTL_I915_GEM_APERTURE failed: %s\n",
2099 bufmgr_gem->gtt_size = 128 * 1024 * 1024;
2100 fprintf(stderr, "Assuming %dkB available aperture size.\n"
2101 "May lead to reduced performance or incorrect "
2103 (int)bufmgr_gem->gtt_size / 1024);
2106 gp.param = I915_PARAM_CHIPSET_ID;
2107 gp.value = &bufmgr_gem->pci_device;
2108 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2110 fprintf(stderr, "get chip id failed: %d [%d]\n", ret, errno);
2111 fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value);
2114 if (IS_GEN2(bufmgr_gem))
2115 bufmgr_gem->gen = 2;
2116 else if (IS_GEN3(bufmgr_gem))
2117 bufmgr_gem->gen = 3;
2118 else if (IS_GEN4(bufmgr_gem))
2119 bufmgr_gem->gen = 4;
2121 bufmgr_gem->gen = 6;
2123 gp.param = I915_PARAM_HAS_EXECBUF2;
2124 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2128 gp.param = I915_PARAM_HAS_BSD;
2129 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2133 if (bufmgr_gem->gen < 4) {
2134 gp.param = I915_PARAM_NUM_FENCES_AVAIL;
2135 gp.value = &bufmgr_gem->available_fences;
2136 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2138 fprintf(stderr, "get fences failed: %d [%d]\n", ret,
2140 fprintf(stderr, "param: %d, val: %d\n", gp.param,
2142 bufmgr_gem->available_fences = 0;
2144 /* XXX The kernel reports the total number of fences,
2145 * including any that may be pinned.
2147 * We presume that there will be at least one pinned
2148 * fence for the scanout buffer, but there may be more
2149 * than one scanout and the user may be manually
2150 * pinning buffers. Let's move to execbuffer2 and
2151 * thereby forget the insanity of using fences...
2153 bufmgr_gem->available_fences -= 2;
2154 if (bufmgr_gem->available_fences < 0)
2155 bufmgr_gem->available_fences = 0;
2159 /* Let's go with one relocation per every 2 dwords (but round down a bit
2160 * since a power of two will mean an extra page allocation for the reloc
2163 * Every 4 was too few for the blender benchmark.
2165 bufmgr_gem->max_relocs = batch_size / sizeof(uint32_t) / 2 - 2;
2167 bufmgr_gem->bufmgr.bo_alloc = drm_intel_gem_bo_alloc;
2168 bufmgr_gem->bufmgr.bo_alloc_for_render =
2169 drm_intel_gem_bo_alloc_for_render;
2170 bufmgr_gem->bufmgr.bo_alloc_tiled = drm_intel_gem_bo_alloc_tiled;
2171 bufmgr_gem->bufmgr.bo_reference = drm_intel_gem_bo_reference;
2172 bufmgr_gem->bufmgr.bo_unreference = drm_intel_gem_bo_unreference;
2173 bufmgr_gem->bufmgr.bo_map = drm_intel_gem_bo_map;
2174 bufmgr_gem->bufmgr.bo_unmap = drm_intel_gem_bo_unmap;
2175 bufmgr_gem->bufmgr.bo_subdata = drm_intel_gem_bo_subdata;
2176 bufmgr_gem->bufmgr.bo_get_subdata = drm_intel_gem_bo_get_subdata;
2177 bufmgr_gem->bufmgr.bo_wait_rendering = drm_intel_gem_bo_wait_rendering;
2178 bufmgr_gem->bufmgr.bo_emit_reloc = drm_intel_gem_bo_emit_reloc;
2179 bufmgr_gem->bufmgr.bo_emit_reloc_fence = drm_intel_gem_bo_emit_reloc_fence;
2180 bufmgr_gem->bufmgr.bo_pin = drm_intel_gem_bo_pin;
2181 bufmgr_gem->bufmgr.bo_unpin = drm_intel_gem_bo_unpin;
2182 bufmgr_gem->bufmgr.bo_get_tiling = drm_intel_gem_bo_get_tiling;
2183 bufmgr_gem->bufmgr.bo_set_tiling = drm_intel_gem_bo_set_tiling;
2184 bufmgr_gem->bufmgr.bo_flink = drm_intel_gem_bo_flink;
2185 /* Use the new one if available */
2187 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec2;
2189 bufmgr_gem->bufmgr.bo_mrb_exec = drm_intel_gem_bo_mrb_exec2;
2191 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec;
2192 bufmgr_gem->bufmgr.bo_busy = drm_intel_gem_bo_busy;
2193 bufmgr_gem->bufmgr.bo_madvise = drm_intel_gem_bo_madvise;
2194 bufmgr_gem->bufmgr.destroy = drm_intel_bufmgr_gem_destroy;
2195 bufmgr_gem->bufmgr.debug = 0;
2196 bufmgr_gem->bufmgr.check_aperture_space =
2197 drm_intel_gem_check_aperture_space;
2198 bufmgr_gem->bufmgr.bo_disable_reuse = drm_intel_gem_bo_disable_reuse;
2199 bufmgr_gem->bufmgr.bo_is_reusable = drm_intel_gem_bo_is_reusable;
2200 bufmgr_gem->bufmgr.get_pipe_from_crtc_id =
2201 drm_intel_gem_get_pipe_from_crtc_id;
2202 bufmgr_gem->bufmgr.bo_references = drm_intel_gem_bo_references;
2204 init_cache_buckets(bufmgr_gem);
2206 return &bufmgr_gem->bufmgr;