1 /**************************************************************************
3 * Copyright © 2007 Red Hat Inc.
4 * Copyright © 2007 Intel Corporation
5 * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
29 **************************************************************************/
31 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
32 * Keith Whitwell <keithw-at-tungstengraphics-dot-com>
33 * Eric Anholt <eric@anholt.net>
34 * Dave Airlie <airlied@linux.ie>
42 #include <xf86atomic.h>
50 #include <sys/ioctl.h>
53 #include <sys/types.h>
56 #include "libdrm_lists.h"
57 #include "intel_bufmgr.h"
58 #include "intel_bufmgr_priv.h"
59 #include "intel_chipset.h"
64 #define DBG(...) do { \
65 if (bufmgr_gem->bufmgr.debug) \
66 fprintf(stderr, __VA_ARGS__); \
69 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
71 typedef struct _drm_intel_bo_gem drm_intel_bo_gem;
73 struct drm_intel_gem_bo_bucket {
78 typedef struct _drm_intel_bufmgr_gem {
79 drm_intel_bufmgr bufmgr;
87 struct drm_i915_gem_exec_object *exec_objects;
88 struct drm_i915_gem_exec_object2 *exec2_objects;
89 drm_intel_bo **exec_bos;
93 /** Array of lists of cached gem objects of power-of-two sizes */
94 struct drm_intel_gem_bo_bucket cache_bucket[14 * 4];
103 } drm_intel_bufmgr_gem;
105 #define DRM_INTEL_RELOC_FENCE (1<<0)
107 typedef struct _drm_intel_reloc_target_info {
110 } drm_intel_reloc_target;
112 struct _drm_intel_bo_gem {
120 * Kenel-assigned global name for this object
122 unsigned int global_name;
125 * Index of the buffer within the validation list while preparing a
126 * batchbuffer execution.
131 * Current tiling mode
133 uint32_t tiling_mode;
134 uint32_t swizzle_mode;
138 /** Array passed to the DRM containing relocation information. */
139 struct drm_i915_gem_relocation_entry *relocs;
141 * Array of info structs corresponding to relocs[i].target_handle etc
143 drm_intel_reloc_target *reloc_target_info;
144 /** Number of entries in relocs */
146 /** Mapped address for the buffer, saved across map/unmap cycles */
148 /** GTT virtual address for the buffer, saved across map/unmap cycles */
155 * Boolean of whether this BO and its children have been included in
156 * the current drm_intel_bufmgr_check_aperture_space() total.
158 char included_in_check_aperture;
161 * Boolean of whether this buffer has been used as a relocation
162 * target and had its size accounted for, and thus can't have any
163 * further relocations added to it.
165 char used_as_reloc_target;
168 * Boolean of whether we have encountered an error whilst building the relocation tree.
173 * Boolean of whether this buffer can be re-used
178 * Size in bytes of this buffer and its relocation descendents.
180 * Used to avoid costly tree walking in
181 * drm_intel_bufmgr_check_aperture in the common case.
186 * Number of potential fence registers required by this buffer and its
189 int reloc_tree_fences;
193 drm_intel_gem_estimate_batch_space(drm_intel_bo ** bo_array, int count);
196 drm_intel_gem_compute_batch_space(drm_intel_bo ** bo_array, int count);
199 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
200 uint32_t * swizzle_mode);
203 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
206 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
209 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo);
211 static void drm_intel_gem_bo_free(drm_intel_bo *bo);
214 drm_intel_gem_bo_tile_size(drm_intel_bufmgr_gem *bufmgr_gem, unsigned long size,
215 uint32_t *tiling_mode)
217 unsigned long min_size, max_size;
220 if (*tiling_mode == I915_TILING_NONE)
223 /* 965+ just need multiples of page size for tiling */
224 if (bufmgr_gem->gen >= 4)
225 return ROUND_UP_TO(size, 4096);
227 /* Older chips need powers of two, of at least 512k or 1M */
228 if (bufmgr_gem->gen == 3) {
229 min_size = 1024*1024;
230 max_size = 128*1024*1024;
233 max_size = 64*1024*1024;
236 if (size > max_size) {
237 *tiling_mode = I915_TILING_NONE;
241 for (i = min_size; i < size; i <<= 1)
248 * Round a given pitch up to the minimum required for X tiling on a
249 * given chip. We use 512 as the minimum to allow for a later tiling
253 drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem,
254 unsigned long pitch, uint32_t tiling_mode)
256 unsigned long tile_width;
259 /* If untiled, then just align it so that we can do rendering
260 * to it with the 3D engine.
262 if (tiling_mode == I915_TILING_NONE)
263 return ALIGN(pitch, 64);
265 if (tiling_mode == I915_TILING_X)
270 /* 965 is flexible */
271 if (bufmgr_gem->gen >= 4)
272 return ROUND_UP_TO(pitch, tile_width);
274 /* Pre-965 needs power of two tile width */
275 for (i = tile_width; i < pitch; i <<= 1)
281 static struct drm_intel_gem_bo_bucket *
282 drm_intel_gem_bo_bucket_for_size(drm_intel_bufmgr_gem *bufmgr_gem,
287 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
288 struct drm_intel_gem_bo_bucket *bucket =
289 &bufmgr_gem->cache_bucket[i];
290 if (bucket->size >= size) {
299 drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem *bufmgr_gem)
303 for (i = 0; i < bufmgr_gem->exec_count; i++) {
304 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
305 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
307 if (bo_gem->relocs == NULL) {
308 DBG("%2d: %d (%s)\n", i, bo_gem->gem_handle,
313 for (j = 0; j < bo_gem->reloc_count; j++) {
314 drm_intel_bo *target_bo = bo_gem->reloc_target_info[j].bo;
315 drm_intel_bo_gem *target_gem =
316 (drm_intel_bo_gem *) target_bo;
318 DBG("%2d: %d (%s)@0x%08llx -> "
319 "%d (%s)@0x%08lx + 0x%08x\n",
321 bo_gem->gem_handle, bo_gem->name,
322 (unsigned long long)bo_gem->relocs[j].offset,
323 target_gem->gem_handle,
326 bo_gem->relocs[j].delta);
332 drm_intel_gem_bo_reference(drm_intel_bo *bo)
334 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
336 assert(atomic_read(&bo_gem->refcount) > 0);
337 atomic_inc(&bo_gem->refcount);
341 * Adds the given buffer to the list of buffers to be validated (moved into the
342 * appropriate memory type) with the next batch submission.
344 * If a buffer is validated multiple times in a batch submission, it ends up
345 * with the intersection of the memory type flags and the union of the
349 drm_intel_add_validate_buffer(drm_intel_bo *bo)
351 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
352 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
355 if (bo_gem->validate_index != -1)
358 /* Extend the array of validation entries as necessary. */
359 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
360 int new_size = bufmgr_gem->exec_size * 2;
365 bufmgr_gem->exec_objects =
366 realloc(bufmgr_gem->exec_objects,
367 sizeof(*bufmgr_gem->exec_objects) * new_size);
368 bufmgr_gem->exec_bos =
369 realloc(bufmgr_gem->exec_bos,
370 sizeof(*bufmgr_gem->exec_bos) * new_size);
371 bufmgr_gem->exec_size = new_size;
374 index = bufmgr_gem->exec_count;
375 bo_gem->validate_index = index;
376 /* Fill in array entry */
377 bufmgr_gem->exec_objects[index].handle = bo_gem->gem_handle;
378 bufmgr_gem->exec_objects[index].relocation_count = bo_gem->reloc_count;
379 bufmgr_gem->exec_objects[index].relocs_ptr = (uintptr_t) bo_gem->relocs;
380 bufmgr_gem->exec_objects[index].alignment = 0;
381 bufmgr_gem->exec_objects[index].offset = 0;
382 bufmgr_gem->exec_bos[index] = bo;
383 bufmgr_gem->exec_count++;
387 drm_intel_add_validate_buffer2(drm_intel_bo *bo, int need_fence)
389 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
390 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
393 if (bo_gem->validate_index != -1) {
395 bufmgr_gem->exec2_objects[bo_gem->validate_index].flags |=
396 EXEC_OBJECT_NEEDS_FENCE;
400 /* Extend the array of validation entries as necessary. */
401 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
402 int new_size = bufmgr_gem->exec_size * 2;
407 bufmgr_gem->exec2_objects =
408 realloc(bufmgr_gem->exec2_objects,
409 sizeof(*bufmgr_gem->exec2_objects) * new_size);
410 bufmgr_gem->exec_bos =
411 realloc(bufmgr_gem->exec_bos,
412 sizeof(*bufmgr_gem->exec_bos) * new_size);
413 bufmgr_gem->exec_size = new_size;
416 index = bufmgr_gem->exec_count;
417 bo_gem->validate_index = index;
418 /* Fill in array entry */
419 bufmgr_gem->exec2_objects[index].handle = bo_gem->gem_handle;
420 bufmgr_gem->exec2_objects[index].relocation_count = bo_gem->reloc_count;
421 bufmgr_gem->exec2_objects[index].relocs_ptr = (uintptr_t)bo_gem->relocs;
422 bufmgr_gem->exec2_objects[index].alignment = 0;
423 bufmgr_gem->exec2_objects[index].offset = 0;
424 bufmgr_gem->exec_bos[index] = bo;
425 bufmgr_gem->exec2_objects[index].flags = 0;
426 bufmgr_gem->exec2_objects[index].rsvd1 = 0;
427 bufmgr_gem->exec2_objects[index].rsvd2 = 0;
429 bufmgr_gem->exec2_objects[index].flags |=
430 EXEC_OBJECT_NEEDS_FENCE;
432 bufmgr_gem->exec_count++;
435 #define RELOC_BUF_SIZE(x) ((I915_RELOC_HEADER + x * I915_RELOC0_STRIDE) * \
439 drm_intel_bo_gem_set_in_aperture_size(drm_intel_bufmgr_gem *bufmgr_gem,
440 drm_intel_bo_gem *bo_gem)
444 assert(!bo_gem->used_as_reloc_target);
446 /* The older chipsets are far-less flexible in terms of tiling,
447 * and require tiled buffer to be size aligned in the aperture.
448 * This means that in the worst possible case we will need a hole
449 * twice as large as the object in order for it to fit into the
450 * aperture. Optimal packing is for wimps.
452 size = bo_gem->bo.size;
453 if (bufmgr_gem->gen < 4 && bo_gem->tiling_mode != I915_TILING_NONE)
456 bo_gem->reloc_tree_size = size;
460 drm_intel_setup_reloc_list(drm_intel_bo *bo)
462 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
463 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
464 unsigned int max_relocs = bufmgr_gem->max_relocs;
466 if (bo->size / 4 < max_relocs)
467 max_relocs = bo->size / 4;
469 bo_gem->relocs = malloc(max_relocs *
470 sizeof(struct drm_i915_gem_relocation_entry));
471 bo_gem->reloc_target_info = malloc(max_relocs *
472 sizeof(drm_intel_reloc_target));
473 if (bo_gem->relocs == NULL || bo_gem->reloc_target_info == NULL) {
474 bo_gem->has_error = 1;
476 free (bo_gem->relocs);
477 bo_gem->relocs = NULL;
479 free (bo_gem->reloc_target_info);
480 bo_gem->reloc_target_info = NULL;
489 drm_intel_gem_bo_busy(drm_intel_bo *bo)
491 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
492 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
493 struct drm_i915_gem_busy busy;
496 memset(&busy, 0, sizeof(busy));
497 busy.handle = bo_gem->gem_handle;
500 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_BUSY, &busy);
501 } while (ret == -1 && errno == EINTR);
503 return (ret == 0 && busy.busy);
507 drm_intel_gem_bo_madvise_internal(drm_intel_bufmgr_gem *bufmgr_gem,
508 drm_intel_bo_gem *bo_gem, int state)
510 struct drm_i915_gem_madvise madv;
512 madv.handle = bo_gem->gem_handle;
515 ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MADVISE, &madv);
517 return madv.retained;
521 drm_intel_gem_bo_madvise(drm_intel_bo *bo, int madv)
523 return drm_intel_gem_bo_madvise_internal
524 ((drm_intel_bufmgr_gem *) bo->bufmgr,
525 (drm_intel_bo_gem *) bo,
529 /* drop the oldest entries that have been purged by the kernel */
531 drm_intel_gem_bo_cache_purge_bucket(drm_intel_bufmgr_gem *bufmgr_gem,
532 struct drm_intel_gem_bo_bucket *bucket)
534 while (!DRMLISTEMPTY(&bucket->head)) {
535 drm_intel_bo_gem *bo_gem;
537 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
538 bucket->head.next, head);
539 if (drm_intel_gem_bo_madvise_internal
540 (bufmgr_gem, bo_gem, I915_MADV_DONTNEED))
543 DRMLISTDEL(&bo_gem->head);
544 drm_intel_gem_bo_free(&bo_gem->bo);
548 static drm_intel_bo *
549 drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr,
554 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
555 drm_intel_bo_gem *bo_gem;
556 unsigned int page_size = getpagesize();
558 struct drm_intel_gem_bo_bucket *bucket;
559 int alloc_from_cache;
560 unsigned long bo_size;
563 if (flags & BO_ALLOC_FOR_RENDER)
566 /* Round the allocated size up to a power of two number of pages. */
567 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, size);
569 /* If we don't have caching at this size, don't actually round the
572 if (bucket == NULL) {
574 if (bo_size < page_size)
577 bo_size = bucket->size;
580 pthread_mutex_lock(&bufmgr_gem->lock);
581 /* Get a buffer out of the cache if available */
583 alloc_from_cache = 0;
584 if (bucket != NULL && !DRMLISTEMPTY(&bucket->head)) {
586 /* Allocate new render-target BOs from the tail (MRU)
587 * of the list, as it will likely be hot in the GPU
588 * cache and in the aperture for us.
590 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
591 bucket->head.prev, head);
592 DRMLISTDEL(&bo_gem->head);
593 alloc_from_cache = 1;
595 /* For non-render-target BOs (where we're probably
596 * going to map it first thing in order to fill it
597 * with data), check if the last BO in the cache is
598 * unbusy, and only reuse in that case. Otherwise,
599 * allocating a new buffer is probably faster than
600 * waiting for the GPU to finish.
602 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
603 bucket->head.next, head);
604 if (!drm_intel_gem_bo_busy(&bo_gem->bo)) {
605 alloc_from_cache = 1;
606 DRMLISTDEL(&bo_gem->head);
610 if (alloc_from_cache) {
611 if (!drm_intel_gem_bo_madvise_internal
612 (bufmgr_gem, bo_gem, I915_MADV_WILLNEED)) {
613 drm_intel_gem_bo_free(&bo_gem->bo);
614 drm_intel_gem_bo_cache_purge_bucket(bufmgr_gem,
620 pthread_mutex_unlock(&bufmgr_gem->lock);
622 if (!alloc_from_cache) {
623 struct drm_i915_gem_create create;
625 bo_gem = calloc(1, sizeof(*bo_gem));
629 bo_gem->bo.size = bo_size;
630 memset(&create, 0, sizeof(create));
631 create.size = bo_size;
634 ret = ioctl(bufmgr_gem->fd,
635 DRM_IOCTL_I915_GEM_CREATE,
637 } while (ret == -1 && errno == EINTR);
638 bo_gem->gem_handle = create.handle;
639 bo_gem->bo.handle = bo_gem->gem_handle;
644 bo_gem->bo.bufmgr = bufmgr;
648 atomic_set(&bo_gem->refcount, 1);
649 bo_gem->validate_index = -1;
650 bo_gem->reloc_tree_fences = 0;
651 bo_gem->used_as_reloc_target = 0;
652 bo_gem->has_error = 0;
653 bo_gem->tiling_mode = I915_TILING_NONE;
654 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
655 bo_gem->reusable = 1;
657 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
659 DBG("bo_create: buf %d (%s) %ldb\n",
660 bo_gem->gem_handle, bo_gem->name, size);
665 static drm_intel_bo *
666 drm_intel_gem_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
669 unsigned int alignment)
671 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size,
672 BO_ALLOC_FOR_RENDER);
675 static drm_intel_bo *
676 drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr,
679 unsigned int alignment)
681 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, 0);
684 static drm_intel_bo *
685 drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
686 int x, int y, int cpp, uint32_t *tiling_mode,
687 unsigned long *pitch, unsigned long flags)
689 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
691 unsigned long size, stride;
696 unsigned long aligned_y;
698 tiling = *tiling_mode;
700 /* If we're tiled, our allocations are in 8 or 32-row blocks,
701 * so failure to align our height means that we won't allocate
704 * If we're untiled, we still have to align to 2 rows high
705 * because the data port accesses 2x2 blocks even if the
706 * bottom row isn't to be rendered, so failure to align means
707 * we could walk off the end of the GTT and fault. This is
708 * documented on 965, and may be the case on older chipsets
709 * too so we try to be careful.
712 if (tiling == I915_TILING_NONE)
713 aligned_y = ALIGN(y, 2);
714 else if (tiling == I915_TILING_X)
715 aligned_y = ALIGN(y, 8);
716 else if (tiling == I915_TILING_Y)
717 aligned_y = ALIGN(y, 32);
720 stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, tiling);
721 size = stride * aligned_y;
722 size = drm_intel_gem_bo_tile_size(bufmgr_gem, size, tiling_mode);
723 } while (*tiling_mode != tiling);
725 bo = drm_intel_gem_bo_alloc_internal(bufmgr, name, size, flags);
729 ret = drm_intel_gem_bo_set_tiling(bo, tiling_mode, stride);
731 drm_intel_gem_bo_unreference(bo);
741 * Returns a drm_intel_bo wrapping the given buffer object handle.
743 * This can be used when one application needs to pass a buffer object
747 drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
751 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
752 drm_intel_bo_gem *bo_gem;
754 struct drm_gem_open open_arg;
755 struct drm_i915_gem_get_tiling get_tiling;
757 bo_gem = calloc(1, sizeof(*bo_gem));
761 memset(&open_arg, 0, sizeof(open_arg));
762 open_arg.name = handle;
764 ret = ioctl(bufmgr_gem->fd,
767 } while (ret == -1 && errno == EINTR);
769 fprintf(stderr, "Couldn't reference %s handle 0x%08x: %s\n",
770 name, handle, strerror(errno));
774 bo_gem->bo.size = open_arg.size;
775 bo_gem->bo.offset = 0;
776 bo_gem->bo.virtual = NULL;
777 bo_gem->bo.bufmgr = bufmgr;
779 atomic_set(&bo_gem->refcount, 1);
780 bo_gem->validate_index = -1;
781 bo_gem->gem_handle = open_arg.handle;
782 bo_gem->global_name = handle;
783 bo_gem->reusable = 0;
785 memset(&get_tiling, 0, sizeof(get_tiling));
786 get_tiling.handle = bo_gem->gem_handle;
787 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_GET_TILING, &get_tiling);
789 drm_intel_gem_bo_unreference(&bo_gem->bo);
792 bo_gem->tiling_mode = get_tiling.tiling_mode;
793 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
794 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
796 DBG("bo_create_from_handle: %d (%s)\n", handle, bo_gem->name);
802 drm_intel_gem_bo_free(drm_intel_bo *bo)
804 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
805 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
806 struct drm_gem_close close;
809 if (bo_gem->mem_virtual)
810 munmap(bo_gem->mem_virtual, bo_gem->bo.size);
811 if (bo_gem->gtt_virtual)
812 munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
814 /* Close this object */
815 memset(&close, 0, sizeof(close));
816 close.handle = bo_gem->gem_handle;
817 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close);
820 "DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
821 bo_gem->gem_handle, bo_gem->name, strerror(errno));
826 /** Frees all cached buffers significantly older than @time. */
828 drm_intel_gem_cleanup_bo_cache(drm_intel_bufmgr_gem *bufmgr_gem, time_t time)
832 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
833 struct drm_intel_gem_bo_bucket *bucket =
834 &bufmgr_gem->cache_bucket[i];
836 while (!DRMLISTEMPTY(&bucket->head)) {
837 drm_intel_bo_gem *bo_gem;
839 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
840 bucket->head.next, head);
841 if (time - bo_gem->free_time <= 1)
844 DRMLISTDEL(&bo_gem->head);
846 drm_intel_gem_bo_free(&bo_gem->bo);
852 drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time)
854 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
855 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
856 struct drm_intel_gem_bo_bucket *bucket;
857 uint32_t tiling_mode;
860 /* Unreference all the target buffers */
861 for (i = 0; i < bo_gem->reloc_count; i++) {
862 if (bo_gem->reloc_target_info[i].bo != bo) {
863 drm_intel_gem_bo_unreference_locked_timed(bo_gem->
864 reloc_target_info[i].bo,
868 bo_gem->reloc_count = 0;
869 bo_gem->used_as_reloc_target = 0;
871 DBG("bo_unreference final: %d (%s)\n",
872 bo_gem->gem_handle, bo_gem->name);
874 /* release memory associated with this object */
875 if (bo_gem->reloc_target_info) {
876 free(bo_gem->reloc_target_info);
877 bo_gem->reloc_target_info = NULL;
879 if (bo_gem->relocs) {
880 free(bo_gem->relocs);
881 bo_gem->relocs = NULL;
884 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, bo->size);
885 /* Put the buffer into our internal cache for reuse if we can. */
886 tiling_mode = I915_TILING_NONE;
887 if (bufmgr_gem->bo_reuse && bo_gem->reusable && bucket != NULL &&
888 drm_intel_gem_bo_set_tiling(bo, &tiling_mode, 0) == 0 &&
889 drm_intel_gem_bo_madvise_internal(bufmgr_gem, bo_gem,
890 I915_MADV_DONTNEED)) {
891 bo_gem->free_time = time;
894 bo_gem->validate_index = -1;
896 DRMLISTADDTAIL(&bo_gem->head, &bucket->head);
898 drm_intel_gem_cleanup_bo_cache(bufmgr_gem, time);
900 drm_intel_gem_bo_free(bo);
904 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
907 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
909 assert(atomic_read(&bo_gem->refcount) > 0);
910 if (atomic_dec_and_test(&bo_gem->refcount))
911 drm_intel_gem_bo_unreference_final(bo, time);
914 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo)
916 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
918 assert(atomic_read(&bo_gem->refcount) > 0);
919 if (atomic_dec_and_test(&bo_gem->refcount)) {
920 drm_intel_bufmgr_gem *bufmgr_gem =
921 (drm_intel_bufmgr_gem *) bo->bufmgr;
922 struct timespec time;
924 clock_gettime(CLOCK_MONOTONIC, &time);
926 pthread_mutex_lock(&bufmgr_gem->lock);
927 drm_intel_gem_bo_unreference_final(bo, time.tv_sec);
928 pthread_mutex_unlock(&bufmgr_gem->lock);
932 static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable)
934 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
935 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
936 struct drm_i915_gem_set_domain set_domain;
939 pthread_mutex_lock(&bufmgr_gem->lock);
941 /* Allow recursive mapping. Mesa may recursively map buffers with
942 * nested display loops.
944 if (!bo_gem->mem_virtual) {
945 struct drm_i915_gem_mmap mmap_arg;
947 DBG("bo_map: %d (%s)\n", bo_gem->gem_handle, bo_gem->name);
949 memset(&mmap_arg, 0, sizeof(mmap_arg));
950 mmap_arg.handle = bo_gem->gem_handle;
952 mmap_arg.size = bo->size;
954 ret = ioctl(bufmgr_gem->fd,
955 DRM_IOCTL_I915_GEM_MMAP,
957 } while (ret == -1 && errno == EINTR);
961 "%s:%d: Error mapping buffer %d (%s): %s .\n",
962 __FILE__, __LINE__, bo_gem->gem_handle,
963 bo_gem->name, strerror(errno));
964 pthread_mutex_unlock(&bufmgr_gem->lock);
967 bo_gem->mem_virtual = (void *)(uintptr_t) mmap_arg.addr_ptr;
969 DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
970 bo_gem->mem_virtual);
971 bo->virtual = bo_gem->mem_virtual;
973 set_domain.handle = bo_gem->gem_handle;
974 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
976 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
978 set_domain.write_domain = 0;
980 ret = ioctl(bufmgr_gem->fd,
981 DRM_IOCTL_I915_GEM_SET_DOMAIN,
983 } while (ret == -1 && errno == EINTR);
986 fprintf(stderr, "%s:%d: Error setting to CPU domain %d: %s\n",
987 __FILE__, __LINE__, bo_gem->gem_handle,
989 pthread_mutex_unlock(&bufmgr_gem->lock);
993 pthread_mutex_unlock(&bufmgr_gem->lock);
998 int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
1000 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1001 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1002 struct drm_i915_gem_set_domain set_domain;
1005 pthread_mutex_lock(&bufmgr_gem->lock);
1007 /* Get a mapping of the buffer if we haven't before. */
1008 if (bo_gem->gtt_virtual == NULL) {
1009 struct drm_i915_gem_mmap_gtt mmap_arg;
1011 DBG("bo_map_gtt: mmap %d (%s)\n", bo_gem->gem_handle,
1014 memset(&mmap_arg, 0, sizeof(mmap_arg));
1015 mmap_arg.handle = bo_gem->gem_handle;
1017 /* Get the fake offset back... */
1019 ret = ioctl(bufmgr_gem->fd,
1020 DRM_IOCTL_I915_GEM_MMAP_GTT,
1022 } while (ret == -1 && errno == EINTR);
1026 "%s:%d: Error preparing buffer map %d (%s): %s .\n",
1028 bo_gem->gem_handle, bo_gem->name,
1030 pthread_mutex_unlock(&bufmgr_gem->lock);
1035 bo_gem->gtt_virtual = mmap(0, bo->size, PROT_READ | PROT_WRITE,
1036 MAP_SHARED, bufmgr_gem->fd,
1038 if (bo_gem->gtt_virtual == MAP_FAILED) {
1039 bo_gem->gtt_virtual = NULL;
1042 "%s:%d: Error mapping buffer %d (%s): %s .\n",
1044 bo_gem->gem_handle, bo_gem->name,
1046 pthread_mutex_unlock(&bufmgr_gem->lock);
1051 bo->virtual = bo_gem->gtt_virtual;
1053 DBG("bo_map_gtt: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1054 bo_gem->gtt_virtual);
1056 /* Now move it to the GTT domain so that the CPU caches are flushed */
1057 set_domain.handle = bo_gem->gem_handle;
1058 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1059 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
1061 ret = ioctl(bufmgr_gem->fd,
1062 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1064 } while (ret == -1 && errno == EINTR);
1068 fprintf(stderr, "%s:%d: Error setting domain %d: %s\n",
1069 __FILE__, __LINE__, bo_gem->gem_handle,
1073 pthread_mutex_unlock(&bufmgr_gem->lock);
1078 int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo)
1080 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1081 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1087 assert(bo_gem->gtt_virtual != NULL);
1089 pthread_mutex_lock(&bufmgr_gem->lock);
1091 pthread_mutex_unlock(&bufmgr_gem->lock);
1096 static int drm_intel_gem_bo_unmap(drm_intel_bo *bo)
1098 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1099 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1100 struct drm_i915_gem_sw_finish sw_finish;
1106 assert(bo_gem->mem_virtual != NULL);
1108 pthread_mutex_lock(&bufmgr_gem->lock);
1110 /* Cause a flush to happen if the buffer's pinned for scanout, so the
1111 * results show up in a timely manner.
1113 sw_finish.handle = bo_gem->gem_handle;
1115 ret = ioctl(bufmgr_gem->fd,
1116 DRM_IOCTL_I915_GEM_SW_FINISH,
1118 } while (ret == -1 && errno == EINTR);
1119 ret = ret == -1 ? -errno : 0;
1122 pthread_mutex_unlock(&bufmgr_gem->lock);
1128 drm_intel_gem_bo_subdata(drm_intel_bo *bo, unsigned long offset,
1129 unsigned long size, const void *data)
1131 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1132 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1133 struct drm_i915_gem_pwrite pwrite;
1136 memset(&pwrite, 0, sizeof(pwrite));
1137 pwrite.handle = bo_gem->gem_handle;
1138 pwrite.offset = offset;
1140 pwrite.data_ptr = (uint64_t) (uintptr_t) data;
1142 ret = ioctl(bufmgr_gem->fd,
1143 DRM_IOCTL_I915_GEM_PWRITE,
1145 } while (ret == -1 && errno == EINTR);
1149 "%s:%d: Error writing data to buffer %d: (%d %d) %s .\n",
1150 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1151 (int)size, strerror(errno));
1158 drm_intel_gem_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id)
1160 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1161 struct drm_i915_get_pipe_from_crtc_id get_pipe_from_crtc_id;
1164 get_pipe_from_crtc_id.crtc_id = crtc_id;
1165 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID,
1166 &get_pipe_from_crtc_id);
1168 /* We return -1 here to signal that we don't
1169 * know which pipe is associated with this crtc.
1170 * This lets the caller know that this information
1171 * isn't available; using the wrong pipe for
1172 * vblank waiting can cause the chipset to lock up
1177 return get_pipe_from_crtc_id.pipe;
1181 drm_intel_gem_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
1182 unsigned long size, void *data)
1184 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1185 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1186 struct drm_i915_gem_pread pread;
1189 memset(&pread, 0, sizeof(pread));
1190 pread.handle = bo_gem->gem_handle;
1191 pread.offset = offset;
1193 pread.data_ptr = (uint64_t) (uintptr_t) data;
1195 ret = ioctl(bufmgr_gem->fd,
1196 DRM_IOCTL_I915_GEM_PREAD,
1198 } while (ret == -1 && errno == EINTR);
1202 "%s:%d: Error reading data from buffer %d: (%d %d) %s .\n",
1203 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1204 (int)size, strerror(errno));
1210 /** Waits for all GPU rendering to the object to have completed. */
1212 drm_intel_gem_bo_wait_rendering(drm_intel_bo *bo)
1214 drm_intel_gem_bo_start_gtt_access(bo, 0);
1218 * Sets the object to the GTT read and possibly write domain, used by the X
1219 * 2D driver in the absence of kernel support to do drm_intel_gem_bo_map_gtt().
1221 * In combination with drm_intel_gem_bo_pin() and manual fence management, we
1222 * can do tiled pixmaps this way.
1225 drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable)
1227 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1228 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1229 struct drm_i915_gem_set_domain set_domain;
1232 set_domain.handle = bo_gem->gem_handle;
1233 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1234 set_domain.write_domain = write_enable ? I915_GEM_DOMAIN_GTT : 0;
1236 ret = ioctl(bufmgr_gem->fd,
1237 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1239 } while (ret == -1 && errno == EINTR);
1242 "%s:%d: Error setting memory domains %d (%08x %08x): %s .\n",
1243 __FILE__, __LINE__, bo_gem->gem_handle,
1244 set_domain.read_domains, set_domain.write_domain,
1250 drm_intel_bufmgr_gem_destroy(drm_intel_bufmgr *bufmgr)
1252 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1255 free(bufmgr_gem->exec2_objects);
1256 free(bufmgr_gem->exec_objects);
1257 free(bufmgr_gem->exec_bos);
1259 pthread_mutex_destroy(&bufmgr_gem->lock);
1261 /* Free any cached buffer objects we were going to reuse */
1262 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
1263 struct drm_intel_gem_bo_bucket *bucket =
1264 &bufmgr_gem->cache_bucket[i];
1265 drm_intel_bo_gem *bo_gem;
1267 while (!DRMLISTEMPTY(&bucket->head)) {
1268 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1269 bucket->head.next, head);
1270 DRMLISTDEL(&bo_gem->head);
1272 drm_intel_gem_bo_free(&bo_gem->bo);
1280 * Adds the target buffer to the validation list and adds the relocation
1281 * to the reloc_buffer's relocation list.
1283 * The relocation entry at the given offset must already contain the
1284 * precomputed relocation value, because the kernel will optimize out
1285 * the relocation entry write when the buffer hasn't moved from the
1286 * last known offset in target_bo.
1289 do_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1290 drm_intel_bo *target_bo, uint32_t target_offset,
1291 uint32_t read_domains, uint32_t write_domain,
1294 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1295 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1296 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
1298 if (bo_gem->has_error)
1301 if (target_bo_gem->has_error) {
1302 bo_gem->has_error = 1;
1306 if (target_bo_gem->tiling_mode == I915_TILING_NONE)
1309 /* We never use HW fences for rendering on 965+ */
1310 if (bufmgr_gem->gen >= 4)
1313 /* Create a new relocation list if needed */
1314 if (bo_gem->relocs == NULL && drm_intel_setup_reloc_list(bo))
1317 /* Check overflow */
1318 assert(bo_gem->reloc_count < bufmgr_gem->max_relocs);
1321 assert(offset <= bo->size - 4);
1322 assert((write_domain & (write_domain - 1)) == 0);
1324 /* Make sure that we're not adding a reloc to something whose size has
1325 * already been accounted for.
1327 assert(!bo_gem->used_as_reloc_target);
1328 if (target_bo_gem != bo_gem) {
1329 target_bo_gem->used_as_reloc_target = 1;
1330 bo_gem->reloc_tree_size += target_bo_gem->reloc_tree_size;
1332 /* An object needing a fence is a tiled buffer, so it won't have
1333 * relocs to other buffers.
1336 target_bo_gem->reloc_tree_fences = 1;
1337 bo_gem->reloc_tree_fences += target_bo_gem->reloc_tree_fences;
1339 /* Flag the target to disallow further relocations in it. */
1341 bo_gem->relocs[bo_gem->reloc_count].offset = offset;
1342 bo_gem->relocs[bo_gem->reloc_count].delta = target_offset;
1343 bo_gem->relocs[bo_gem->reloc_count].target_handle =
1344 target_bo_gem->gem_handle;
1345 bo_gem->relocs[bo_gem->reloc_count].read_domains = read_domains;
1346 bo_gem->relocs[bo_gem->reloc_count].write_domain = write_domain;
1347 bo_gem->relocs[bo_gem->reloc_count].presumed_offset = target_bo->offset;
1349 bo_gem->reloc_target_info[bo_gem->reloc_count].bo = target_bo;
1350 if (target_bo != bo)
1351 drm_intel_gem_bo_reference(target_bo);
1353 bo_gem->reloc_target_info[bo_gem->reloc_count].flags =
1354 DRM_INTEL_RELOC_FENCE;
1356 bo_gem->reloc_target_info[bo_gem->reloc_count].flags = 0;
1358 bo_gem->reloc_count++;
1364 drm_intel_gem_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1365 drm_intel_bo *target_bo, uint32_t target_offset,
1366 uint32_t read_domains, uint32_t write_domain)
1368 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1370 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1371 read_domains, write_domain,
1372 !bufmgr_gem->fenced_relocs);
1376 drm_intel_gem_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
1377 drm_intel_bo *target_bo,
1378 uint32_t target_offset,
1379 uint32_t read_domains, uint32_t write_domain)
1381 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1382 read_domains, write_domain, 1);
1386 * Walk the tree of relocations rooted at BO and accumulate the list of
1387 * validations to be performed and update the relocation buffers with
1388 * index values into the validation list.
1391 drm_intel_gem_bo_process_reloc(drm_intel_bo *bo)
1393 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1396 if (bo_gem->relocs == NULL)
1399 for (i = 0; i < bo_gem->reloc_count; i++) {
1400 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1402 if (target_bo == bo)
1405 /* Continue walking the tree depth-first. */
1406 drm_intel_gem_bo_process_reloc(target_bo);
1408 /* Add the target to the validate list */
1409 drm_intel_add_validate_buffer(target_bo);
1414 drm_intel_gem_bo_process_reloc2(drm_intel_bo *bo)
1416 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1419 if (bo_gem->relocs == NULL)
1422 for (i = 0; i < bo_gem->reloc_count; i++) {
1423 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1426 if (target_bo == bo)
1429 /* Continue walking the tree depth-first. */
1430 drm_intel_gem_bo_process_reloc2(target_bo);
1432 need_fence = (bo_gem->reloc_target_info[i].flags &
1433 DRM_INTEL_RELOC_FENCE);
1435 /* Add the target to the validate list */
1436 drm_intel_add_validate_buffer2(target_bo, need_fence);
1442 drm_intel_update_buffer_offsets(drm_intel_bufmgr_gem *bufmgr_gem)
1446 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1447 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1448 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1450 /* Update the buffer offset */
1451 if (bufmgr_gem->exec_objects[i].offset != bo->offset) {
1452 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1453 bo_gem->gem_handle, bo_gem->name, bo->offset,
1454 (unsigned long long)bufmgr_gem->exec_objects[i].
1456 bo->offset = bufmgr_gem->exec_objects[i].offset;
1462 drm_intel_update_buffer_offsets2 (drm_intel_bufmgr_gem *bufmgr_gem)
1466 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1467 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1468 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1470 /* Update the buffer offset */
1471 if (bufmgr_gem->exec2_objects[i].offset != bo->offset) {
1472 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1473 bo_gem->gem_handle, bo_gem->name, bo->offset,
1474 (unsigned long long)bufmgr_gem->exec2_objects[i].offset);
1475 bo->offset = bufmgr_gem->exec2_objects[i].offset;
1481 drm_intel_gem_bo_exec(drm_intel_bo *bo, int used,
1482 drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
1484 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1485 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1486 struct drm_i915_gem_execbuffer execbuf;
1489 if (bo_gem->has_error)
1492 pthread_mutex_lock(&bufmgr_gem->lock);
1493 /* Update indices and set up the validate list. */
1494 drm_intel_gem_bo_process_reloc(bo);
1496 /* Add the batch buffer to the validation list. There are no
1497 * relocations pointing to it.
1499 drm_intel_add_validate_buffer(bo);
1501 execbuf.buffers_ptr = (uintptr_t) bufmgr_gem->exec_objects;
1502 execbuf.buffer_count = bufmgr_gem->exec_count;
1503 execbuf.batch_start_offset = 0;
1504 execbuf.batch_len = used;
1505 execbuf.cliprects_ptr = (uintptr_t) cliprects;
1506 execbuf.num_cliprects = num_cliprects;
1511 ret = ioctl(bufmgr_gem->fd,
1512 DRM_IOCTL_I915_GEM_EXECBUFFER,
1514 } while (ret != 0 && errno == EINTR);
1518 if (errno == ENOSPC) {
1520 "Execbuffer fails to pin. "
1521 "Estimate: %u. Actual: %u. Available: %u\n",
1522 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
1525 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
1528 (unsigned int)bufmgr_gem->gtt_size);
1531 drm_intel_update_buffer_offsets(bufmgr_gem);
1533 if (bufmgr_gem->bufmgr.debug)
1534 drm_intel_gem_dump_validation_list(bufmgr_gem);
1536 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1537 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1538 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1540 /* Disconnect the buffer from the validate list */
1541 bo_gem->validate_index = -1;
1542 bufmgr_gem->exec_bos[i] = NULL;
1544 bufmgr_gem->exec_count = 0;
1545 pthread_mutex_unlock(&bufmgr_gem->lock);
1551 drm_intel_gem_bo_mrb_exec2(drm_intel_bo *bo, int used,
1552 drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
1555 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1556 struct drm_i915_gem_execbuffer2 execbuf;
1559 if ((ring_flag != I915_EXEC_RENDER) && (ring_flag != I915_EXEC_BSD))
1562 pthread_mutex_lock(&bufmgr_gem->lock);
1563 /* Update indices and set up the validate list. */
1564 drm_intel_gem_bo_process_reloc2(bo);
1566 /* Add the batch buffer to the validation list. There are no relocations
1569 drm_intel_add_validate_buffer2(bo, 0);
1571 execbuf.buffers_ptr = (uintptr_t)bufmgr_gem->exec2_objects;
1572 execbuf.buffer_count = bufmgr_gem->exec_count;
1573 execbuf.batch_start_offset = 0;
1574 execbuf.batch_len = used;
1575 execbuf.cliprects_ptr = (uintptr_t)cliprects;
1576 execbuf.num_cliprects = num_cliprects;
1579 execbuf.flags = ring_flag;
1584 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_EXECBUFFER2,
1586 } while (ret != 0 && errno == EINTR);
1590 if (ret == -ENOMEM) {
1592 "Execbuffer fails to pin. "
1593 "Estimate: %u. Actual: %u. Available: %u\n",
1594 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
1595 bufmgr_gem->exec_count),
1596 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
1597 bufmgr_gem->exec_count),
1598 (unsigned int) bufmgr_gem->gtt_size);
1601 drm_intel_update_buffer_offsets2(bufmgr_gem);
1603 if (bufmgr_gem->bufmgr.debug)
1604 drm_intel_gem_dump_validation_list(bufmgr_gem);
1606 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1607 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1608 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1610 /* Disconnect the buffer from the validate list */
1611 bo_gem->validate_index = -1;
1612 bufmgr_gem->exec_bos[i] = NULL;
1614 bufmgr_gem->exec_count = 0;
1615 pthread_mutex_unlock(&bufmgr_gem->lock);
1621 drm_intel_gem_bo_exec2(drm_intel_bo *bo, int used,
1622 drm_clip_rect_t *cliprects, int num_cliprects,
1625 return drm_intel_gem_bo_mrb_exec2(bo, used,
1626 cliprects, num_cliprects, DR4,
1631 drm_intel_gem_bo_pin(drm_intel_bo *bo, uint32_t alignment)
1633 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1634 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1635 struct drm_i915_gem_pin pin;
1638 memset(&pin, 0, sizeof(pin));
1639 pin.handle = bo_gem->gem_handle;
1640 pin.alignment = alignment;
1643 ret = ioctl(bufmgr_gem->fd,
1644 DRM_IOCTL_I915_GEM_PIN,
1646 } while (ret == -1 && errno == EINTR);
1651 bo->offset = pin.offset;
1656 drm_intel_gem_bo_unpin(drm_intel_bo *bo)
1658 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1659 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1660 struct drm_i915_gem_unpin unpin;
1663 memset(&unpin, 0, sizeof(unpin));
1664 unpin.handle = bo_gem->gem_handle;
1666 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_UNPIN, &unpin);
1674 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1677 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1678 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1679 struct drm_i915_gem_set_tiling set_tiling;
1682 if (bo_gem->global_name == 0 && *tiling_mode == bo_gem->tiling_mode)
1685 memset(&set_tiling, 0, sizeof(set_tiling));
1686 set_tiling.handle = bo_gem->gem_handle;
1689 set_tiling.tiling_mode = *tiling_mode;
1690 set_tiling.stride = stride;
1692 ret = ioctl(bufmgr_gem->fd,
1693 DRM_IOCTL_I915_GEM_SET_TILING,
1695 } while (ret == -1 && errno == EINTR);
1697 bo_gem->tiling_mode = set_tiling.tiling_mode;
1698 bo_gem->swizzle_mode = set_tiling.swizzle_mode;
1699 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
1703 *tiling_mode = bo_gem->tiling_mode;
1708 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1709 uint32_t * swizzle_mode)
1711 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1713 *tiling_mode = bo_gem->tiling_mode;
1714 *swizzle_mode = bo_gem->swizzle_mode;
1719 drm_intel_gem_bo_flink(drm_intel_bo *bo, uint32_t * name)
1721 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1722 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1723 struct drm_gem_flink flink;
1726 if (!bo_gem->global_name) {
1727 memset(&flink, 0, sizeof(flink));
1728 flink.handle = bo_gem->gem_handle;
1730 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_FLINK, &flink);
1733 bo_gem->global_name = flink.name;
1734 bo_gem->reusable = 0;
1737 *name = bo_gem->global_name;
1742 * Enables unlimited caching of buffer objects for reuse.
1744 * This is potentially very memory expensive, as the cache at each bucket
1745 * size is only bounded by how many buffers of that size we've managed to have
1746 * in flight at once.
1749 drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr)
1751 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1753 bufmgr_gem->bo_reuse = 1;
1757 * Enable use of fenced reloc type.
1759 * New code should enable this to avoid unnecessary fence register
1760 * allocation. If this option is not enabled, all relocs will have fence
1761 * register allocated.
1764 drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr)
1766 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
1768 if (bufmgr_gem->bufmgr.bo_exec == drm_intel_gem_bo_exec2)
1769 bufmgr_gem->fenced_relocs = 1;
1773 * Return the additional aperture space required by the tree of buffer objects
1777 drm_intel_gem_bo_get_aperture_space(drm_intel_bo *bo)
1779 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1783 if (bo == NULL || bo_gem->included_in_check_aperture)
1787 bo_gem->included_in_check_aperture = 1;
1789 for (i = 0; i < bo_gem->reloc_count; i++)
1791 drm_intel_gem_bo_get_aperture_space(bo_gem->
1792 reloc_target_info[i].bo);
1798 * Count the number of buffers in this list that need a fence reg
1800 * If the count is greater than the number of available regs, we'll have
1801 * to ask the caller to resubmit a batch with fewer tiled buffers.
1803 * This function over-counts if the same buffer is used multiple times.
1806 drm_intel_gem_total_fences(drm_intel_bo ** bo_array, int count)
1809 unsigned int total = 0;
1811 for (i = 0; i < count; i++) {
1812 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
1817 total += bo_gem->reloc_tree_fences;
1823 * Clear the flag set by drm_intel_gem_bo_get_aperture_space() so we're ready
1824 * for the next drm_intel_bufmgr_check_aperture_space() call.
1827 drm_intel_gem_bo_clear_aperture_space_flag(drm_intel_bo *bo)
1829 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1832 if (bo == NULL || !bo_gem->included_in_check_aperture)
1835 bo_gem->included_in_check_aperture = 0;
1837 for (i = 0; i < bo_gem->reloc_count; i++)
1838 drm_intel_gem_bo_clear_aperture_space_flag(bo_gem->
1839 reloc_target_info[i].bo);
1843 * Return a conservative estimate for the amount of aperture required
1844 * for a collection of buffers. This may double-count some buffers.
1847 drm_intel_gem_estimate_batch_space(drm_intel_bo **bo_array, int count)
1850 unsigned int total = 0;
1852 for (i = 0; i < count; i++) {
1853 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
1855 total += bo_gem->reloc_tree_size;
1861 * Return the amount of aperture needed for a collection of buffers.
1862 * This avoids double counting any buffers, at the cost of looking
1863 * at every buffer in the set.
1866 drm_intel_gem_compute_batch_space(drm_intel_bo **bo_array, int count)
1869 unsigned int total = 0;
1871 for (i = 0; i < count; i++) {
1872 total += drm_intel_gem_bo_get_aperture_space(bo_array[i]);
1873 /* For the first buffer object in the array, we get an
1874 * accurate count back for its reloc_tree size (since nothing
1875 * had been flagged as being counted yet). We can save that
1876 * value out as a more conservative reloc_tree_size that
1877 * avoids double-counting target buffers. Since the first
1878 * buffer happens to usually be the batch buffer in our
1879 * callers, this can pull us back from doing the tree
1880 * walk on every new batch emit.
1883 drm_intel_bo_gem *bo_gem =
1884 (drm_intel_bo_gem *) bo_array[i];
1885 bo_gem->reloc_tree_size = total;
1889 for (i = 0; i < count; i++)
1890 drm_intel_gem_bo_clear_aperture_space_flag(bo_array[i]);
1895 * Return -1 if the batchbuffer should be flushed before attempting to
1896 * emit rendering referencing the buffers pointed to by bo_array.
1898 * This is required because if we try to emit a batchbuffer with relocations
1899 * to a tree of buffers that won't simultaneously fit in the aperture,
1900 * the rendering will return an error at a point where the software is not
1901 * prepared to recover from it.
1903 * However, we also want to emit the batchbuffer significantly before we reach
1904 * the limit, as a series of batchbuffers each of which references buffers
1905 * covering almost all of the aperture means that at each emit we end up
1906 * waiting to evict a buffer from the last rendering, and we get synchronous
1907 * performance. By emitting smaller batchbuffers, we eat some CPU overhead to
1908 * get better parallelism.
1911 drm_intel_gem_check_aperture_space(drm_intel_bo **bo_array, int count)
1913 drm_intel_bufmgr_gem *bufmgr_gem =
1914 (drm_intel_bufmgr_gem *) bo_array[0]->bufmgr;
1915 unsigned int total = 0;
1916 unsigned int threshold = bufmgr_gem->gtt_size * 3 / 4;
1919 /* Check for fence reg constraints if necessary */
1920 if (bufmgr_gem->available_fences) {
1921 total_fences = drm_intel_gem_total_fences(bo_array, count);
1922 if (total_fences > bufmgr_gem->available_fences)
1926 total = drm_intel_gem_estimate_batch_space(bo_array, count);
1928 if (total > threshold)
1929 total = drm_intel_gem_compute_batch_space(bo_array, count);
1931 if (total > threshold) {
1932 DBG("check_space: overflowed available aperture, "
1934 total / 1024, (int)bufmgr_gem->gtt_size / 1024);
1937 DBG("drm_check_space: total %dkb vs bufgr %dkb\n", total / 1024,
1938 (int)bufmgr_gem->gtt_size / 1024);
1944 * Disable buffer reuse for objects which are shared with the kernel
1945 * as scanout buffers
1948 drm_intel_gem_bo_disable_reuse(drm_intel_bo *bo)
1950 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1952 bo_gem->reusable = 0;
1957 drm_intel_gem_bo_is_reusable(drm_intel_bo *bo)
1959 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1961 return bo_gem->reusable;
1965 _drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
1967 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1970 for (i = 0; i < bo_gem->reloc_count; i++) {
1971 if (bo_gem->reloc_target_info[i].bo == target_bo)
1973 if (bo == bo_gem->reloc_target_info[i].bo)
1975 if (_drm_intel_gem_bo_references(bo_gem->reloc_target_info[i].bo,
1983 /** Return true if target_bo is referenced by bo's relocation tree. */
1985 drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
1987 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
1989 if (bo == NULL || target_bo == NULL)
1991 if (target_bo_gem->used_as_reloc_target)
1992 return _drm_intel_gem_bo_references(bo, target_bo);
1997 add_bucket(drm_intel_bufmgr_gem *bufmgr_gem, int size)
1999 unsigned int i = bufmgr_gem->num_buckets;
2001 assert(i < ARRAY_SIZE(bufmgr_gem->cache_bucket));
2003 DRMINITLISTHEAD(&bufmgr_gem->cache_bucket[i].head);
2004 bufmgr_gem->cache_bucket[i].size = size;
2005 bufmgr_gem->num_buckets++;
2009 init_cache_buckets(drm_intel_bufmgr_gem *bufmgr_gem)
2011 unsigned long size, cache_max_size = 64 * 1024 * 1024;
2013 /* OK, so power of two buckets was too wasteful of memory.
2014 * Give 3 other sizes between each power of two, to hopefully
2015 * cover things accurately enough. (The alternative is
2016 * probably to just go for exact matching of sizes, and assume
2017 * that for things like composited window resize the tiled
2018 * width/height alignment and rounding of sizes to pages will
2019 * get us useful cache hit rates anyway)
2021 add_bucket(bufmgr_gem, 4096);
2022 add_bucket(bufmgr_gem, 4096 * 2);
2023 add_bucket(bufmgr_gem, 4096 * 3);
2025 /* Initialize the linked lists for BO reuse cache. */
2026 for (size = 4 * 4096; size <= cache_max_size; size *= 2) {
2027 add_bucket(bufmgr_gem, size);
2029 add_bucket(bufmgr_gem, size + size * 1 / 4);
2030 add_bucket(bufmgr_gem, size + size * 2 / 4);
2031 add_bucket(bufmgr_gem, size + size * 3 / 4);
2036 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
2037 * and manage map buffer objections.
2039 * \param fd File descriptor of the opened DRM device.
2042 drm_intel_bufmgr_gem_init(int fd, int batch_size)
2044 drm_intel_bufmgr_gem *bufmgr_gem;
2045 struct drm_i915_gem_get_aperture aperture;
2046 drm_i915_getparam_t gp;
2048 int exec2 = 0, has_bsd = 0;
2050 bufmgr_gem = calloc(1, sizeof(*bufmgr_gem));
2051 if (bufmgr_gem == NULL)
2054 bufmgr_gem->fd = fd;
2056 if (pthread_mutex_init(&bufmgr_gem->lock, NULL) != 0) {
2061 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
2064 bufmgr_gem->gtt_size = aperture.aper_available_size;
2066 fprintf(stderr, "DRM_IOCTL_I915_GEM_APERTURE failed: %s\n",
2068 bufmgr_gem->gtt_size = 128 * 1024 * 1024;
2069 fprintf(stderr, "Assuming %dkB available aperture size.\n"
2070 "May lead to reduced performance or incorrect "
2072 (int)bufmgr_gem->gtt_size / 1024);
2075 gp.param = I915_PARAM_CHIPSET_ID;
2076 gp.value = &bufmgr_gem->pci_device;
2077 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2079 fprintf(stderr, "get chip id failed: %d [%d]\n", ret, errno);
2080 fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value);
2083 if (IS_GEN2(bufmgr_gem))
2084 bufmgr_gem->gen = 2;
2085 else if (IS_GEN3(bufmgr_gem))
2086 bufmgr_gem->gen = 3;
2087 else if (IS_GEN4(bufmgr_gem))
2088 bufmgr_gem->gen = 4;
2090 bufmgr_gem->gen = 6;
2092 gp.param = I915_PARAM_HAS_EXECBUF2;
2093 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2097 gp.param = I915_PARAM_HAS_BSD;
2098 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2102 if (bufmgr_gem->gen < 4) {
2103 gp.param = I915_PARAM_NUM_FENCES_AVAIL;
2104 gp.value = &bufmgr_gem->available_fences;
2105 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2107 fprintf(stderr, "get fences failed: %d [%d]\n", ret,
2109 fprintf(stderr, "param: %d, val: %d\n", gp.param,
2111 bufmgr_gem->available_fences = 0;
2113 /* XXX The kernel reports the total number of fences,
2114 * including any that may be pinned.
2116 * We presume that there will be at least one pinned
2117 * fence for the scanout buffer, but there may be more
2118 * than one scanout and the user may be manually
2119 * pinning buffers. Let's move to execbuffer2 and
2120 * thereby forget the insanity of using fences...
2122 bufmgr_gem->available_fences -= 2;
2123 if (bufmgr_gem->available_fences < 0)
2124 bufmgr_gem->available_fences = 0;
2128 /* Let's go with one relocation per every 2 dwords (but round down a bit
2129 * since a power of two will mean an extra page allocation for the reloc
2132 * Every 4 was too few for the blender benchmark.
2134 bufmgr_gem->max_relocs = batch_size / sizeof(uint32_t) / 2 - 2;
2136 bufmgr_gem->bufmgr.bo_alloc = drm_intel_gem_bo_alloc;
2137 bufmgr_gem->bufmgr.bo_alloc_for_render =
2138 drm_intel_gem_bo_alloc_for_render;
2139 bufmgr_gem->bufmgr.bo_alloc_tiled = drm_intel_gem_bo_alloc_tiled;
2140 bufmgr_gem->bufmgr.bo_reference = drm_intel_gem_bo_reference;
2141 bufmgr_gem->bufmgr.bo_unreference = drm_intel_gem_bo_unreference;
2142 bufmgr_gem->bufmgr.bo_map = drm_intel_gem_bo_map;
2143 bufmgr_gem->bufmgr.bo_unmap = drm_intel_gem_bo_unmap;
2144 bufmgr_gem->bufmgr.bo_subdata = drm_intel_gem_bo_subdata;
2145 bufmgr_gem->bufmgr.bo_get_subdata = drm_intel_gem_bo_get_subdata;
2146 bufmgr_gem->bufmgr.bo_wait_rendering = drm_intel_gem_bo_wait_rendering;
2147 bufmgr_gem->bufmgr.bo_emit_reloc = drm_intel_gem_bo_emit_reloc;
2148 bufmgr_gem->bufmgr.bo_emit_reloc_fence = drm_intel_gem_bo_emit_reloc_fence;
2149 bufmgr_gem->bufmgr.bo_pin = drm_intel_gem_bo_pin;
2150 bufmgr_gem->bufmgr.bo_unpin = drm_intel_gem_bo_unpin;
2151 bufmgr_gem->bufmgr.bo_get_tiling = drm_intel_gem_bo_get_tiling;
2152 bufmgr_gem->bufmgr.bo_set_tiling = drm_intel_gem_bo_set_tiling;
2153 bufmgr_gem->bufmgr.bo_flink = drm_intel_gem_bo_flink;
2154 /* Use the new one if available */
2156 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec2;
2158 bufmgr_gem->bufmgr.bo_mrb_exec = drm_intel_gem_bo_mrb_exec2;
2160 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec;
2161 bufmgr_gem->bufmgr.bo_busy = drm_intel_gem_bo_busy;
2162 bufmgr_gem->bufmgr.bo_madvise = drm_intel_gem_bo_madvise;
2163 bufmgr_gem->bufmgr.destroy = drm_intel_bufmgr_gem_destroy;
2164 bufmgr_gem->bufmgr.debug = 0;
2165 bufmgr_gem->bufmgr.check_aperture_space =
2166 drm_intel_gem_check_aperture_space;
2167 bufmgr_gem->bufmgr.bo_disable_reuse = drm_intel_gem_bo_disable_reuse;
2168 bufmgr_gem->bufmgr.bo_is_reusable = drm_intel_gem_bo_is_reusable;
2169 bufmgr_gem->bufmgr.get_pipe_from_crtc_id =
2170 drm_intel_gem_get_pipe_from_crtc_id;
2171 bufmgr_gem->bufmgr.bo_references = drm_intel_gem_bo_references;
2173 init_cache_buckets(bufmgr_gem);
2175 return &bufmgr_gem->bufmgr;