1 /**************************************************************************
3 * Copyright © 2007 Red Hat Inc.
4 * Copyright © 2007 Intel Corporation
5 * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
29 **************************************************************************/
31 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
32 * Keith Whitwell <keithw-at-tungstengraphics-dot-com>
33 * Eric Anholt <eric@anholt.net>
34 * Dave Airlie <airlied@linux.ie>
42 #include <xf86atomic.h>
50 #include <sys/ioctl.h>
53 #include <sys/types.h>
56 #include "libdrm_lists.h"
57 #include "intel_bufmgr.h"
58 #include "intel_bufmgr_priv.h"
59 #include "intel_chipset.h"
64 #define DBG(...) do { \
65 if (bufmgr_gem->bufmgr.debug) \
66 fprintf(stderr, __VA_ARGS__); \
69 typedef struct _drm_intel_bo_gem drm_intel_bo_gem;
71 struct drm_intel_gem_bo_bucket {
76 /* Only cache objects up to 64MB. Bigger than that, and the rounding of the
77 * size makes many operations fail that wouldn't otherwise.
79 #define DRM_INTEL_GEM_BO_BUCKETS 14
80 typedef struct _drm_intel_bufmgr_gem {
81 drm_intel_bufmgr bufmgr;
89 struct drm_i915_gem_exec_object *exec_objects;
90 struct drm_i915_gem_exec_object2 *exec2_objects;
91 drm_intel_bo **exec_bos;
95 /** Array of lists of cached gem objects of power-of-two sizes */
96 struct drm_intel_gem_bo_bucket cache_bucket[DRM_INTEL_GEM_BO_BUCKETS];
104 } drm_intel_bufmgr_gem;
106 #define DRM_INTEL_RELOC_FENCE (1<<0)
108 typedef struct _drm_intel_reloc_target_info {
111 } drm_intel_reloc_target;
113 struct _drm_intel_bo_gem {
121 * Kenel-assigned global name for this object
123 unsigned int global_name;
126 * Index of the buffer within the validation list while preparing a
127 * batchbuffer execution.
132 * Current tiling mode
134 uint32_t tiling_mode;
135 uint32_t swizzle_mode;
139 /** Array passed to the DRM containing relocation information. */
140 struct drm_i915_gem_relocation_entry *relocs;
142 * Array of info structs corresponding to relocs[i].target_handle etc
144 drm_intel_reloc_target *reloc_target_info;
145 /** Number of entries in relocs */
147 /** Mapped address for the buffer, saved across map/unmap cycles */
149 /** GTT virtual address for the buffer, saved across map/unmap cycles */
156 * Boolean of whether this BO and its children have been included in
157 * the current drm_intel_bufmgr_check_aperture_space() total.
159 char included_in_check_aperture;
162 * Boolean of whether this buffer has been used as a relocation
163 * target and had its size accounted for, and thus can't have any
164 * further relocations added to it.
166 char used_as_reloc_target;
169 * Boolean of whether we have encountered an error whilst building the relocation tree.
174 * Boolean of whether this buffer can be re-used
179 * Size in bytes of this buffer and its relocation descendents.
181 * Used to avoid costly tree walking in
182 * drm_intel_bufmgr_check_aperture in the common case.
187 * Number of potential fence registers required by this buffer and its
190 int reloc_tree_fences;
194 drm_intel_gem_estimate_batch_space(drm_intel_bo ** bo_array, int count);
197 drm_intel_gem_compute_batch_space(drm_intel_bo ** bo_array, int count);
200 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
201 uint32_t * swizzle_mode);
204 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
207 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
210 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo);
212 static void drm_intel_gem_bo_free(drm_intel_bo *bo);
215 drm_intel_gem_bo_tile_size(drm_intel_bufmgr_gem *bufmgr_gem, unsigned long size,
216 uint32_t *tiling_mode)
218 unsigned long min_size, max_size;
221 if (*tiling_mode == I915_TILING_NONE)
224 /* 965+ just need multiples of page size for tiling */
225 if (bufmgr_gem->gen >= 4)
226 return ROUND_UP_TO(size, 4096);
228 /* Older chips need powers of two, of at least 512k or 1M */
229 if (bufmgr_gem->gen == 3) {
230 min_size = 1024*1024;
231 max_size = 128*1024*1024;
234 max_size = 64*1024*1024;
237 if (size > max_size) {
238 *tiling_mode = I915_TILING_NONE;
242 for (i = min_size; i < size; i <<= 1)
249 * Round a given pitch up to the minimum required for X tiling on a
250 * given chip. We use 512 as the minimum to allow for a later tiling
254 drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem,
255 unsigned long pitch, uint32_t tiling_mode)
257 unsigned long tile_width;
260 /* If untiled, then just align it so that we can do rendering
261 * to it with the 3D engine.
263 if (tiling_mode == I915_TILING_NONE)
264 return ALIGN(pitch, 64);
266 if (tiling_mode == I915_TILING_X)
271 /* 965 is flexible */
272 if (bufmgr_gem->gen >= 4)
273 return ROUND_UP_TO(pitch, tile_width);
275 /* Pre-965 needs power of two tile width */
276 for (i = tile_width; i < pitch; i <<= 1)
282 static struct drm_intel_gem_bo_bucket *
283 drm_intel_gem_bo_bucket_for_size(drm_intel_bufmgr_gem *bufmgr_gem,
288 for (i = 0; i < DRM_INTEL_GEM_BO_BUCKETS; i++) {
289 struct drm_intel_gem_bo_bucket *bucket =
290 &bufmgr_gem->cache_bucket[i];
291 if (bucket->size >= size) {
300 drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem *bufmgr_gem)
304 for (i = 0; i < bufmgr_gem->exec_count; i++) {
305 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
306 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
308 if (bo_gem->relocs == NULL) {
309 DBG("%2d: %d (%s)\n", i, bo_gem->gem_handle,
314 for (j = 0; j < bo_gem->reloc_count; j++) {
315 drm_intel_bo *target_bo = bo_gem->reloc_target_info[j].bo;
316 drm_intel_bo_gem *target_gem =
317 (drm_intel_bo_gem *) target_bo;
319 DBG("%2d: %d (%s)@0x%08llx -> "
320 "%d (%s)@0x%08lx + 0x%08x\n",
322 bo_gem->gem_handle, bo_gem->name,
323 (unsigned long long)bo_gem->relocs[j].offset,
324 target_gem->gem_handle,
327 bo_gem->relocs[j].delta);
333 drm_intel_gem_bo_reference(drm_intel_bo *bo)
335 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
337 assert(atomic_read(&bo_gem->refcount) > 0);
338 atomic_inc(&bo_gem->refcount);
342 * Adds the given buffer to the list of buffers to be validated (moved into the
343 * appropriate memory type) with the next batch submission.
345 * If a buffer is validated multiple times in a batch submission, it ends up
346 * with the intersection of the memory type flags and the union of the
350 drm_intel_add_validate_buffer(drm_intel_bo *bo)
352 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
353 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
356 if (bo_gem->validate_index != -1)
359 /* Extend the array of validation entries as necessary. */
360 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
361 int new_size = bufmgr_gem->exec_size * 2;
366 bufmgr_gem->exec_objects =
367 realloc(bufmgr_gem->exec_objects,
368 sizeof(*bufmgr_gem->exec_objects) * new_size);
369 bufmgr_gem->exec_bos =
370 realloc(bufmgr_gem->exec_bos,
371 sizeof(*bufmgr_gem->exec_bos) * new_size);
372 bufmgr_gem->exec_size = new_size;
375 index = bufmgr_gem->exec_count;
376 bo_gem->validate_index = index;
377 /* Fill in array entry */
378 bufmgr_gem->exec_objects[index].handle = bo_gem->gem_handle;
379 bufmgr_gem->exec_objects[index].relocation_count = bo_gem->reloc_count;
380 bufmgr_gem->exec_objects[index].relocs_ptr = (uintptr_t) bo_gem->relocs;
381 bufmgr_gem->exec_objects[index].alignment = 0;
382 bufmgr_gem->exec_objects[index].offset = 0;
383 bufmgr_gem->exec_bos[index] = bo;
384 bufmgr_gem->exec_count++;
388 drm_intel_add_validate_buffer2(drm_intel_bo *bo, int need_fence)
390 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
391 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
394 if (bo_gem->validate_index != -1) {
396 bufmgr_gem->exec2_objects[bo_gem->validate_index].flags |=
397 EXEC_OBJECT_NEEDS_FENCE;
401 /* Extend the array of validation entries as necessary. */
402 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
403 int new_size = bufmgr_gem->exec_size * 2;
408 bufmgr_gem->exec2_objects =
409 realloc(bufmgr_gem->exec2_objects,
410 sizeof(*bufmgr_gem->exec2_objects) * new_size);
411 bufmgr_gem->exec_bos =
412 realloc(bufmgr_gem->exec_bos,
413 sizeof(*bufmgr_gem->exec_bos) * new_size);
414 bufmgr_gem->exec_size = new_size;
417 index = bufmgr_gem->exec_count;
418 bo_gem->validate_index = index;
419 /* Fill in array entry */
420 bufmgr_gem->exec2_objects[index].handle = bo_gem->gem_handle;
421 bufmgr_gem->exec2_objects[index].relocation_count = bo_gem->reloc_count;
422 bufmgr_gem->exec2_objects[index].relocs_ptr = (uintptr_t)bo_gem->relocs;
423 bufmgr_gem->exec2_objects[index].alignment = 0;
424 bufmgr_gem->exec2_objects[index].offset = 0;
425 bufmgr_gem->exec_bos[index] = bo;
426 bufmgr_gem->exec2_objects[index].flags = 0;
427 bufmgr_gem->exec2_objects[index].rsvd1 = 0;
428 bufmgr_gem->exec2_objects[index].rsvd2 = 0;
430 bufmgr_gem->exec2_objects[index].flags |=
431 EXEC_OBJECT_NEEDS_FENCE;
433 bufmgr_gem->exec_count++;
436 #define RELOC_BUF_SIZE(x) ((I915_RELOC_HEADER + x * I915_RELOC0_STRIDE) * \
440 drm_intel_bo_gem_set_in_aperture_size(drm_intel_bufmgr_gem *bufmgr_gem,
441 drm_intel_bo_gem *bo_gem)
445 assert(!bo_gem->used_as_reloc_target);
447 /* The older chipsets are far-less flexible in terms of tiling,
448 * and require tiled buffer to be size aligned in the aperture.
449 * This means that in the worst possible case we will need a hole
450 * twice as large as the object in order for it to fit into the
451 * aperture. Optimal packing is for wimps.
453 size = bo_gem->bo.size;
454 if (bufmgr_gem->gen < 4 && bo_gem->tiling_mode != I915_TILING_NONE)
457 bo_gem->reloc_tree_size = size;
461 drm_intel_setup_reloc_list(drm_intel_bo *bo)
463 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
464 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
465 unsigned int max_relocs = bufmgr_gem->max_relocs;
467 if (bo->size / 4 < max_relocs)
468 max_relocs = bo->size / 4;
470 bo_gem->relocs = malloc(max_relocs *
471 sizeof(struct drm_i915_gem_relocation_entry));
472 bo_gem->reloc_target_info = malloc(max_relocs *
473 sizeof(drm_intel_reloc_target));
474 if (bo_gem->relocs == NULL || bo_gem->reloc_target_info == NULL) {
475 bo_gem->has_error = 1;
477 free (bo_gem->relocs);
478 bo_gem->relocs = NULL;
480 free (bo_gem->reloc_target_info);
481 bo_gem->reloc_target_info = NULL;
490 drm_intel_gem_bo_busy(drm_intel_bo *bo)
492 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
493 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
494 struct drm_i915_gem_busy busy;
497 memset(&busy, 0, sizeof(busy));
498 busy.handle = bo_gem->gem_handle;
501 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_BUSY, &busy);
502 } while (ret == -1 && errno == EINTR);
504 return (ret == 0 && busy.busy);
508 drm_intel_gem_bo_madvise_internal(drm_intel_bufmgr_gem *bufmgr_gem,
509 drm_intel_bo_gem *bo_gem, int state)
511 struct drm_i915_gem_madvise madv;
513 madv.handle = bo_gem->gem_handle;
516 ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MADVISE, &madv);
518 return madv.retained;
522 drm_intel_gem_bo_madvise(drm_intel_bo *bo, int madv)
524 return drm_intel_gem_bo_madvise_internal
525 ((drm_intel_bufmgr_gem *) bo->bufmgr,
526 (drm_intel_bo_gem *) bo,
530 /* drop the oldest entries that have been purged by the kernel */
532 drm_intel_gem_bo_cache_purge_bucket(drm_intel_bufmgr_gem *bufmgr_gem,
533 struct drm_intel_gem_bo_bucket *bucket)
535 while (!DRMLISTEMPTY(&bucket->head)) {
536 drm_intel_bo_gem *bo_gem;
538 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
539 bucket->head.next, head);
540 if (drm_intel_gem_bo_madvise_internal
541 (bufmgr_gem, bo_gem, I915_MADV_DONTNEED))
544 DRMLISTDEL(&bo_gem->head);
545 drm_intel_gem_bo_free(&bo_gem->bo);
549 static drm_intel_bo *
550 drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr,
555 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
556 drm_intel_bo_gem *bo_gem;
557 unsigned int page_size = getpagesize();
559 struct drm_intel_gem_bo_bucket *bucket;
560 int alloc_from_cache;
561 unsigned long bo_size;
564 if (flags & BO_ALLOC_FOR_RENDER)
567 /* Round the allocated size up to a power of two number of pages. */
568 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, size);
570 /* If we don't have caching at this size, don't actually round the
573 if (bucket == NULL) {
575 if (bo_size < page_size)
578 bo_size = bucket->size;
581 pthread_mutex_lock(&bufmgr_gem->lock);
582 /* Get a buffer out of the cache if available */
584 alloc_from_cache = 0;
585 if (bucket != NULL && !DRMLISTEMPTY(&bucket->head)) {
587 /* Allocate new render-target BOs from the tail (MRU)
588 * of the list, as it will likely be hot in the GPU
589 * cache and in the aperture for us.
591 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
592 bucket->head.prev, head);
593 DRMLISTDEL(&bo_gem->head);
594 alloc_from_cache = 1;
596 /* For non-render-target BOs (where we're probably
597 * going to map it first thing in order to fill it
598 * with data), check if the last BO in the cache is
599 * unbusy, and only reuse in that case. Otherwise,
600 * allocating a new buffer is probably faster than
601 * waiting for the GPU to finish.
603 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
604 bucket->head.next, head);
605 if (!drm_intel_gem_bo_busy(&bo_gem->bo)) {
606 alloc_from_cache = 1;
607 DRMLISTDEL(&bo_gem->head);
611 if (alloc_from_cache) {
612 if (!drm_intel_gem_bo_madvise_internal
613 (bufmgr_gem, bo_gem, I915_MADV_WILLNEED)) {
614 drm_intel_gem_bo_free(&bo_gem->bo);
615 drm_intel_gem_bo_cache_purge_bucket(bufmgr_gem,
621 pthread_mutex_unlock(&bufmgr_gem->lock);
623 if (!alloc_from_cache) {
624 struct drm_i915_gem_create create;
626 bo_gem = calloc(1, sizeof(*bo_gem));
630 bo_gem->bo.size = bo_size;
631 memset(&create, 0, sizeof(create));
632 create.size = bo_size;
635 ret = ioctl(bufmgr_gem->fd,
636 DRM_IOCTL_I915_GEM_CREATE,
638 } while (ret == -1 && errno == EINTR);
639 bo_gem->gem_handle = create.handle;
640 bo_gem->bo.handle = bo_gem->gem_handle;
645 bo_gem->bo.bufmgr = bufmgr;
649 atomic_set(&bo_gem->refcount, 1);
650 bo_gem->validate_index = -1;
651 bo_gem->reloc_tree_fences = 0;
652 bo_gem->used_as_reloc_target = 0;
653 bo_gem->has_error = 0;
654 bo_gem->tiling_mode = I915_TILING_NONE;
655 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
656 bo_gem->reusable = 1;
658 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
660 DBG("bo_create: buf %d (%s) %ldb\n",
661 bo_gem->gem_handle, bo_gem->name, size);
666 static drm_intel_bo *
667 drm_intel_gem_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
670 unsigned int alignment)
672 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size,
673 BO_ALLOC_FOR_RENDER);
676 static drm_intel_bo *
677 drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr,
680 unsigned int alignment)
682 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, 0);
685 static drm_intel_bo *
686 drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
687 int x, int y, int cpp, uint32_t *tiling_mode,
688 unsigned long *pitch, unsigned long flags)
690 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
692 unsigned long size, stride, aligned_y = y;
695 /* If we're tiled, our allocations are in 8 or 32-row blocks,
696 * so failure to align our height means that we won't allocate
699 * If we're untiled, we still have to align to 2 rows high
700 * because the data port accesses 2x2 blocks even if the
701 * bottom row isn't to be rendered, so failure to align means
702 * we could walk off the end of the GTT and fault. This is
703 * documented on 965, and may be the case on older chipsets
704 * too so we try to be careful.
706 if (*tiling_mode == I915_TILING_NONE)
707 aligned_y = ALIGN(y, 2);
708 else if (*tiling_mode == I915_TILING_X)
709 aligned_y = ALIGN(y, 8);
710 else if (*tiling_mode == I915_TILING_Y)
711 aligned_y = ALIGN(y, 32);
714 stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, *tiling_mode);
715 size = stride * aligned_y;
716 size = drm_intel_gem_bo_tile_size(bufmgr_gem, size, tiling_mode);
718 bo = drm_intel_gem_bo_alloc_internal(bufmgr, name, size, flags);
722 ret = drm_intel_gem_bo_set_tiling(bo, tiling_mode, stride);
724 drm_intel_gem_bo_unreference(bo);
734 * Returns a drm_intel_bo wrapping the given buffer object handle.
736 * This can be used when one application needs to pass a buffer object
740 drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
744 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
745 drm_intel_bo_gem *bo_gem;
747 struct drm_gem_open open_arg;
748 struct drm_i915_gem_get_tiling get_tiling;
750 bo_gem = calloc(1, sizeof(*bo_gem));
754 memset(&open_arg, 0, sizeof(open_arg));
755 open_arg.name = handle;
757 ret = ioctl(bufmgr_gem->fd,
760 } while (ret == -1 && errno == EINTR);
762 fprintf(stderr, "Couldn't reference %s handle 0x%08x: %s\n",
763 name, handle, strerror(errno));
767 bo_gem->bo.size = open_arg.size;
768 bo_gem->bo.offset = 0;
769 bo_gem->bo.virtual = NULL;
770 bo_gem->bo.bufmgr = bufmgr;
772 atomic_set(&bo_gem->refcount, 1);
773 bo_gem->validate_index = -1;
774 bo_gem->gem_handle = open_arg.handle;
775 bo_gem->global_name = handle;
776 bo_gem->reusable = 0;
778 memset(&get_tiling, 0, sizeof(get_tiling));
779 get_tiling.handle = bo_gem->gem_handle;
780 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_GET_TILING, &get_tiling);
782 drm_intel_gem_bo_unreference(&bo_gem->bo);
785 bo_gem->tiling_mode = get_tiling.tiling_mode;
786 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
787 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
789 DBG("bo_create_from_handle: %d (%s)\n", handle, bo_gem->name);
795 drm_intel_gem_bo_free(drm_intel_bo *bo)
797 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
798 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
799 struct drm_gem_close close;
802 if (bo_gem->mem_virtual)
803 munmap(bo_gem->mem_virtual, bo_gem->bo.size);
804 if (bo_gem->gtt_virtual)
805 munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
807 /* Close this object */
808 memset(&close, 0, sizeof(close));
809 close.handle = bo_gem->gem_handle;
810 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close);
813 "DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
814 bo_gem->gem_handle, bo_gem->name, strerror(errno));
819 /** Frees all cached buffers significantly older than @time. */
821 drm_intel_gem_cleanup_bo_cache(drm_intel_bufmgr_gem *bufmgr_gem, time_t time)
825 for (i = 0; i < DRM_INTEL_GEM_BO_BUCKETS; i++) {
826 struct drm_intel_gem_bo_bucket *bucket =
827 &bufmgr_gem->cache_bucket[i];
829 while (!DRMLISTEMPTY(&bucket->head)) {
830 drm_intel_bo_gem *bo_gem;
832 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
833 bucket->head.next, head);
834 if (time - bo_gem->free_time <= 1)
837 DRMLISTDEL(&bo_gem->head);
839 drm_intel_gem_bo_free(&bo_gem->bo);
845 drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time)
847 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
848 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
849 struct drm_intel_gem_bo_bucket *bucket;
850 uint32_t tiling_mode;
853 /* Unreference all the target buffers */
854 for (i = 0; i < bo_gem->reloc_count; i++) {
855 drm_intel_gem_bo_unreference_locked_timed(bo_gem->
856 reloc_target_info[i].bo,
859 bo_gem->reloc_count = 0;
860 bo_gem->used_as_reloc_target = 0;
862 DBG("bo_unreference final: %d (%s)\n",
863 bo_gem->gem_handle, bo_gem->name);
865 /* release memory associated with this object */
866 if (bo_gem->reloc_target_info) {
867 free(bo_gem->reloc_target_info);
868 bo_gem->reloc_target_info = NULL;
870 if (bo_gem->relocs) {
871 free(bo_gem->relocs);
872 bo_gem->relocs = NULL;
875 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, bo->size);
876 /* Put the buffer into our internal cache for reuse if we can. */
877 tiling_mode = I915_TILING_NONE;
878 if (bufmgr_gem->bo_reuse && bo_gem->reusable && bucket != NULL &&
879 drm_intel_gem_bo_set_tiling(bo, &tiling_mode, 0) == 0 &&
880 drm_intel_gem_bo_madvise_internal(bufmgr_gem, bo_gem,
881 I915_MADV_DONTNEED)) {
882 bo_gem->free_time = time;
885 bo_gem->validate_index = -1;
887 DRMLISTADDTAIL(&bo_gem->head, &bucket->head);
889 drm_intel_gem_cleanup_bo_cache(bufmgr_gem, time);
891 drm_intel_gem_bo_free(bo);
895 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
898 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
900 assert(atomic_read(&bo_gem->refcount) > 0);
901 if (atomic_dec_and_test(&bo_gem->refcount))
902 drm_intel_gem_bo_unreference_final(bo, time);
905 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo)
907 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
909 assert(atomic_read(&bo_gem->refcount) > 0);
910 if (atomic_dec_and_test(&bo_gem->refcount)) {
911 drm_intel_bufmgr_gem *bufmgr_gem =
912 (drm_intel_bufmgr_gem *) bo->bufmgr;
913 struct timespec time;
915 clock_gettime(CLOCK_MONOTONIC, &time);
917 pthread_mutex_lock(&bufmgr_gem->lock);
918 drm_intel_gem_bo_unreference_final(bo, time.tv_sec);
919 pthread_mutex_unlock(&bufmgr_gem->lock);
923 static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable)
925 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
926 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
927 struct drm_i915_gem_set_domain set_domain;
930 /* Allow recursive mapping. Mesa may recursively map buffers with
931 * nested display loops.
933 if (!bo_gem->mem_virtual) {
934 struct drm_i915_gem_mmap mmap_arg;
936 DBG("bo_map: %d (%s)\n", bo_gem->gem_handle, bo_gem->name);
938 memset(&mmap_arg, 0, sizeof(mmap_arg));
939 mmap_arg.handle = bo_gem->gem_handle;
941 mmap_arg.size = bo->size;
943 ret = ioctl(bufmgr_gem->fd,
944 DRM_IOCTL_I915_GEM_MMAP,
946 } while (ret == -1 && errno == EINTR);
950 "%s:%d: Error mapping buffer %d (%s): %s .\n",
951 __FILE__, __LINE__, bo_gem->gem_handle,
952 bo_gem->name, strerror(errno));
955 bo_gem->mem_virtual = (void *)(uintptr_t) mmap_arg.addr_ptr;
957 DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
958 bo_gem->mem_virtual);
959 bo->virtual = bo_gem->mem_virtual;
961 set_domain.handle = bo_gem->gem_handle;
962 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
964 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
966 set_domain.write_domain = 0;
968 ret = ioctl(bufmgr_gem->fd,
969 DRM_IOCTL_I915_GEM_SET_DOMAIN,
971 } while (ret == -1 && errno == EINTR);
974 fprintf(stderr, "%s:%d: Error setting to CPU domain %d: %s\n",
975 __FILE__, __LINE__, bo_gem->gem_handle,
983 int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
985 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
986 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
987 struct drm_i915_gem_set_domain set_domain;
990 /* Get a mapping of the buffer if we haven't before. */
991 if (bo_gem->gtt_virtual == NULL) {
992 struct drm_i915_gem_mmap_gtt mmap_arg;
994 DBG("bo_map_gtt: mmap %d (%s)\n", bo_gem->gem_handle,
997 memset(&mmap_arg, 0, sizeof(mmap_arg));
998 mmap_arg.handle = bo_gem->gem_handle;
1000 /* Get the fake offset back... */
1002 ret = ioctl(bufmgr_gem->fd,
1003 DRM_IOCTL_I915_GEM_MMAP_GTT,
1005 } while (ret == -1 && errno == EINTR);
1009 "%s:%d: Error preparing buffer map %d (%s): %s .\n",
1011 bo_gem->gem_handle, bo_gem->name,
1017 bo_gem->gtt_virtual = mmap(0, bo->size, PROT_READ | PROT_WRITE,
1018 MAP_SHARED, bufmgr_gem->fd,
1020 if (bo_gem->gtt_virtual == MAP_FAILED) {
1021 bo_gem->gtt_virtual = NULL;
1024 "%s:%d: Error mapping buffer %d (%s): %s .\n",
1026 bo_gem->gem_handle, bo_gem->name,
1032 bo->virtual = bo_gem->gtt_virtual;
1034 DBG("bo_map_gtt: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1035 bo_gem->gtt_virtual);
1037 /* Now move it to the GTT domain so that the CPU caches are flushed */
1038 set_domain.handle = bo_gem->gem_handle;
1039 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1040 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
1042 ret = ioctl(bufmgr_gem->fd,
1043 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1045 } while (ret == -1 && errno == EINTR);
1049 fprintf(stderr, "%s:%d: Error setting domain %d: %s\n",
1050 __FILE__, __LINE__, bo_gem->gem_handle,
1057 int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo)
1059 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1060 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1066 assert(bo_gem->gtt_virtual != NULL);
1073 static int drm_intel_gem_bo_unmap(drm_intel_bo *bo)
1075 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1076 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1077 struct drm_i915_gem_sw_finish sw_finish;
1083 assert(bo_gem->mem_virtual != NULL);
1085 /* Cause a flush to happen if the buffer's pinned for scanout, so the
1086 * results show up in a timely manner.
1088 sw_finish.handle = bo_gem->gem_handle;
1090 ret = ioctl(bufmgr_gem->fd,
1091 DRM_IOCTL_I915_GEM_SW_FINISH,
1093 } while (ret == -1 && errno == EINTR);
1094 ret = ret == -1 ? -errno : 0;
1102 drm_intel_gem_bo_subdata(drm_intel_bo *bo, unsigned long offset,
1103 unsigned long size, const void *data)
1105 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1106 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1107 struct drm_i915_gem_pwrite pwrite;
1110 memset(&pwrite, 0, sizeof(pwrite));
1111 pwrite.handle = bo_gem->gem_handle;
1112 pwrite.offset = offset;
1114 pwrite.data_ptr = (uint64_t) (uintptr_t) data;
1116 ret = ioctl(bufmgr_gem->fd,
1117 DRM_IOCTL_I915_GEM_PWRITE,
1119 } while (ret == -1 && errno == EINTR);
1123 "%s:%d: Error writing data to buffer %d: (%d %d) %s .\n",
1124 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1125 (int)size, strerror(errno));
1132 drm_intel_gem_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id)
1134 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1135 struct drm_i915_get_pipe_from_crtc_id get_pipe_from_crtc_id;
1138 get_pipe_from_crtc_id.crtc_id = crtc_id;
1139 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID,
1140 &get_pipe_from_crtc_id);
1142 /* We return -1 here to signal that we don't
1143 * know which pipe is associated with this crtc.
1144 * This lets the caller know that this information
1145 * isn't available; using the wrong pipe for
1146 * vblank waiting can cause the chipset to lock up
1151 return get_pipe_from_crtc_id.pipe;
1155 drm_intel_gem_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
1156 unsigned long size, void *data)
1158 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1159 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1160 struct drm_i915_gem_pread pread;
1163 memset(&pread, 0, sizeof(pread));
1164 pread.handle = bo_gem->gem_handle;
1165 pread.offset = offset;
1167 pread.data_ptr = (uint64_t) (uintptr_t) data;
1169 ret = ioctl(bufmgr_gem->fd,
1170 DRM_IOCTL_I915_GEM_PREAD,
1172 } while (ret == -1 && errno == EINTR);
1176 "%s:%d: Error reading data from buffer %d: (%d %d) %s .\n",
1177 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1178 (int)size, strerror(errno));
1184 /** Waits for all GPU rendering to the object to have completed. */
1186 drm_intel_gem_bo_wait_rendering(drm_intel_bo *bo)
1188 drm_intel_gem_bo_start_gtt_access(bo, 0);
1192 * Sets the object to the GTT read and possibly write domain, used by the X
1193 * 2D driver in the absence of kernel support to do drm_intel_gem_bo_map_gtt().
1195 * In combination with drm_intel_gem_bo_pin() and manual fence management, we
1196 * can do tiled pixmaps this way.
1199 drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable)
1201 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1202 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1203 struct drm_i915_gem_set_domain set_domain;
1206 set_domain.handle = bo_gem->gem_handle;
1207 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1208 set_domain.write_domain = write_enable ? I915_GEM_DOMAIN_GTT : 0;
1210 ret = ioctl(bufmgr_gem->fd,
1211 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1213 } while (ret == -1 && errno == EINTR);
1216 "%s:%d: Error setting memory domains %d (%08x %08x): %s .\n",
1217 __FILE__, __LINE__, bo_gem->gem_handle,
1218 set_domain.read_domains, set_domain.write_domain,
1224 drm_intel_bufmgr_gem_destroy(drm_intel_bufmgr *bufmgr)
1226 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1229 free(bufmgr_gem->exec2_objects);
1230 free(bufmgr_gem->exec_objects);
1231 free(bufmgr_gem->exec_bos);
1233 pthread_mutex_destroy(&bufmgr_gem->lock);
1235 /* Free any cached buffer objects we were going to reuse */
1236 for (i = 0; i < DRM_INTEL_GEM_BO_BUCKETS; i++) {
1237 struct drm_intel_gem_bo_bucket *bucket =
1238 &bufmgr_gem->cache_bucket[i];
1239 drm_intel_bo_gem *bo_gem;
1241 while (!DRMLISTEMPTY(&bucket->head)) {
1242 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1243 bucket->head.next, head);
1244 DRMLISTDEL(&bo_gem->head);
1246 drm_intel_gem_bo_free(&bo_gem->bo);
1254 * Adds the target buffer to the validation list and adds the relocation
1255 * to the reloc_buffer's relocation list.
1257 * The relocation entry at the given offset must already contain the
1258 * precomputed relocation value, because the kernel will optimize out
1259 * the relocation entry write when the buffer hasn't moved from the
1260 * last known offset in target_bo.
1263 do_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1264 drm_intel_bo *target_bo, uint32_t target_offset,
1265 uint32_t read_domains, uint32_t write_domain,
1268 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1269 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1270 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
1272 if (bo_gem->has_error)
1275 if (target_bo_gem->has_error) {
1276 bo_gem->has_error = 1;
1280 if (target_bo_gem->tiling_mode == I915_TILING_NONE)
1283 /* We never use HW fences for rendering on 965+ */
1284 if (bufmgr_gem->gen >= 4)
1287 /* Create a new relocation list if needed */
1288 if (bo_gem->relocs == NULL && drm_intel_setup_reloc_list(bo))
1291 /* Check overflow */
1292 assert(bo_gem->reloc_count < bufmgr_gem->max_relocs);
1295 assert(offset <= bo->size - 4);
1296 assert((write_domain & (write_domain - 1)) == 0);
1298 /* Make sure that we're not adding a reloc to something whose size has
1299 * already been accounted for.
1301 assert(!bo_gem->used_as_reloc_target);
1302 bo_gem->reloc_tree_size += target_bo_gem->reloc_tree_size;
1303 /* An object needing a fence is a tiled buffer, so it won't have
1304 * relocs to other buffers.
1307 target_bo_gem->reloc_tree_fences = 1;
1308 bo_gem->reloc_tree_fences += target_bo_gem->reloc_tree_fences;
1310 /* Flag the target to disallow further relocations in it. */
1311 target_bo_gem->used_as_reloc_target = 1;
1313 bo_gem->relocs[bo_gem->reloc_count].offset = offset;
1314 bo_gem->relocs[bo_gem->reloc_count].delta = target_offset;
1315 bo_gem->relocs[bo_gem->reloc_count].target_handle =
1316 target_bo_gem->gem_handle;
1317 bo_gem->relocs[bo_gem->reloc_count].read_domains = read_domains;
1318 bo_gem->relocs[bo_gem->reloc_count].write_domain = write_domain;
1319 bo_gem->relocs[bo_gem->reloc_count].presumed_offset = target_bo->offset;
1321 bo_gem->reloc_target_info[bo_gem->reloc_count].bo = target_bo;
1322 drm_intel_gem_bo_reference(target_bo);
1324 bo_gem->reloc_target_info[bo_gem->reloc_count].flags =
1325 DRM_INTEL_RELOC_FENCE;
1327 bo_gem->reloc_target_info[bo_gem->reloc_count].flags = 0;
1329 bo_gem->reloc_count++;
1335 drm_intel_gem_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1336 drm_intel_bo *target_bo, uint32_t target_offset,
1337 uint32_t read_domains, uint32_t write_domain)
1339 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1341 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1342 read_domains, write_domain,
1343 !bufmgr_gem->fenced_relocs);
1347 drm_intel_gem_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
1348 drm_intel_bo *target_bo,
1349 uint32_t target_offset,
1350 uint32_t read_domains, uint32_t write_domain)
1352 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1353 read_domains, write_domain, 1);
1357 * Walk the tree of relocations rooted at BO and accumulate the list of
1358 * validations to be performed and update the relocation buffers with
1359 * index values into the validation list.
1362 drm_intel_gem_bo_process_reloc(drm_intel_bo *bo)
1364 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1367 if (bo_gem->relocs == NULL)
1370 for (i = 0; i < bo_gem->reloc_count; i++) {
1371 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1373 /* Continue walking the tree depth-first. */
1374 drm_intel_gem_bo_process_reloc(target_bo);
1376 /* Add the target to the validate list */
1377 drm_intel_add_validate_buffer(target_bo);
1382 drm_intel_gem_bo_process_reloc2(drm_intel_bo *bo)
1384 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1387 if (bo_gem->relocs == NULL)
1390 for (i = 0; i < bo_gem->reloc_count; i++) {
1391 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1394 /* Continue walking the tree depth-first. */
1395 drm_intel_gem_bo_process_reloc2(target_bo);
1397 need_fence = (bo_gem->reloc_target_info[i].flags &
1398 DRM_INTEL_RELOC_FENCE);
1400 /* Add the target to the validate list */
1401 drm_intel_add_validate_buffer2(target_bo, need_fence);
1407 drm_intel_update_buffer_offsets(drm_intel_bufmgr_gem *bufmgr_gem)
1411 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1412 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1413 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1415 /* Update the buffer offset */
1416 if (bufmgr_gem->exec_objects[i].offset != bo->offset) {
1417 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1418 bo_gem->gem_handle, bo_gem->name, bo->offset,
1419 (unsigned long long)bufmgr_gem->exec_objects[i].
1421 bo->offset = bufmgr_gem->exec_objects[i].offset;
1427 drm_intel_update_buffer_offsets2 (drm_intel_bufmgr_gem *bufmgr_gem)
1431 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1432 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1433 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1435 /* Update the buffer offset */
1436 if (bufmgr_gem->exec2_objects[i].offset != bo->offset) {
1437 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1438 bo_gem->gem_handle, bo_gem->name, bo->offset,
1439 (unsigned long long)bufmgr_gem->exec2_objects[i].offset);
1440 bo->offset = bufmgr_gem->exec2_objects[i].offset;
1446 drm_intel_gem_bo_exec(drm_intel_bo *bo, int used,
1447 drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
1449 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1450 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1451 struct drm_i915_gem_execbuffer execbuf;
1454 if (bo_gem->has_error)
1457 pthread_mutex_lock(&bufmgr_gem->lock);
1458 /* Update indices and set up the validate list. */
1459 drm_intel_gem_bo_process_reloc(bo);
1461 /* Add the batch buffer to the validation list. There are no
1462 * relocations pointing to it.
1464 drm_intel_add_validate_buffer(bo);
1466 execbuf.buffers_ptr = (uintptr_t) bufmgr_gem->exec_objects;
1467 execbuf.buffer_count = bufmgr_gem->exec_count;
1468 execbuf.batch_start_offset = 0;
1469 execbuf.batch_len = used;
1470 execbuf.cliprects_ptr = (uintptr_t) cliprects;
1471 execbuf.num_cliprects = num_cliprects;
1476 ret = ioctl(bufmgr_gem->fd,
1477 DRM_IOCTL_I915_GEM_EXECBUFFER,
1479 } while (ret != 0 && errno == EINTR);
1483 if (errno == ENOSPC) {
1485 "Execbuffer fails to pin. "
1486 "Estimate: %u. Actual: %u. Available: %u\n",
1487 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
1490 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
1493 (unsigned int)bufmgr_gem->gtt_size);
1496 drm_intel_update_buffer_offsets(bufmgr_gem);
1498 if (bufmgr_gem->bufmgr.debug)
1499 drm_intel_gem_dump_validation_list(bufmgr_gem);
1501 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1502 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1503 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1505 /* Disconnect the buffer from the validate list */
1506 bo_gem->validate_index = -1;
1507 bufmgr_gem->exec_bos[i] = NULL;
1509 bufmgr_gem->exec_count = 0;
1510 pthread_mutex_unlock(&bufmgr_gem->lock);
1516 drm_intel_gem_bo_exec2(drm_intel_bo *bo, int used,
1517 drm_clip_rect_t *cliprects, int num_cliprects,
1520 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1521 struct drm_i915_gem_execbuffer2 execbuf;
1524 pthread_mutex_lock(&bufmgr_gem->lock);
1525 /* Update indices and set up the validate list. */
1526 drm_intel_gem_bo_process_reloc2(bo);
1528 /* Add the batch buffer to the validation list. There are no relocations
1531 drm_intel_add_validate_buffer2(bo, 0);
1533 execbuf.buffers_ptr = (uintptr_t)bufmgr_gem->exec2_objects;
1534 execbuf.buffer_count = bufmgr_gem->exec_count;
1535 execbuf.batch_start_offset = 0;
1536 execbuf.batch_len = used;
1537 execbuf.cliprects_ptr = (uintptr_t)cliprects;
1538 execbuf.num_cliprects = num_cliprects;
1546 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_EXECBUFFER2,
1548 } while (ret != 0 && errno == EINTR);
1552 if (ret == -ENOMEM) {
1554 "Execbuffer fails to pin. "
1555 "Estimate: %u. Actual: %u. Available: %u\n",
1556 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
1557 bufmgr_gem->exec_count),
1558 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
1559 bufmgr_gem->exec_count),
1560 (unsigned int) bufmgr_gem->gtt_size);
1563 drm_intel_update_buffer_offsets2(bufmgr_gem);
1565 if (bufmgr_gem->bufmgr.debug)
1566 drm_intel_gem_dump_validation_list(bufmgr_gem);
1568 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1569 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1570 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1572 /* Disconnect the buffer from the validate list */
1573 bo_gem->validate_index = -1;
1574 bufmgr_gem->exec_bos[i] = NULL;
1576 bufmgr_gem->exec_count = 0;
1577 pthread_mutex_unlock(&bufmgr_gem->lock);
1583 drm_intel_gem_bo_pin(drm_intel_bo *bo, uint32_t alignment)
1585 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1586 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1587 struct drm_i915_gem_pin pin;
1590 memset(&pin, 0, sizeof(pin));
1591 pin.handle = bo_gem->gem_handle;
1592 pin.alignment = alignment;
1595 ret = ioctl(bufmgr_gem->fd,
1596 DRM_IOCTL_I915_GEM_PIN,
1598 } while (ret == -1 && errno == EINTR);
1603 bo->offset = pin.offset;
1608 drm_intel_gem_bo_unpin(drm_intel_bo *bo)
1610 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1611 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1612 struct drm_i915_gem_unpin unpin;
1615 memset(&unpin, 0, sizeof(unpin));
1616 unpin.handle = bo_gem->gem_handle;
1618 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_UNPIN, &unpin);
1626 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1629 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1630 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1631 struct drm_i915_gem_set_tiling set_tiling;
1634 if (bo_gem->global_name == 0 && *tiling_mode == bo_gem->tiling_mode)
1637 memset(&set_tiling, 0, sizeof(set_tiling));
1638 set_tiling.handle = bo_gem->gem_handle;
1641 set_tiling.tiling_mode = *tiling_mode;
1642 set_tiling.stride = stride;
1644 ret = ioctl(bufmgr_gem->fd,
1645 DRM_IOCTL_I915_GEM_SET_TILING,
1647 } while (ret == -1 && errno == EINTR);
1648 bo_gem->tiling_mode = set_tiling.tiling_mode;
1649 bo_gem->swizzle_mode = set_tiling.swizzle_mode;
1651 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
1653 *tiling_mode = bo_gem->tiling_mode;
1654 return ret == 0 ? 0 : -errno;
1658 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1659 uint32_t * swizzle_mode)
1661 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1663 *tiling_mode = bo_gem->tiling_mode;
1664 *swizzle_mode = bo_gem->swizzle_mode;
1669 drm_intel_gem_bo_flink(drm_intel_bo *bo, uint32_t * name)
1671 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1672 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1673 struct drm_gem_flink flink;
1676 if (!bo_gem->global_name) {
1677 memset(&flink, 0, sizeof(flink));
1678 flink.handle = bo_gem->gem_handle;
1680 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_FLINK, &flink);
1683 bo_gem->global_name = flink.name;
1684 bo_gem->reusable = 0;
1687 *name = bo_gem->global_name;
1692 * Enables unlimited caching of buffer objects for reuse.
1694 * This is potentially very memory expensive, as the cache at each bucket
1695 * size is only bounded by how many buffers of that size we've managed to have
1696 * in flight at once.
1699 drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr)
1701 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1703 bufmgr_gem->bo_reuse = 1;
1707 * Enable use of fenced reloc type.
1709 * New code should enable this to avoid unnecessary fence register
1710 * allocation. If this option is not enabled, all relocs will have fence
1711 * register allocated.
1714 drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr)
1716 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
1718 if (bufmgr_gem->bufmgr.bo_exec == drm_intel_gem_bo_exec2)
1719 bufmgr_gem->fenced_relocs = 1;
1723 * Return the additional aperture space required by the tree of buffer objects
1727 drm_intel_gem_bo_get_aperture_space(drm_intel_bo *bo)
1729 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1733 if (bo == NULL || bo_gem->included_in_check_aperture)
1737 bo_gem->included_in_check_aperture = 1;
1739 for (i = 0; i < bo_gem->reloc_count; i++)
1741 drm_intel_gem_bo_get_aperture_space(bo_gem->
1742 reloc_target_info[i].bo);
1748 * Count the number of buffers in this list that need a fence reg
1750 * If the count is greater than the number of available regs, we'll have
1751 * to ask the caller to resubmit a batch with fewer tiled buffers.
1753 * This function over-counts if the same buffer is used multiple times.
1756 drm_intel_gem_total_fences(drm_intel_bo ** bo_array, int count)
1759 unsigned int total = 0;
1761 for (i = 0; i < count; i++) {
1762 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
1767 total += bo_gem->reloc_tree_fences;
1773 * Clear the flag set by drm_intel_gem_bo_get_aperture_space() so we're ready
1774 * for the next drm_intel_bufmgr_check_aperture_space() call.
1777 drm_intel_gem_bo_clear_aperture_space_flag(drm_intel_bo *bo)
1779 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1782 if (bo == NULL || !bo_gem->included_in_check_aperture)
1785 bo_gem->included_in_check_aperture = 0;
1787 for (i = 0; i < bo_gem->reloc_count; i++)
1788 drm_intel_gem_bo_clear_aperture_space_flag(bo_gem->
1789 reloc_target_info[i].bo);
1793 * Return a conservative estimate for the amount of aperture required
1794 * for a collection of buffers. This may double-count some buffers.
1797 drm_intel_gem_estimate_batch_space(drm_intel_bo **bo_array, int count)
1800 unsigned int total = 0;
1802 for (i = 0; i < count; i++) {
1803 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
1805 total += bo_gem->reloc_tree_size;
1811 * Return the amount of aperture needed for a collection of buffers.
1812 * This avoids double counting any buffers, at the cost of looking
1813 * at every buffer in the set.
1816 drm_intel_gem_compute_batch_space(drm_intel_bo **bo_array, int count)
1819 unsigned int total = 0;
1821 for (i = 0; i < count; i++) {
1822 total += drm_intel_gem_bo_get_aperture_space(bo_array[i]);
1823 /* For the first buffer object in the array, we get an
1824 * accurate count back for its reloc_tree size (since nothing
1825 * had been flagged as being counted yet). We can save that
1826 * value out as a more conservative reloc_tree_size that
1827 * avoids double-counting target buffers. Since the first
1828 * buffer happens to usually be the batch buffer in our
1829 * callers, this can pull us back from doing the tree
1830 * walk on every new batch emit.
1833 drm_intel_bo_gem *bo_gem =
1834 (drm_intel_bo_gem *) bo_array[i];
1835 bo_gem->reloc_tree_size = total;
1839 for (i = 0; i < count; i++)
1840 drm_intel_gem_bo_clear_aperture_space_flag(bo_array[i]);
1845 * Return -1 if the batchbuffer should be flushed before attempting to
1846 * emit rendering referencing the buffers pointed to by bo_array.
1848 * This is required because if we try to emit a batchbuffer with relocations
1849 * to a tree of buffers that won't simultaneously fit in the aperture,
1850 * the rendering will return an error at a point where the software is not
1851 * prepared to recover from it.
1853 * However, we also want to emit the batchbuffer significantly before we reach
1854 * the limit, as a series of batchbuffers each of which references buffers
1855 * covering almost all of the aperture means that at each emit we end up
1856 * waiting to evict a buffer from the last rendering, and we get synchronous
1857 * performance. By emitting smaller batchbuffers, we eat some CPU overhead to
1858 * get better parallelism.
1861 drm_intel_gem_check_aperture_space(drm_intel_bo **bo_array, int count)
1863 drm_intel_bufmgr_gem *bufmgr_gem =
1864 (drm_intel_bufmgr_gem *) bo_array[0]->bufmgr;
1865 unsigned int total = 0;
1866 unsigned int threshold = bufmgr_gem->gtt_size * 3 / 4;
1869 /* Check for fence reg constraints if necessary */
1870 if (bufmgr_gem->available_fences) {
1871 total_fences = drm_intel_gem_total_fences(bo_array, count);
1872 if (total_fences > bufmgr_gem->available_fences)
1876 total = drm_intel_gem_estimate_batch_space(bo_array, count);
1878 if (total > threshold)
1879 total = drm_intel_gem_compute_batch_space(bo_array, count);
1881 if (total > threshold) {
1882 DBG("check_space: overflowed available aperture, "
1884 total / 1024, (int)bufmgr_gem->gtt_size / 1024);
1887 DBG("drm_check_space: total %dkb vs bufgr %dkb\n", total / 1024,
1888 (int)bufmgr_gem->gtt_size / 1024);
1894 * Disable buffer reuse for objects which are shared with the kernel
1895 * as scanout buffers
1898 drm_intel_gem_bo_disable_reuse(drm_intel_bo *bo)
1900 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1902 bo_gem->reusable = 0;
1907 _drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
1909 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1912 for (i = 0; i < bo_gem->reloc_count; i++) {
1913 if (bo_gem->reloc_target_info[i].bo == target_bo)
1915 if (_drm_intel_gem_bo_references(bo_gem->reloc_target_info[i].bo,
1923 /** Return true if target_bo is referenced by bo's relocation tree. */
1925 drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
1927 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
1929 if (bo == NULL || target_bo == NULL)
1931 if (target_bo_gem->used_as_reloc_target)
1932 return _drm_intel_gem_bo_references(bo, target_bo);
1937 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
1938 * and manage map buffer objections.
1940 * \param fd File descriptor of the opened DRM device.
1943 drm_intel_bufmgr_gem_init(int fd, int batch_size)
1945 drm_intel_bufmgr_gem *bufmgr_gem;
1946 struct drm_i915_gem_get_aperture aperture;
1947 drm_i915_getparam_t gp;
1952 bufmgr_gem = calloc(1, sizeof(*bufmgr_gem));
1953 if (bufmgr_gem == NULL)
1956 bufmgr_gem->fd = fd;
1958 if (pthread_mutex_init(&bufmgr_gem->lock, NULL) != 0) {
1963 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
1966 bufmgr_gem->gtt_size = aperture.aper_available_size;
1968 fprintf(stderr, "DRM_IOCTL_I915_GEM_APERTURE failed: %s\n",
1970 bufmgr_gem->gtt_size = 128 * 1024 * 1024;
1971 fprintf(stderr, "Assuming %dkB available aperture size.\n"
1972 "May lead to reduced performance or incorrect "
1974 (int)bufmgr_gem->gtt_size / 1024);
1977 gp.param = I915_PARAM_CHIPSET_ID;
1978 gp.value = &bufmgr_gem->pci_device;
1979 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
1981 fprintf(stderr, "get chip id failed: %d [%d]\n", ret, errno);
1982 fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value);
1985 if (IS_GEN2(bufmgr_gem))
1986 bufmgr_gem->gen = 2;
1987 else if (IS_GEN3(bufmgr_gem))
1988 bufmgr_gem->gen = 3;
1989 else if (IS_GEN4(bufmgr_gem))
1990 bufmgr_gem->gen = 4;
1992 bufmgr_gem->gen = 6;
1994 gp.param = I915_PARAM_HAS_EXECBUF2;
1995 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
1999 if (bufmgr_gem->gen < 4) {
2000 gp.param = I915_PARAM_NUM_FENCES_AVAIL;
2001 gp.value = &bufmgr_gem->available_fences;
2002 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2004 fprintf(stderr, "get fences failed: %d [%d]\n", ret,
2006 fprintf(stderr, "param: %d, val: %d\n", gp.param,
2008 bufmgr_gem->available_fences = 0;
2010 /* XXX The kernel reports the total number of fences,
2011 * including any that may be pinned.
2013 * We presume that there will be at least one pinned
2014 * fence for the scanout buffer, but there may be more
2015 * than one scanout and the user may be manually
2016 * pinning buffers. Let's move to execbuffer2 and
2017 * thereby forget the insanity of using fences...
2019 bufmgr_gem->available_fences -= 2;
2020 if (bufmgr_gem->available_fences < 0)
2021 bufmgr_gem->available_fences = 0;
2025 /* Let's go with one relocation per every 2 dwords (but round down a bit
2026 * since a power of two will mean an extra page allocation for the reloc
2029 * Every 4 was too few for the blender benchmark.
2031 bufmgr_gem->max_relocs = batch_size / sizeof(uint32_t) / 2 - 2;
2033 bufmgr_gem->bufmgr.bo_alloc = drm_intel_gem_bo_alloc;
2034 bufmgr_gem->bufmgr.bo_alloc_for_render =
2035 drm_intel_gem_bo_alloc_for_render;
2036 bufmgr_gem->bufmgr.bo_alloc_tiled = drm_intel_gem_bo_alloc_tiled;
2037 bufmgr_gem->bufmgr.bo_reference = drm_intel_gem_bo_reference;
2038 bufmgr_gem->bufmgr.bo_unreference = drm_intel_gem_bo_unreference;
2039 bufmgr_gem->bufmgr.bo_map = drm_intel_gem_bo_map;
2040 bufmgr_gem->bufmgr.bo_unmap = drm_intel_gem_bo_unmap;
2041 bufmgr_gem->bufmgr.bo_subdata = drm_intel_gem_bo_subdata;
2042 bufmgr_gem->bufmgr.bo_get_subdata = drm_intel_gem_bo_get_subdata;
2043 bufmgr_gem->bufmgr.bo_wait_rendering = drm_intel_gem_bo_wait_rendering;
2044 bufmgr_gem->bufmgr.bo_emit_reloc = drm_intel_gem_bo_emit_reloc;
2045 bufmgr_gem->bufmgr.bo_emit_reloc_fence = drm_intel_gem_bo_emit_reloc_fence;
2046 bufmgr_gem->bufmgr.bo_pin = drm_intel_gem_bo_pin;
2047 bufmgr_gem->bufmgr.bo_unpin = drm_intel_gem_bo_unpin;
2048 bufmgr_gem->bufmgr.bo_get_tiling = drm_intel_gem_bo_get_tiling;
2049 bufmgr_gem->bufmgr.bo_set_tiling = drm_intel_gem_bo_set_tiling;
2050 bufmgr_gem->bufmgr.bo_flink = drm_intel_gem_bo_flink;
2051 /* Use the new one if available */
2053 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec2;
2055 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec;
2056 bufmgr_gem->bufmgr.bo_busy = drm_intel_gem_bo_busy;
2057 bufmgr_gem->bufmgr.bo_madvise = drm_intel_gem_bo_madvise;
2058 bufmgr_gem->bufmgr.destroy = drm_intel_bufmgr_gem_destroy;
2059 bufmgr_gem->bufmgr.debug = 0;
2060 bufmgr_gem->bufmgr.check_aperture_space =
2061 drm_intel_gem_check_aperture_space;
2062 bufmgr_gem->bufmgr.bo_disable_reuse = drm_intel_gem_bo_disable_reuse;
2063 bufmgr_gem->bufmgr.get_pipe_from_crtc_id =
2064 drm_intel_gem_get_pipe_from_crtc_id;
2065 bufmgr_gem->bufmgr.bo_references = drm_intel_gem_bo_references;
2067 /* Initialize the linked lists for BO reuse cache. */
2068 for (i = 0, size = 4096; i < DRM_INTEL_GEM_BO_BUCKETS; i++, size *= 2) {
2069 DRMINITLISTHEAD(&bufmgr_gem->cache_bucket[i].head);
2070 bufmgr_gem->cache_bucket[i].size = size;
2073 return &bufmgr_gem->bufmgr;