1 /**************************************************************************
3 * Copyright © 2007 Red Hat Inc.
4 * Copyright © 2007 Intel Corporation
5 * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
29 **************************************************************************/
31 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
32 * Keith Whitwell <keithw-at-tungstengraphics-dot-com>
33 * Eric Anholt <eric@anholt.net>
34 * Dave Airlie <airlied@linux.ie>
42 #include <xf86atomic.h>
50 #include <sys/ioctl.h>
53 #include <sys/types.h>
56 #include "libdrm_lists.h"
57 #include "intel_bufmgr.h"
58 #include "intel_bufmgr_priv.h"
59 #include "intel_chipset.h"
64 #define DBG(...) do { \
65 if (bufmgr_gem->bufmgr.debug) \
66 fprintf(stderr, __VA_ARGS__); \
69 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
71 typedef struct _drm_intel_bo_gem drm_intel_bo_gem;
73 struct drm_intel_gem_bo_bucket {
78 typedef struct _drm_intel_bufmgr_gem {
79 drm_intel_bufmgr bufmgr;
87 struct drm_i915_gem_exec_object *exec_objects;
88 struct drm_i915_gem_exec_object2 *exec2_objects;
89 drm_intel_bo **exec_bos;
93 /** Array of lists of cached gem objects of power-of-two sizes */
94 struct drm_intel_gem_bo_bucket cache_bucket[14 * 4];
101 int available_fences;
104 unsigned int has_bsd : 1;
105 unsigned int has_blt : 1;
106 unsigned int has_relaxed_fencing : 1;
107 unsigned int bo_reuse : 1;
109 } drm_intel_bufmgr_gem;
111 #define DRM_INTEL_RELOC_FENCE (1<<0)
113 typedef struct _drm_intel_reloc_target_info {
116 } drm_intel_reloc_target;
118 struct _drm_intel_bo_gem {
126 * Kenel-assigned global name for this object
128 unsigned int global_name;
129 drmMMListHead name_list;
132 * Index of the buffer within the validation list while preparing a
133 * batchbuffer execution.
138 * Current tiling mode
140 uint32_t tiling_mode;
141 uint32_t swizzle_mode;
142 unsigned long stride;
146 /** Array passed to the DRM containing relocation information. */
147 struct drm_i915_gem_relocation_entry *relocs;
149 * Array of info structs corresponding to relocs[i].target_handle etc
151 drm_intel_reloc_target *reloc_target_info;
152 /** Number of entries in relocs */
154 /** Mapped address for the buffer, saved across map/unmap cycles */
156 /** GTT virtual address for the buffer, saved across map/unmap cycles */
163 * Boolean of whether this BO and its children have been included in
164 * the current drm_intel_bufmgr_check_aperture_space() total.
166 char included_in_check_aperture;
169 * Boolean of whether this buffer has been used as a relocation
170 * target and had its size accounted for, and thus can't have any
171 * further relocations added to it.
173 char used_as_reloc_target;
176 * Boolean of whether we have encountered an error whilst building the relocation tree.
181 * Boolean of whether this buffer can be re-used
186 * Size in bytes of this buffer and its relocation descendents.
188 * Used to avoid costly tree walking in
189 * drm_intel_bufmgr_check_aperture in the common case.
194 * Number of potential fence registers required by this buffer and its
197 int reloc_tree_fences;
201 drm_intel_gem_estimate_batch_space(drm_intel_bo ** bo_array, int count);
204 drm_intel_gem_compute_batch_space(drm_intel_bo ** bo_array, int count);
207 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
208 uint32_t * swizzle_mode);
211 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
212 uint32_t tiling_mode,
215 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
218 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo);
220 static void drm_intel_gem_bo_free(drm_intel_bo *bo);
223 drm_intel_gem_bo_tile_size(drm_intel_bufmgr_gem *bufmgr_gem, unsigned long size,
224 uint32_t *tiling_mode)
226 unsigned long min_size, max_size;
229 if (*tiling_mode == I915_TILING_NONE)
232 /* 965+ just need multiples of page size for tiling */
233 if (bufmgr_gem->gen >= 4)
234 return ROUND_UP_TO(size, 4096);
236 /* Older chips need powers of two, of at least 512k or 1M */
237 if (bufmgr_gem->gen == 3) {
238 min_size = 1024*1024;
239 max_size = 128*1024*1024;
242 max_size = 64*1024*1024;
245 if (size > max_size) {
246 *tiling_mode = I915_TILING_NONE;
250 /* Do we need to allocate every page for the fence? */
251 if (bufmgr_gem->has_relaxed_fencing)
252 return ROUND_UP_TO(size, 4096);
254 for (i = min_size; i < size; i <<= 1)
261 * Round a given pitch up to the minimum required for X tiling on a
262 * given chip. We use 512 as the minimum to allow for a later tiling
266 drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem,
267 unsigned long pitch, uint32_t *tiling_mode)
269 unsigned long tile_width;
272 /* If untiled, then just align it so that we can do rendering
273 * to it with the 3D engine.
275 if (*tiling_mode == I915_TILING_NONE)
276 return ALIGN(pitch, 64);
278 if (*tiling_mode == I915_TILING_X)
283 /* 965 is flexible */
284 if (bufmgr_gem->gen >= 4)
285 return ROUND_UP_TO(pitch, tile_width);
287 /* The older hardware has a maximum pitch of 8192 with tiled
288 * surfaces, so fallback to untiled if it's too large.
291 *tiling_mode = I915_TILING_NONE;
292 return ALIGN(pitch, 64);
295 /* Pre-965 needs power of two tile width */
296 for (i = tile_width; i < pitch; i <<= 1)
302 static struct drm_intel_gem_bo_bucket *
303 drm_intel_gem_bo_bucket_for_size(drm_intel_bufmgr_gem *bufmgr_gem,
308 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
309 struct drm_intel_gem_bo_bucket *bucket =
310 &bufmgr_gem->cache_bucket[i];
311 if (bucket->size >= size) {
320 drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem *bufmgr_gem)
324 for (i = 0; i < bufmgr_gem->exec_count; i++) {
325 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
326 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
328 if (bo_gem->relocs == NULL) {
329 DBG("%2d: %d (%s)\n", i, bo_gem->gem_handle,
334 for (j = 0; j < bo_gem->reloc_count; j++) {
335 drm_intel_bo *target_bo = bo_gem->reloc_target_info[j].bo;
336 drm_intel_bo_gem *target_gem =
337 (drm_intel_bo_gem *) target_bo;
339 DBG("%2d: %d (%s)@0x%08llx -> "
340 "%d (%s)@0x%08lx + 0x%08x\n",
342 bo_gem->gem_handle, bo_gem->name,
343 (unsigned long long)bo_gem->relocs[j].offset,
344 target_gem->gem_handle,
347 bo_gem->relocs[j].delta);
353 drm_intel_gem_bo_reference(drm_intel_bo *bo)
355 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
357 atomic_inc(&bo_gem->refcount);
361 * Adds the given buffer to the list of buffers to be validated (moved into the
362 * appropriate memory type) with the next batch submission.
364 * If a buffer is validated multiple times in a batch submission, it ends up
365 * with the intersection of the memory type flags and the union of the
369 drm_intel_add_validate_buffer(drm_intel_bo *bo)
371 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
372 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
375 if (bo_gem->validate_index != -1)
378 /* Extend the array of validation entries as necessary. */
379 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
380 int new_size = bufmgr_gem->exec_size * 2;
385 bufmgr_gem->exec_objects =
386 realloc(bufmgr_gem->exec_objects,
387 sizeof(*bufmgr_gem->exec_objects) * new_size);
388 bufmgr_gem->exec_bos =
389 realloc(bufmgr_gem->exec_bos,
390 sizeof(*bufmgr_gem->exec_bos) * new_size);
391 bufmgr_gem->exec_size = new_size;
394 index = bufmgr_gem->exec_count;
395 bo_gem->validate_index = index;
396 /* Fill in array entry */
397 bufmgr_gem->exec_objects[index].handle = bo_gem->gem_handle;
398 bufmgr_gem->exec_objects[index].relocation_count = bo_gem->reloc_count;
399 bufmgr_gem->exec_objects[index].relocs_ptr = (uintptr_t) bo_gem->relocs;
400 bufmgr_gem->exec_objects[index].alignment = 0;
401 bufmgr_gem->exec_objects[index].offset = 0;
402 bufmgr_gem->exec_bos[index] = bo;
403 bufmgr_gem->exec_count++;
407 drm_intel_add_validate_buffer2(drm_intel_bo *bo, int need_fence)
409 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
410 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
413 if (bo_gem->validate_index != -1) {
415 bufmgr_gem->exec2_objects[bo_gem->validate_index].flags |=
416 EXEC_OBJECT_NEEDS_FENCE;
420 /* Extend the array of validation entries as necessary. */
421 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
422 int new_size = bufmgr_gem->exec_size * 2;
427 bufmgr_gem->exec2_objects =
428 realloc(bufmgr_gem->exec2_objects,
429 sizeof(*bufmgr_gem->exec2_objects) * new_size);
430 bufmgr_gem->exec_bos =
431 realloc(bufmgr_gem->exec_bos,
432 sizeof(*bufmgr_gem->exec_bos) * new_size);
433 bufmgr_gem->exec_size = new_size;
436 index = bufmgr_gem->exec_count;
437 bo_gem->validate_index = index;
438 /* Fill in array entry */
439 bufmgr_gem->exec2_objects[index].handle = bo_gem->gem_handle;
440 bufmgr_gem->exec2_objects[index].relocation_count = bo_gem->reloc_count;
441 bufmgr_gem->exec2_objects[index].relocs_ptr = (uintptr_t)bo_gem->relocs;
442 bufmgr_gem->exec2_objects[index].alignment = 0;
443 bufmgr_gem->exec2_objects[index].offset = 0;
444 bufmgr_gem->exec_bos[index] = bo;
445 bufmgr_gem->exec2_objects[index].flags = 0;
446 bufmgr_gem->exec2_objects[index].rsvd1 = 0;
447 bufmgr_gem->exec2_objects[index].rsvd2 = 0;
449 bufmgr_gem->exec2_objects[index].flags |=
450 EXEC_OBJECT_NEEDS_FENCE;
452 bufmgr_gem->exec_count++;
455 #define RELOC_BUF_SIZE(x) ((I915_RELOC_HEADER + x * I915_RELOC0_STRIDE) * \
459 drm_intel_bo_gem_set_in_aperture_size(drm_intel_bufmgr_gem *bufmgr_gem,
460 drm_intel_bo_gem *bo_gem)
464 assert(!bo_gem->used_as_reloc_target);
466 /* The older chipsets are far-less flexible in terms of tiling,
467 * and require tiled buffer to be size aligned in the aperture.
468 * This means that in the worst possible case we will need a hole
469 * twice as large as the object in order for it to fit into the
470 * aperture. Optimal packing is for wimps.
472 size = bo_gem->bo.size;
473 if (bufmgr_gem->gen < 4 && bo_gem->tiling_mode != I915_TILING_NONE) {
476 if (bufmgr_gem->has_relaxed_fencing) {
477 if (bufmgr_gem->gen == 3)
478 min_size = 1024*1024;
482 while (min_size < size)
487 /* Account for worst-case alignment. */
491 bo_gem->reloc_tree_size = size;
495 drm_intel_setup_reloc_list(drm_intel_bo *bo)
497 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
498 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
499 unsigned int max_relocs = bufmgr_gem->max_relocs;
501 if (bo->size / 4 < max_relocs)
502 max_relocs = bo->size / 4;
504 bo_gem->relocs = malloc(max_relocs *
505 sizeof(struct drm_i915_gem_relocation_entry));
506 bo_gem->reloc_target_info = malloc(max_relocs *
507 sizeof(drm_intel_reloc_target));
508 if (bo_gem->relocs == NULL || bo_gem->reloc_target_info == NULL) {
509 bo_gem->has_error = 1;
511 free (bo_gem->relocs);
512 bo_gem->relocs = NULL;
514 free (bo_gem->reloc_target_info);
515 bo_gem->reloc_target_info = NULL;
524 drm_intel_gem_bo_busy(drm_intel_bo *bo)
526 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
527 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
528 struct drm_i915_gem_busy busy;
531 memset(&busy, 0, sizeof(busy));
532 busy.handle = bo_gem->gem_handle;
534 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_BUSY, &busy);
536 return (ret == 0 && busy.busy);
540 drm_intel_gem_bo_madvise_internal(drm_intel_bufmgr_gem *bufmgr_gem,
541 drm_intel_bo_gem *bo_gem, int state)
543 struct drm_i915_gem_madvise madv;
545 madv.handle = bo_gem->gem_handle;
548 drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MADVISE, &madv);
550 return madv.retained;
554 drm_intel_gem_bo_madvise(drm_intel_bo *bo, int madv)
556 return drm_intel_gem_bo_madvise_internal
557 ((drm_intel_bufmgr_gem *) bo->bufmgr,
558 (drm_intel_bo_gem *) bo,
562 /* drop the oldest entries that have been purged by the kernel */
564 drm_intel_gem_bo_cache_purge_bucket(drm_intel_bufmgr_gem *bufmgr_gem,
565 struct drm_intel_gem_bo_bucket *bucket)
567 while (!DRMLISTEMPTY(&bucket->head)) {
568 drm_intel_bo_gem *bo_gem;
570 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
571 bucket->head.next, head);
572 if (drm_intel_gem_bo_madvise_internal
573 (bufmgr_gem, bo_gem, I915_MADV_DONTNEED))
576 DRMLISTDEL(&bo_gem->head);
577 drm_intel_gem_bo_free(&bo_gem->bo);
581 static drm_intel_bo *
582 drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr,
586 uint32_t tiling_mode,
587 unsigned long stride)
589 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
590 drm_intel_bo_gem *bo_gem;
591 unsigned int page_size = getpagesize();
593 struct drm_intel_gem_bo_bucket *bucket;
594 int alloc_from_cache;
595 unsigned long bo_size;
598 if (flags & BO_ALLOC_FOR_RENDER)
601 /* Round the allocated size up to a power of two number of pages. */
602 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, size);
604 /* If we don't have caching at this size, don't actually round the
607 if (bucket == NULL) {
609 if (bo_size < page_size)
612 bo_size = bucket->size;
615 pthread_mutex_lock(&bufmgr_gem->lock);
616 /* Get a buffer out of the cache if available */
618 alloc_from_cache = 0;
619 if (bucket != NULL && !DRMLISTEMPTY(&bucket->head)) {
621 /* Allocate new render-target BOs from the tail (MRU)
622 * of the list, as it will likely be hot in the GPU
623 * cache and in the aperture for us.
625 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
626 bucket->head.prev, head);
627 DRMLISTDEL(&bo_gem->head);
628 alloc_from_cache = 1;
630 /* For non-render-target BOs (where we're probably
631 * going to map it first thing in order to fill it
632 * with data), check if the last BO in the cache is
633 * unbusy, and only reuse in that case. Otherwise,
634 * allocating a new buffer is probably faster than
635 * waiting for the GPU to finish.
637 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
638 bucket->head.next, head);
639 if (!drm_intel_gem_bo_busy(&bo_gem->bo)) {
640 alloc_from_cache = 1;
641 DRMLISTDEL(&bo_gem->head);
645 if (alloc_from_cache) {
646 if (!drm_intel_gem_bo_madvise_internal
647 (bufmgr_gem, bo_gem, I915_MADV_WILLNEED)) {
648 drm_intel_gem_bo_free(&bo_gem->bo);
649 drm_intel_gem_bo_cache_purge_bucket(bufmgr_gem,
654 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
657 drm_intel_gem_bo_free(&bo_gem->bo);
662 pthread_mutex_unlock(&bufmgr_gem->lock);
664 if (!alloc_from_cache) {
665 struct drm_i915_gem_create create;
667 bo_gem = calloc(1, sizeof(*bo_gem));
671 bo_gem->bo.size = bo_size;
672 memset(&create, 0, sizeof(create));
673 create.size = bo_size;
675 ret = drmIoctl(bufmgr_gem->fd,
676 DRM_IOCTL_I915_GEM_CREATE,
678 bo_gem->gem_handle = create.handle;
679 bo_gem->bo.handle = bo_gem->gem_handle;
684 bo_gem->bo.bufmgr = bufmgr;
686 bo_gem->tiling_mode = I915_TILING_NONE;
687 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
690 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
693 drm_intel_gem_bo_free(&bo_gem->bo);
697 DRMINITLISTHEAD(&bo_gem->name_list);
701 atomic_set(&bo_gem->refcount, 1);
702 bo_gem->validate_index = -1;
703 bo_gem->reloc_tree_fences = 0;
704 bo_gem->used_as_reloc_target = 0;
705 bo_gem->has_error = 0;
706 bo_gem->reusable = 1;
708 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
710 DBG("bo_create: buf %d (%s) %ldb\n",
711 bo_gem->gem_handle, bo_gem->name, size);
716 static drm_intel_bo *
717 drm_intel_gem_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
720 unsigned int alignment)
722 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size,
724 I915_TILING_NONE, 0);
727 static drm_intel_bo *
728 drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr,
731 unsigned int alignment)
733 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, 0,
734 I915_TILING_NONE, 0);
737 static drm_intel_bo *
738 drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
739 int x, int y, int cpp, uint32_t *tiling_mode,
740 unsigned long *pitch, unsigned long flags)
742 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
743 unsigned long size, stride;
747 unsigned long aligned_y, height_alignment;
749 tiling = *tiling_mode;
751 /* If we're tiled, our allocations are in 8 or 32-row blocks,
752 * so failure to align our height means that we won't allocate
755 * If we're untiled, we still have to align to 2 rows high
756 * because the data port accesses 2x2 blocks even if the
757 * bottom row isn't to be rendered, so failure to align means
758 * we could walk off the end of the GTT and fault. This is
759 * documented on 965, and may be the case on older chipsets
760 * too so we try to be careful.
763 height_alignment = 2;
765 if (IS_GEN2(bufmgr_gem) && tiling != I915_TILING_NONE)
766 height_alignment = 16;
767 else if (tiling == I915_TILING_X)
768 height_alignment = 8;
769 else if (tiling == I915_TILING_Y)
770 height_alignment = 32;
771 aligned_y = ALIGN(y, height_alignment);
774 stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, tiling_mode);
775 size = stride * aligned_y;
776 size = drm_intel_gem_bo_tile_size(bufmgr_gem, size, tiling_mode);
777 } while (*tiling_mode != tiling);
780 if (tiling == I915_TILING_NONE)
783 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, flags,
788 * Returns a drm_intel_bo wrapping the given buffer object handle.
790 * This can be used when one application needs to pass a buffer object
794 drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
798 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
799 drm_intel_bo_gem *bo_gem;
801 struct drm_gem_open open_arg;
802 struct drm_i915_gem_get_tiling get_tiling;
805 /* At the moment most applications only have a few named bo.
806 * For instance, in a DRI client only the render buffers passed
807 * between X and the client are named. And since X returns the
808 * alternating names for the front/back buffer a linear search
809 * provides a sufficiently fast match.
811 for (list = bufmgr_gem->named.next;
812 list != &bufmgr_gem->named;
814 bo_gem = DRMLISTENTRY(drm_intel_bo_gem, list, name_list);
815 if (bo_gem->global_name == handle) {
816 drm_intel_gem_bo_reference(&bo_gem->bo);
821 bo_gem = calloc(1, sizeof(*bo_gem));
825 memset(&open_arg, 0, sizeof(open_arg));
826 open_arg.name = handle;
827 ret = drmIoctl(bufmgr_gem->fd,
831 DBG("Couldn't reference %s handle 0x%08x: %s\n",
832 name, handle, strerror(errno));
836 bo_gem->bo.size = open_arg.size;
837 bo_gem->bo.offset = 0;
838 bo_gem->bo.virtual = NULL;
839 bo_gem->bo.bufmgr = bufmgr;
841 atomic_set(&bo_gem->refcount, 1);
842 bo_gem->validate_index = -1;
843 bo_gem->gem_handle = open_arg.handle;
844 bo_gem->bo.handle = open_arg.handle;
845 bo_gem->global_name = handle;
846 bo_gem->reusable = 0;
848 memset(&get_tiling, 0, sizeof(get_tiling));
849 get_tiling.handle = bo_gem->gem_handle;
850 ret = drmIoctl(bufmgr_gem->fd,
851 DRM_IOCTL_I915_GEM_GET_TILING,
854 drm_intel_gem_bo_unreference(&bo_gem->bo);
857 bo_gem->tiling_mode = get_tiling.tiling_mode;
858 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
859 /* XXX stride is unknown */
860 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
862 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
863 DBG("bo_create_from_handle: %d (%s)\n", handle, bo_gem->name);
869 drm_intel_gem_bo_free(drm_intel_bo *bo)
871 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
872 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
873 struct drm_gem_close close;
876 if (bo_gem->mem_virtual)
877 munmap(bo_gem->mem_virtual, bo_gem->bo.size);
878 if (bo_gem->gtt_virtual)
879 munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
881 /* Close this object */
882 memset(&close, 0, sizeof(close));
883 close.handle = bo_gem->gem_handle;
884 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close);
886 DBG("DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
887 bo_gem->gem_handle, bo_gem->name, strerror(errno));
892 /** Frees all cached buffers significantly older than @time. */
894 drm_intel_gem_cleanup_bo_cache(drm_intel_bufmgr_gem *bufmgr_gem, time_t time)
898 if (bufmgr_gem->time == time)
901 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
902 struct drm_intel_gem_bo_bucket *bucket =
903 &bufmgr_gem->cache_bucket[i];
905 while (!DRMLISTEMPTY(&bucket->head)) {
906 drm_intel_bo_gem *bo_gem;
908 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
909 bucket->head.next, head);
910 if (time - bo_gem->free_time <= 1)
913 DRMLISTDEL(&bo_gem->head);
915 drm_intel_gem_bo_free(&bo_gem->bo);
919 bufmgr_gem->time = time;
923 drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time)
925 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
926 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
927 struct drm_intel_gem_bo_bucket *bucket;
930 /* Unreference all the target buffers */
931 for (i = 0; i < bo_gem->reloc_count; i++) {
932 if (bo_gem->reloc_target_info[i].bo != bo) {
933 drm_intel_gem_bo_unreference_locked_timed(bo_gem->
934 reloc_target_info[i].bo,
938 bo_gem->reloc_count = 0;
939 bo_gem->used_as_reloc_target = 0;
941 DBG("bo_unreference final: %d (%s)\n",
942 bo_gem->gem_handle, bo_gem->name);
944 /* release memory associated with this object */
945 if (bo_gem->reloc_target_info) {
946 free(bo_gem->reloc_target_info);
947 bo_gem->reloc_target_info = NULL;
949 if (bo_gem->relocs) {
950 free(bo_gem->relocs);
951 bo_gem->relocs = NULL;
954 DRMLISTDEL(&bo_gem->name_list);
956 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, bo->size);
957 /* Put the buffer into our internal cache for reuse if we can. */
958 if (bufmgr_gem->bo_reuse && bo_gem->reusable && bucket != NULL &&
959 drm_intel_gem_bo_madvise_internal(bufmgr_gem, bo_gem,
960 I915_MADV_DONTNEED)) {
961 bo_gem->free_time = time;
964 bo_gem->validate_index = -1;
966 DRMLISTADDTAIL(&bo_gem->head, &bucket->head);
968 drm_intel_gem_bo_free(bo);
972 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
975 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
977 assert(atomic_read(&bo_gem->refcount) > 0);
978 if (atomic_dec_and_test(&bo_gem->refcount))
979 drm_intel_gem_bo_unreference_final(bo, time);
982 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo)
984 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
986 assert(atomic_read(&bo_gem->refcount) > 0);
987 if (atomic_dec_and_test(&bo_gem->refcount)) {
988 drm_intel_bufmgr_gem *bufmgr_gem =
989 (drm_intel_bufmgr_gem *) bo->bufmgr;
990 struct timespec time;
992 clock_gettime(CLOCK_MONOTONIC, &time);
994 pthread_mutex_lock(&bufmgr_gem->lock);
995 drm_intel_gem_bo_unreference_final(bo, time.tv_sec);
996 drm_intel_gem_cleanup_bo_cache(bufmgr_gem, time.tv_sec);
997 pthread_mutex_unlock(&bufmgr_gem->lock);
1001 static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable)
1003 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1004 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1005 struct drm_i915_gem_set_domain set_domain;
1008 pthread_mutex_lock(&bufmgr_gem->lock);
1010 /* Allow recursive mapping. Mesa may recursively map buffers with
1011 * nested display loops.
1013 if (!bo_gem->mem_virtual) {
1014 struct drm_i915_gem_mmap mmap_arg;
1016 DBG("bo_map: %d (%s)\n", bo_gem->gem_handle, bo_gem->name);
1018 memset(&mmap_arg, 0, sizeof(mmap_arg));
1019 mmap_arg.handle = bo_gem->gem_handle;
1020 mmap_arg.offset = 0;
1021 mmap_arg.size = bo->size;
1022 ret = drmIoctl(bufmgr_gem->fd,
1023 DRM_IOCTL_I915_GEM_MMAP,
1027 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1028 __FILE__, __LINE__, bo_gem->gem_handle,
1029 bo_gem->name, strerror(errno));
1030 pthread_mutex_unlock(&bufmgr_gem->lock);
1033 bo_gem->mem_virtual = (void *)(uintptr_t) mmap_arg.addr_ptr;
1035 DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1036 bo_gem->mem_virtual);
1037 bo->virtual = bo_gem->mem_virtual;
1039 set_domain.handle = bo_gem->gem_handle;
1040 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
1042 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
1044 set_domain.write_domain = 0;
1045 ret = drmIoctl(bufmgr_gem->fd,
1046 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1049 DBG("%s:%d: Error setting to CPU domain %d: %s\n",
1050 __FILE__, __LINE__, bo_gem->gem_handle,
1054 pthread_mutex_unlock(&bufmgr_gem->lock);
1059 int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
1061 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1062 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1063 struct drm_i915_gem_set_domain set_domain;
1066 pthread_mutex_lock(&bufmgr_gem->lock);
1068 /* Get a mapping of the buffer if we haven't before. */
1069 if (bo_gem->gtt_virtual == NULL) {
1070 struct drm_i915_gem_mmap_gtt mmap_arg;
1072 DBG("bo_map_gtt: mmap %d (%s)\n", bo_gem->gem_handle,
1075 memset(&mmap_arg, 0, sizeof(mmap_arg));
1076 mmap_arg.handle = bo_gem->gem_handle;
1078 /* Get the fake offset back... */
1079 ret = drmIoctl(bufmgr_gem->fd,
1080 DRM_IOCTL_I915_GEM_MMAP_GTT,
1084 DBG("%s:%d: Error preparing buffer map %d (%s): %s .\n",
1086 bo_gem->gem_handle, bo_gem->name,
1088 pthread_mutex_unlock(&bufmgr_gem->lock);
1093 bo_gem->gtt_virtual = mmap(0, bo->size, PROT_READ | PROT_WRITE,
1094 MAP_SHARED, bufmgr_gem->fd,
1096 if (bo_gem->gtt_virtual == MAP_FAILED) {
1097 bo_gem->gtt_virtual = NULL;
1099 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1101 bo_gem->gem_handle, bo_gem->name,
1103 pthread_mutex_unlock(&bufmgr_gem->lock);
1108 bo->virtual = bo_gem->gtt_virtual;
1110 DBG("bo_map_gtt: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1111 bo_gem->gtt_virtual);
1113 /* Now move it to the GTT domain so that the CPU caches are flushed */
1114 set_domain.handle = bo_gem->gem_handle;
1115 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1116 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
1117 ret = drmIoctl(bufmgr_gem->fd,
1118 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1121 DBG("%s:%d: Error setting domain %d: %s\n",
1122 __FILE__, __LINE__, bo_gem->gem_handle,
1126 pthread_mutex_unlock(&bufmgr_gem->lock);
1131 int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo)
1133 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1139 pthread_mutex_lock(&bufmgr_gem->lock);
1141 pthread_mutex_unlock(&bufmgr_gem->lock);
1146 static int drm_intel_gem_bo_unmap(drm_intel_bo *bo)
1148 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1149 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1150 struct drm_i915_gem_sw_finish sw_finish;
1156 pthread_mutex_lock(&bufmgr_gem->lock);
1158 /* Cause a flush to happen if the buffer's pinned for scanout, so the
1159 * results show up in a timely manner.
1161 sw_finish.handle = bo_gem->gem_handle;
1162 ret = drmIoctl(bufmgr_gem->fd,
1163 DRM_IOCTL_I915_GEM_SW_FINISH,
1165 ret = ret == -1 ? -errno : 0;
1168 pthread_mutex_unlock(&bufmgr_gem->lock);
1174 drm_intel_gem_bo_subdata(drm_intel_bo *bo, unsigned long offset,
1175 unsigned long size, const void *data)
1177 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1178 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1179 struct drm_i915_gem_pwrite pwrite;
1182 memset(&pwrite, 0, sizeof(pwrite));
1183 pwrite.handle = bo_gem->gem_handle;
1184 pwrite.offset = offset;
1186 pwrite.data_ptr = (uint64_t) (uintptr_t) data;
1187 ret = drmIoctl(bufmgr_gem->fd,
1188 DRM_IOCTL_I915_GEM_PWRITE,
1192 DBG("%s:%d: Error writing data to buffer %d: (%d %d) %s .\n",
1193 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1194 (int)size, strerror(errno));
1201 drm_intel_gem_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id)
1203 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1204 struct drm_i915_get_pipe_from_crtc_id get_pipe_from_crtc_id;
1207 get_pipe_from_crtc_id.crtc_id = crtc_id;
1208 ret = drmIoctl(bufmgr_gem->fd,
1209 DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID,
1210 &get_pipe_from_crtc_id);
1212 /* We return -1 here to signal that we don't
1213 * know which pipe is associated with this crtc.
1214 * This lets the caller know that this information
1215 * isn't available; using the wrong pipe for
1216 * vblank waiting can cause the chipset to lock up
1221 return get_pipe_from_crtc_id.pipe;
1225 drm_intel_gem_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
1226 unsigned long size, void *data)
1228 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1229 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1230 struct drm_i915_gem_pread pread;
1233 memset(&pread, 0, sizeof(pread));
1234 pread.handle = bo_gem->gem_handle;
1235 pread.offset = offset;
1237 pread.data_ptr = (uint64_t) (uintptr_t) data;
1238 ret = drmIoctl(bufmgr_gem->fd,
1239 DRM_IOCTL_I915_GEM_PREAD,
1243 DBG("%s:%d: Error reading data from buffer %d: (%d %d) %s .\n",
1244 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1245 (int)size, strerror(errno));
1251 /** Waits for all GPU rendering with the object to have completed. */
1253 drm_intel_gem_bo_wait_rendering(drm_intel_bo *bo)
1255 drm_intel_gem_bo_start_gtt_access(bo, 1);
1259 * Sets the object to the GTT read and possibly write domain, used by the X
1260 * 2D driver in the absence of kernel support to do drm_intel_gem_bo_map_gtt().
1262 * In combination with drm_intel_gem_bo_pin() and manual fence management, we
1263 * can do tiled pixmaps this way.
1266 drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable)
1268 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1269 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1270 struct drm_i915_gem_set_domain set_domain;
1273 set_domain.handle = bo_gem->gem_handle;
1274 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1275 set_domain.write_domain = write_enable ? I915_GEM_DOMAIN_GTT : 0;
1276 ret = drmIoctl(bufmgr_gem->fd,
1277 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1280 DBG("%s:%d: Error setting memory domains %d (%08x %08x): %s .\n",
1281 __FILE__, __LINE__, bo_gem->gem_handle,
1282 set_domain.read_domains, set_domain.write_domain,
1288 drm_intel_bufmgr_gem_destroy(drm_intel_bufmgr *bufmgr)
1290 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1293 free(bufmgr_gem->exec2_objects);
1294 free(bufmgr_gem->exec_objects);
1295 free(bufmgr_gem->exec_bos);
1297 pthread_mutex_destroy(&bufmgr_gem->lock);
1299 /* Free any cached buffer objects we were going to reuse */
1300 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
1301 struct drm_intel_gem_bo_bucket *bucket =
1302 &bufmgr_gem->cache_bucket[i];
1303 drm_intel_bo_gem *bo_gem;
1305 while (!DRMLISTEMPTY(&bucket->head)) {
1306 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1307 bucket->head.next, head);
1308 DRMLISTDEL(&bo_gem->head);
1310 drm_intel_gem_bo_free(&bo_gem->bo);
1318 * Adds the target buffer to the validation list and adds the relocation
1319 * to the reloc_buffer's relocation list.
1321 * The relocation entry at the given offset must already contain the
1322 * precomputed relocation value, because the kernel will optimize out
1323 * the relocation entry write when the buffer hasn't moved from the
1324 * last known offset in target_bo.
1327 do_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1328 drm_intel_bo *target_bo, uint32_t target_offset,
1329 uint32_t read_domains, uint32_t write_domain,
1332 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1333 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1334 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
1337 if (bo_gem->has_error)
1340 if (target_bo_gem->has_error) {
1341 bo_gem->has_error = 1;
1345 /* We never use HW fences for rendering on 965+ */
1346 if (bufmgr_gem->gen >= 4)
1349 fenced_command = need_fence;
1350 if (target_bo_gem->tiling_mode == I915_TILING_NONE)
1353 /* Create a new relocation list if needed */
1354 if (bo_gem->relocs == NULL && drm_intel_setup_reloc_list(bo))
1357 /* Check overflow */
1358 assert(bo_gem->reloc_count < bufmgr_gem->max_relocs);
1361 assert(offset <= bo->size - 4);
1362 assert((write_domain & (write_domain - 1)) == 0);
1364 /* Make sure that we're not adding a reloc to something whose size has
1365 * already been accounted for.
1367 assert(!bo_gem->used_as_reloc_target);
1368 if (target_bo_gem != bo_gem) {
1369 target_bo_gem->used_as_reloc_target = 1;
1370 bo_gem->reloc_tree_size += target_bo_gem->reloc_tree_size;
1372 /* An object needing a fence is a tiled buffer, so it won't have
1373 * relocs to other buffers.
1376 target_bo_gem->reloc_tree_fences = 1;
1377 bo_gem->reloc_tree_fences += target_bo_gem->reloc_tree_fences;
1379 bo_gem->relocs[bo_gem->reloc_count].offset = offset;
1380 bo_gem->relocs[bo_gem->reloc_count].delta = target_offset;
1381 bo_gem->relocs[bo_gem->reloc_count].target_handle =
1382 target_bo_gem->gem_handle;
1383 bo_gem->relocs[bo_gem->reloc_count].read_domains = read_domains;
1384 bo_gem->relocs[bo_gem->reloc_count].write_domain = write_domain;
1385 bo_gem->relocs[bo_gem->reloc_count].presumed_offset = target_bo->offset;
1387 bo_gem->reloc_target_info[bo_gem->reloc_count].bo = target_bo;
1388 if (target_bo != bo)
1389 drm_intel_gem_bo_reference(target_bo);
1391 bo_gem->reloc_target_info[bo_gem->reloc_count].flags =
1392 DRM_INTEL_RELOC_FENCE;
1394 bo_gem->reloc_target_info[bo_gem->reloc_count].flags = 0;
1396 bo_gem->reloc_count++;
1402 drm_intel_gem_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1403 drm_intel_bo *target_bo, uint32_t target_offset,
1404 uint32_t read_domains, uint32_t write_domain)
1406 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1408 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1409 read_domains, write_domain,
1410 !bufmgr_gem->fenced_relocs);
1414 drm_intel_gem_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
1415 drm_intel_bo *target_bo,
1416 uint32_t target_offset,
1417 uint32_t read_domains, uint32_t write_domain)
1419 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1420 read_domains, write_domain, 1);
1424 * Walk the tree of relocations rooted at BO and accumulate the list of
1425 * validations to be performed and update the relocation buffers with
1426 * index values into the validation list.
1429 drm_intel_gem_bo_process_reloc(drm_intel_bo *bo)
1431 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1434 if (bo_gem->relocs == NULL)
1437 for (i = 0; i < bo_gem->reloc_count; i++) {
1438 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1440 if (target_bo == bo)
1443 /* Continue walking the tree depth-first. */
1444 drm_intel_gem_bo_process_reloc(target_bo);
1446 /* Add the target to the validate list */
1447 drm_intel_add_validate_buffer(target_bo);
1452 drm_intel_gem_bo_process_reloc2(drm_intel_bo *bo)
1454 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1457 if (bo_gem->relocs == NULL)
1460 for (i = 0; i < bo_gem->reloc_count; i++) {
1461 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1464 if (target_bo == bo)
1467 /* Continue walking the tree depth-first. */
1468 drm_intel_gem_bo_process_reloc2(target_bo);
1470 need_fence = (bo_gem->reloc_target_info[i].flags &
1471 DRM_INTEL_RELOC_FENCE);
1473 /* Add the target to the validate list */
1474 drm_intel_add_validate_buffer2(target_bo, need_fence);
1480 drm_intel_update_buffer_offsets(drm_intel_bufmgr_gem *bufmgr_gem)
1484 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1485 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1486 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1488 /* Update the buffer offset */
1489 if (bufmgr_gem->exec_objects[i].offset != bo->offset) {
1490 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1491 bo_gem->gem_handle, bo_gem->name, bo->offset,
1492 (unsigned long long)bufmgr_gem->exec_objects[i].
1494 bo->offset = bufmgr_gem->exec_objects[i].offset;
1500 drm_intel_update_buffer_offsets2 (drm_intel_bufmgr_gem *bufmgr_gem)
1504 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1505 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1506 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1508 /* Update the buffer offset */
1509 if (bufmgr_gem->exec2_objects[i].offset != bo->offset) {
1510 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1511 bo_gem->gem_handle, bo_gem->name, bo->offset,
1512 (unsigned long long)bufmgr_gem->exec2_objects[i].offset);
1513 bo->offset = bufmgr_gem->exec2_objects[i].offset;
1519 drm_intel_gem_bo_exec(drm_intel_bo *bo, int used,
1520 drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
1522 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1523 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1524 struct drm_i915_gem_execbuffer execbuf;
1527 if (bo_gem->has_error)
1530 pthread_mutex_lock(&bufmgr_gem->lock);
1531 /* Update indices and set up the validate list. */
1532 drm_intel_gem_bo_process_reloc(bo);
1534 /* Add the batch buffer to the validation list. There are no
1535 * relocations pointing to it.
1537 drm_intel_add_validate_buffer(bo);
1539 execbuf.buffers_ptr = (uintptr_t) bufmgr_gem->exec_objects;
1540 execbuf.buffer_count = bufmgr_gem->exec_count;
1541 execbuf.batch_start_offset = 0;
1542 execbuf.batch_len = used;
1543 execbuf.cliprects_ptr = (uintptr_t) cliprects;
1544 execbuf.num_cliprects = num_cliprects;
1548 ret = drmIoctl(bufmgr_gem->fd,
1549 DRM_IOCTL_I915_GEM_EXECBUFFER,
1553 if (errno == ENOSPC) {
1554 DBG("Execbuffer fails to pin. "
1555 "Estimate: %u. Actual: %u. Available: %u\n",
1556 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
1559 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
1562 (unsigned int)bufmgr_gem->gtt_size);
1565 drm_intel_update_buffer_offsets(bufmgr_gem);
1567 if (bufmgr_gem->bufmgr.debug)
1568 drm_intel_gem_dump_validation_list(bufmgr_gem);
1570 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1571 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1572 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1574 /* Disconnect the buffer from the validate list */
1575 bo_gem->validate_index = -1;
1576 bufmgr_gem->exec_bos[i] = NULL;
1578 bufmgr_gem->exec_count = 0;
1579 pthread_mutex_unlock(&bufmgr_gem->lock);
1585 drm_intel_gem_bo_mrb_exec2(drm_intel_bo *bo, int used,
1586 drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
1589 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1590 struct drm_i915_gem_execbuffer2 execbuf;
1593 switch (flags & 0x7) {
1597 if (!bufmgr_gem->has_blt)
1601 if (!bufmgr_gem->has_bsd)
1604 case I915_EXEC_RENDER:
1605 case I915_EXEC_DEFAULT:
1609 pthread_mutex_lock(&bufmgr_gem->lock);
1610 /* Update indices and set up the validate list. */
1611 drm_intel_gem_bo_process_reloc2(bo);
1613 /* Add the batch buffer to the validation list. There are no relocations
1616 drm_intel_add_validate_buffer2(bo, 0);
1618 execbuf.buffers_ptr = (uintptr_t)bufmgr_gem->exec2_objects;
1619 execbuf.buffer_count = bufmgr_gem->exec_count;
1620 execbuf.batch_start_offset = 0;
1621 execbuf.batch_len = used;
1622 execbuf.cliprects_ptr = (uintptr_t)cliprects;
1623 execbuf.num_cliprects = num_cliprects;
1626 execbuf.flags = flags;
1630 ret = drmIoctl(bufmgr_gem->fd,
1631 DRM_IOCTL_I915_GEM_EXECBUFFER2,
1635 if (ret == -ENOSPC) {
1636 DBG("Execbuffer fails to pin. "
1637 "Estimate: %u. Actual: %u. Available: %u\n",
1638 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
1639 bufmgr_gem->exec_count),
1640 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
1641 bufmgr_gem->exec_count),
1642 (unsigned int) bufmgr_gem->gtt_size);
1645 drm_intel_update_buffer_offsets2(bufmgr_gem);
1647 if (bufmgr_gem->bufmgr.debug)
1648 drm_intel_gem_dump_validation_list(bufmgr_gem);
1650 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1651 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1652 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1654 /* Disconnect the buffer from the validate list */
1655 bo_gem->validate_index = -1;
1656 bufmgr_gem->exec_bos[i] = NULL;
1658 bufmgr_gem->exec_count = 0;
1659 pthread_mutex_unlock(&bufmgr_gem->lock);
1665 drm_intel_gem_bo_exec2(drm_intel_bo *bo, int used,
1666 drm_clip_rect_t *cliprects, int num_cliprects,
1669 return drm_intel_gem_bo_mrb_exec2(bo, used,
1670 cliprects, num_cliprects, DR4,
1675 drm_intel_gem_bo_pin(drm_intel_bo *bo, uint32_t alignment)
1677 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1678 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1679 struct drm_i915_gem_pin pin;
1682 memset(&pin, 0, sizeof(pin));
1683 pin.handle = bo_gem->gem_handle;
1684 pin.alignment = alignment;
1686 ret = drmIoctl(bufmgr_gem->fd,
1687 DRM_IOCTL_I915_GEM_PIN,
1692 bo->offset = pin.offset;
1697 drm_intel_gem_bo_unpin(drm_intel_bo *bo)
1699 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1700 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1701 struct drm_i915_gem_unpin unpin;
1704 memset(&unpin, 0, sizeof(unpin));
1705 unpin.handle = bo_gem->gem_handle;
1707 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_UNPIN, &unpin);
1715 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
1716 uint32_t tiling_mode,
1719 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1720 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1721 struct drm_i915_gem_set_tiling set_tiling;
1724 if (bo_gem->global_name == 0 &&
1725 tiling_mode == bo_gem->tiling_mode &&
1726 stride == bo_gem->stride)
1729 memset(&set_tiling, 0, sizeof(set_tiling));
1731 /* set_tiling is slightly broken and overwrites the
1732 * input on the error path, so we have to open code
1735 set_tiling.handle = bo_gem->gem_handle;
1736 set_tiling.tiling_mode = tiling_mode;
1737 set_tiling.stride = stride;
1739 ret = ioctl(bufmgr_gem->fd,
1740 DRM_IOCTL_I915_GEM_SET_TILING,
1742 } while (ret == -1 && (errno == EINTR || errno == EAGAIN));
1746 bo_gem->tiling_mode = set_tiling.tiling_mode;
1747 bo_gem->swizzle_mode = set_tiling.swizzle_mode;
1748 bo_gem->stride = set_tiling.stride;
1753 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1756 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1757 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1760 /* Linear buffers have no stride. By ensuring that we only ever use
1761 * stride 0 with linear buffers, we simplify our code.
1763 if (*tiling_mode == I915_TILING_NONE)
1766 ret = drm_intel_gem_bo_set_tiling_internal(bo, *tiling_mode, stride);
1768 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
1770 *tiling_mode = bo_gem->tiling_mode;
1775 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1776 uint32_t * swizzle_mode)
1778 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1780 *tiling_mode = bo_gem->tiling_mode;
1781 *swizzle_mode = bo_gem->swizzle_mode;
1786 drm_intel_gem_bo_flink(drm_intel_bo *bo, uint32_t * name)
1788 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1789 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1790 struct drm_gem_flink flink;
1793 if (!bo_gem->global_name) {
1794 memset(&flink, 0, sizeof(flink));
1795 flink.handle = bo_gem->gem_handle;
1797 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_FLINK, &flink);
1800 bo_gem->global_name = flink.name;
1801 bo_gem->reusable = 0;
1803 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
1806 *name = bo_gem->global_name;
1811 * Enables unlimited caching of buffer objects for reuse.
1813 * This is potentially very memory expensive, as the cache at each bucket
1814 * size is only bounded by how many buffers of that size we've managed to have
1815 * in flight at once.
1818 drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr)
1820 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1822 bufmgr_gem->bo_reuse = 1;
1826 * Enable use of fenced reloc type.
1828 * New code should enable this to avoid unnecessary fence register
1829 * allocation. If this option is not enabled, all relocs will have fence
1830 * register allocated.
1833 drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr)
1835 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
1837 if (bufmgr_gem->bufmgr.bo_exec == drm_intel_gem_bo_exec2)
1838 bufmgr_gem->fenced_relocs = 1;
1842 * Return the additional aperture space required by the tree of buffer objects
1846 drm_intel_gem_bo_get_aperture_space(drm_intel_bo *bo)
1848 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1852 if (bo == NULL || bo_gem->included_in_check_aperture)
1856 bo_gem->included_in_check_aperture = 1;
1858 for (i = 0; i < bo_gem->reloc_count; i++)
1860 drm_intel_gem_bo_get_aperture_space(bo_gem->
1861 reloc_target_info[i].bo);
1867 * Count the number of buffers in this list that need a fence reg
1869 * If the count is greater than the number of available regs, we'll have
1870 * to ask the caller to resubmit a batch with fewer tiled buffers.
1872 * This function over-counts if the same buffer is used multiple times.
1875 drm_intel_gem_total_fences(drm_intel_bo ** bo_array, int count)
1878 unsigned int total = 0;
1880 for (i = 0; i < count; i++) {
1881 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
1886 total += bo_gem->reloc_tree_fences;
1892 * Clear the flag set by drm_intel_gem_bo_get_aperture_space() so we're ready
1893 * for the next drm_intel_bufmgr_check_aperture_space() call.
1896 drm_intel_gem_bo_clear_aperture_space_flag(drm_intel_bo *bo)
1898 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1901 if (bo == NULL || !bo_gem->included_in_check_aperture)
1904 bo_gem->included_in_check_aperture = 0;
1906 for (i = 0; i < bo_gem->reloc_count; i++)
1907 drm_intel_gem_bo_clear_aperture_space_flag(bo_gem->
1908 reloc_target_info[i].bo);
1912 * Return a conservative estimate for the amount of aperture required
1913 * for a collection of buffers. This may double-count some buffers.
1916 drm_intel_gem_estimate_batch_space(drm_intel_bo **bo_array, int count)
1919 unsigned int total = 0;
1921 for (i = 0; i < count; i++) {
1922 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
1924 total += bo_gem->reloc_tree_size;
1930 * Return the amount of aperture needed for a collection of buffers.
1931 * This avoids double counting any buffers, at the cost of looking
1932 * at every buffer in the set.
1935 drm_intel_gem_compute_batch_space(drm_intel_bo **bo_array, int count)
1938 unsigned int total = 0;
1940 for (i = 0; i < count; i++) {
1941 total += drm_intel_gem_bo_get_aperture_space(bo_array[i]);
1942 /* For the first buffer object in the array, we get an
1943 * accurate count back for its reloc_tree size (since nothing
1944 * had been flagged as being counted yet). We can save that
1945 * value out as a more conservative reloc_tree_size that
1946 * avoids double-counting target buffers. Since the first
1947 * buffer happens to usually be the batch buffer in our
1948 * callers, this can pull us back from doing the tree
1949 * walk on every new batch emit.
1952 drm_intel_bo_gem *bo_gem =
1953 (drm_intel_bo_gem *) bo_array[i];
1954 bo_gem->reloc_tree_size = total;
1958 for (i = 0; i < count; i++)
1959 drm_intel_gem_bo_clear_aperture_space_flag(bo_array[i]);
1964 * Return -1 if the batchbuffer should be flushed before attempting to
1965 * emit rendering referencing the buffers pointed to by bo_array.
1967 * This is required because if we try to emit a batchbuffer with relocations
1968 * to a tree of buffers that won't simultaneously fit in the aperture,
1969 * the rendering will return an error at a point where the software is not
1970 * prepared to recover from it.
1972 * However, we also want to emit the batchbuffer significantly before we reach
1973 * the limit, as a series of batchbuffers each of which references buffers
1974 * covering almost all of the aperture means that at each emit we end up
1975 * waiting to evict a buffer from the last rendering, and we get synchronous
1976 * performance. By emitting smaller batchbuffers, we eat some CPU overhead to
1977 * get better parallelism.
1980 drm_intel_gem_check_aperture_space(drm_intel_bo **bo_array, int count)
1982 drm_intel_bufmgr_gem *bufmgr_gem =
1983 (drm_intel_bufmgr_gem *) bo_array[0]->bufmgr;
1984 unsigned int total = 0;
1985 unsigned int threshold = bufmgr_gem->gtt_size * 3 / 4;
1988 /* Check for fence reg constraints if necessary */
1989 if (bufmgr_gem->available_fences) {
1990 total_fences = drm_intel_gem_total_fences(bo_array, count);
1991 if (total_fences > bufmgr_gem->available_fences)
1995 total = drm_intel_gem_estimate_batch_space(bo_array, count);
1997 if (total > threshold)
1998 total = drm_intel_gem_compute_batch_space(bo_array, count);
2000 if (total > threshold) {
2001 DBG("check_space: overflowed available aperture, "
2003 total / 1024, (int)bufmgr_gem->gtt_size / 1024);
2006 DBG("drm_check_space: total %dkb vs bufgr %dkb\n", total / 1024,
2007 (int)bufmgr_gem->gtt_size / 1024);
2013 * Disable buffer reuse for objects which are shared with the kernel
2014 * as scanout buffers
2017 drm_intel_gem_bo_disable_reuse(drm_intel_bo *bo)
2019 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2021 bo_gem->reusable = 0;
2026 drm_intel_gem_bo_is_reusable(drm_intel_bo *bo)
2028 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2030 return bo_gem->reusable;
2034 _drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
2036 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2039 for (i = 0; i < bo_gem->reloc_count; i++) {
2040 if (bo_gem->reloc_target_info[i].bo == target_bo)
2042 if (bo == bo_gem->reloc_target_info[i].bo)
2044 if (_drm_intel_gem_bo_references(bo_gem->reloc_target_info[i].bo,
2052 /** Return true if target_bo is referenced by bo's relocation tree. */
2054 drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
2056 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
2058 if (bo == NULL || target_bo == NULL)
2060 if (target_bo_gem->used_as_reloc_target)
2061 return _drm_intel_gem_bo_references(bo, target_bo);
2066 add_bucket(drm_intel_bufmgr_gem *bufmgr_gem, int size)
2068 unsigned int i = bufmgr_gem->num_buckets;
2070 assert(i < ARRAY_SIZE(bufmgr_gem->cache_bucket));
2072 DRMINITLISTHEAD(&bufmgr_gem->cache_bucket[i].head);
2073 bufmgr_gem->cache_bucket[i].size = size;
2074 bufmgr_gem->num_buckets++;
2078 init_cache_buckets(drm_intel_bufmgr_gem *bufmgr_gem)
2080 unsigned long size, cache_max_size = 64 * 1024 * 1024;
2082 /* OK, so power of two buckets was too wasteful of memory.
2083 * Give 3 other sizes between each power of two, to hopefully
2084 * cover things accurately enough. (The alternative is
2085 * probably to just go for exact matching of sizes, and assume
2086 * that for things like composited window resize the tiled
2087 * width/height alignment and rounding of sizes to pages will
2088 * get us useful cache hit rates anyway)
2090 add_bucket(bufmgr_gem, 4096);
2091 add_bucket(bufmgr_gem, 4096 * 2);
2092 add_bucket(bufmgr_gem, 4096 * 3);
2094 /* Initialize the linked lists for BO reuse cache. */
2095 for (size = 4 * 4096; size <= cache_max_size; size *= 2) {
2096 add_bucket(bufmgr_gem, size);
2098 add_bucket(bufmgr_gem, size + size * 1 / 4);
2099 add_bucket(bufmgr_gem, size + size * 2 / 4);
2100 add_bucket(bufmgr_gem, size + size * 3 / 4);
2105 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
2106 * and manage map buffer objections.
2108 * \param fd File descriptor of the opened DRM device.
2111 drm_intel_bufmgr_gem_init(int fd, int batch_size)
2113 drm_intel_bufmgr_gem *bufmgr_gem;
2114 struct drm_i915_gem_get_aperture aperture;
2115 drm_i915_getparam_t gp;
2119 bufmgr_gem = calloc(1, sizeof(*bufmgr_gem));
2120 if (bufmgr_gem == NULL)
2123 bufmgr_gem->fd = fd;
2125 if (pthread_mutex_init(&bufmgr_gem->lock, NULL) != 0) {
2130 ret = drmIoctl(bufmgr_gem->fd,
2131 DRM_IOCTL_I915_GEM_GET_APERTURE,
2135 bufmgr_gem->gtt_size = aperture.aper_available_size;
2137 fprintf(stderr, "DRM_IOCTL_I915_GEM_APERTURE failed: %s\n",
2139 bufmgr_gem->gtt_size = 128 * 1024 * 1024;
2140 fprintf(stderr, "Assuming %dkB available aperture size.\n"
2141 "May lead to reduced performance or incorrect "
2143 (int)bufmgr_gem->gtt_size / 1024);
2146 gp.param = I915_PARAM_CHIPSET_ID;
2147 gp.value = &bufmgr_gem->pci_device;
2148 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2150 fprintf(stderr, "get chip id failed: %d [%d]\n", ret, errno);
2151 fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value);
2154 if (IS_GEN2(bufmgr_gem))
2155 bufmgr_gem->gen = 2;
2156 else if (IS_GEN3(bufmgr_gem))
2157 bufmgr_gem->gen = 3;
2158 else if (IS_GEN4(bufmgr_gem))
2159 bufmgr_gem->gen = 4;
2161 bufmgr_gem->gen = 6;
2163 gp.param = I915_PARAM_HAS_EXECBUF2;
2164 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2168 gp.param = I915_PARAM_HAS_BSD;
2169 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2170 bufmgr_gem->has_bsd = ret == 0;
2172 gp.param = I915_PARAM_HAS_BLT;
2173 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2174 bufmgr_gem->has_blt = ret == 0;
2176 gp.param = I915_PARAM_HAS_RELAXED_FENCING;
2177 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2178 bufmgr_gem->has_relaxed_fencing = ret == 0;
2180 if (bufmgr_gem->gen < 4) {
2181 gp.param = I915_PARAM_NUM_FENCES_AVAIL;
2182 gp.value = &bufmgr_gem->available_fences;
2183 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2185 fprintf(stderr, "get fences failed: %d [%d]\n", ret,
2187 fprintf(stderr, "param: %d, val: %d\n", gp.param,
2189 bufmgr_gem->available_fences = 0;
2191 /* XXX The kernel reports the total number of fences,
2192 * including any that may be pinned.
2194 * We presume that there will be at least one pinned
2195 * fence for the scanout buffer, but there may be more
2196 * than one scanout and the user may be manually
2197 * pinning buffers. Let's move to execbuffer2 and
2198 * thereby forget the insanity of using fences...
2200 bufmgr_gem->available_fences -= 2;
2201 if (bufmgr_gem->available_fences < 0)
2202 bufmgr_gem->available_fences = 0;
2206 /* Let's go with one relocation per every 2 dwords (but round down a bit
2207 * since a power of two will mean an extra page allocation for the reloc
2210 * Every 4 was too few for the blender benchmark.
2212 bufmgr_gem->max_relocs = batch_size / sizeof(uint32_t) / 2 - 2;
2214 bufmgr_gem->bufmgr.bo_alloc = drm_intel_gem_bo_alloc;
2215 bufmgr_gem->bufmgr.bo_alloc_for_render =
2216 drm_intel_gem_bo_alloc_for_render;
2217 bufmgr_gem->bufmgr.bo_alloc_tiled = drm_intel_gem_bo_alloc_tiled;
2218 bufmgr_gem->bufmgr.bo_reference = drm_intel_gem_bo_reference;
2219 bufmgr_gem->bufmgr.bo_unreference = drm_intel_gem_bo_unreference;
2220 bufmgr_gem->bufmgr.bo_map = drm_intel_gem_bo_map;
2221 bufmgr_gem->bufmgr.bo_unmap = drm_intel_gem_bo_unmap;
2222 bufmgr_gem->bufmgr.bo_subdata = drm_intel_gem_bo_subdata;
2223 bufmgr_gem->bufmgr.bo_get_subdata = drm_intel_gem_bo_get_subdata;
2224 bufmgr_gem->bufmgr.bo_wait_rendering = drm_intel_gem_bo_wait_rendering;
2225 bufmgr_gem->bufmgr.bo_emit_reloc = drm_intel_gem_bo_emit_reloc;
2226 bufmgr_gem->bufmgr.bo_emit_reloc_fence = drm_intel_gem_bo_emit_reloc_fence;
2227 bufmgr_gem->bufmgr.bo_pin = drm_intel_gem_bo_pin;
2228 bufmgr_gem->bufmgr.bo_unpin = drm_intel_gem_bo_unpin;
2229 bufmgr_gem->bufmgr.bo_get_tiling = drm_intel_gem_bo_get_tiling;
2230 bufmgr_gem->bufmgr.bo_set_tiling = drm_intel_gem_bo_set_tiling;
2231 bufmgr_gem->bufmgr.bo_flink = drm_intel_gem_bo_flink;
2232 /* Use the new one if available */
2234 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec2;
2235 bufmgr_gem->bufmgr.bo_mrb_exec = drm_intel_gem_bo_mrb_exec2;
2237 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec;
2238 bufmgr_gem->bufmgr.bo_busy = drm_intel_gem_bo_busy;
2239 bufmgr_gem->bufmgr.bo_madvise = drm_intel_gem_bo_madvise;
2240 bufmgr_gem->bufmgr.destroy = drm_intel_bufmgr_gem_destroy;
2241 bufmgr_gem->bufmgr.debug = 0;
2242 bufmgr_gem->bufmgr.check_aperture_space =
2243 drm_intel_gem_check_aperture_space;
2244 bufmgr_gem->bufmgr.bo_disable_reuse = drm_intel_gem_bo_disable_reuse;
2245 bufmgr_gem->bufmgr.bo_is_reusable = drm_intel_gem_bo_is_reusable;
2246 bufmgr_gem->bufmgr.get_pipe_from_crtc_id =
2247 drm_intel_gem_get_pipe_from_crtc_id;
2248 bufmgr_gem->bufmgr.bo_references = drm_intel_gem_bo_references;
2250 DRMINITLISTHEAD(&bufmgr_gem->named);
2251 init_cache_buckets(bufmgr_gem);
2253 return &bufmgr_gem->bufmgr;