1 /**************************************************************************
3 * Copyright © 2007 Red Hat Inc.
4 * Copyright © 2007-2012 Intel Corporation
5 * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
29 **************************************************************************/
31 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
32 * Keith Whitwell <keithw-at-tungstengraphics-dot-com>
33 * Eric Anholt <eric@anholt.net>
34 * Dave Airlie <airlied@linux.ie>
42 #include <xf86atomic.h>
50 #include <sys/ioctl.h>
53 #include <sys/types.h>
58 #define ETIME ETIMEDOUT
60 #include "libdrm_lists.h"
61 #include "intel_bufmgr.h"
62 #include "intel_bufmgr_priv.h"
63 #include "intel_chipset.h"
64 #include "intel_aub.h"
77 #define VG_CLEAR(s) VG(memset(&s, 0, sizeof(s)))
79 #define DBG(...) do { \
80 if (bufmgr_gem->bufmgr.debug) \
81 fprintf(stderr, __VA_ARGS__); \
84 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
86 typedef struct _drm_intel_bo_gem drm_intel_bo_gem;
88 struct drm_intel_gem_bo_bucket {
93 typedef struct _drm_intel_bufmgr_gem {
94 drm_intel_bufmgr bufmgr;
100 pthread_mutex_t lock;
102 struct drm_i915_gem_exec_object *exec_objects;
103 struct drm_i915_gem_exec_object2 *exec2_objects;
104 drm_intel_bo **exec_bos;
108 /** Array of lists of cached gem objects of power-of-two sizes */
109 struct drm_intel_gem_bo_bucket cache_bucket[14 * 4];
114 drmMMListHead vma_cache;
115 int vma_count, vma_open, vma_max;
118 int available_fences;
121 unsigned int has_bsd : 1;
122 unsigned int has_blt : 1;
123 unsigned int has_relaxed_fencing : 1;
124 unsigned int has_llc : 1;
125 unsigned int has_wait_timeout : 1;
126 unsigned int bo_reuse : 1;
127 unsigned int no_exec : 1;
128 unsigned int has_vebox : 1;
134 } drm_intel_bufmgr_gem;
136 #define DRM_INTEL_RELOC_FENCE (1<<0)
138 typedef struct _drm_intel_reloc_target_info {
141 } drm_intel_reloc_target;
143 struct _drm_intel_bo_gem {
151 * Kenel-assigned global name for this object
153 unsigned int global_name;
154 drmMMListHead name_list;
157 * Index of the buffer within the validation list while preparing a
158 * batchbuffer execution.
163 * Current tiling mode
165 uint32_t tiling_mode;
166 uint32_t swizzle_mode;
167 unsigned long stride;
171 /** Array passed to the DRM containing relocation information. */
172 struct drm_i915_gem_relocation_entry *relocs;
174 * Array of info structs corresponding to relocs[i].target_handle etc
176 drm_intel_reloc_target *reloc_target_info;
177 /** Number of entries in relocs */
179 /** Mapped address for the buffer, saved across map/unmap cycles */
181 /** GTT virtual address for the buffer, saved across map/unmap cycles */
184 drmMMListHead vma_list;
190 * Boolean of whether this BO and its children have been included in
191 * the current drm_intel_bufmgr_check_aperture_space() total.
193 bool included_in_check_aperture;
196 * Boolean of whether this buffer has been used as a relocation
197 * target and had its size accounted for, and thus can't have any
198 * further relocations added to it.
200 bool used_as_reloc_target;
203 * Boolean of whether we have encountered an error whilst building the relocation tree.
208 * Boolean of whether this buffer can be re-used
213 * Size in bytes of this buffer and its relocation descendents.
215 * Used to avoid costly tree walking in
216 * drm_intel_bufmgr_check_aperture in the common case.
221 * Number of potential fence registers required by this buffer and its
224 int reloc_tree_fences;
226 /** Flags that we may need to do the SW_FINSIH ioctl on unmap. */
227 bool mapped_cpu_write;
231 drm_intel_aub_annotation *aub_annotations;
232 unsigned aub_annotation_count;
236 drm_intel_gem_estimate_batch_space(drm_intel_bo ** bo_array, int count);
239 drm_intel_gem_compute_batch_space(drm_intel_bo ** bo_array, int count);
242 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
243 uint32_t * swizzle_mode);
246 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
247 uint32_t tiling_mode,
250 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
253 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo);
255 static void drm_intel_gem_bo_free(drm_intel_bo *bo);
258 drm_intel_gem_bo_tile_size(drm_intel_bufmgr_gem *bufmgr_gem, unsigned long size,
259 uint32_t *tiling_mode)
261 unsigned long min_size, max_size;
264 if (*tiling_mode == I915_TILING_NONE)
267 /* 965+ just need multiples of page size for tiling */
268 if (bufmgr_gem->gen >= 4)
269 return ROUND_UP_TO(size, 4096);
271 /* Older chips need powers of two, of at least 512k or 1M */
272 if (bufmgr_gem->gen == 3) {
273 min_size = 1024*1024;
274 max_size = 128*1024*1024;
277 max_size = 64*1024*1024;
280 if (size > max_size) {
281 *tiling_mode = I915_TILING_NONE;
285 /* Do we need to allocate every page for the fence? */
286 if (bufmgr_gem->has_relaxed_fencing)
287 return ROUND_UP_TO(size, 4096);
289 for (i = min_size; i < size; i <<= 1)
296 * Round a given pitch up to the minimum required for X tiling on a
297 * given chip. We use 512 as the minimum to allow for a later tiling
301 drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem,
302 unsigned long pitch, uint32_t *tiling_mode)
304 unsigned long tile_width;
307 /* If untiled, then just align it so that we can do rendering
308 * to it with the 3D engine.
310 if (*tiling_mode == I915_TILING_NONE)
311 return ALIGN(pitch, 64);
313 if (*tiling_mode == I915_TILING_X
314 || (IS_915(bufmgr_gem->pci_device)
315 && *tiling_mode == I915_TILING_Y))
320 /* 965 is flexible */
321 if (bufmgr_gem->gen >= 4)
322 return ROUND_UP_TO(pitch, tile_width);
324 /* The older hardware has a maximum pitch of 8192 with tiled
325 * surfaces, so fallback to untiled if it's too large.
328 *tiling_mode = I915_TILING_NONE;
329 return ALIGN(pitch, 64);
332 /* Pre-965 needs power of two tile width */
333 for (i = tile_width; i < pitch; i <<= 1)
339 static struct drm_intel_gem_bo_bucket *
340 drm_intel_gem_bo_bucket_for_size(drm_intel_bufmgr_gem *bufmgr_gem,
345 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
346 struct drm_intel_gem_bo_bucket *bucket =
347 &bufmgr_gem->cache_bucket[i];
348 if (bucket->size >= size) {
357 drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem *bufmgr_gem)
361 for (i = 0; i < bufmgr_gem->exec_count; i++) {
362 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
363 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
365 if (bo_gem->relocs == NULL) {
366 DBG("%2d: %d (%s)\n", i, bo_gem->gem_handle,
371 for (j = 0; j < bo_gem->reloc_count; j++) {
372 drm_intel_bo *target_bo = bo_gem->reloc_target_info[j].bo;
373 drm_intel_bo_gem *target_gem =
374 (drm_intel_bo_gem *) target_bo;
376 DBG("%2d: %d (%s)@0x%08llx -> "
377 "%d (%s)@0x%08lx + 0x%08x\n",
379 bo_gem->gem_handle, bo_gem->name,
380 (unsigned long long)bo_gem->relocs[j].offset,
381 target_gem->gem_handle,
384 bo_gem->relocs[j].delta);
390 drm_intel_gem_bo_reference(drm_intel_bo *bo)
392 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
394 atomic_inc(&bo_gem->refcount);
398 * Adds the given buffer to the list of buffers to be validated (moved into the
399 * appropriate memory type) with the next batch submission.
401 * If a buffer is validated multiple times in a batch submission, it ends up
402 * with the intersection of the memory type flags and the union of the
406 drm_intel_add_validate_buffer(drm_intel_bo *bo)
408 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
409 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
412 if (bo_gem->validate_index != -1)
415 /* Extend the array of validation entries as necessary. */
416 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
417 int new_size = bufmgr_gem->exec_size * 2;
422 bufmgr_gem->exec_objects =
423 realloc(bufmgr_gem->exec_objects,
424 sizeof(*bufmgr_gem->exec_objects) * new_size);
425 bufmgr_gem->exec_bos =
426 realloc(bufmgr_gem->exec_bos,
427 sizeof(*bufmgr_gem->exec_bos) * new_size);
428 bufmgr_gem->exec_size = new_size;
431 index = bufmgr_gem->exec_count;
432 bo_gem->validate_index = index;
433 /* Fill in array entry */
434 bufmgr_gem->exec_objects[index].handle = bo_gem->gem_handle;
435 bufmgr_gem->exec_objects[index].relocation_count = bo_gem->reloc_count;
436 bufmgr_gem->exec_objects[index].relocs_ptr = (uintptr_t) bo_gem->relocs;
437 bufmgr_gem->exec_objects[index].alignment = 0;
438 bufmgr_gem->exec_objects[index].offset = 0;
439 bufmgr_gem->exec_bos[index] = bo;
440 bufmgr_gem->exec_count++;
444 drm_intel_add_validate_buffer2(drm_intel_bo *bo, int need_fence)
446 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
447 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
450 if (bo_gem->validate_index != -1) {
452 bufmgr_gem->exec2_objects[bo_gem->validate_index].flags |=
453 EXEC_OBJECT_NEEDS_FENCE;
457 /* Extend the array of validation entries as necessary. */
458 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
459 int new_size = bufmgr_gem->exec_size * 2;
464 bufmgr_gem->exec2_objects =
465 realloc(bufmgr_gem->exec2_objects,
466 sizeof(*bufmgr_gem->exec2_objects) * new_size);
467 bufmgr_gem->exec_bos =
468 realloc(bufmgr_gem->exec_bos,
469 sizeof(*bufmgr_gem->exec_bos) * new_size);
470 bufmgr_gem->exec_size = new_size;
473 index = bufmgr_gem->exec_count;
474 bo_gem->validate_index = index;
475 /* Fill in array entry */
476 bufmgr_gem->exec2_objects[index].handle = bo_gem->gem_handle;
477 bufmgr_gem->exec2_objects[index].relocation_count = bo_gem->reloc_count;
478 bufmgr_gem->exec2_objects[index].relocs_ptr = (uintptr_t)bo_gem->relocs;
479 bufmgr_gem->exec2_objects[index].alignment = 0;
480 bufmgr_gem->exec2_objects[index].offset = 0;
481 bufmgr_gem->exec_bos[index] = bo;
482 bufmgr_gem->exec2_objects[index].flags = 0;
483 bufmgr_gem->exec2_objects[index].rsvd1 = 0;
484 bufmgr_gem->exec2_objects[index].rsvd2 = 0;
486 bufmgr_gem->exec2_objects[index].flags |=
487 EXEC_OBJECT_NEEDS_FENCE;
489 bufmgr_gem->exec_count++;
492 #define RELOC_BUF_SIZE(x) ((I915_RELOC_HEADER + x * I915_RELOC0_STRIDE) * \
496 drm_intel_bo_gem_set_in_aperture_size(drm_intel_bufmgr_gem *bufmgr_gem,
497 drm_intel_bo_gem *bo_gem)
501 assert(!bo_gem->used_as_reloc_target);
503 /* The older chipsets are far-less flexible in terms of tiling,
504 * and require tiled buffer to be size aligned in the aperture.
505 * This means that in the worst possible case we will need a hole
506 * twice as large as the object in order for it to fit into the
507 * aperture. Optimal packing is for wimps.
509 size = bo_gem->bo.size;
510 if (bufmgr_gem->gen < 4 && bo_gem->tiling_mode != I915_TILING_NONE) {
513 if (bufmgr_gem->has_relaxed_fencing) {
514 if (bufmgr_gem->gen == 3)
515 min_size = 1024*1024;
519 while (min_size < size)
524 /* Account for worst-case alignment. */
528 bo_gem->reloc_tree_size = size;
532 drm_intel_setup_reloc_list(drm_intel_bo *bo)
534 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
535 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
536 unsigned int max_relocs = bufmgr_gem->max_relocs;
538 if (bo->size / 4 < max_relocs)
539 max_relocs = bo->size / 4;
541 bo_gem->relocs = malloc(max_relocs *
542 sizeof(struct drm_i915_gem_relocation_entry));
543 bo_gem->reloc_target_info = malloc(max_relocs *
544 sizeof(drm_intel_reloc_target));
545 if (bo_gem->relocs == NULL || bo_gem->reloc_target_info == NULL) {
546 bo_gem->has_error = true;
548 free (bo_gem->relocs);
549 bo_gem->relocs = NULL;
551 free (bo_gem->reloc_target_info);
552 bo_gem->reloc_target_info = NULL;
561 drm_intel_gem_bo_busy(drm_intel_bo *bo)
563 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
564 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
565 struct drm_i915_gem_busy busy;
569 busy.handle = bo_gem->gem_handle;
571 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_BUSY, &busy);
573 return (ret == 0 && busy.busy);
577 drm_intel_gem_bo_madvise_internal(drm_intel_bufmgr_gem *bufmgr_gem,
578 drm_intel_bo_gem *bo_gem, int state)
580 struct drm_i915_gem_madvise madv;
583 madv.handle = bo_gem->gem_handle;
586 drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MADVISE, &madv);
588 return madv.retained;
592 drm_intel_gem_bo_madvise(drm_intel_bo *bo, int madv)
594 return drm_intel_gem_bo_madvise_internal
595 ((drm_intel_bufmgr_gem *) bo->bufmgr,
596 (drm_intel_bo_gem *) bo,
600 /* drop the oldest entries that have been purged by the kernel */
602 drm_intel_gem_bo_cache_purge_bucket(drm_intel_bufmgr_gem *bufmgr_gem,
603 struct drm_intel_gem_bo_bucket *bucket)
605 while (!DRMLISTEMPTY(&bucket->head)) {
606 drm_intel_bo_gem *bo_gem;
608 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
609 bucket->head.next, head);
610 if (drm_intel_gem_bo_madvise_internal
611 (bufmgr_gem, bo_gem, I915_MADV_DONTNEED))
614 DRMLISTDEL(&bo_gem->head);
615 drm_intel_gem_bo_free(&bo_gem->bo);
619 static drm_intel_bo *
620 drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr,
624 uint32_t tiling_mode,
625 unsigned long stride)
627 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
628 drm_intel_bo_gem *bo_gem;
629 unsigned int page_size = getpagesize();
631 struct drm_intel_gem_bo_bucket *bucket;
632 bool alloc_from_cache;
633 unsigned long bo_size;
634 bool for_render = false;
636 if (flags & BO_ALLOC_FOR_RENDER)
639 /* Round the allocated size up to a power of two number of pages. */
640 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, size);
642 /* If we don't have caching at this size, don't actually round the
645 if (bucket == NULL) {
647 if (bo_size < page_size)
650 bo_size = bucket->size;
653 pthread_mutex_lock(&bufmgr_gem->lock);
654 /* Get a buffer out of the cache if available */
656 alloc_from_cache = false;
657 if (bucket != NULL && !DRMLISTEMPTY(&bucket->head)) {
659 /* Allocate new render-target BOs from the tail (MRU)
660 * of the list, as it will likely be hot in the GPU
661 * cache and in the aperture for us.
663 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
664 bucket->head.prev, head);
665 DRMLISTDEL(&bo_gem->head);
666 alloc_from_cache = true;
668 /* For non-render-target BOs (where we're probably
669 * going to map it first thing in order to fill it
670 * with data), check if the last BO in the cache is
671 * unbusy, and only reuse in that case. Otherwise,
672 * allocating a new buffer is probably faster than
673 * waiting for the GPU to finish.
675 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
676 bucket->head.next, head);
677 if (!drm_intel_gem_bo_busy(&bo_gem->bo)) {
678 alloc_from_cache = true;
679 DRMLISTDEL(&bo_gem->head);
683 if (alloc_from_cache) {
684 if (!drm_intel_gem_bo_madvise_internal
685 (bufmgr_gem, bo_gem, I915_MADV_WILLNEED)) {
686 drm_intel_gem_bo_free(&bo_gem->bo);
687 drm_intel_gem_bo_cache_purge_bucket(bufmgr_gem,
692 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
695 drm_intel_gem_bo_free(&bo_gem->bo);
700 pthread_mutex_unlock(&bufmgr_gem->lock);
702 if (!alloc_from_cache) {
703 struct drm_i915_gem_create create;
705 bo_gem = calloc(1, sizeof(*bo_gem));
709 bo_gem->bo.size = bo_size;
712 create.size = bo_size;
714 ret = drmIoctl(bufmgr_gem->fd,
715 DRM_IOCTL_I915_GEM_CREATE,
717 bo_gem->gem_handle = create.handle;
718 bo_gem->bo.handle = bo_gem->gem_handle;
723 bo_gem->bo.bufmgr = bufmgr;
725 bo_gem->tiling_mode = I915_TILING_NONE;
726 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
729 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
732 drm_intel_gem_bo_free(&bo_gem->bo);
736 DRMINITLISTHEAD(&bo_gem->name_list);
737 DRMINITLISTHEAD(&bo_gem->vma_list);
741 atomic_set(&bo_gem->refcount, 1);
742 bo_gem->validate_index = -1;
743 bo_gem->reloc_tree_fences = 0;
744 bo_gem->used_as_reloc_target = false;
745 bo_gem->has_error = false;
746 bo_gem->reusable = true;
747 bo_gem->aub_annotations = NULL;
748 bo_gem->aub_annotation_count = 0;
750 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
752 DBG("bo_create: buf %d (%s) %ldb\n",
753 bo_gem->gem_handle, bo_gem->name, size);
758 static drm_intel_bo *
759 drm_intel_gem_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
762 unsigned int alignment)
764 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size,
766 I915_TILING_NONE, 0);
769 static drm_intel_bo *
770 drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr,
773 unsigned int alignment)
775 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, 0,
776 I915_TILING_NONE, 0);
779 static drm_intel_bo *
780 drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
781 int x, int y, int cpp, uint32_t *tiling_mode,
782 unsigned long *pitch, unsigned long flags)
784 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
785 unsigned long size, stride;
789 unsigned long aligned_y, height_alignment;
791 tiling = *tiling_mode;
793 /* If we're tiled, our allocations are in 8 or 32-row blocks,
794 * so failure to align our height means that we won't allocate
797 * If we're untiled, we still have to align to 2 rows high
798 * because the data port accesses 2x2 blocks even if the
799 * bottom row isn't to be rendered, so failure to align means
800 * we could walk off the end of the GTT and fault. This is
801 * documented on 965, and may be the case on older chipsets
802 * too so we try to be careful.
805 height_alignment = 2;
807 if ((bufmgr_gem->gen == 2) && tiling != I915_TILING_NONE)
808 height_alignment = 16;
809 else if (tiling == I915_TILING_X
810 || (IS_915(bufmgr_gem->pci_device)
811 && tiling == I915_TILING_Y))
812 height_alignment = 8;
813 else if (tiling == I915_TILING_Y)
814 height_alignment = 32;
815 aligned_y = ALIGN(y, height_alignment);
818 stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, tiling_mode);
819 size = stride * aligned_y;
820 size = drm_intel_gem_bo_tile_size(bufmgr_gem, size, tiling_mode);
821 } while (*tiling_mode != tiling);
824 if (tiling == I915_TILING_NONE)
827 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, flags,
832 * Returns a drm_intel_bo wrapping the given buffer object handle.
834 * This can be used when one application needs to pass a buffer object
838 drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
842 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
843 drm_intel_bo_gem *bo_gem;
845 struct drm_gem_open open_arg;
846 struct drm_i915_gem_get_tiling get_tiling;
849 /* At the moment most applications only have a few named bo.
850 * For instance, in a DRI client only the render buffers passed
851 * between X and the client are named. And since X returns the
852 * alternating names for the front/back buffer a linear search
853 * provides a sufficiently fast match.
855 for (list = bufmgr_gem->named.next;
856 list != &bufmgr_gem->named;
858 bo_gem = DRMLISTENTRY(drm_intel_bo_gem, list, name_list);
859 if (bo_gem->global_name == handle) {
860 drm_intel_gem_bo_reference(&bo_gem->bo);
865 bo_gem = calloc(1, sizeof(*bo_gem));
870 open_arg.name = handle;
871 ret = drmIoctl(bufmgr_gem->fd,
875 DBG("Couldn't reference %s handle 0x%08x: %s\n",
876 name, handle, strerror(errno));
880 bo_gem->bo.size = open_arg.size;
881 bo_gem->bo.offset = 0;
882 bo_gem->bo.virtual = NULL;
883 bo_gem->bo.bufmgr = bufmgr;
885 atomic_set(&bo_gem->refcount, 1);
886 bo_gem->validate_index = -1;
887 bo_gem->gem_handle = open_arg.handle;
888 bo_gem->bo.handle = open_arg.handle;
889 bo_gem->global_name = handle;
890 bo_gem->reusable = false;
892 VG_CLEAR(get_tiling);
893 get_tiling.handle = bo_gem->gem_handle;
894 ret = drmIoctl(bufmgr_gem->fd,
895 DRM_IOCTL_I915_GEM_GET_TILING,
898 drm_intel_gem_bo_unreference(&bo_gem->bo);
901 bo_gem->tiling_mode = get_tiling.tiling_mode;
902 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
903 /* XXX stride is unknown */
904 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
906 DRMINITLISTHEAD(&bo_gem->vma_list);
907 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
908 DBG("bo_create_from_handle: %d (%s)\n", handle, bo_gem->name);
914 drm_intel_gem_bo_free(drm_intel_bo *bo)
916 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
917 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
918 struct drm_gem_close close;
921 DRMLISTDEL(&bo_gem->vma_list);
922 if (bo_gem->mem_virtual) {
923 VG(VALGRIND_FREELIKE_BLOCK(bo_gem->mem_virtual, 0));
924 munmap(bo_gem->mem_virtual, bo_gem->bo.size);
925 bufmgr_gem->vma_count--;
927 if (bo_gem->gtt_virtual) {
928 munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
929 bufmgr_gem->vma_count--;
932 /* Close this object */
934 close.handle = bo_gem->gem_handle;
935 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close);
937 DBG("DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
938 bo_gem->gem_handle, bo_gem->name, strerror(errno));
940 free(bo_gem->aub_annotations);
945 drm_intel_gem_bo_mark_mmaps_incoherent(drm_intel_bo *bo)
948 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
950 if (bo_gem->mem_virtual)
951 VALGRIND_MAKE_MEM_NOACCESS(bo_gem->mem_virtual, bo->size);
953 if (bo_gem->gtt_virtual)
954 VALGRIND_MAKE_MEM_NOACCESS(bo_gem->gtt_virtual, bo->size);
958 /** Frees all cached buffers significantly older than @time. */
960 drm_intel_gem_cleanup_bo_cache(drm_intel_bufmgr_gem *bufmgr_gem, time_t time)
964 if (bufmgr_gem->time == time)
967 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
968 struct drm_intel_gem_bo_bucket *bucket =
969 &bufmgr_gem->cache_bucket[i];
971 while (!DRMLISTEMPTY(&bucket->head)) {
972 drm_intel_bo_gem *bo_gem;
974 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
975 bucket->head.next, head);
976 if (time - bo_gem->free_time <= 1)
979 DRMLISTDEL(&bo_gem->head);
981 drm_intel_gem_bo_free(&bo_gem->bo);
985 bufmgr_gem->time = time;
988 static void drm_intel_gem_bo_purge_vma_cache(drm_intel_bufmgr_gem *bufmgr_gem)
992 DBG("%s: cached=%d, open=%d, limit=%d\n", __FUNCTION__,
993 bufmgr_gem->vma_count, bufmgr_gem->vma_open, bufmgr_gem->vma_max);
995 if (bufmgr_gem->vma_max < 0)
998 /* We may need to evict a few entries in order to create new mmaps */
999 limit = bufmgr_gem->vma_max - 2*bufmgr_gem->vma_open;
1003 while (bufmgr_gem->vma_count > limit) {
1004 drm_intel_bo_gem *bo_gem;
1006 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1007 bufmgr_gem->vma_cache.next,
1009 assert(bo_gem->map_count == 0);
1010 DRMLISTDELINIT(&bo_gem->vma_list);
1012 if (bo_gem->mem_virtual) {
1013 munmap(bo_gem->mem_virtual, bo_gem->bo.size);
1014 bo_gem->mem_virtual = NULL;
1015 bufmgr_gem->vma_count--;
1017 if (bo_gem->gtt_virtual) {
1018 munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
1019 bo_gem->gtt_virtual = NULL;
1020 bufmgr_gem->vma_count--;
1025 static void drm_intel_gem_bo_close_vma(drm_intel_bufmgr_gem *bufmgr_gem,
1026 drm_intel_bo_gem *bo_gem)
1028 bufmgr_gem->vma_open--;
1029 DRMLISTADDTAIL(&bo_gem->vma_list, &bufmgr_gem->vma_cache);
1030 if (bo_gem->mem_virtual)
1031 bufmgr_gem->vma_count++;
1032 if (bo_gem->gtt_virtual)
1033 bufmgr_gem->vma_count++;
1034 drm_intel_gem_bo_purge_vma_cache(bufmgr_gem);
1037 static void drm_intel_gem_bo_open_vma(drm_intel_bufmgr_gem *bufmgr_gem,
1038 drm_intel_bo_gem *bo_gem)
1040 bufmgr_gem->vma_open++;
1041 DRMLISTDEL(&bo_gem->vma_list);
1042 if (bo_gem->mem_virtual)
1043 bufmgr_gem->vma_count--;
1044 if (bo_gem->gtt_virtual)
1045 bufmgr_gem->vma_count--;
1046 drm_intel_gem_bo_purge_vma_cache(bufmgr_gem);
1050 drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time)
1052 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1053 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1054 struct drm_intel_gem_bo_bucket *bucket;
1057 /* Unreference all the target buffers */
1058 for (i = 0; i < bo_gem->reloc_count; i++) {
1059 if (bo_gem->reloc_target_info[i].bo != bo) {
1060 drm_intel_gem_bo_unreference_locked_timed(bo_gem->
1061 reloc_target_info[i].bo,
1065 bo_gem->reloc_count = 0;
1066 bo_gem->used_as_reloc_target = false;
1068 DBG("bo_unreference final: %d (%s)\n",
1069 bo_gem->gem_handle, bo_gem->name);
1071 /* release memory associated with this object */
1072 if (bo_gem->reloc_target_info) {
1073 free(bo_gem->reloc_target_info);
1074 bo_gem->reloc_target_info = NULL;
1076 if (bo_gem->relocs) {
1077 free(bo_gem->relocs);
1078 bo_gem->relocs = NULL;
1081 /* Clear any left-over mappings */
1082 if (bo_gem->map_count) {
1083 DBG("bo freed with non-zero map-count %d\n", bo_gem->map_count);
1084 bo_gem->map_count = 0;
1085 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1086 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1089 DRMLISTDEL(&bo_gem->name_list);
1091 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, bo->size);
1092 /* Put the buffer into our internal cache for reuse if we can. */
1093 if (bufmgr_gem->bo_reuse && bo_gem->reusable && bucket != NULL &&
1094 drm_intel_gem_bo_madvise_internal(bufmgr_gem, bo_gem,
1095 I915_MADV_DONTNEED)) {
1096 bo_gem->free_time = time;
1098 bo_gem->name = NULL;
1099 bo_gem->validate_index = -1;
1101 DRMLISTADDTAIL(&bo_gem->head, &bucket->head);
1103 drm_intel_gem_bo_free(bo);
1107 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
1110 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1112 assert(atomic_read(&bo_gem->refcount) > 0);
1113 if (atomic_dec_and_test(&bo_gem->refcount))
1114 drm_intel_gem_bo_unreference_final(bo, time);
1117 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo)
1119 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1121 assert(atomic_read(&bo_gem->refcount) > 0);
1122 if (atomic_dec_and_test(&bo_gem->refcount)) {
1123 drm_intel_bufmgr_gem *bufmgr_gem =
1124 (drm_intel_bufmgr_gem *) bo->bufmgr;
1125 struct timespec time;
1127 clock_gettime(CLOCK_MONOTONIC, &time);
1129 pthread_mutex_lock(&bufmgr_gem->lock);
1130 drm_intel_gem_bo_unreference_final(bo, time.tv_sec);
1131 drm_intel_gem_cleanup_bo_cache(bufmgr_gem, time.tv_sec);
1132 pthread_mutex_unlock(&bufmgr_gem->lock);
1136 static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable)
1138 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1139 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1140 struct drm_i915_gem_set_domain set_domain;
1143 pthread_mutex_lock(&bufmgr_gem->lock);
1145 if (bo_gem->map_count++ == 0)
1146 drm_intel_gem_bo_open_vma(bufmgr_gem, bo_gem);
1148 if (!bo_gem->mem_virtual) {
1149 struct drm_i915_gem_mmap mmap_arg;
1151 DBG("bo_map: %d (%s), map_count=%d\n",
1152 bo_gem->gem_handle, bo_gem->name, bo_gem->map_count);
1155 mmap_arg.handle = bo_gem->gem_handle;
1156 mmap_arg.offset = 0;
1157 mmap_arg.size = bo->size;
1158 ret = drmIoctl(bufmgr_gem->fd,
1159 DRM_IOCTL_I915_GEM_MMAP,
1163 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1164 __FILE__, __LINE__, bo_gem->gem_handle,
1165 bo_gem->name, strerror(errno));
1166 if (--bo_gem->map_count == 0)
1167 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1168 pthread_mutex_unlock(&bufmgr_gem->lock);
1171 VG(VALGRIND_MALLOCLIKE_BLOCK(mmap_arg.addr_ptr, mmap_arg.size, 0, 1));
1172 bo_gem->mem_virtual = (void *)(uintptr_t) mmap_arg.addr_ptr;
1174 DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1175 bo_gem->mem_virtual);
1176 bo->virtual = bo_gem->mem_virtual;
1178 VG_CLEAR(set_domain);
1179 set_domain.handle = bo_gem->gem_handle;
1180 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
1182 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
1184 set_domain.write_domain = 0;
1185 ret = drmIoctl(bufmgr_gem->fd,
1186 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1189 DBG("%s:%d: Error setting to CPU domain %d: %s\n",
1190 __FILE__, __LINE__, bo_gem->gem_handle,
1195 bo_gem->mapped_cpu_write = true;
1197 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1198 VG(VALGRIND_MAKE_MEM_DEFINED(bo_gem->mem_virtual, bo->size));
1199 pthread_mutex_unlock(&bufmgr_gem->lock);
1205 map_gtt(drm_intel_bo *bo)
1207 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1208 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1211 if (bo_gem->map_count++ == 0)
1212 drm_intel_gem_bo_open_vma(bufmgr_gem, bo_gem);
1214 /* Get a mapping of the buffer if we haven't before. */
1215 if (bo_gem->gtt_virtual == NULL) {
1216 struct drm_i915_gem_mmap_gtt mmap_arg;
1218 DBG("bo_map_gtt: mmap %d (%s), map_count=%d\n",
1219 bo_gem->gem_handle, bo_gem->name, bo_gem->map_count);
1222 mmap_arg.handle = bo_gem->gem_handle;
1224 /* Get the fake offset back... */
1225 ret = drmIoctl(bufmgr_gem->fd,
1226 DRM_IOCTL_I915_GEM_MMAP_GTT,
1230 DBG("%s:%d: Error preparing buffer map %d (%s): %s .\n",
1232 bo_gem->gem_handle, bo_gem->name,
1234 if (--bo_gem->map_count == 0)
1235 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1240 bo_gem->gtt_virtual = mmap(0, bo->size, PROT_READ | PROT_WRITE,
1241 MAP_SHARED, bufmgr_gem->fd,
1243 if (bo_gem->gtt_virtual == MAP_FAILED) {
1244 bo_gem->gtt_virtual = NULL;
1246 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1248 bo_gem->gem_handle, bo_gem->name,
1250 if (--bo_gem->map_count == 0)
1251 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1256 bo->virtual = bo_gem->gtt_virtual;
1258 DBG("bo_map_gtt: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1259 bo_gem->gtt_virtual);
1264 int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
1266 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1267 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1268 struct drm_i915_gem_set_domain set_domain;
1271 pthread_mutex_lock(&bufmgr_gem->lock);
1275 pthread_mutex_unlock(&bufmgr_gem->lock);
1279 /* Now move it to the GTT domain so that the GPU and CPU
1280 * caches are flushed and the GPU isn't actively using the
1283 * The pagefault handler does this domain change for us when
1284 * it has unbound the BO from the GTT, but it's up to us to
1285 * tell it when we're about to use things if we had done
1286 * rendering and it still happens to be bound to the GTT.
1288 VG_CLEAR(set_domain);
1289 set_domain.handle = bo_gem->gem_handle;
1290 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1291 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
1292 ret = drmIoctl(bufmgr_gem->fd,
1293 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1296 DBG("%s:%d: Error setting domain %d: %s\n",
1297 __FILE__, __LINE__, bo_gem->gem_handle,
1301 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1302 VG(VALGRIND_MAKE_MEM_DEFINED(bo_gem->gtt_virtual, bo->size));
1303 pthread_mutex_unlock(&bufmgr_gem->lock);
1309 * Performs a mapping of the buffer object like the normal GTT
1310 * mapping, but avoids waiting for the GPU to be done reading from or
1311 * rendering to the buffer.
1313 * This is used in the implementation of GL_ARB_map_buffer_range: The
1314 * user asks to create a buffer, then does a mapping, fills some
1315 * space, runs a drawing command, then asks to map it again without
1316 * synchronizing because it guarantees that it won't write over the
1317 * data that the GPU is busy using (or, more specifically, that if it
1318 * does write over the data, it acknowledges that rendering is
1322 int drm_intel_gem_bo_map_unsynchronized(drm_intel_bo *bo)
1324 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1325 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1328 /* If the CPU cache isn't coherent with the GTT, then use a
1329 * regular synchronized mapping. The problem is that we don't
1330 * track where the buffer was last used on the CPU side in
1331 * terms of drm_intel_bo_map vs drm_intel_gem_bo_map_gtt, so
1332 * we would potentially corrupt the buffer even when the user
1333 * does reasonable things.
1335 if (!bufmgr_gem->has_llc)
1336 return drm_intel_gem_bo_map_gtt(bo);
1338 pthread_mutex_lock(&bufmgr_gem->lock);
1342 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1343 VG(VALGRIND_MAKE_MEM_DEFINED(bo_gem->gtt_virtual, bo->size));
1346 pthread_mutex_unlock(&bufmgr_gem->lock);
1351 static int drm_intel_gem_bo_unmap(drm_intel_bo *bo)
1353 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1354 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1360 pthread_mutex_lock(&bufmgr_gem->lock);
1362 if (bo_gem->map_count <= 0) {
1363 DBG("attempted to unmap an unmapped bo\n");
1364 pthread_mutex_unlock(&bufmgr_gem->lock);
1365 /* Preserve the old behaviour of just treating this as a
1366 * no-op rather than reporting the error.
1371 if (bo_gem->mapped_cpu_write) {
1372 struct drm_i915_gem_sw_finish sw_finish;
1374 /* Cause a flush to happen if the buffer's pinned for
1375 * scanout, so the results show up in a timely manner.
1376 * Unlike GTT set domains, this only does work if the
1377 * buffer should be scanout-related.
1379 VG_CLEAR(sw_finish);
1380 sw_finish.handle = bo_gem->gem_handle;
1381 ret = drmIoctl(bufmgr_gem->fd,
1382 DRM_IOCTL_I915_GEM_SW_FINISH,
1384 ret = ret == -1 ? -errno : 0;
1386 bo_gem->mapped_cpu_write = false;
1389 /* We need to unmap after every innovation as we cannot track
1390 * an open vma for every bo as that will exhaasut the system
1391 * limits and cause later failures.
1393 if (--bo_gem->map_count == 0) {
1394 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1395 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1398 pthread_mutex_unlock(&bufmgr_gem->lock);
1403 int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo)
1405 return drm_intel_gem_bo_unmap(bo);
1409 drm_intel_gem_bo_subdata(drm_intel_bo *bo, unsigned long offset,
1410 unsigned long size, const void *data)
1412 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1413 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1414 struct drm_i915_gem_pwrite pwrite;
1418 pwrite.handle = bo_gem->gem_handle;
1419 pwrite.offset = offset;
1421 pwrite.data_ptr = (uint64_t) (uintptr_t) data;
1422 ret = drmIoctl(bufmgr_gem->fd,
1423 DRM_IOCTL_I915_GEM_PWRITE,
1427 DBG("%s:%d: Error writing data to buffer %d: (%d %d) %s .\n",
1428 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1429 (int)size, strerror(errno));
1436 drm_intel_gem_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id)
1438 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1439 struct drm_i915_get_pipe_from_crtc_id get_pipe_from_crtc_id;
1442 VG_CLEAR(get_pipe_from_crtc_id);
1443 get_pipe_from_crtc_id.crtc_id = crtc_id;
1444 ret = drmIoctl(bufmgr_gem->fd,
1445 DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID,
1446 &get_pipe_from_crtc_id);
1448 /* We return -1 here to signal that we don't
1449 * know which pipe is associated with this crtc.
1450 * This lets the caller know that this information
1451 * isn't available; using the wrong pipe for
1452 * vblank waiting can cause the chipset to lock up
1457 return get_pipe_from_crtc_id.pipe;
1461 drm_intel_gem_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
1462 unsigned long size, void *data)
1464 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1465 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1466 struct drm_i915_gem_pread pread;
1470 pread.handle = bo_gem->gem_handle;
1471 pread.offset = offset;
1473 pread.data_ptr = (uint64_t) (uintptr_t) data;
1474 ret = drmIoctl(bufmgr_gem->fd,
1475 DRM_IOCTL_I915_GEM_PREAD,
1479 DBG("%s:%d: Error reading data from buffer %d: (%d %d) %s .\n",
1480 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1481 (int)size, strerror(errno));
1487 /** Waits for all GPU rendering with the object to have completed. */
1489 drm_intel_gem_bo_wait_rendering(drm_intel_bo *bo)
1491 drm_intel_gem_bo_start_gtt_access(bo, 1);
1495 * Waits on a BO for the given amount of time.
1497 * @bo: buffer object to wait for
1498 * @timeout_ns: amount of time to wait in nanoseconds.
1499 * If value is less than 0, an infinite wait will occur.
1501 * Returns 0 if the wait was successful ie. the last batch referencing the
1502 * object has completed within the allotted time. Otherwise some negative return
1503 * value describes the error. Of particular interest is -ETIME when the wait has
1504 * failed to yield the desired result.
1506 * Similar to drm_intel_gem_bo_wait_rendering except a timeout parameter allows
1507 * the operation to give up after a certain amount of time. Another subtle
1508 * difference is the internal locking semantics are different (this variant does
1509 * not hold the lock for the duration of the wait). This makes the wait subject
1510 * to a larger userspace race window.
1512 * The implementation shall wait until the object is no longer actively
1513 * referenced within a batch buffer at the time of the call. The wait will
1514 * not guarantee that the buffer is re-issued via another thread, or an flinked
1515 * handle. Userspace must make sure this race does not occur if such precision
1518 int drm_intel_gem_bo_wait(drm_intel_bo *bo, int64_t timeout_ns)
1520 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1521 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1522 struct drm_i915_gem_wait wait;
1525 if (!bufmgr_gem->has_wait_timeout) {
1526 DBG("%s:%d: Timed wait is not supported. Falling back to "
1527 "infinite wait\n", __FILE__, __LINE__);
1529 drm_intel_gem_bo_wait_rendering(bo);
1532 return drm_intel_gem_bo_busy(bo) ? -ETIME : 0;
1536 wait.bo_handle = bo_gem->gem_handle;
1537 wait.timeout_ns = timeout_ns;
1539 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_WAIT, &wait);
1547 * Sets the object to the GTT read and possibly write domain, used by the X
1548 * 2D driver in the absence of kernel support to do drm_intel_gem_bo_map_gtt().
1550 * In combination with drm_intel_gem_bo_pin() and manual fence management, we
1551 * can do tiled pixmaps this way.
1554 drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable)
1556 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1557 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1558 struct drm_i915_gem_set_domain set_domain;
1561 VG_CLEAR(set_domain);
1562 set_domain.handle = bo_gem->gem_handle;
1563 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1564 set_domain.write_domain = write_enable ? I915_GEM_DOMAIN_GTT : 0;
1565 ret = drmIoctl(bufmgr_gem->fd,
1566 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1569 DBG("%s:%d: Error setting memory domains %d (%08x %08x): %s .\n",
1570 __FILE__, __LINE__, bo_gem->gem_handle,
1571 set_domain.read_domains, set_domain.write_domain,
1577 drm_intel_bufmgr_gem_destroy(drm_intel_bufmgr *bufmgr)
1579 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1582 free(bufmgr_gem->exec2_objects);
1583 free(bufmgr_gem->exec_objects);
1584 free(bufmgr_gem->exec_bos);
1585 free(bufmgr_gem->aub_filename);
1587 pthread_mutex_destroy(&bufmgr_gem->lock);
1589 /* Free any cached buffer objects we were going to reuse */
1590 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
1591 struct drm_intel_gem_bo_bucket *bucket =
1592 &bufmgr_gem->cache_bucket[i];
1593 drm_intel_bo_gem *bo_gem;
1595 while (!DRMLISTEMPTY(&bucket->head)) {
1596 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1597 bucket->head.next, head);
1598 DRMLISTDEL(&bo_gem->head);
1600 drm_intel_gem_bo_free(&bo_gem->bo);
1608 * Adds the target buffer to the validation list and adds the relocation
1609 * to the reloc_buffer's relocation list.
1611 * The relocation entry at the given offset must already contain the
1612 * precomputed relocation value, because the kernel will optimize out
1613 * the relocation entry write when the buffer hasn't moved from the
1614 * last known offset in target_bo.
1617 do_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1618 drm_intel_bo *target_bo, uint32_t target_offset,
1619 uint32_t read_domains, uint32_t write_domain,
1622 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1623 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1624 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
1625 bool fenced_command;
1627 if (bo_gem->has_error)
1630 if (target_bo_gem->has_error) {
1631 bo_gem->has_error = true;
1635 /* We never use HW fences for rendering on 965+ */
1636 if (bufmgr_gem->gen >= 4)
1639 fenced_command = need_fence;
1640 if (target_bo_gem->tiling_mode == I915_TILING_NONE)
1643 /* Create a new relocation list if needed */
1644 if (bo_gem->relocs == NULL && drm_intel_setup_reloc_list(bo))
1647 /* Check overflow */
1648 assert(bo_gem->reloc_count < bufmgr_gem->max_relocs);
1651 assert(offset <= bo->size - 4);
1652 assert((write_domain & (write_domain - 1)) == 0);
1654 /* Make sure that we're not adding a reloc to something whose size has
1655 * already been accounted for.
1657 assert(!bo_gem->used_as_reloc_target);
1658 if (target_bo_gem != bo_gem) {
1659 target_bo_gem->used_as_reloc_target = true;
1660 bo_gem->reloc_tree_size += target_bo_gem->reloc_tree_size;
1662 /* An object needing a fence is a tiled buffer, so it won't have
1663 * relocs to other buffers.
1666 target_bo_gem->reloc_tree_fences = 1;
1667 bo_gem->reloc_tree_fences += target_bo_gem->reloc_tree_fences;
1669 bo_gem->relocs[bo_gem->reloc_count].offset = offset;
1670 bo_gem->relocs[bo_gem->reloc_count].delta = target_offset;
1671 bo_gem->relocs[bo_gem->reloc_count].target_handle =
1672 target_bo_gem->gem_handle;
1673 bo_gem->relocs[bo_gem->reloc_count].read_domains = read_domains;
1674 bo_gem->relocs[bo_gem->reloc_count].write_domain = write_domain;
1675 bo_gem->relocs[bo_gem->reloc_count].presumed_offset = target_bo->offset;
1677 bo_gem->reloc_target_info[bo_gem->reloc_count].bo = target_bo;
1678 if (target_bo != bo)
1679 drm_intel_gem_bo_reference(target_bo);
1681 bo_gem->reloc_target_info[bo_gem->reloc_count].flags =
1682 DRM_INTEL_RELOC_FENCE;
1684 bo_gem->reloc_target_info[bo_gem->reloc_count].flags = 0;
1686 bo_gem->reloc_count++;
1692 drm_intel_gem_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1693 drm_intel_bo *target_bo, uint32_t target_offset,
1694 uint32_t read_domains, uint32_t write_domain)
1696 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1698 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1699 read_domains, write_domain,
1700 !bufmgr_gem->fenced_relocs);
1704 drm_intel_gem_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
1705 drm_intel_bo *target_bo,
1706 uint32_t target_offset,
1707 uint32_t read_domains, uint32_t write_domain)
1709 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1710 read_domains, write_domain, true);
1714 drm_intel_gem_bo_get_reloc_count(drm_intel_bo *bo)
1716 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1718 return bo_gem->reloc_count;
1722 * Removes existing relocation entries in the BO after "start".
1724 * This allows a user to avoid a two-step process for state setup with
1725 * counting up all the buffer objects and doing a
1726 * drm_intel_bufmgr_check_aperture_space() before emitting any of the
1727 * relocations for the state setup. Instead, save the state of the
1728 * batchbuffer including drm_intel_gem_get_reloc_count(), emit all the
1729 * state, and then check if it still fits in the aperture.
1731 * Any further drm_intel_bufmgr_check_aperture_space() queries
1732 * involving this buffer in the tree are undefined after this call.
1735 drm_intel_gem_bo_clear_relocs(drm_intel_bo *bo, int start)
1737 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1739 struct timespec time;
1741 clock_gettime(CLOCK_MONOTONIC, &time);
1743 assert(bo_gem->reloc_count >= start);
1744 /* Unreference the cleared target buffers */
1745 for (i = start; i < bo_gem->reloc_count; i++) {
1746 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) bo_gem->reloc_target_info[i].bo;
1747 if (&target_bo_gem->bo != bo) {
1748 bo_gem->reloc_tree_fences -= target_bo_gem->reloc_tree_fences;
1749 drm_intel_gem_bo_unreference_locked_timed(&target_bo_gem->bo,
1753 bo_gem->reloc_count = start;
1757 * Walk the tree of relocations rooted at BO and accumulate the list of
1758 * validations to be performed and update the relocation buffers with
1759 * index values into the validation list.
1762 drm_intel_gem_bo_process_reloc(drm_intel_bo *bo)
1764 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1767 if (bo_gem->relocs == NULL)
1770 for (i = 0; i < bo_gem->reloc_count; i++) {
1771 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1773 if (target_bo == bo)
1776 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1778 /* Continue walking the tree depth-first. */
1779 drm_intel_gem_bo_process_reloc(target_bo);
1781 /* Add the target to the validate list */
1782 drm_intel_add_validate_buffer(target_bo);
1787 drm_intel_gem_bo_process_reloc2(drm_intel_bo *bo)
1789 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1792 if (bo_gem->relocs == NULL)
1795 for (i = 0; i < bo_gem->reloc_count; i++) {
1796 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1799 if (target_bo == bo)
1802 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1804 /* Continue walking the tree depth-first. */
1805 drm_intel_gem_bo_process_reloc2(target_bo);
1807 need_fence = (bo_gem->reloc_target_info[i].flags &
1808 DRM_INTEL_RELOC_FENCE);
1810 /* Add the target to the validate list */
1811 drm_intel_add_validate_buffer2(target_bo, need_fence);
1817 drm_intel_update_buffer_offsets(drm_intel_bufmgr_gem *bufmgr_gem)
1821 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1822 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1823 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1825 /* Update the buffer offset */
1826 if (bufmgr_gem->exec_objects[i].offset != bo->offset) {
1827 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1828 bo_gem->gem_handle, bo_gem->name, bo->offset,
1829 (unsigned long long)bufmgr_gem->exec_objects[i].
1831 bo->offset = bufmgr_gem->exec_objects[i].offset;
1837 drm_intel_update_buffer_offsets2 (drm_intel_bufmgr_gem *bufmgr_gem)
1841 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1842 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1843 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1845 /* Update the buffer offset */
1846 if (bufmgr_gem->exec2_objects[i].offset != bo->offset) {
1847 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1848 bo_gem->gem_handle, bo_gem->name, bo->offset,
1849 (unsigned long long)bufmgr_gem->exec2_objects[i].offset);
1850 bo->offset = bufmgr_gem->exec2_objects[i].offset;
1856 aub_out(drm_intel_bufmgr_gem *bufmgr_gem, uint32_t data)
1858 fwrite(&data, 1, 4, bufmgr_gem->aub_file);
1862 aub_out_data(drm_intel_bufmgr_gem *bufmgr_gem, void *data, size_t size)
1864 fwrite(data, 1, size, bufmgr_gem->aub_file);
1868 aub_write_bo_data(drm_intel_bo *bo, uint32_t offset, uint32_t size)
1870 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1871 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1875 data = malloc(bo->size);
1876 drm_intel_bo_get_subdata(bo, offset, size, data);
1878 /* Easy mode: write out bo with no relocations */
1879 if (!bo_gem->reloc_count) {
1880 aub_out_data(bufmgr_gem, data, size);
1885 /* Otherwise, handle the relocations while writing. */
1886 for (i = 0; i < size / 4; i++) {
1888 for (r = 0; r < bo_gem->reloc_count; r++) {
1889 struct drm_i915_gem_relocation_entry *reloc;
1890 drm_intel_reloc_target *info;
1892 reloc = &bo_gem->relocs[r];
1893 info = &bo_gem->reloc_target_info[r];
1895 if (reloc->offset == offset + i * 4) {
1896 drm_intel_bo_gem *target_gem;
1899 target_gem = (drm_intel_bo_gem *)info->bo;
1902 val += target_gem->aub_offset;
1904 aub_out(bufmgr_gem, val);
1909 if (r == bo_gem->reloc_count) {
1910 /* no relocation, just the data */
1911 aub_out(bufmgr_gem, data[i]);
1919 aub_bo_get_address(drm_intel_bo *bo)
1921 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1922 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1924 /* Give the object a graphics address in the AUB file. We
1925 * don't just use the GEM object address because we do AUB
1926 * dumping before execution -- we want to successfully log
1927 * when the hardware might hang, and we might even want to aub
1928 * capture for a driver trying to execute on a different
1929 * generation of hardware by disabling the actual kernel exec
1932 bo_gem->aub_offset = bufmgr_gem->aub_offset;
1933 bufmgr_gem->aub_offset += bo->size;
1934 /* XXX: Handle aperture overflow. */
1935 assert(bufmgr_gem->aub_offset < 256 * 1024 * 1024);
1939 aub_write_trace_block(drm_intel_bo *bo, uint32_t type, uint32_t subtype,
1940 uint32_t offset, uint32_t size)
1942 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1943 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1946 CMD_AUB_TRACE_HEADER_BLOCK |
1947 ((bufmgr_gem->gen >= 8 ? 6 : 5) - 2));
1949 AUB_TRACE_MEMTYPE_GTT | type | AUB_TRACE_OP_DATA_WRITE);
1950 aub_out(bufmgr_gem, subtype);
1951 aub_out(bufmgr_gem, bo_gem->aub_offset + offset);
1952 aub_out(bufmgr_gem, size);
1953 if (bufmgr_gem->gen >= 8)
1954 aub_out(bufmgr_gem, 0);
1955 aub_write_bo_data(bo, offset, size);
1959 * Break up large objects into multiple writes. Otherwise a 128kb VBO
1960 * would overflow the 16 bits of size field in the packet header and
1961 * everything goes badly after that.
1964 aub_write_large_trace_block(drm_intel_bo *bo, uint32_t type, uint32_t subtype,
1965 uint32_t offset, uint32_t size)
1967 uint32_t block_size;
1968 uint32_t sub_offset;
1970 for (sub_offset = 0; sub_offset < size; sub_offset += block_size) {
1971 block_size = size - sub_offset;
1973 if (block_size > 8 * 4096)
1974 block_size = 8 * 4096;
1976 aub_write_trace_block(bo, type, subtype, offset + sub_offset,
1982 aub_write_bo(drm_intel_bo *bo)
1984 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1985 uint32_t offset = 0;
1988 aub_bo_get_address(bo);
1990 /* Write out each annotated section separately. */
1991 for (i = 0; i < bo_gem->aub_annotation_count; ++i) {
1992 drm_intel_aub_annotation *annotation =
1993 &bo_gem->aub_annotations[i];
1994 uint32_t ending_offset = annotation->ending_offset;
1995 if (ending_offset > bo->size)
1996 ending_offset = bo->size;
1997 if (ending_offset > offset) {
1998 aub_write_large_trace_block(bo, annotation->type,
1999 annotation->subtype,
2001 ending_offset - offset);
2002 offset = ending_offset;
2006 /* Write out any remaining unannotated data */
2007 if (offset < bo->size) {
2008 aub_write_large_trace_block(bo, AUB_TRACE_TYPE_NOTYPE, 0,
2009 offset, bo->size - offset);
2014 * Make a ringbuffer on fly and dump it
2017 aub_build_dump_ringbuffer(drm_intel_bufmgr_gem *bufmgr_gem,
2018 uint32_t batch_buffer, int ring_flag)
2020 uint32_t ringbuffer[4096];
2021 int ring = AUB_TRACE_TYPE_RING_PRB0; /* The default ring */
2024 if (ring_flag == I915_EXEC_BSD)
2025 ring = AUB_TRACE_TYPE_RING_PRB1;
2026 else if (ring_flag == I915_EXEC_BLT)
2027 ring = AUB_TRACE_TYPE_RING_PRB2;
2029 /* Make a ring buffer to execute our batchbuffer. */
2030 memset(ringbuffer, 0, sizeof(ringbuffer));
2031 ringbuffer[ring_count++] = AUB_MI_BATCH_BUFFER_START;
2032 ringbuffer[ring_count++] = batch_buffer;
2034 /* Write out the ring. This appears to trigger execution of
2035 * the ring in the simulator.
2038 CMD_AUB_TRACE_HEADER_BLOCK |
2039 ((bufmgr_gem->gen >= 8 ? 6 : 5) - 2));
2041 AUB_TRACE_MEMTYPE_GTT | ring | AUB_TRACE_OP_COMMAND_WRITE);
2042 aub_out(bufmgr_gem, 0); /* general/surface subtype */
2043 aub_out(bufmgr_gem, bufmgr_gem->aub_offset);
2044 aub_out(bufmgr_gem, ring_count * 4);
2045 if (bufmgr_gem->gen >= 8)
2046 aub_out(bufmgr_gem, 0);
2048 /* FIXME: Need some flush operations here? */
2049 aub_out_data(bufmgr_gem, ringbuffer, ring_count * 4);
2051 /* Update offset pointer */
2052 bufmgr_gem->aub_offset += 4096;
2056 drm_intel_gem_bo_aub_dump_bmp(drm_intel_bo *bo,
2057 int x1, int y1, int width, int height,
2058 enum aub_dump_bmp_format format,
2059 int pitch, int offset)
2061 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2062 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
2066 case AUB_DUMP_BMP_FORMAT_8BIT:
2069 case AUB_DUMP_BMP_FORMAT_ARGB_4444:
2072 case AUB_DUMP_BMP_FORMAT_ARGB_0888:
2073 case AUB_DUMP_BMP_FORMAT_ARGB_8888:
2077 printf("Unknown AUB dump format %d\n", format);
2081 if (!bufmgr_gem->aub_file)
2084 aub_out(bufmgr_gem, CMD_AUB_DUMP_BMP | 4);
2085 aub_out(bufmgr_gem, (y1 << 16) | x1);
2090 aub_out(bufmgr_gem, (height << 16) | width);
2091 aub_out(bufmgr_gem, bo_gem->aub_offset + offset);
2093 ((bo_gem->tiling_mode != I915_TILING_NONE) ? (1 << 2) : 0) |
2094 ((bo_gem->tiling_mode == I915_TILING_Y) ? (1 << 3) : 0));
2098 aub_exec(drm_intel_bo *bo, int ring_flag, int used)
2100 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2101 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2103 bool batch_buffer_needs_annotations;
2105 if (!bufmgr_gem->aub_file)
2108 /* If batch buffer is not annotated, annotate it the best we
2111 batch_buffer_needs_annotations = bo_gem->aub_annotation_count == 0;
2112 if (batch_buffer_needs_annotations) {
2113 drm_intel_aub_annotation annotations[2] = {
2114 { AUB_TRACE_TYPE_BATCH, 0, used },
2115 { AUB_TRACE_TYPE_NOTYPE, 0, bo->size }
2117 drm_intel_bufmgr_gem_set_aub_annotations(bo, annotations, 2);
2120 /* Write out all buffers to AUB memory */
2121 for (i = 0; i < bufmgr_gem->exec_count; i++) {
2122 aub_write_bo(bufmgr_gem->exec_bos[i]);
2125 /* Remove any annotations we added */
2126 if (batch_buffer_needs_annotations)
2127 drm_intel_bufmgr_gem_set_aub_annotations(bo, NULL, 0);
2129 /* Dump ring buffer */
2130 aub_build_dump_ringbuffer(bufmgr_gem, bo_gem->aub_offset, ring_flag);
2132 fflush(bufmgr_gem->aub_file);
2135 * One frame has been dumped. So reset the aub_offset for the next frame.
2137 * FIXME: Can we do this?
2139 bufmgr_gem->aub_offset = 0x10000;
2143 drm_intel_gem_bo_exec(drm_intel_bo *bo, int used,
2144 drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
2146 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2147 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2148 struct drm_i915_gem_execbuffer execbuf;
2151 if (bo_gem->has_error)
2154 pthread_mutex_lock(&bufmgr_gem->lock);
2155 /* Update indices and set up the validate list. */
2156 drm_intel_gem_bo_process_reloc(bo);
2158 /* Add the batch buffer to the validation list. There are no
2159 * relocations pointing to it.
2161 drm_intel_add_validate_buffer(bo);
2164 execbuf.buffers_ptr = (uintptr_t) bufmgr_gem->exec_objects;
2165 execbuf.buffer_count = bufmgr_gem->exec_count;
2166 execbuf.batch_start_offset = 0;
2167 execbuf.batch_len = used;
2168 execbuf.cliprects_ptr = (uintptr_t) cliprects;
2169 execbuf.num_cliprects = num_cliprects;
2173 ret = drmIoctl(bufmgr_gem->fd,
2174 DRM_IOCTL_I915_GEM_EXECBUFFER,
2178 if (errno == ENOSPC) {
2179 DBG("Execbuffer fails to pin. "
2180 "Estimate: %u. Actual: %u. Available: %u\n",
2181 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
2184 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
2187 (unsigned int)bufmgr_gem->gtt_size);
2190 drm_intel_update_buffer_offsets(bufmgr_gem);
2192 if (bufmgr_gem->bufmgr.debug)
2193 drm_intel_gem_dump_validation_list(bufmgr_gem);
2195 for (i = 0; i < bufmgr_gem->exec_count; i++) {
2196 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
2197 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2199 /* Disconnect the buffer from the validate list */
2200 bo_gem->validate_index = -1;
2201 bufmgr_gem->exec_bos[i] = NULL;
2203 bufmgr_gem->exec_count = 0;
2204 pthread_mutex_unlock(&bufmgr_gem->lock);
2210 do_exec2(drm_intel_bo *bo, int used, drm_intel_context *ctx,
2211 drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
2214 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
2215 struct drm_i915_gem_execbuffer2 execbuf;
2219 switch (flags & 0x7) {
2223 if (!bufmgr_gem->has_blt)
2227 if (!bufmgr_gem->has_bsd)
2230 case I915_EXEC_VEBOX:
2231 if (!bufmgr_gem->has_vebox)
2234 case I915_EXEC_RENDER:
2235 case I915_EXEC_DEFAULT:
2239 pthread_mutex_lock(&bufmgr_gem->lock);
2240 /* Update indices and set up the validate list. */
2241 drm_intel_gem_bo_process_reloc2(bo);
2243 /* Add the batch buffer to the validation list. There are no relocations
2246 drm_intel_add_validate_buffer2(bo, 0);
2249 execbuf.buffers_ptr = (uintptr_t)bufmgr_gem->exec2_objects;
2250 execbuf.buffer_count = bufmgr_gem->exec_count;
2251 execbuf.batch_start_offset = 0;
2252 execbuf.batch_len = used;
2253 execbuf.cliprects_ptr = (uintptr_t)cliprects;
2254 execbuf.num_cliprects = num_cliprects;
2257 execbuf.flags = flags;
2259 i915_execbuffer2_set_context_id(execbuf, 0);
2261 i915_execbuffer2_set_context_id(execbuf, ctx->ctx_id);
2264 aub_exec(bo, flags, used);
2266 if (bufmgr_gem->no_exec)
2267 goto skip_execution;
2269 ret = drmIoctl(bufmgr_gem->fd,
2270 DRM_IOCTL_I915_GEM_EXECBUFFER2,
2274 if (ret == -ENOSPC) {
2275 DBG("Execbuffer fails to pin. "
2276 "Estimate: %u. Actual: %u. Available: %u\n",
2277 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
2278 bufmgr_gem->exec_count),
2279 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
2280 bufmgr_gem->exec_count),
2281 (unsigned int) bufmgr_gem->gtt_size);
2284 drm_intel_update_buffer_offsets2(bufmgr_gem);
2287 if (bufmgr_gem->bufmgr.debug)
2288 drm_intel_gem_dump_validation_list(bufmgr_gem);
2290 for (i = 0; i < bufmgr_gem->exec_count; i++) {
2291 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
2292 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
2294 /* Disconnect the buffer from the validate list */
2295 bo_gem->validate_index = -1;
2296 bufmgr_gem->exec_bos[i] = NULL;
2298 bufmgr_gem->exec_count = 0;
2299 pthread_mutex_unlock(&bufmgr_gem->lock);
2305 drm_intel_gem_bo_exec2(drm_intel_bo *bo, int used,
2306 drm_clip_rect_t *cliprects, int num_cliprects,
2309 return do_exec2(bo, used, NULL, cliprects, num_cliprects, DR4,
2314 drm_intel_gem_bo_mrb_exec2(drm_intel_bo *bo, int used,
2315 drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
2318 return do_exec2(bo, used, NULL, cliprects, num_cliprects, DR4,
2323 drm_intel_gem_bo_context_exec(drm_intel_bo *bo, drm_intel_context *ctx,
2324 int used, unsigned int flags)
2326 return do_exec2(bo, used, ctx, NULL, 0, 0, flags);
2330 drm_intel_gem_bo_pin(drm_intel_bo *bo, uint32_t alignment)
2332 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2333 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2334 struct drm_i915_gem_pin pin;
2338 pin.handle = bo_gem->gem_handle;
2339 pin.alignment = alignment;
2341 ret = drmIoctl(bufmgr_gem->fd,
2342 DRM_IOCTL_I915_GEM_PIN,
2347 bo->offset = pin.offset;
2352 drm_intel_gem_bo_unpin(drm_intel_bo *bo)
2354 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2355 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2356 struct drm_i915_gem_unpin unpin;
2360 unpin.handle = bo_gem->gem_handle;
2362 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_UNPIN, &unpin);
2370 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
2371 uint32_t tiling_mode,
2374 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2375 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2376 struct drm_i915_gem_set_tiling set_tiling;
2379 if (bo_gem->global_name == 0 &&
2380 tiling_mode == bo_gem->tiling_mode &&
2381 stride == bo_gem->stride)
2384 memset(&set_tiling, 0, sizeof(set_tiling));
2386 /* set_tiling is slightly broken and overwrites the
2387 * input on the error path, so we have to open code
2390 set_tiling.handle = bo_gem->gem_handle;
2391 set_tiling.tiling_mode = tiling_mode;
2392 set_tiling.stride = stride;
2394 ret = ioctl(bufmgr_gem->fd,
2395 DRM_IOCTL_I915_GEM_SET_TILING,
2397 } while (ret == -1 && (errno == EINTR || errno == EAGAIN));
2401 bo_gem->tiling_mode = set_tiling.tiling_mode;
2402 bo_gem->swizzle_mode = set_tiling.swizzle_mode;
2403 bo_gem->stride = set_tiling.stride;
2408 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
2411 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2412 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2415 /* Linear buffers have no stride. By ensuring that we only ever use
2416 * stride 0 with linear buffers, we simplify our code.
2418 if (*tiling_mode == I915_TILING_NONE)
2421 ret = drm_intel_gem_bo_set_tiling_internal(bo, *tiling_mode, stride);
2423 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
2425 *tiling_mode = bo_gem->tiling_mode;
2430 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
2431 uint32_t * swizzle_mode)
2433 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2435 *tiling_mode = bo_gem->tiling_mode;
2436 *swizzle_mode = bo_gem->swizzle_mode;
2441 drm_intel_bo_gem_create_from_prime(drm_intel_bufmgr *bufmgr, int prime_fd, int size)
2443 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
2446 drm_intel_bo_gem *bo_gem;
2447 struct drm_i915_gem_get_tiling get_tiling;
2449 ret = drmPrimeFDToHandle(bufmgr_gem->fd, prime_fd, &handle);
2451 fprintf(stderr,"ret is %d %d\n", ret, errno);
2455 bo_gem = calloc(1, sizeof(*bo_gem));
2459 /* Determine size of bo. The fd-to-handle ioctl really should
2460 * return the size, but it doesn't. If we have kernel 3.12 or
2461 * later, we can lseek on the prime fd to get the size. Older
2462 * kernels will just fail, in which case we fall back to the
2463 * provided (estimated or guess size). */
2464 ret = lseek(prime_fd, 0, SEEK_END);
2466 bo_gem->bo.size = ret;
2468 bo_gem->bo.size = size;
2470 bo_gem->bo.handle = handle;
2471 bo_gem->bo.bufmgr = bufmgr;
2473 bo_gem->gem_handle = handle;
2475 atomic_set(&bo_gem->refcount, 1);
2477 bo_gem->name = "prime";
2478 bo_gem->validate_index = -1;
2479 bo_gem->reloc_tree_fences = 0;
2480 bo_gem->used_as_reloc_target = false;
2481 bo_gem->has_error = false;
2482 bo_gem->reusable = false;
2484 DRMINITLISTHEAD(&bo_gem->name_list);
2485 DRMINITLISTHEAD(&bo_gem->vma_list);
2487 VG_CLEAR(get_tiling);
2488 get_tiling.handle = bo_gem->gem_handle;
2489 ret = drmIoctl(bufmgr_gem->fd,
2490 DRM_IOCTL_I915_GEM_GET_TILING,
2493 drm_intel_gem_bo_unreference(&bo_gem->bo);
2496 bo_gem->tiling_mode = get_tiling.tiling_mode;
2497 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
2498 /* XXX stride is unknown */
2499 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
2505 drm_intel_bo_gem_export_to_prime(drm_intel_bo *bo, int *prime_fd)
2507 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2508 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2510 if (drmPrimeHandleToFD(bufmgr_gem->fd, bo_gem->gem_handle,
2511 DRM_CLOEXEC, prime_fd) != 0)
2514 bo_gem->reusable = false;
2520 drm_intel_gem_bo_flink(drm_intel_bo *bo, uint32_t * name)
2522 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2523 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2526 if (!bo_gem->global_name) {
2527 struct drm_gem_flink flink;
2530 flink.handle = bo_gem->gem_handle;
2532 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_FLINK, &flink);
2536 bo_gem->global_name = flink.name;
2537 bo_gem->reusable = false;
2539 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
2542 *name = bo_gem->global_name;
2547 * Enables unlimited caching of buffer objects for reuse.
2549 * This is potentially very memory expensive, as the cache at each bucket
2550 * size is only bounded by how many buffers of that size we've managed to have
2551 * in flight at once.
2554 drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr)
2556 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
2558 bufmgr_gem->bo_reuse = true;
2562 * Enable use of fenced reloc type.
2564 * New code should enable this to avoid unnecessary fence register
2565 * allocation. If this option is not enabled, all relocs will have fence
2566 * register allocated.
2569 drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr)
2571 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
2573 if (bufmgr_gem->bufmgr.bo_exec == drm_intel_gem_bo_exec2)
2574 bufmgr_gem->fenced_relocs = true;
2578 * Return the additional aperture space required by the tree of buffer objects
2582 drm_intel_gem_bo_get_aperture_space(drm_intel_bo *bo)
2584 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2588 if (bo == NULL || bo_gem->included_in_check_aperture)
2592 bo_gem->included_in_check_aperture = true;
2594 for (i = 0; i < bo_gem->reloc_count; i++)
2596 drm_intel_gem_bo_get_aperture_space(bo_gem->
2597 reloc_target_info[i].bo);
2603 * Count the number of buffers in this list that need a fence reg
2605 * If the count is greater than the number of available regs, we'll have
2606 * to ask the caller to resubmit a batch with fewer tiled buffers.
2608 * This function over-counts if the same buffer is used multiple times.
2611 drm_intel_gem_total_fences(drm_intel_bo ** bo_array, int count)
2614 unsigned int total = 0;
2616 for (i = 0; i < count; i++) {
2617 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
2622 total += bo_gem->reloc_tree_fences;
2628 * Clear the flag set by drm_intel_gem_bo_get_aperture_space() so we're ready
2629 * for the next drm_intel_bufmgr_check_aperture_space() call.
2632 drm_intel_gem_bo_clear_aperture_space_flag(drm_intel_bo *bo)
2634 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2637 if (bo == NULL || !bo_gem->included_in_check_aperture)
2640 bo_gem->included_in_check_aperture = false;
2642 for (i = 0; i < bo_gem->reloc_count; i++)
2643 drm_intel_gem_bo_clear_aperture_space_flag(bo_gem->
2644 reloc_target_info[i].bo);
2648 * Return a conservative estimate for the amount of aperture required
2649 * for a collection of buffers. This may double-count some buffers.
2652 drm_intel_gem_estimate_batch_space(drm_intel_bo **bo_array, int count)
2655 unsigned int total = 0;
2657 for (i = 0; i < count; i++) {
2658 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
2660 total += bo_gem->reloc_tree_size;
2666 * Return the amount of aperture needed for a collection of buffers.
2667 * This avoids double counting any buffers, at the cost of looking
2668 * at every buffer in the set.
2671 drm_intel_gem_compute_batch_space(drm_intel_bo **bo_array, int count)
2674 unsigned int total = 0;
2676 for (i = 0; i < count; i++) {
2677 total += drm_intel_gem_bo_get_aperture_space(bo_array[i]);
2678 /* For the first buffer object in the array, we get an
2679 * accurate count back for its reloc_tree size (since nothing
2680 * had been flagged as being counted yet). We can save that
2681 * value out as a more conservative reloc_tree_size that
2682 * avoids double-counting target buffers. Since the first
2683 * buffer happens to usually be the batch buffer in our
2684 * callers, this can pull us back from doing the tree
2685 * walk on every new batch emit.
2688 drm_intel_bo_gem *bo_gem =
2689 (drm_intel_bo_gem *) bo_array[i];
2690 bo_gem->reloc_tree_size = total;
2694 for (i = 0; i < count; i++)
2695 drm_intel_gem_bo_clear_aperture_space_flag(bo_array[i]);
2700 * Return -1 if the batchbuffer should be flushed before attempting to
2701 * emit rendering referencing the buffers pointed to by bo_array.
2703 * This is required because if we try to emit a batchbuffer with relocations
2704 * to a tree of buffers that won't simultaneously fit in the aperture,
2705 * the rendering will return an error at a point where the software is not
2706 * prepared to recover from it.
2708 * However, we also want to emit the batchbuffer significantly before we reach
2709 * the limit, as a series of batchbuffers each of which references buffers
2710 * covering almost all of the aperture means that at each emit we end up
2711 * waiting to evict a buffer from the last rendering, and we get synchronous
2712 * performance. By emitting smaller batchbuffers, we eat some CPU overhead to
2713 * get better parallelism.
2716 drm_intel_gem_check_aperture_space(drm_intel_bo **bo_array, int count)
2718 drm_intel_bufmgr_gem *bufmgr_gem =
2719 (drm_intel_bufmgr_gem *) bo_array[0]->bufmgr;
2720 unsigned int total = 0;
2721 unsigned int threshold = bufmgr_gem->gtt_size * 3 / 4;
2724 /* Check for fence reg constraints if necessary */
2725 if (bufmgr_gem->available_fences) {
2726 total_fences = drm_intel_gem_total_fences(bo_array, count);
2727 if (total_fences > bufmgr_gem->available_fences)
2731 total = drm_intel_gem_estimate_batch_space(bo_array, count);
2733 if (total > threshold)
2734 total = drm_intel_gem_compute_batch_space(bo_array, count);
2736 if (total > threshold) {
2737 DBG("check_space: overflowed available aperture, "
2739 total / 1024, (int)bufmgr_gem->gtt_size / 1024);
2742 DBG("drm_check_space: total %dkb vs bufgr %dkb\n", total / 1024,
2743 (int)bufmgr_gem->gtt_size / 1024);
2749 * Disable buffer reuse for objects which are shared with the kernel
2750 * as scanout buffers
2753 drm_intel_gem_bo_disable_reuse(drm_intel_bo *bo)
2755 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2757 bo_gem->reusable = false;
2762 drm_intel_gem_bo_is_reusable(drm_intel_bo *bo)
2764 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2766 return bo_gem->reusable;
2770 _drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
2772 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2775 for (i = 0; i < bo_gem->reloc_count; i++) {
2776 if (bo_gem->reloc_target_info[i].bo == target_bo)
2778 if (bo == bo_gem->reloc_target_info[i].bo)
2780 if (_drm_intel_gem_bo_references(bo_gem->reloc_target_info[i].bo,
2788 /** Return true if target_bo is referenced by bo's relocation tree. */
2790 drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
2792 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
2794 if (bo == NULL || target_bo == NULL)
2796 if (target_bo_gem->used_as_reloc_target)
2797 return _drm_intel_gem_bo_references(bo, target_bo);
2802 add_bucket(drm_intel_bufmgr_gem *bufmgr_gem, int size)
2804 unsigned int i = bufmgr_gem->num_buckets;
2806 assert(i < ARRAY_SIZE(bufmgr_gem->cache_bucket));
2808 DRMINITLISTHEAD(&bufmgr_gem->cache_bucket[i].head);
2809 bufmgr_gem->cache_bucket[i].size = size;
2810 bufmgr_gem->num_buckets++;
2814 init_cache_buckets(drm_intel_bufmgr_gem *bufmgr_gem)
2816 unsigned long size, cache_max_size = 64 * 1024 * 1024;
2818 /* OK, so power of two buckets was too wasteful of memory.
2819 * Give 3 other sizes between each power of two, to hopefully
2820 * cover things accurately enough. (The alternative is
2821 * probably to just go for exact matching of sizes, and assume
2822 * that for things like composited window resize the tiled
2823 * width/height alignment and rounding of sizes to pages will
2824 * get us useful cache hit rates anyway)
2826 add_bucket(bufmgr_gem, 4096);
2827 add_bucket(bufmgr_gem, 4096 * 2);
2828 add_bucket(bufmgr_gem, 4096 * 3);
2830 /* Initialize the linked lists for BO reuse cache. */
2831 for (size = 4 * 4096; size <= cache_max_size; size *= 2) {
2832 add_bucket(bufmgr_gem, size);
2834 add_bucket(bufmgr_gem, size + size * 1 / 4);
2835 add_bucket(bufmgr_gem, size + size * 2 / 4);
2836 add_bucket(bufmgr_gem, size + size * 3 / 4);
2841 drm_intel_bufmgr_gem_set_vma_cache_size(drm_intel_bufmgr *bufmgr, int limit)
2843 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
2845 bufmgr_gem->vma_max = limit;
2847 drm_intel_gem_bo_purge_vma_cache(bufmgr_gem);
2851 * Get the PCI ID for the device. This can be overridden by setting the
2852 * INTEL_DEVID_OVERRIDE environment variable to the desired ID.
2855 get_pci_device_id(drm_intel_bufmgr_gem *bufmgr_gem)
2857 char *devid_override;
2860 drm_i915_getparam_t gp;
2862 if (geteuid() == getuid()) {
2863 devid_override = getenv("INTEL_DEVID_OVERRIDE");
2864 if (devid_override) {
2865 bufmgr_gem->no_exec = true;
2866 return strtod(devid_override, NULL);
2872 gp.param = I915_PARAM_CHIPSET_ID;
2874 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2876 fprintf(stderr, "get chip id failed: %d [%d]\n", ret, errno);
2877 fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value);
2883 drm_intel_bufmgr_gem_get_devid(drm_intel_bufmgr *bufmgr)
2885 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
2887 return bufmgr_gem->pci_device;
2891 * Sets the AUB filename.
2893 * This function has to be called before drm_intel_bufmgr_gem_set_aub_dump()
2894 * for it to have any effect.
2897 drm_intel_bufmgr_gem_set_aub_filename(drm_intel_bufmgr *bufmgr,
2898 const char *filename)
2900 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
2902 free(bufmgr_gem->aub_filename);
2904 bufmgr_gem->aub_filename = strdup(filename);
2908 * Sets up AUB dumping.
2910 * This is a trace file format that can be used with the simulator.
2911 * Packets are emitted in a format somewhat like GPU command packets.
2912 * You can set up a GTT and upload your objects into the referenced
2913 * space, then send off batchbuffers and get BMPs out the other end.
2916 drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable)
2918 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
2919 int entry = 0x200003;
2921 int gtt_size = 0x10000;
2922 const char *filename;
2925 if (bufmgr_gem->aub_file) {
2926 fclose(bufmgr_gem->aub_file);
2927 bufmgr_gem->aub_file = NULL;
2932 if (geteuid() != getuid())
2935 if (bufmgr_gem->aub_filename)
2936 filename = bufmgr_gem->aub_filename;
2938 filename = "intel.aub";
2939 bufmgr_gem->aub_file = fopen(filename, "w+");
2940 if (!bufmgr_gem->aub_file)
2943 /* Start allocating objects from just after the GTT. */
2944 bufmgr_gem->aub_offset = gtt_size;
2946 /* Start with a (required) version packet. */
2947 aub_out(bufmgr_gem, CMD_AUB_HEADER | (13 - 2));
2949 (4 << AUB_HEADER_MAJOR_SHIFT) |
2950 (0 << AUB_HEADER_MINOR_SHIFT));
2951 for (i = 0; i < 8; i++) {
2952 aub_out(bufmgr_gem, 0); /* app name */
2954 aub_out(bufmgr_gem, 0); /* timestamp */
2955 aub_out(bufmgr_gem, 0); /* timestamp */
2956 aub_out(bufmgr_gem, 0); /* comment len */
2958 /* Set up the GTT. The max we can handle is 256M */
2959 aub_out(bufmgr_gem, CMD_AUB_TRACE_HEADER_BLOCK | ((bufmgr_gem->gen >= 8 ? 6 : 5) - 2));
2960 aub_out(bufmgr_gem, AUB_TRACE_MEMTYPE_NONLOCAL | 0 | AUB_TRACE_OP_DATA_WRITE);
2961 aub_out(bufmgr_gem, 0); /* subtype */
2962 aub_out(bufmgr_gem, 0); /* offset */
2963 aub_out(bufmgr_gem, gtt_size); /* size */
2964 if (bufmgr_gem->gen >= 8)
2965 aub_out(bufmgr_gem, 0);
2966 for (i = 0x000; i < gtt_size; i += 4, entry += 0x1000) {
2967 aub_out(bufmgr_gem, entry);
2972 drm_intel_gem_context_create(drm_intel_bufmgr *bufmgr)
2974 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
2975 struct drm_i915_gem_context_create create;
2976 drm_intel_context *context = NULL;
2980 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_CONTEXT_CREATE, &create);
2982 DBG("DRM_IOCTL_I915_GEM_CONTEXT_CREATE failed: %s\n",
2987 context = calloc(1, sizeof(*context));
2988 context->ctx_id = create.ctx_id;
2989 context->bufmgr = bufmgr;
2995 drm_intel_gem_context_destroy(drm_intel_context *ctx)
2997 drm_intel_bufmgr_gem *bufmgr_gem;
2998 struct drm_i915_gem_context_destroy destroy;
3006 bufmgr_gem = (drm_intel_bufmgr_gem *)ctx->bufmgr;
3007 destroy.ctx_id = ctx->ctx_id;
3008 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_CONTEXT_DESTROY,
3011 fprintf(stderr, "DRM_IOCTL_I915_GEM_CONTEXT_DESTROY failed: %s\n",
3018 drm_intel_reg_read(drm_intel_bufmgr *bufmgr,
3022 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
3023 struct drm_i915_reg_read reg_read;
3027 reg_read.offset = offset;
3029 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_REG_READ, ®_read);
3031 *result = reg_read.val;
3037 * Annotate the given bo for use in aub dumping.
3039 * \param annotations is an array of drm_intel_aub_annotation objects
3040 * describing the type of data in various sections of the bo. Each
3041 * element of the array specifies the type and subtype of a section of
3042 * the bo, and the past-the-end offset of that section. The elements
3043 * of \c annotations must be sorted so that ending_offset is
3046 * \param count is the number of elements in the \c annotations array.
3047 * If \c count is zero, then \c annotations will not be dereferenced.
3049 * Annotations are copied into a private data structure, so caller may
3050 * re-use the memory pointed to by \c annotations after the call
3053 * Annotations are stored for the lifetime of the bo; to reset to the
3054 * default state (no annotations), call this function with a \c count
3058 drm_intel_bufmgr_gem_set_aub_annotations(drm_intel_bo *bo,
3059 drm_intel_aub_annotation *annotations,
3062 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
3063 unsigned size = sizeof(*annotations) * count;
3064 drm_intel_aub_annotation *new_annotations =
3065 count > 0 ? realloc(bo_gem->aub_annotations, size) : NULL;
3066 if (new_annotations == NULL) {
3067 free(bo_gem->aub_annotations);
3068 bo_gem->aub_annotations = NULL;
3069 bo_gem->aub_annotation_count = 0;
3072 memcpy(new_annotations, annotations, size);
3073 bo_gem->aub_annotations = new_annotations;
3074 bo_gem->aub_annotation_count = count;
3078 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
3079 * and manage map buffer objections.
3081 * \param fd File descriptor of the opened DRM device.
3084 drm_intel_bufmgr_gem_init(int fd, int batch_size)
3086 drm_intel_bufmgr_gem *bufmgr_gem;
3087 struct drm_i915_gem_get_aperture aperture;
3088 drm_i915_getparam_t gp;
3092 bufmgr_gem = calloc(1, sizeof(*bufmgr_gem));
3093 if (bufmgr_gem == NULL)
3096 bufmgr_gem->fd = fd;
3098 if (pthread_mutex_init(&bufmgr_gem->lock, NULL) != 0) {
3103 ret = drmIoctl(bufmgr_gem->fd,
3104 DRM_IOCTL_I915_GEM_GET_APERTURE,
3108 bufmgr_gem->gtt_size = aperture.aper_available_size;
3110 fprintf(stderr, "DRM_IOCTL_I915_GEM_APERTURE failed: %s\n",
3112 bufmgr_gem->gtt_size = 128 * 1024 * 1024;
3113 fprintf(stderr, "Assuming %dkB available aperture size.\n"
3114 "May lead to reduced performance or incorrect "
3116 (int)bufmgr_gem->gtt_size / 1024);
3119 bufmgr_gem->pci_device = get_pci_device_id(bufmgr_gem);
3121 if (IS_GEN2(bufmgr_gem->pci_device))
3122 bufmgr_gem->gen = 2;
3123 else if (IS_GEN3(bufmgr_gem->pci_device))
3124 bufmgr_gem->gen = 3;
3125 else if (IS_GEN4(bufmgr_gem->pci_device))
3126 bufmgr_gem->gen = 4;
3127 else if (IS_GEN5(bufmgr_gem->pci_device))
3128 bufmgr_gem->gen = 5;
3129 else if (IS_GEN6(bufmgr_gem->pci_device))
3130 bufmgr_gem->gen = 6;
3131 else if (IS_GEN7(bufmgr_gem->pci_device))
3132 bufmgr_gem->gen = 7;
3133 else if (IS_GEN8(bufmgr_gem->pci_device))
3134 bufmgr_gem->gen = 8;
3140 if (IS_GEN3(bufmgr_gem->pci_device) &&
3141 bufmgr_gem->gtt_size > 256*1024*1024) {
3142 /* The unmappable part of gtt on gen 3 (i.e. above 256MB) can't
3143 * be used for tiled blits. To simplify the accounting, just
3144 * substract the unmappable part (fixed to 256MB on all known
3145 * gen3 devices) if the kernel advertises it. */
3146 bufmgr_gem->gtt_size -= 256*1024*1024;
3152 gp.param = I915_PARAM_HAS_EXECBUF2;
3153 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3157 gp.param = I915_PARAM_HAS_BSD;
3158 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3159 bufmgr_gem->has_bsd = ret == 0;
3161 gp.param = I915_PARAM_HAS_BLT;
3162 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3163 bufmgr_gem->has_blt = ret == 0;
3165 gp.param = I915_PARAM_HAS_RELAXED_FENCING;
3166 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3167 bufmgr_gem->has_relaxed_fencing = ret == 0;
3169 gp.param = I915_PARAM_HAS_WAIT_TIMEOUT;
3170 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3171 bufmgr_gem->has_wait_timeout = ret == 0;
3173 gp.param = I915_PARAM_HAS_LLC;
3174 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3176 /* Kernel does not supports HAS_LLC query, fallback to GPU
3177 * generation detection and assume that we have LLC on GEN6/7
3179 bufmgr_gem->has_llc = (IS_GEN6(bufmgr_gem->pci_device) |
3180 IS_GEN7(bufmgr_gem->pci_device));
3182 bufmgr_gem->has_llc = *gp.value;
3184 gp.param = I915_PARAM_HAS_VEBOX;
3185 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3186 bufmgr_gem->has_vebox = (ret == 0) & (*gp.value > 0);
3188 if (bufmgr_gem->gen < 4) {
3189 gp.param = I915_PARAM_NUM_FENCES_AVAIL;
3190 gp.value = &bufmgr_gem->available_fences;
3191 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3193 fprintf(stderr, "get fences failed: %d [%d]\n", ret,
3195 fprintf(stderr, "param: %d, val: %d\n", gp.param,
3197 bufmgr_gem->available_fences = 0;
3199 /* XXX The kernel reports the total number of fences,
3200 * including any that may be pinned.
3202 * We presume that there will be at least one pinned
3203 * fence for the scanout buffer, but there may be more
3204 * than one scanout and the user may be manually
3205 * pinning buffers. Let's move to execbuffer2 and
3206 * thereby forget the insanity of using fences...
3208 bufmgr_gem->available_fences -= 2;
3209 if (bufmgr_gem->available_fences < 0)
3210 bufmgr_gem->available_fences = 0;
3214 /* Let's go with one relocation per every 2 dwords (but round down a bit
3215 * since a power of two will mean an extra page allocation for the reloc
3218 * Every 4 was too few for the blender benchmark.
3220 bufmgr_gem->max_relocs = batch_size / sizeof(uint32_t) / 2 - 2;
3222 bufmgr_gem->bufmgr.bo_alloc = drm_intel_gem_bo_alloc;
3223 bufmgr_gem->bufmgr.bo_alloc_for_render =
3224 drm_intel_gem_bo_alloc_for_render;
3225 bufmgr_gem->bufmgr.bo_alloc_tiled = drm_intel_gem_bo_alloc_tiled;
3226 bufmgr_gem->bufmgr.bo_reference = drm_intel_gem_bo_reference;
3227 bufmgr_gem->bufmgr.bo_unreference = drm_intel_gem_bo_unreference;
3228 bufmgr_gem->bufmgr.bo_map = drm_intel_gem_bo_map;
3229 bufmgr_gem->bufmgr.bo_unmap = drm_intel_gem_bo_unmap;
3230 bufmgr_gem->bufmgr.bo_subdata = drm_intel_gem_bo_subdata;
3231 bufmgr_gem->bufmgr.bo_get_subdata = drm_intel_gem_bo_get_subdata;
3232 bufmgr_gem->bufmgr.bo_wait_rendering = drm_intel_gem_bo_wait_rendering;
3233 bufmgr_gem->bufmgr.bo_emit_reloc = drm_intel_gem_bo_emit_reloc;
3234 bufmgr_gem->bufmgr.bo_emit_reloc_fence = drm_intel_gem_bo_emit_reloc_fence;
3235 bufmgr_gem->bufmgr.bo_pin = drm_intel_gem_bo_pin;
3236 bufmgr_gem->bufmgr.bo_unpin = drm_intel_gem_bo_unpin;
3237 bufmgr_gem->bufmgr.bo_get_tiling = drm_intel_gem_bo_get_tiling;
3238 bufmgr_gem->bufmgr.bo_set_tiling = drm_intel_gem_bo_set_tiling;
3239 bufmgr_gem->bufmgr.bo_flink = drm_intel_gem_bo_flink;
3240 /* Use the new one if available */
3242 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec2;
3243 bufmgr_gem->bufmgr.bo_mrb_exec = drm_intel_gem_bo_mrb_exec2;
3245 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec;
3246 bufmgr_gem->bufmgr.bo_busy = drm_intel_gem_bo_busy;
3247 bufmgr_gem->bufmgr.bo_madvise = drm_intel_gem_bo_madvise;
3248 bufmgr_gem->bufmgr.destroy = drm_intel_bufmgr_gem_destroy;
3249 bufmgr_gem->bufmgr.debug = 0;
3250 bufmgr_gem->bufmgr.check_aperture_space =
3251 drm_intel_gem_check_aperture_space;
3252 bufmgr_gem->bufmgr.bo_disable_reuse = drm_intel_gem_bo_disable_reuse;
3253 bufmgr_gem->bufmgr.bo_is_reusable = drm_intel_gem_bo_is_reusable;
3254 bufmgr_gem->bufmgr.get_pipe_from_crtc_id =
3255 drm_intel_gem_get_pipe_from_crtc_id;
3256 bufmgr_gem->bufmgr.bo_references = drm_intel_gem_bo_references;
3258 DRMINITLISTHEAD(&bufmgr_gem->named);
3259 init_cache_buckets(bufmgr_gem);
3261 DRMINITLISTHEAD(&bufmgr_gem->vma_cache);
3262 bufmgr_gem->vma_max = -1; /* unlimited by default */
3264 return &bufmgr_gem->bufmgr;