1 /**************************************************************************
3 * Copyright © 2007 Red Hat Inc.
4 * Copyright © 2007-2012 Intel Corporation
5 * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
29 **************************************************************************/
31 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
32 * Keith Whitwell <keithw-at-tungstengraphics-dot-com>
33 * Eric Anholt <eric@anholt.net>
34 * Dave Airlie <airlied@linux.ie>
42 #include <xf86atomic.h>
50 #include <sys/ioctl.h>
53 #include <sys/types.h>
58 #define ETIME ETIMEDOUT
60 #include "libdrm_lists.h"
61 #include "intel_bufmgr.h"
62 #include "intel_bufmgr_priv.h"
63 #include "intel_chipset.h"
64 #include "intel_aub.h"
77 #define VG_CLEAR(s) VG(memset(&s, 0, sizeof(s)))
79 #define DBG(...) do { \
80 if (bufmgr_gem->bufmgr.debug) \
81 fprintf(stderr, __VA_ARGS__); \
84 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
86 typedef struct _drm_intel_bo_gem drm_intel_bo_gem;
88 struct drm_intel_gem_bo_bucket {
93 typedef struct _drm_intel_bufmgr_gem {
94 drm_intel_bufmgr bufmgr;
100 pthread_mutex_t lock;
102 struct drm_i915_gem_exec_object *exec_objects;
103 struct drm_i915_gem_exec_object2 *exec2_objects;
104 drm_intel_bo **exec_bos;
108 /** Array of lists of cached gem objects of power-of-two sizes */
109 struct drm_intel_gem_bo_bucket cache_bucket[14 * 4];
114 drmMMListHead vma_cache;
115 int vma_count, vma_open, vma_max;
118 int available_fences;
121 unsigned int has_bsd : 1;
122 unsigned int has_blt : 1;
123 unsigned int has_relaxed_fencing : 1;
124 unsigned int has_llc : 1;
125 unsigned int has_wait_timeout : 1;
126 unsigned int bo_reuse : 1;
127 unsigned int no_exec : 1;
128 unsigned int has_vebox : 1;
134 } drm_intel_bufmgr_gem;
136 #define DRM_INTEL_RELOC_FENCE (1<<0)
138 typedef struct _drm_intel_reloc_target_info {
141 } drm_intel_reloc_target;
143 struct _drm_intel_bo_gem {
151 * Kenel-assigned global name for this object
153 * List contains both flink named and prime fd'd objects
155 unsigned int global_name;
156 drmMMListHead name_list;
159 * Index of the buffer within the validation list while preparing a
160 * batchbuffer execution.
165 * Current tiling mode
167 uint32_t tiling_mode;
168 uint32_t swizzle_mode;
169 unsigned long stride;
173 /** Array passed to the DRM containing relocation information. */
174 struct drm_i915_gem_relocation_entry *relocs;
176 * Array of info structs corresponding to relocs[i].target_handle etc
178 drm_intel_reloc_target *reloc_target_info;
179 /** Number of entries in relocs */
181 /** Mapped address for the buffer, saved across map/unmap cycles */
183 /** GTT virtual address for the buffer, saved across map/unmap cycles */
186 drmMMListHead vma_list;
192 * Boolean of whether this BO and its children have been included in
193 * the current drm_intel_bufmgr_check_aperture_space() total.
195 bool included_in_check_aperture;
198 * Boolean of whether this buffer has been used as a relocation
199 * target and had its size accounted for, and thus can't have any
200 * further relocations added to it.
202 bool used_as_reloc_target;
205 * Boolean of whether we have encountered an error whilst building the relocation tree.
210 * Boolean of whether this buffer can be re-used
215 * Boolean of whether the GPU is definitely not accessing the buffer.
217 * This is only valid when reusable, since non-reusable
218 * buffers are those that have been shared wth other
219 * processes, so we don't know their state.
224 * Size in bytes of this buffer and its relocation descendents.
226 * Used to avoid costly tree walking in
227 * drm_intel_bufmgr_check_aperture in the common case.
232 * Number of potential fence registers required by this buffer and its
235 int reloc_tree_fences;
237 /** Flags that we may need to do the SW_FINSIH ioctl on unmap. */
238 bool mapped_cpu_write;
242 drm_intel_aub_annotation *aub_annotations;
243 unsigned aub_annotation_count;
247 drm_intel_gem_estimate_batch_space(drm_intel_bo ** bo_array, int count);
250 drm_intel_gem_compute_batch_space(drm_intel_bo ** bo_array, int count);
253 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
254 uint32_t * swizzle_mode);
257 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
258 uint32_t tiling_mode,
261 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
264 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo);
266 static void drm_intel_gem_bo_free(drm_intel_bo *bo);
269 drm_intel_gem_bo_tile_size(drm_intel_bufmgr_gem *bufmgr_gem, unsigned long size,
270 uint32_t *tiling_mode)
272 unsigned long min_size, max_size;
275 if (*tiling_mode == I915_TILING_NONE)
278 /* 965+ just need multiples of page size for tiling */
279 if (bufmgr_gem->gen >= 4)
280 return ROUND_UP_TO(size, 4096);
282 /* Older chips need powers of two, of at least 512k or 1M */
283 if (bufmgr_gem->gen == 3) {
284 min_size = 1024*1024;
285 max_size = 128*1024*1024;
288 max_size = 64*1024*1024;
291 if (size > max_size) {
292 *tiling_mode = I915_TILING_NONE;
296 /* Do we need to allocate every page for the fence? */
297 if (bufmgr_gem->has_relaxed_fencing)
298 return ROUND_UP_TO(size, 4096);
300 for (i = min_size; i < size; i <<= 1)
307 * Round a given pitch up to the minimum required for X tiling on a
308 * given chip. We use 512 as the minimum to allow for a later tiling
312 drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem,
313 unsigned long pitch, uint32_t *tiling_mode)
315 unsigned long tile_width;
318 /* If untiled, then just align it so that we can do rendering
319 * to it with the 3D engine.
321 if (*tiling_mode == I915_TILING_NONE)
322 return ALIGN(pitch, 64);
324 if (*tiling_mode == I915_TILING_X
325 || (IS_915(bufmgr_gem->pci_device)
326 && *tiling_mode == I915_TILING_Y))
331 /* 965 is flexible */
332 if (bufmgr_gem->gen >= 4)
333 return ROUND_UP_TO(pitch, tile_width);
335 /* The older hardware has a maximum pitch of 8192 with tiled
336 * surfaces, so fallback to untiled if it's too large.
339 *tiling_mode = I915_TILING_NONE;
340 return ALIGN(pitch, 64);
343 /* Pre-965 needs power of two tile width */
344 for (i = tile_width; i < pitch; i <<= 1)
350 static struct drm_intel_gem_bo_bucket *
351 drm_intel_gem_bo_bucket_for_size(drm_intel_bufmgr_gem *bufmgr_gem,
356 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
357 struct drm_intel_gem_bo_bucket *bucket =
358 &bufmgr_gem->cache_bucket[i];
359 if (bucket->size >= size) {
368 drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem *bufmgr_gem)
372 for (i = 0; i < bufmgr_gem->exec_count; i++) {
373 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
374 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
376 if (bo_gem->relocs == NULL) {
377 DBG("%2d: %d (%s)\n", i, bo_gem->gem_handle,
382 for (j = 0; j < bo_gem->reloc_count; j++) {
383 drm_intel_bo *target_bo = bo_gem->reloc_target_info[j].bo;
384 drm_intel_bo_gem *target_gem =
385 (drm_intel_bo_gem *) target_bo;
387 DBG("%2d: %d (%s)@0x%08llx -> "
388 "%d (%s)@0x%08lx + 0x%08x\n",
390 bo_gem->gem_handle, bo_gem->name,
391 (unsigned long long)bo_gem->relocs[j].offset,
392 target_gem->gem_handle,
395 bo_gem->relocs[j].delta);
401 drm_intel_gem_bo_reference(drm_intel_bo *bo)
403 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
405 atomic_inc(&bo_gem->refcount);
409 * Adds the given buffer to the list of buffers to be validated (moved into the
410 * appropriate memory type) with the next batch submission.
412 * If a buffer is validated multiple times in a batch submission, it ends up
413 * with the intersection of the memory type flags and the union of the
417 drm_intel_add_validate_buffer(drm_intel_bo *bo)
419 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
420 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
423 if (bo_gem->validate_index != -1)
426 /* Extend the array of validation entries as necessary. */
427 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
428 int new_size = bufmgr_gem->exec_size * 2;
433 bufmgr_gem->exec_objects =
434 realloc(bufmgr_gem->exec_objects,
435 sizeof(*bufmgr_gem->exec_objects) * new_size);
436 bufmgr_gem->exec_bos =
437 realloc(bufmgr_gem->exec_bos,
438 sizeof(*bufmgr_gem->exec_bos) * new_size);
439 bufmgr_gem->exec_size = new_size;
442 index = bufmgr_gem->exec_count;
443 bo_gem->validate_index = index;
444 /* Fill in array entry */
445 bufmgr_gem->exec_objects[index].handle = bo_gem->gem_handle;
446 bufmgr_gem->exec_objects[index].relocation_count = bo_gem->reloc_count;
447 bufmgr_gem->exec_objects[index].relocs_ptr = (uintptr_t) bo_gem->relocs;
448 bufmgr_gem->exec_objects[index].alignment = 0;
449 bufmgr_gem->exec_objects[index].offset = 0;
450 bufmgr_gem->exec_bos[index] = bo;
451 bufmgr_gem->exec_count++;
455 drm_intel_add_validate_buffer2(drm_intel_bo *bo, int need_fence)
457 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
458 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
461 if (bo_gem->validate_index != -1) {
463 bufmgr_gem->exec2_objects[bo_gem->validate_index].flags |=
464 EXEC_OBJECT_NEEDS_FENCE;
468 /* Extend the array of validation entries as necessary. */
469 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
470 int new_size = bufmgr_gem->exec_size * 2;
475 bufmgr_gem->exec2_objects =
476 realloc(bufmgr_gem->exec2_objects,
477 sizeof(*bufmgr_gem->exec2_objects) * new_size);
478 bufmgr_gem->exec_bos =
479 realloc(bufmgr_gem->exec_bos,
480 sizeof(*bufmgr_gem->exec_bos) * new_size);
481 bufmgr_gem->exec_size = new_size;
484 index = bufmgr_gem->exec_count;
485 bo_gem->validate_index = index;
486 /* Fill in array entry */
487 bufmgr_gem->exec2_objects[index].handle = bo_gem->gem_handle;
488 bufmgr_gem->exec2_objects[index].relocation_count = bo_gem->reloc_count;
489 bufmgr_gem->exec2_objects[index].relocs_ptr = (uintptr_t)bo_gem->relocs;
490 bufmgr_gem->exec2_objects[index].alignment = 0;
491 bufmgr_gem->exec2_objects[index].offset = 0;
492 bufmgr_gem->exec_bos[index] = bo;
493 bufmgr_gem->exec2_objects[index].flags = 0;
494 bufmgr_gem->exec2_objects[index].rsvd1 = 0;
495 bufmgr_gem->exec2_objects[index].rsvd2 = 0;
497 bufmgr_gem->exec2_objects[index].flags |=
498 EXEC_OBJECT_NEEDS_FENCE;
500 bufmgr_gem->exec_count++;
503 #define RELOC_BUF_SIZE(x) ((I915_RELOC_HEADER + x * I915_RELOC0_STRIDE) * \
507 drm_intel_bo_gem_set_in_aperture_size(drm_intel_bufmgr_gem *bufmgr_gem,
508 drm_intel_bo_gem *bo_gem)
512 assert(!bo_gem->used_as_reloc_target);
514 /* The older chipsets are far-less flexible in terms of tiling,
515 * and require tiled buffer to be size aligned in the aperture.
516 * This means that in the worst possible case we will need a hole
517 * twice as large as the object in order for it to fit into the
518 * aperture. Optimal packing is for wimps.
520 size = bo_gem->bo.size;
521 if (bufmgr_gem->gen < 4 && bo_gem->tiling_mode != I915_TILING_NONE) {
524 if (bufmgr_gem->has_relaxed_fencing) {
525 if (bufmgr_gem->gen == 3)
526 min_size = 1024*1024;
530 while (min_size < size)
535 /* Account for worst-case alignment. */
539 bo_gem->reloc_tree_size = size;
543 drm_intel_setup_reloc_list(drm_intel_bo *bo)
545 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
546 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
547 unsigned int max_relocs = bufmgr_gem->max_relocs;
549 if (bo->size / 4 < max_relocs)
550 max_relocs = bo->size / 4;
552 bo_gem->relocs = malloc(max_relocs *
553 sizeof(struct drm_i915_gem_relocation_entry));
554 bo_gem->reloc_target_info = malloc(max_relocs *
555 sizeof(drm_intel_reloc_target));
556 if (bo_gem->relocs == NULL || bo_gem->reloc_target_info == NULL) {
557 bo_gem->has_error = true;
559 free (bo_gem->relocs);
560 bo_gem->relocs = NULL;
562 free (bo_gem->reloc_target_info);
563 bo_gem->reloc_target_info = NULL;
572 drm_intel_gem_bo_busy(drm_intel_bo *bo)
574 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
575 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
576 struct drm_i915_gem_busy busy;
579 if (bo_gem->reusable && bo_gem->idle)
583 busy.handle = bo_gem->gem_handle;
585 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_BUSY, &busy);
587 bo_gem->idle = !busy.busy;
592 return (ret == 0 && busy.busy);
596 drm_intel_gem_bo_madvise_internal(drm_intel_bufmgr_gem *bufmgr_gem,
597 drm_intel_bo_gem *bo_gem, int state)
599 struct drm_i915_gem_madvise madv;
602 madv.handle = bo_gem->gem_handle;
605 drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MADVISE, &madv);
607 return madv.retained;
611 drm_intel_gem_bo_madvise(drm_intel_bo *bo, int madv)
613 return drm_intel_gem_bo_madvise_internal
614 ((drm_intel_bufmgr_gem *) bo->bufmgr,
615 (drm_intel_bo_gem *) bo,
619 /* drop the oldest entries that have been purged by the kernel */
621 drm_intel_gem_bo_cache_purge_bucket(drm_intel_bufmgr_gem *bufmgr_gem,
622 struct drm_intel_gem_bo_bucket *bucket)
624 while (!DRMLISTEMPTY(&bucket->head)) {
625 drm_intel_bo_gem *bo_gem;
627 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
628 bucket->head.next, head);
629 if (drm_intel_gem_bo_madvise_internal
630 (bufmgr_gem, bo_gem, I915_MADV_DONTNEED))
633 DRMLISTDEL(&bo_gem->head);
634 drm_intel_gem_bo_free(&bo_gem->bo);
638 static drm_intel_bo *
639 drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr,
643 uint32_t tiling_mode,
644 unsigned long stride)
646 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
647 drm_intel_bo_gem *bo_gem;
648 unsigned int page_size = getpagesize();
650 struct drm_intel_gem_bo_bucket *bucket;
651 bool alloc_from_cache;
652 unsigned long bo_size;
653 bool for_render = false;
655 if (flags & BO_ALLOC_FOR_RENDER)
658 /* Round the allocated size up to a power of two number of pages. */
659 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, size);
661 /* If we don't have caching at this size, don't actually round the
664 if (bucket == NULL) {
666 if (bo_size < page_size)
669 bo_size = bucket->size;
672 pthread_mutex_lock(&bufmgr_gem->lock);
673 /* Get a buffer out of the cache if available */
675 alloc_from_cache = false;
676 if (bucket != NULL && !DRMLISTEMPTY(&bucket->head)) {
678 /* Allocate new render-target BOs from the tail (MRU)
679 * of the list, as it will likely be hot in the GPU
680 * cache and in the aperture for us.
682 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
683 bucket->head.prev, head);
684 DRMLISTDEL(&bo_gem->head);
685 alloc_from_cache = true;
687 /* For non-render-target BOs (where we're probably
688 * going to map it first thing in order to fill it
689 * with data), check if the last BO in the cache is
690 * unbusy, and only reuse in that case. Otherwise,
691 * allocating a new buffer is probably faster than
692 * waiting for the GPU to finish.
694 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
695 bucket->head.next, head);
696 if (!drm_intel_gem_bo_busy(&bo_gem->bo)) {
697 alloc_from_cache = true;
698 DRMLISTDEL(&bo_gem->head);
702 if (alloc_from_cache) {
703 if (!drm_intel_gem_bo_madvise_internal
704 (bufmgr_gem, bo_gem, I915_MADV_WILLNEED)) {
705 drm_intel_gem_bo_free(&bo_gem->bo);
706 drm_intel_gem_bo_cache_purge_bucket(bufmgr_gem,
711 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
714 drm_intel_gem_bo_free(&bo_gem->bo);
719 pthread_mutex_unlock(&bufmgr_gem->lock);
721 if (!alloc_from_cache) {
722 struct drm_i915_gem_create create;
724 bo_gem = calloc(1, sizeof(*bo_gem));
728 bo_gem->bo.size = bo_size;
731 create.size = bo_size;
733 ret = drmIoctl(bufmgr_gem->fd,
734 DRM_IOCTL_I915_GEM_CREATE,
736 bo_gem->gem_handle = create.handle;
737 bo_gem->bo.handle = bo_gem->gem_handle;
742 bo_gem->bo.bufmgr = bufmgr;
744 bo_gem->tiling_mode = I915_TILING_NONE;
745 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
748 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
751 drm_intel_gem_bo_free(&bo_gem->bo);
755 DRMINITLISTHEAD(&bo_gem->name_list);
756 DRMINITLISTHEAD(&bo_gem->vma_list);
760 atomic_set(&bo_gem->refcount, 1);
761 bo_gem->validate_index = -1;
762 bo_gem->reloc_tree_fences = 0;
763 bo_gem->used_as_reloc_target = false;
764 bo_gem->has_error = false;
765 bo_gem->reusable = true;
766 bo_gem->aub_annotations = NULL;
767 bo_gem->aub_annotation_count = 0;
769 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
771 DBG("bo_create: buf %d (%s) %ldb\n",
772 bo_gem->gem_handle, bo_gem->name, size);
777 static drm_intel_bo *
778 drm_intel_gem_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
781 unsigned int alignment)
783 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size,
785 I915_TILING_NONE, 0);
788 static drm_intel_bo *
789 drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr,
792 unsigned int alignment)
794 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, 0,
795 I915_TILING_NONE, 0);
798 static drm_intel_bo *
799 drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
800 int x, int y, int cpp, uint32_t *tiling_mode,
801 unsigned long *pitch, unsigned long flags)
803 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
804 unsigned long size, stride;
808 unsigned long aligned_y, height_alignment;
810 tiling = *tiling_mode;
812 /* If we're tiled, our allocations are in 8 or 32-row blocks,
813 * so failure to align our height means that we won't allocate
816 * If we're untiled, we still have to align to 2 rows high
817 * because the data port accesses 2x2 blocks even if the
818 * bottom row isn't to be rendered, so failure to align means
819 * we could walk off the end of the GTT and fault. This is
820 * documented on 965, and may be the case on older chipsets
821 * too so we try to be careful.
824 height_alignment = 2;
826 if ((bufmgr_gem->gen == 2) && tiling != I915_TILING_NONE)
827 height_alignment = 16;
828 else if (tiling == I915_TILING_X
829 || (IS_915(bufmgr_gem->pci_device)
830 && tiling == I915_TILING_Y))
831 height_alignment = 8;
832 else if (tiling == I915_TILING_Y)
833 height_alignment = 32;
834 aligned_y = ALIGN(y, height_alignment);
837 stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, tiling_mode);
838 size = stride * aligned_y;
839 size = drm_intel_gem_bo_tile_size(bufmgr_gem, size, tiling_mode);
840 } while (*tiling_mode != tiling);
843 if (tiling == I915_TILING_NONE)
846 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, flags,
851 * Returns a drm_intel_bo wrapping the given buffer object handle.
853 * This can be used when one application needs to pass a buffer object
857 drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
861 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
862 drm_intel_bo_gem *bo_gem;
864 struct drm_gem_open open_arg;
865 struct drm_i915_gem_get_tiling get_tiling;
868 /* At the moment most applications only have a few named bo.
869 * For instance, in a DRI client only the render buffers passed
870 * between X and the client are named. And since X returns the
871 * alternating names for the front/back buffer a linear search
872 * provides a sufficiently fast match.
874 for (list = bufmgr_gem->named.next;
875 list != &bufmgr_gem->named;
877 bo_gem = DRMLISTENTRY(drm_intel_bo_gem, list, name_list);
878 if (bo_gem->global_name == handle) {
879 drm_intel_gem_bo_reference(&bo_gem->bo);
885 open_arg.name = handle;
886 ret = drmIoctl(bufmgr_gem->fd,
890 DBG("Couldn't reference %s handle 0x%08x: %s\n",
891 name, handle, strerror(errno));
894 /* Now see if someone has used a prime handle to get this
895 * object from the kernel before by looking through the list
896 * again for a matching gem_handle
898 for (list = bufmgr_gem->named.next;
899 list != &bufmgr_gem->named;
901 bo_gem = DRMLISTENTRY(drm_intel_bo_gem, list, name_list);
902 if (bo_gem->gem_handle == open_arg.handle) {
903 drm_intel_gem_bo_reference(&bo_gem->bo);
908 bo_gem = calloc(1, sizeof(*bo_gem));
912 bo_gem->bo.size = open_arg.size;
913 bo_gem->bo.offset = 0;
914 bo_gem->bo.offset64 = 0;
915 bo_gem->bo.virtual = NULL;
916 bo_gem->bo.bufmgr = bufmgr;
918 atomic_set(&bo_gem->refcount, 1);
919 bo_gem->validate_index = -1;
920 bo_gem->gem_handle = open_arg.handle;
921 bo_gem->bo.handle = open_arg.handle;
922 bo_gem->global_name = handle;
923 bo_gem->reusable = false;
925 VG_CLEAR(get_tiling);
926 get_tiling.handle = bo_gem->gem_handle;
927 ret = drmIoctl(bufmgr_gem->fd,
928 DRM_IOCTL_I915_GEM_GET_TILING,
931 drm_intel_gem_bo_unreference(&bo_gem->bo);
934 bo_gem->tiling_mode = get_tiling.tiling_mode;
935 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
936 /* XXX stride is unknown */
937 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
939 DRMINITLISTHEAD(&bo_gem->vma_list);
940 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
941 DBG("bo_create_from_handle: %d (%s)\n", handle, bo_gem->name);
947 drm_intel_gem_bo_free(drm_intel_bo *bo)
949 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
950 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
951 struct drm_gem_close close;
954 DRMLISTDEL(&bo_gem->vma_list);
955 if (bo_gem->mem_virtual) {
956 VG(VALGRIND_FREELIKE_BLOCK(bo_gem->mem_virtual, 0));
957 munmap(bo_gem->mem_virtual, bo_gem->bo.size);
958 bufmgr_gem->vma_count--;
960 if (bo_gem->gtt_virtual) {
961 munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
962 bufmgr_gem->vma_count--;
965 /* Close this object */
967 close.handle = bo_gem->gem_handle;
968 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close);
970 DBG("DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
971 bo_gem->gem_handle, bo_gem->name, strerror(errno));
973 free(bo_gem->aub_annotations);
978 drm_intel_gem_bo_mark_mmaps_incoherent(drm_intel_bo *bo)
981 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
983 if (bo_gem->mem_virtual)
984 VALGRIND_MAKE_MEM_NOACCESS(bo_gem->mem_virtual, bo->size);
986 if (bo_gem->gtt_virtual)
987 VALGRIND_MAKE_MEM_NOACCESS(bo_gem->gtt_virtual, bo->size);
991 /** Frees all cached buffers significantly older than @time. */
993 drm_intel_gem_cleanup_bo_cache(drm_intel_bufmgr_gem *bufmgr_gem, time_t time)
997 if (bufmgr_gem->time == time)
1000 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
1001 struct drm_intel_gem_bo_bucket *bucket =
1002 &bufmgr_gem->cache_bucket[i];
1004 while (!DRMLISTEMPTY(&bucket->head)) {
1005 drm_intel_bo_gem *bo_gem;
1007 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1008 bucket->head.next, head);
1009 if (time - bo_gem->free_time <= 1)
1012 DRMLISTDEL(&bo_gem->head);
1014 drm_intel_gem_bo_free(&bo_gem->bo);
1018 bufmgr_gem->time = time;
1021 static void drm_intel_gem_bo_purge_vma_cache(drm_intel_bufmgr_gem *bufmgr_gem)
1025 DBG("%s: cached=%d, open=%d, limit=%d\n", __FUNCTION__,
1026 bufmgr_gem->vma_count, bufmgr_gem->vma_open, bufmgr_gem->vma_max);
1028 if (bufmgr_gem->vma_max < 0)
1031 /* We may need to evict a few entries in order to create new mmaps */
1032 limit = bufmgr_gem->vma_max - 2*bufmgr_gem->vma_open;
1036 while (bufmgr_gem->vma_count > limit) {
1037 drm_intel_bo_gem *bo_gem;
1039 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1040 bufmgr_gem->vma_cache.next,
1042 assert(bo_gem->map_count == 0);
1043 DRMLISTDELINIT(&bo_gem->vma_list);
1045 if (bo_gem->mem_virtual) {
1046 munmap(bo_gem->mem_virtual, bo_gem->bo.size);
1047 bo_gem->mem_virtual = NULL;
1048 bufmgr_gem->vma_count--;
1050 if (bo_gem->gtt_virtual) {
1051 munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
1052 bo_gem->gtt_virtual = NULL;
1053 bufmgr_gem->vma_count--;
1058 static void drm_intel_gem_bo_close_vma(drm_intel_bufmgr_gem *bufmgr_gem,
1059 drm_intel_bo_gem *bo_gem)
1061 bufmgr_gem->vma_open--;
1062 DRMLISTADDTAIL(&bo_gem->vma_list, &bufmgr_gem->vma_cache);
1063 if (bo_gem->mem_virtual)
1064 bufmgr_gem->vma_count++;
1065 if (bo_gem->gtt_virtual)
1066 bufmgr_gem->vma_count++;
1067 drm_intel_gem_bo_purge_vma_cache(bufmgr_gem);
1070 static void drm_intel_gem_bo_open_vma(drm_intel_bufmgr_gem *bufmgr_gem,
1071 drm_intel_bo_gem *bo_gem)
1073 bufmgr_gem->vma_open++;
1074 DRMLISTDEL(&bo_gem->vma_list);
1075 if (bo_gem->mem_virtual)
1076 bufmgr_gem->vma_count--;
1077 if (bo_gem->gtt_virtual)
1078 bufmgr_gem->vma_count--;
1079 drm_intel_gem_bo_purge_vma_cache(bufmgr_gem);
1083 drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time)
1085 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1086 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1087 struct drm_intel_gem_bo_bucket *bucket;
1090 /* Unreference all the target buffers */
1091 for (i = 0; i < bo_gem->reloc_count; i++) {
1092 if (bo_gem->reloc_target_info[i].bo != bo) {
1093 drm_intel_gem_bo_unreference_locked_timed(bo_gem->
1094 reloc_target_info[i].bo,
1098 bo_gem->reloc_count = 0;
1099 bo_gem->used_as_reloc_target = false;
1101 DBG("bo_unreference final: %d (%s)\n",
1102 bo_gem->gem_handle, bo_gem->name);
1104 /* release memory associated with this object */
1105 if (bo_gem->reloc_target_info) {
1106 free(bo_gem->reloc_target_info);
1107 bo_gem->reloc_target_info = NULL;
1109 if (bo_gem->relocs) {
1110 free(bo_gem->relocs);
1111 bo_gem->relocs = NULL;
1114 /* Clear any left-over mappings */
1115 if (bo_gem->map_count) {
1116 DBG("bo freed with non-zero map-count %d\n", bo_gem->map_count);
1117 bo_gem->map_count = 0;
1118 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1119 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1122 DRMLISTDEL(&bo_gem->name_list);
1124 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, bo->size);
1125 /* Put the buffer into our internal cache for reuse if we can. */
1126 if (bufmgr_gem->bo_reuse && bo_gem->reusable && bucket != NULL &&
1127 drm_intel_gem_bo_madvise_internal(bufmgr_gem, bo_gem,
1128 I915_MADV_DONTNEED)) {
1129 bo_gem->free_time = time;
1131 bo_gem->name = NULL;
1132 bo_gem->validate_index = -1;
1134 DRMLISTADDTAIL(&bo_gem->head, &bucket->head);
1136 drm_intel_gem_bo_free(bo);
1140 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
1143 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1145 assert(atomic_read(&bo_gem->refcount) > 0);
1146 if (atomic_dec_and_test(&bo_gem->refcount))
1147 drm_intel_gem_bo_unreference_final(bo, time);
1150 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo)
1152 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1154 assert(atomic_read(&bo_gem->refcount) > 0);
1155 if (atomic_dec_and_test(&bo_gem->refcount)) {
1156 drm_intel_bufmgr_gem *bufmgr_gem =
1157 (drm_intel_bufmgr_gem *) bo->bufmgr;
1158 struct timespec time;
1160 clock_gettime(CLOCK_MONOTONIC, &time);
1162 pthread_mutex_lock(&bufmgr_gem->lock);
1163 drm_intel_gem_bo_unreference_final(bo, time.tv_sec);
1164 drm_intel_gem_cleanup_bo_cache(bufmgr_gem, time.tv_sec);
1165 pthread_mutex_unlock(&bufmgr_gem->lock);
1169 static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable)
1171 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1172 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1173 struct drm_i915_gem_set_domain set_domain;
1176 pthread_mutex_lock(&bufmgr_gem->lock);
1178 if (bo_gem->map_count++ == 0)
1179 drm_intel_gem_bo_open_vma(bufmgr_gem, bo_gem);
1181 if (!bo_gem->mem_virtual) {
1182 struct drm_i915_gem_mmap mmap_arg;
1184 DBG("bo_map: %d (%s), map_count=%d\n",
1185 bo_gem->gem_handle, bo_gem->name, bo_gem->map_count);
1188 mmap_arg.handle = bo_gem->gem_handle;
1189 mmap_arg.offset = 0;
1190 mmap_arg.size = bo->size;
1191 ret = drmIoctl(bufmgr_gem->fd,
1192 DRM_IOCTL_I915_GEM_MMAP,
1196 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1197 __FILE__, __LINE__, bo_gem->gem_handle,
1198 bo_gem->name, strerror(errno));
1199 if (--bo_gem->map_count == 0)
1200 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1201 pthread_mutex_unlock(&bufmgr_gem->lock);
1204 VG(VALGRIND_MALLOCLIKE_BLOCK(mmap_arg.addr_ptr, mmap_arg.size, 0, 1));
1205 bo_gem->mem_virtual = (void *)(uintptr_t) mmap_arg.addr_ptr;
1207 DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1208 bo_gem->mem_virtual);
1209 bo->virtual = bo_gem->mem_virtual;
1211 VG_CLEAR(set_domain);
1212 set_domain.handle = bo_gem->gem_handle;
1213 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
1215 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
1217 set_domain.write_domain = 0;
1218 ret = drmIoctl(bufmgr_gem->fd,
1219 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1222 DBG("%s:%d: Error setting to CPU domain %d: %s\n",
1223 __FILE__, __LINE__, bo_gem->gem_handle,
1228 bo_gem->mapped_cpu_write = true;
1230 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1231 VG(VALGRIND_MAKE_MEM_DEFINED(bo_gem->mem_virtual, bo->size));
1232 pthread_mutex_unlock(&bufmgr_gem->lock);
1238 map_gtt(drm_intel_bo *bo)
1240 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1241 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1244 if (bo_gem->map_count++ == 0)
1245 drm_intel_gem_bo_open_vma(bufmgr_gem, bo_gem);
1247 /* Get a mapping of the buffer if we haven't before. */
1248 if (bo_gem->gtt_virtual == NULL) {
1249 struct drm_i915_gem_mmap_gtt mmap_arg;
1251 DBG("bo_map_gtt: mmap %d (%s), map_count=%d\n",
1252 bo_gem->gem_handle, bo_gem->name, bo_gem->map_count);
1255 mmap_arg.handle = bo_gem->gem_handle;
1257 /* Get the fake offset back... */
1258 ret = drmIoctl(bufmgr_gem->fd,
1259 DRM_IOCTL_I915_GEM_MMAP_GTT,
1263 DBG("%s:%d: Error preparing buffer map %d (%s): %s .\n",
1265 bo_gem->gem_handle, bo_gem->name,
1267 if (--bo_gem->map_count == 0)
1268 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1273 bo_gem->gtt_virtual = mmap(0, bo->size, PROT_READ | PROT_WRITE,
1274 MAP_SHARED, bufmgr_gem->fd,
1276 if (bo_gem->gtt_virtual == MAP_FAILED) {
1277 bo_gem->gtt_virtual = NULL;
1279 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1281 bo_gem->gem_handle, bo_gem->name,
1283 if (--bo_gem->map_count == 0)
1284 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1289 bo->virtual = bo_gem->gtt_virtual;
1291 DBG("bo_map_gtt: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1292 bo_gem->gtt_virtual);
1297 int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
1299 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1300 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1301 struct drm_i915_gem_set_domain set_domain;
1304 pthread_mutex_lock(&bufmgr_gem->lock);
1308 pthread_mutex_unlock(&bufmgr_gem->lock);
1312 /* Now move it to the GTT domain so that the GPU and CPU
1313 * caches are flushed and the GPU isn't actively using the
1316 * The pagefault handler does this domain change for us when
1317 * it has unbound the BO from the GTT, but it's up to us to
1318 * tell it when we're about to use things if we had done
1319 * rendering and it still happens to be bound to the GTT.
1321 VG_CLEAR(set_domain);
1322 set_domain.handle = bo_gem->gem_handle;
1323 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1324 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
1325 ret = drmIoctl(bufmgr_gem->fd,
1326 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1329 DBG("%s:%d: Error setting domain %d: %s\n",
1330 __FILE__, __LINE__, bo_gem->gem_handle,
1334 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1335 VG(VALGRIND_MAKE_MEM_DEFINED(bo_gem->gtt_virtual, bo->size));
1336 pthread_mutex_unlock(&bufmgr_gem->lock);
1342 * Performs a mapping of the buffer object like the normal GTT
1343 * mapping, but avoids waiting for the GPU to be done reading from or
1344 * rendering to the buffer.
1346 * This is used in the implementation of GL_ARB_map_buffer_range: The
1347 * user asks to create a buffer, then does a mapping, fills some
1348 * space, runs a drawing command, then asks to map it again without
1349 * synchronizing because it guarantees that it won't write over the
1350 * data that the GPU is busy using (or, more specifically, that if it
1351 * does write over the data, it acknowledges that rendering is
1355 int drm_intel_gem_bo_map_unsynchronized(drm_intel_bo *bo)
1357 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1358 #ifdef HAVE_VALGRIND
1359 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1363 /* If the CPU cache isn't coherent with the GTT, then use a
1364 * regular synchronized mapping. The problem is that we don't
1365 * track where the buffer was last used on the CPU side in
1366 * terms of drm_intel_bo_map vs drm_intel_gem_bo_map_gtt, so
1367 * we would potentially corrupt the buffer even when the user
1368 * does reasonable things.
1370 if (!bufmgr_gem->has_llc)
1371 return drm_intel_gem_bo_map_gtt(bo);
1373 pthread_mutex_lock(&bufmgr_gem->lock);
1377 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1378 VG(VALGRIND_MAKE_MEM_DEFINED(bo_gem->gtt_virtual, bo->size));
1381 pthread_mutex_unlock(&bufmgr_gem->lock);
1386 static int drm_intel_gem_bo_unmap(drm_intel_bo *bo)
1388 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1389 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1395 pthread_mutex_lock(&bufmgr_gem->lock);
1397 if (bo_gem->map_count <= 0) {
1398 DBG("attempted to unmap an unmapped bo\n");
1399 pthread_mutex_unlock(&bufmgr_gem->lock);
1400 /* Preserve the old behaviour of just treating this as a
1401 * no-op rather than reporting the error.
1406 if (bo_gem->mapped_cpu_write) {
1407 struct drm_i915_gem_sw_finish sw_finish;
1409 /* Cause a flush to happen if the buffer's pinned for
1410 * scanout, so the results show up in a timely manner.
1411 * Unlike GTT set domains, this only does work if the
1412 * buffer should be scanout-related.
1414 VG_CLEAR(sw_finish);
1415 sw_finish.handle = bo_gem->gem_handle;
1416 ret = drmIoctl(bufmgr_gem->fd,
1417 DRM_IOCTL_I915_GEM_SW_FINISH,
1419 ret = ret == -1 ? -errno : 0;
1421 bo_gem->mapped_cpu_write = false;
1424 /* We need to unmap after every innovation as we cannot track
1425 * an open vma for every bo as that will exhaasut the system
1426 * limits and cause later failures.
1428 if (--bo_gem->map_count == 0) {
1429 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1430 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1433 pthread_mutex_unlock(&bufmgr_gem->lock);
1438 int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo)
1440 return drm_intel_gem_bo_unmap(bo);
1444 drm_intel_gem_bo_subdata(drm_intel_bo *bo, unsigned long offset,
1445 unsigned long size, const void *data)
1447 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1448 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1449 struct drm_i915_gem_pwrite pwrite;
1453 pwrite.handle = bo_gem->gem_handle;
1454 pwrite.offset = offset;
1456 pwrite.data_ptr = (uint64_t) (uintptr_t) data;
1457 ret = drmIoctl(bufmgr_gem->fd,
1458 DRM_IOCTL_I915_GEM_PWRITE,
1462 DBG("%s:%d: Error writing data to buffer %d: (%d %d) %s .\n",
1463 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1464 (int)size, strerror(errno));
1471 drm_intel_gem_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id)
1473 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1474 struct drm_i915_get_pipe_from_crtc_id get_pipe_from_crtc_id;
1477 VG_CLEAR(get_pipe_from_crtc_id);
1478 get_pipe_from_crtc_id.crtc_id = crtc_id;
1479 ret = drmIoctl(bufmgr_gem->fd,
1480 DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID,
1481 &get_pipe_from_crtc_id);
1483 /* We return -1 here to signal that we don't
1484 * know which pipe is associated with this crtc.
1485 * This lets the caller know that this information
1486 * isn't available; using the wrong pipe for
1487 * vblank waiting can cause the chipset to lock up
1492 return get_pipe_from_crtc_id.pipe;
1496 drm_intel_gem_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
1497 unsigned long size, void *data)
1499 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1500 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1501 struct drm_i915_gem_pread pread;
1505 pread.handle = bo_gem->gem_handle;
1506 pread.offset = offset;
1508 pread.data_ptr = (uint64_t) (uintptr_t) data;
1509 ret = drmIoctl(bufmgr_gem->fd,
1510 DRM_IOCTL_I915_GEM_PREAD,
1514 DBG("%s:%d: Error reading data from buffer %d: (%d %d) %s .\n",
1515 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1516 (int)size, strerror(errno));
1522 /** Waits for all GPU rendering with the object to have completed. */
1524 drm_intel_gem_bo_wait_rendering(drm_intel_bo *bo)
1526 drm_intel_gem_bo_start_gtt_access(bo, 1);
1530 * Waits on a BO for the given amount of time.
1532 * @bo: buffer object to wait for
1533 * @timeout_ns: amount of time to wait in nanoseconds.
1534 * If value is less than 0, an infinite wait will occur.
1536 * Returns 0 if the wait was successful ie. the last batch referencing the
1537 * object has completed within the allotted time. Otherwise some negative return
1538 * value describes the error. Of particular interest is -ETIME when the wait has
1539 * failed to yield the desired result.
1541 * Similar to drm_intel_gem_bo_wait_rendering except a timeout parameter allows
1542 * the operation to give up after a certain amount of time. Another subtle
1543 * difference is the internal locking semantics are different (this variant does
1544 * not hold the lock for the duration of the wait). This makes the wait subject
1545 * to a larger userspace race window.
1547 * The implementation shall wait until the object is no longer actively
1548 * referenced within a batch buffer at the time of the call. The wait will
1549 * not guarantee that the buffer is re-issued via another thread, or an flinked
1550 * handle. Userspace must make sure this race does not occur if such precision
1553 int drm_intel_gem_bo_wait(drm_intel_bo *bo, int64_t timeout_ns)
1555 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1556 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1557 struct drm_i915_gem_wait wait;
1560 if (!bufmgr_gem->has_wait_timeout) {
1561 DBG("%s:%d: Timed wait is not supported. Falling back to "
1562 "infinite wait\n", __FILE__, __LINE__);
1564 drm_intel_gem_bo_wait_rendering(bo);
1567 return drm_intel_gem_bo_busy(bo) ? -ETIME : 0;
1571 wait.bo_handle = bo_gem->gem_handle;
1572 wait.timeout_ns = timeout_ns;
1574 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_WAIT, &wait);
1582 * Sets the object to the GTT read and possibly write domain, used by the X
1583 * 2D driver in the absence of kernel support to do drm_intel_gem_bo_map_gtt().
1585 * In combination with drm_intel_gem_bo_pin() and manual fence management, we
1586 * can do tiled pixmaps this way.
1589 drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable)
1591 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1592 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1593 struct drm_i915_gem_set_domain set_domain;
1596 VG_CLEAR(set_domain);
1597 set_domain.handle = bo_gem->gem_handle;
1598 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1599 set_domain.write_domain = write_enable ? I915_GEM_DOMAIN_GTT : 0;
1600 ret = drmIoctl(bufmgr_gem->fd,
1601 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1604 DBG("%s:%d: Error setting memory domains %d (%08x %08x): %s .\n",
1605 __FILE__, __LINE__, bo_gem->gem_handle,
1606 set_domain.read_domains, set_domain.write_domain,
1612 drm_intel_bufmgr_gem_destroy(drm_intel_bufmgr *bufmgr)
1614 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1617 free(bufmgr_gem->exec2_objects);
1618 free(bufmgr_gem->exec_objects);
1619 free(bufmgr_gem->exec_bos);
1620 free(bufmgr_gem->aub_filename);
1622 pthread_mutex_destroy(&bufmgr_gem->lock);
1624 /* Free any cached buffer objects we were going to reuse */
1625 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
1626 struct drm_intel_gem_bo_bucket *bucket =
1627 &bufmgr_gem->cache_bucket[i];
1628 drm_intel_bo_gem *bo_gem;
1630 while (!DRMLISTEMPTY(&bucket->head)) {
1631 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1632 bucket->head.next, head);
1633 DRMLISTDEL(&bo_gem->head);
1635 drm_intel_gem_bo_free(&bo_gem->bo);
1643 * Adds the target buffer to the validation list and adds the relocation
1644 * to the reloc_buffer's relocation list.
1646 * The relocation entry at the given offset must already contain the
1647 * precomputed relocation value, because the kernel will optimize out
1648 * the relocation entry write when the buffer hasn't moved from the
1649 * last known offset in target_bo.
1652 do_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1653 drm_intel_bo *target_bo, uint32_t target_offset,
1654 uint32_t read_domains, uint32_t write_domain,
1657 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1658 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1659 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
1660 bool fenced_command;
1662 if (bo_gem->has_error)
1665 if (target_bo_gem->has_error) {
1666 bo_gem->has_error = true;
1670 /* We never use HW fences for rendering on 965+ */
1671 if (bufmgr_gem->gen >= 4)
1674 fenced_command = need_fence;
1675 if (target_bo_gem->tiling_mode == I915_TILING_NONE)
1678 /* Create a new relocation list if needed */
1679 if (bo_gem->relocs == NULL && drm_intel_setup_reloc_list(bo))
1682 /* Check overflow */
1683 assert(bo_gem->reloc_count < bufmgr_gem->max_relocs);
1686 assert(offset <= bo->size - 4);
1687 assert((write_domain & (write_domain - 1)) == 0);
1689 /* Make sure that we're not adding a reloc to something whose size has
1690 * already been accounted for.
1692 assert(!bo_gem->used_as_reloc_target);
1693 if (target_bo_gem != bo_gem) {
1694 target_bo_gem->used_as_reloc_target = true;
1695 bo_gem->reloc_tree_size += target_bo_gem->reloc_tree_size;
1697 /* An object needing a fence is a tiled buffer, so it won't have
1698 * relocs to other buffers.
1701 target_bo_gem->reloc_tree_fences = 1;
1702 bo_gem->reloc_tree_fences += target_bo_gem->reloc_tree_fences;
1704 bo_gem->relocs[bo_gem->reloc_count].offset = offset;
1705 bo_gem->relocs[bo_gem->reloc_count].delta = target_offset;
1706 bo_gem->relocs[bo_gem->reloc_count].target_handle =
1707 target_bo_gem->gem_handle;
1708 bo_gem->relocs[bo_gem->reloc_count].read_domains = read_domains;
1709 bo_gem->relocs[bo_gem->reloc_count].write_domain = write_domain;
1710 bo_gem->relocs[bo_gem->reloc_count].presumed_offset = target_bo->offset64;
1712 bo_gem->reloc_target_info[bo_gem->reloc_count].bo = target_bo;
1713 if (target_bo != bo)
1714 drm_intel_gem_bo_reference(target_bo);
1716 bo_gem->reloc_target_info[bo_gem->reloc_count].flags =
1717 DRM_INTEL_RELOC_FENCE;
1719 bo_gem->reloc_target_info[bo_gem->reloc_count].flags = 0;
1721 bo_gem->reloc_count++;
1727 drm_intel_gem_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1728 drm_intel_bo *target_bo, uint32_t target_offset,
1729 uint32_t read_domains, uint32_t write_domain)
1731 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1733 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1734 read_domains, write_domain,
1735 !bufmgr_gem->fenced_relocs);
1739 drm_intel_gem_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
1740 drm_intel_bo *target_bo,
1741 uint32_t target_offset,
1742 uint32_t read_domains, uint32_t write_domain)
1744 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1745 read_domains, write_domain, true);
1749 drm_intel_gem_bo_get_reloc_count(drm_intel_bo *bo)
1751 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1753 return bo_gem->reloc_count;
1757 * Removes existing relocation entries in the BO after "start".
1759 * This allows a user to avoid a two-step process for state setup with
1760 * counting up all the buffer objects and doing a
1761 * drm_intel_bufmgr_check_aperture_space() before emitting any of the
1762 * relocations for the state setup. Instead, save the state of the
1763 * batchbuffer including drm_intel_gem_get_reloc_count(), emit all the
1764 * state, and then check if it still fits in the aperture.
1766 * Any further drm_intel_bufmgr_check_aperture_space() queries
1767 * involving this buffer in the tree are undefined after this call.
1770 drm_intel_gem_bo_clear_relocs(drm_intel_bo *bo, int start)
1772 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1774 struct timespec time;
1776 clock_gettime(CLOCK_MONOTONIC, &time);
1778 assert(bo_gem->reloc_count >= start);
1779 /* Unreference the cleared target buffers */
1780 for (i = start; i < bo_gem->reloc_count; i++) {
1781 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) bo_gem->reloc_target_info[i].bo;
1782 if (&target_bo_gem->bo != bo) {
1783 bo_gem->reloc_tree_fences -= target_bo_gem->reloc_tree_fences;
1784 drm_intel_gem_bo_unreference_locked_timed(&target_bo_gem->bo,
1788 bo_gem->reloc_count = start;
1792 * Walk the tree of relocations rooted at BO and accumulate the list of
1793 * validations to be performed and update the relocation buffers with
1794 * index values into the validation list.
1797 drm_intel_gem_bo_process_reloc(drm_intel_bo *bo)
1799 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1802 if (bo_gem->relocs == NULL)
1805 for (i = 0; i < bo_gem->reloc_count; i++) {
1806 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1808 if (target_bo == bo)
1811 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1813 /* Continue walking the tree depth-first. */
1814 drm_intel_gem_bo_process_reloc(target_bo);
1816 /* Add the target to the validate list */
1817 drm_intel_add_validate_buffer(target_bo);
1822 drm_intel_gem_bo_process_reloc2(drm_intel_bo *bo)
1824 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1827 if (bo_gem->relocs == NULL)
1830 for (i = 0; i < bo_gem->reloc_count; i++) {
1831 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1834 if (target_bo == bo)
1837 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1839 /* Continue walking the tree depth-first. */
1840 drm_intel_gem_bo_process_reloc2(target_bo);
1842 need_fence = (bo_gem->reloc_target_info[i].flags &
1843 DRM_INTEL_RELOC_FENCE);
1845 /* Add the target to the validate list */
1846 drm_intel_add_validate_buffer2(target_bo, need_fence);
1852 drm_intel_update_buffer_offsets(drm_intel_bufmgr_gem *bufmgr_gem)
1856 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1857 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1858 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1860 /* Update the buffer offset */
1861 if (bufmgr_gem->exec_objects[i].offset != bo->offset64) {
1862 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1863 bo_gem->gem_handle, bo_gem->name, bo->offset64,
1864 (unsigned long long)bufmgr_gem->exec_objects[i].
1866 bo->offset64 = bufmgr_gem->exec_objects[i].offset;
1867 bo->offset = bufmgr_gem->exec_objects[i].offset;
1873 drm_intel_update_buffer_offsets2 (drm_intel_bufmgr_gem *bufmgr_gem)
1877 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1878 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1879 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1881 /* Update the buffer offset */
1882 if (bufmgr_gem->exec2_objects[i].offset != bo->offset64) {
1883 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1884 bo_gem->gem_handle, bo_gem->name, bo->offset64,
1885 (unsigned long long)bufmgr_gem->exec2_objects[i].offset);
1886 bo->offset64 = bufmgr_gem->exec2_objects[i].offset;
1887 bo->offset = bufmgr_gem->exec2_objects[i].offset;
1893 aub_out(drm_intel_bufmgr_gem *bufmgr_gem, uint32_t data)
1895 fwrite(&data, 1, 4, bufmgr_gem->aub_file);
1899 aub_out_data(drm_intel_bufmgr_gem *bufmgr_gem, void *data, size_t size)
1901 fwrite(data, 1, size, bufmgr_gem->aub_file);
1905 aub_write_bo_data(drm_intel_bo *bo, uint32_t offset, uint32_t size)
1907 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1908 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1912 data = malloc(bo->size);
1913 drm_intel_bo_get_subdata(bo, offset, size, data);
1915 /* Easy mode: write out bo with no relocations */
1916 if (!bo_gem->reloc_count) {
1917 aub_out_data(bufmgr_gem, data, size);
1922 /* Otherwise, handle the relocations while writing. */
1923 for (i = 0; i < size / 4; i++) {
1925 for (r = 0; r < bo_gem->reloc_count; r++) {
1926 struct drm_i915_gem_relocation_entry *reloc;
1927 drm_intel_reloc_target *info;
1929 reloc = &bo_gem->relocs[r];
1930 info = &bo_gem->reloc_target_info[r];
1932 if (reloc->offset == offset + i * 4) {
1933 drm_intel_bo_gem *target_gem;
1936 target_gem = (drm_intel_bo_gem *)info->bo;
1939 val += target_gem->aub_offset;
1941 aub_out(bufmgr_gem, val);
1946 if (r == bo_gem->reloc_count) {
1947 /* no relocation, just the data */
1948 aub_out(bufmgr_gem, data[i]);
1956 aub_bo_get_address(drm_intel_bo *bo)
1958 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1959 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1961 /* Give the object a graphics address in the AUB file. We
1962 * don't just use the GEM object address because we do AUB
1963 * dumping before execution -- we want to successfully log
1964 * when the hardware might hang, and we might even want to aub
1965 * capture for a driver trying to execute on a different
1966 * generation of hardware by disabling the actual kernel exec
1969 bo_gem->aub_offset = bufmgr_gem->aub_offset;
1970 bufmgr_gem->aub_offset += bo->size;
1971 /* XXX: Handle aperture overflow. */
1972 assert(bufmgr_gem->aub_offset < 256 * 1024 * 1024);
1976 aub_write_trace_block(drm_intel_bo *bo, uint32_t type, uint32_t subtype,
1977 uint32_t offset, uint32_t size)
1979 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1980 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1983 CMD_AUB_TRACE_HEADER_BLOCK |
1984 ((bufmgr_gem->gen >= 8 ? 6 : 5) - 2));
1986 AUB_TRACE_MEMTYPE_GTT | type | AUB_TRACE_OP_DATA_WRITE);
1987 aub_out(bufmgr_gem, subtype);
1988 aub_out(bufmgr_gem, bo_gem->aub_offset + offset);
1989 aub_out(bufmgr_gem, size);
1990 if (bufmgr_gem->gen >= 8)
1991 aub_out(bufmgr_gem, 0);
1992 aub_write_bo_data(bo, offset, size);
1996 * Break up large objects into multiple writes. Otherwise a 128kb VBO
1997 * would overflow the 16 bits of size field in the packet header and
1998 * everything goes badly after that.
2001 aub_write_large_trace_block(drm_intel_bo *bo, uint32_t type, uint32_t subtype,
2002 uint32_t offset, uint32_t size)
2004 uint32_t block_size;
2005 uint32_t sub_offset;
2007 for (sub_offset = 0; sub_offset < size; sub_offset += block_size) {
2008 block_size = size - sub_offset;
2010 if (block_size > 8 * 4096)
2011 block_size = 8 * 4096;
2013 aub_write_trace_block(bo, type, subtype, offset + sub_offset,
2019 aub_write_bo(drm_intel_bo *bo)
2021 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2022 uint32_t offset = 0;
2025 aub_bo_get_address(bo);
2027 /* Write out each annotated section separately. */
2028 for (i = 0; i < bo_gem->aub_annotation_count; ++i) {
2029 drm_intel_aub_annotation *annotation =
2030 &bo_gem->aub_annotations[i];
2031 uint32_t ending_offset = annotation->ending_offset;
2032 if (ending_offset > bo->size)
2033 ending_offset = bo->size;
2034 if (ending_offset > offset) {
2035 aub_write_large_trace_block(bo, annotation->type,
2036 annotation->subtype,
2038 ending_offset - offset);
2039 offset = ending_offset;
2043 /* Write out any remaining unannotated data */
2044 if (offset < bo->size) {
2045 aub_write_large_trace_block(bo, AUB_TRACE_TYPE_NOTYPE, 0,
2046 offset, bo->size - offset);
2051 * Make a ringbuffer on fly and dump it
2054 aub_build_dump_ringbuffer(drm_intel_bufmgr_gem *bufmgr_gem,
2055 uint32_t batch_buffer, int ring_flag)
2057 uint32_t ringbuffer[4096];
2058 int ring = AUB_TRACE_TYPE_RING_PRB0; /* The default ring */
2061 if (ring_flag == I915_EXEC_BSD)
2062 ring = AUB_TRACE_TYPE_RING_PRB1;
2063 else if (ring_flag == I915_EXEC_BLT)
2064 ring = AUB_TRACE_TYPE_RING_PRB2;
2066 /* Make a ring buffer to execute our batchbuffer. */
2067 memset(ringbuffer, 0, sizeof(ringbuffer));
2068 if (bufmgr_gem->gen >= 8) {
2069 ringbuffer[ring_count++] = AUB_MI_BATCH_BUFFER_START | (3 - 2);
2070 ringbuffer[ring_count++] = batch_buffer;
2071 ringbuffer[ring_count++] = 0;
2073 ringbuffer[ring_count++] = AUB_MI_BATCH_BUFFER_START;
2074 ringbuffer[ring_count++] = batch_buffer;
2077 /* Write out the ring. This appears to trigger execution of
2078 * the ring in the simulator.
2081 CMD_AUB_TRACE_HEADER_BLOCK |
2082 ((bufmgr_gem->gen >= 8 ? 6 : 5) - 2));
2084 AUB_TRACE_MEMTYPE_GTT | ring | AUB_TRACE_OP_COMMAND_WRITE);
2085 aub_out(bufmgr_gem, 0); /* general/surface subtype */
2086 aub_out(bufmgr_gem, bufmgr_gem->aub_offset);
2087 aub_out(bufmgr_gem, ring_count * 4);
2088 if (bufmgr_gem->gen >= 8)
2089 aub_out(bufmgr_gem, 0);
2091 /* FIXME: Need some flush operations here? */
2092 aub_out_data(bufmgr_gem, ringbuffer, ring_count * 4);
2094 /* Update offset pointer */
2095 bufmgr_gem->aub_offset += 4096;
2099 drm_intel_gem_bo_aub_dump_bmp(drm_intel_bo *bo,
2100 int x1, int y1, int width, int height,
2101 enum aub_dump_bmp_format format,
2102 int pitch, int offset)
2104 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2105 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
2109 case AUB_DUMP_BMP_FORMAT_8BIT:
2112 case AUB_DUMP_BMP_FORMAT_ARGB_4444:
2115 case AUB_DUMP_BMP_FORMAT_ARGB_0888:
2116 case AUB_DUMP_BMP_FORMAT_ARGB_8888:
2120 printf("Unknown AUB dump format %d\n", format);
2124 if (!bufmgr_gem->aub_file)
2127 aub_out(bufmgr_gem, CMD_AUB_DUMP_BMP | 4);
2128 aub_out(bufmgr_gem, (y1 << 16) | x1);
2133 aub_out(bufmgr_gem, (height << 16) | width);
2134 aub_out(bufmgr_gem, bo_gem->aub_offset + offset);
2136 ((bo_gem->tiling_mode != I915_TILING_NONE) ? (1 << 2) : 0) |
2137 ((bo_gem->tiling_mode == I915_TILING_Y) ? (1 << 3) : 0));
2141 aub_exec(drm_intel_bo *bo, int ring_flag, int used)
2143 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2144 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2146 bool batch_buffer_needs_annotations;
2148 if (!bufmgr_gem->aub_file)
2151 /* If batch buffer is not annotated, annotate it the best we
2154 batch_buffer_needs_annotations = bo_gem->aub_annotation_count == 0;
2155 if (batch_buffer_needs_annotations) {
2156 drm_intel_aub_annotation annotations[2] = {
2157 { AUB_TRACE_TYPE_BATCH, 0, used },
2158 { AUB_TRACE_TYPE_NOTYPE, 0, bo->size }
2160 drm_intel_bufmgr_gem_set_aub_annotations(bo, annotations, 2);
2163 /* Write out all buffers to AUB memory */
2164 for (i = 0; i < bufmgr_gem->exec_count; i++) {
2165 aub_write_bo(bufmgr_gem->exec_bos[i]);
2168 /* Remove any annotations we added */
2169 if (batch_buffer_needs_annotations)
2170 drm_intel_bufmgr_gem_set_aub_annotations(bo, NULL, 0);
2172 /* Dump ring buffer */
2173 aub_build_dump_ringbuffer(bufmgr_gem, bo_gem->aub_offset, ring_flag);
2175 fflush(bufmgr_gem->aub_file);
2178 * One frame has been dumped. So reset the aub_offset for the next frame.
2180 * FIXME: Can we do this?
2182 bufmgr_gem->aub_offset = 0x10000;
2186 drm_intel_gem_bo_exec(drm_intel_bo *bo, int used,
2187 drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
2189 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2190 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2191 struct drm_i915_gem_execbuffer execbuf;
2194 if (bo_gem->has_error)
2197 pthread_mutex_lock(&bufmgr_gem->lock);
2198 /* Update indices and set up the validate list. */
2199 drm_intel_gem_bo_process_reloc(bo);
2201 /* Add the batch buffer to the validation list. There are no
2202 * relocations pointing to it.
2204 drm_intel_add_validate_buffer(bo);
2207 execbuf.buffers_ptr = (uintptr_t) bufmgr_gem->exec_objects;
2208 execbuf.buffer_count = bufmgr_gem->exec_count;
2209 execbuf.batch_start_offset = 0;
2210 execbuf.batch_len = used;
2211 execbuf.cliprects_ptr = (uintptr_t) cliprects;
2212 execbuf.num_cliprects = num_cliprects;
2216 ret = drmIoctl(bufmgr_gem->fd,
2217 DRM_IOCTL_I915_GEM_EXECBUFFER,
2221 if (errno == ENOSPC) {
2222 DBG("Execbuffer fails to pin. "
2223 "Estimate: %u. Actual: %u. Available: %u\n",
2224 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
2227 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
2230 (unsigned int)bufmgr_gem->gtt_size);
2233 drm_intel_update_buffer_offsets(bufmgr_gem);
2235 if (bufmgr_gem->bufmgr.debug)
2236 drm_intel_gem_dump_validation_list(bufmgr_gem);
2238 for (i = 0; i < bufmgr_gem->exec_count; i++) {
2239 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
2240 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2242 bo_gem->idle = false;
2244 /* Disconnect the buffer from the validate list */
2245 bo_gem->validate_index = -1;
2246 bufmgr_gem->exec_bos[i] = NULL;
2248 bufmgr_gem->exec_count = 0;
2249 pthread_mutex_unlock(&bufmgr_gem->lock);
2255 do_exec2(drm_intel_bo *bo, int used, drm_intel_context *ctx,
2256 drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
2259 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
2260 struct drm_i915_gem_execbuffer2 execbuf;
2264 switch (flags & 0x7) {
2268 if (!bufmgr_gem->has_blt)
2272 if (!bufmgr_gem->has_bsd)
2275 case I915_EXEC_VEBOX:
2276 if (!bufmgr_gem->has_vebox)
2279 case I915_EXEC_RENDER:
2280 case I915_EXEC_DEFAULT:
2284 pthread_mutex_lock(&bufmgr_gem->lock);
2285 /* Update indices and set up the validate list. */
2286 drm_intel_gem_bo_process_reloc2(bo);
2288 /* Add the batch buffer to the validation list. There are no relocations
2291 drm_intel_add_validate_buffer2(bo, 0);
2294 execbuf.buffers_ptr = (uintptr_t)bufmgr_gem->exec2_objects;
2295 execbuf.buffer_count = bufmgr_gem->exec_count;
2296 execbuf.batch_start_offset = 0;
2297 execbuf.batch_len = used;
2298 execbuf.cliprects_ptr = (uintptr_t)cliprects;
2299 execbuf.num_cliprects = num_cliprects;
2302 execbuf.flags = flags;
2304 i915_execbuffer2_set_context_id(execbuf, 0);
2306 i915_execbuffer2_set_context_id(execbuf, ctx->ctx_id);
2309 aub_exec(bo, flags, used);
2311 if (bufmgr_gem->no_exec)
2312 goto skip_execution;
2314 ret = drmIoctl(bufmgr_gem->fd,
2315 DRM_IOCTL_I915_GEM_EXECBUFFER2,
2319 if (ret == -ENOSPC) {
2320 DBG("Execbuffer fails to pin. "
2321 "Estimate: %u. Actual: %u. Available: %u\n",
2322 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
2323 bufmgr_gem->exec_count),
2324 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
2325 bufmgr_gem->exec_count),
2326 (unsigned int) bufmgr_gem->gtt_size);
2329 drm_intel_update_buffer_offsets2(bufmgr_gem);
2332 if (bufmgr_gem->bufmgr.debug)
2333 drm_intel_gem_dump_validation_list(bufmgr_gem);
2335 for (i = 0; i < bufmgr_gem->exec_count; i++) {
2336 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
2337 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
2339 bo_gem->idle = false;
2341 /* Disconnect the buffer from the validate list */
2342 bo_gem->validate_index = -1;
2343 bufmgr_gem->exec_bos[i] = NULL;
2345 bufmgr_gem->exec_count = 0;
2346 pthread_mutex_unlock(&bufmgr_gem->lock);
2352 drm_intel_gem_bo_exec2(drm_intel_bo *bo, int used,
2353 drm_clip_rect_t *cliprects, int num_cliprects,
2356 return do_exec2(bo, used, NULL, cliprects, num_cliprects, DR4,
2361 drm_intel_gem_bo_mrb_exec2(drm_intel_bo *bo, int used,
2362 drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
2365 return do_exec2(bo, used, NULL, cliprects, num_cliprects, DR4,
2370 drm_intel_gem_bo_context_exec(drm_intel_bo *bo, drm_intel_context *ctx,
2371 int used, unsigned int flags)
2373 return do_exec2(bo, used, ctx, NULL, 0, 0, flags);
2377 drm_intel_gem_bo_pin(drm_intel_bo *bo, uint32_t alignment)
2379 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2380 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2381 struct drm_i915_gem_pin pin;
2385 pin.handle = bo_gem->gem_handle;
2386 pin.alignment = alignment;
2388 ret = drmIoctl(bufmgr_gem->fd,
2389 DRM_IOCTL_I915_GEM_PIN,
2394 bo->offset64 = pin.offset;
2395 bo->offset = pin.offset;
2400 drm_intel_gem_bo_unpin(drm_intel_bo *bo)
2402 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2403 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2404 struct drm_i915_gem_unpin unpin;
2408 unpin.handle = bo_gem->gem_handle;
2410 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_UNPIN, &unpin);
2418 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
2419 uint32_t tiling_mode,
2422 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2423 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2424 struct drm_i915_gem_set_tiling set_tiling;
2427 if (bo_gem->global_name == 0 &&
2428 tiling_mode == bo_gem->tiling_mode &&
2429 stride == bo_gem->stride)
2432 memset(&set_tiling, 0, sizeof(set_tiling));
2434 /* set_tiling is slightly broken and overwrites the
2435 * input on the error path, so we have to open code
2438 set_tiling.handle = bo_gem->gem_handle;
2439 set_tiling.tiling_mode = tiling_mode;
2440 set_tiling.stride = stride;
2442 ret = ioctl(bufmgr_gem->fd,
2443 DRM_IOCTL_I915_GEM_SET_TILING,
2445 } while (ret == -1 && (errno == EINTR || errno == EAGAIN));
2449 bo_gem->tiling_mode = set_tiling.tiling_mode;
2450 bo_gem->swizzle_mode = set_tiling.swizzle_mode;
2451 bo_gem->stride = set_tiling.stride;
2456 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
2459 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2460 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2463 /* Linear buffers have no stride. By ensuring that we only ever use
2464 * stride 0 with linear buffers, we simplify our code.
2466 if (*tiling_mode == I915_TILING_NONE)
2469 ret = drm_intel_gem_bo_set_tiling_internal(bo, *tiling_mode, stride);
2471 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
2473 *tiling_mode = bo_gem->tiling_mode;
2478 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
2479 uint32_t * swizzle_mode)
2481 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2483 *tiling_mode = bo_gem->tiling_mode;
2484 *swizzle_mode = bo_gem->swizzle_mode;
2489 drm_intel_bo_gem_create_from_prime(drm_intel_bufmgr *bufmgr, int prime_fd, int size)
2491 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
2494 drm_intel_bo_gem *bo_gem;
2495 struct drm_i915_gem_get_tiling get_tiling;
2496 drmMMListHead *list;
2498 ret = drmPrimeFDToHandle(bufmgr_gem->fd, prime_fd, &handle);
2501 * See if the kernel has already returned this buffer to us. Just as
2502 * for named buffers, we must not create two bo's pointing at the same
2505 for (list = bufmgr_gem->named.next;
2506 list != &bufmgr_gem->named;
2507 list = list->next) {
2508 bo_gem = DRMLISTENTRY(drm_intel_bo_gem, list, name_list);
2509 if (bo_gem->gem_handle == handle) {
2510 drm_intel_gem_bo_reference(&bo_gem->bo);
2516 fprintf(stderr,"ret is %d %d\n", ret, errno);
2520 bo_gem = calloc(1, sizeof(*bo_gem));
2524 /* Determine size of bo. The fd-to-handle ioctl really should
2525 * return the size, but it doesn't. If we have kernel 3.12 or
2526 * later, we can lseek on the prime fd to get the size. Older
2527 * kernels will just fail, in which case we fall back to the
2528 * provided (estimated or guess size). */
2529 ret = lseek(prime_fd, 0, SEEK_END);
2531 bo_gem->bo.size = ret;
2533 bo_gem->bo.size = size;
2535 bo_gem->bo.handle = handle;
2536 bo_gem->bo.bufmgr = bufmgr;
2538 bo_gem->gem_handle = handle;
2540 atomic_set(&bo_gem->refcount, 1);
2542 bo_gem->name = "prime";
2543 bo_gem->validate_index = -1;
2544 bo_gem->reloc_tree_fences = 0;
2545 bo_gem->used_as_reloc_target = false;
2546 bo_gem->has_error = false;
2547 bo_gem->reusable = false;
2549 DRMINITLISTHEAD(&bo_gem->vma_list);
2550 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
2552 VG_CLEAR(get_tiling);
2553 get_tiling.handle = bo_gem->gem_handle;
2554 ret = drmIoctl(bufmgr_gem->fd,
2555 DRM_IOCTL_I915_GEM_GET_TILING,
2558 drm_intel_gem_bo_unreference(&bo_gem->bo);
2561 bo_gem->tiling_mode = get_tiling.tiling_mode;
2562 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
2563 /* XXX stride is unknown */
2564 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
2570 drm_intel_bo_gem_export_to_prime(drm_intel_bo *bo, int *prime_fd)
2572 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2573 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2575 if (DRMLISTEMPTY(&bo_gem->name_list))
2576 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
2578 if (drmPrimeHandleToFD(bufmgr_gem->fd, bo_gem->gem_handle,
2579 DRM_CLOEXEC, prime_fd) != 0)
2582 bo_gem->reusable = false;
2588 drm_intel_gem_bo_flink(drm_intel_bo *bo, uint32_t * name)
2590 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2591 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2594 if (!bo_gem->global_name) {
2595 struct drm_gem_flink flink;
2598 flink.handle = bo_gem->gem_handle;
2600 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_FLINK, &flink);
2604 bo_gem->global_name = flink.name;
2605 bo_gem->reusable = false;
2607 if (DRMLISTEMPTY(&bo_gem->name_list))
2608 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
2611 *name = bo_gem->global_name;
2616 * Enables unlimited caching of buffer objects for reuse.
2618 * This is potentially very memory expensive, as the cache at each bucket
2619 * size is only bounded by how many buffers of that size we've managed to have
2620 * in flight at once.
2623 drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr)
2625 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
2627 bufmgr_gem->bo_reuse = true;
2631 * Enable use of fenced reloc type.
2633 * New code should enable this to avoid unnecessary fence register
2634 * allocation. If this option is not enabled, all relocs will have fence
2635 * register allocated.
2638 drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr)
2640 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
2642 if (bufmgr_gem->bufmgr.bo_exec == drm_intel_gem_bo_exec2)
2643 bufmgr_gem->fenced_relocs = true;
2647 * Return the additional aperture space required by the tree of buffer objects
2651 drm_intel_gem_bo_get_aperture_space(drm_intel_bo *bo)
2653 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2657 if (bo == NULL || bo_gem->included_in_check_aperture)
2661 bo_gem->included_in_check_aperture = true;
2663 for (i = 0; i < bo_gem->reloc_count; i++)
2665 drm_intel_gem_bo_get_aperture_space(bo_gem->
2666 reloc_target_info[i].bo);
2672 * Count the number of buffers in this list that need a fence reg
2674 * If the count is greater than the number of available regs, we'll have
2675 * to ask the caller to resubmit a batch with fewer tiled buffers.
2677 * This function over-counts if the same buffer is used multiple times.
2680 drm_intel_gem_total_fences(drm_intel_bo ** bo_array, int count)
2683 unsigned int total = 0;
2685 for (i = 0; i < count; i++) {
2686 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
2691 total += bo_gem->reloc_tree_fences;
2697 * Clear the flag set by drm_intel_gem_bo_get_aperture_space() so we're ready
2698 * for the next drm_intel_bufmgr_check_aperture_space() call.
2701 drm_intel_gem_bo_clear_aperture_space_flag(drm_intel_bo *bo)
2703 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2706 if (bo == NULL || !bo_gem->included_in_check_aperture)
2709 bo_gem->included_in_check_aperture = false;
2711 for (i = 0; i < bo_gem->reloc_count; i++)
2712 drm_intel_gem_bo_clear_aperture_space_flag(bo_gem->
2713 reloc_target_info[i].bo);
2717 * Return a conservative estimate for the amount of aperture required
2718 * for a collection of buffers. This may double-count some buffers.
2721 drm_intel_gem_estimate_batch_space(drm_intel_bo **bo_array, int count)
2724 unsigned int total = 0;
2726 for (i = 0; i < count; i++) {
2727 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
2729 total += bo_gem->reloc_tree_size;
2735 * Return the amount of aperture needed for a collection of buffers.
2736 * This avoids double counting any buffers, at the cost of looking
2737 * at every buffer in the set.
2740 drm_intel_gem_compute_batch_space(drm_intel_bo **bo_array, int count)
2743 unsigned int total = 0;
2745 for (i = 0; i < count; i++) {
2746 total += drm_intel_gem_bo_get_aperture_space(bo_array[i]);
2747 /* For the first buffer object in the array, we get an
2748 * accurate count back for its reloc_tree size (since nothing
2749 * had been flagged as being counted yet). We can save that
2750 * value out as a more conservative reloc_tree_size that
2751 * avoids double-counting target buffers. Since the first
2752 * buffer happens to usually be the batch buffer in our
2753 * callers, this can pull us back from doing the tree
2754 * walk on every new batch emit.
2757 drm_intel_bo_gem *bo_gem =
2758 (drm_intel_bo_gem *) bo_array[i];
2759 bo_gem->reloc_tree_size = total;
2763 for (i = 0; i < count; i++)
2764 drm_intel_gem_bo_clear_aperture_space_flag(bo_array[i]);
2769 * Return -1 if the batchbuffer should be flushed before attempting to
2770 * emit rendering referencing the buffers pointed to by bo_array.
2772 * This is required because if we try to emit a batchbuffer with relocations
2773 * to a tree of buffers that won't simultaneously fit in the aperture,
2774 * the rendering will return an error at a point where the software is not
2775 * prepared to recover from it.
2777 * However, we also want to emit the batchbuffer significantly before we reach
2778 * the limit, as a series of batchbuffers each of which references buffers
2779 * covering almost all of the aperture means that at each emit we end up
2780 * waiting to evict a buffer from the last rendering, and we get synchronous
2781 * performance. By emitting smaller batchbuffers, we eat some CPU overhead to
2782 * get better parallelism.
2785 drm_intel_gem_check_aperture_space(drm_intel_bo **bo_array, int count)
2787 drm_intel_bufmgr_gem *bufmgr_gem =
2788 (drm_intel_bufmgr_gem *) bo_array[0]->bufmgr;
2789 unsigned int total = 0;
2790 unsigned int threshold = bufmgr_gem->gtt_size * 3 / 4;
2793 /* Check for fence reg constraints if necessary */
2794 if (bufmgr_gem->available_fences) {
2795 total_fences = drm_intel_gem_total_fences(bo_array, count);
2796 if (total_fences > bufmgr_gem->available_fences)
2800 total = drm_intel_gem_estimate_batch_space(bo_array, count);
2802 if (total > threshold)
2803 total = drm_intel_gem_compute_batch_space(bo_array, count);
2805 if (total > threshold) {
2806 DBG("check_space: overflowed available aperture, "
2808 total / 1024, (int)bufmgr_gem->gtt_size / 1024);
2811 DBG("drm_check_space: total %dkb vs bufgr %dkb\n", total / 1024,
2812 (int)bufmgr_gem->gtt_size / 1024);
2818 * Disable buffer reuse for objects which are shared with the kernel
2819 * as scanout buffers
2822 drm_intel_gem_bo_disable_reuse(drm_intel_bo *bo)
2824 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2826 bo_gem->reusable = false;
2831 drm_intel_gem_bo_is_reusable(drm_intel_bo *bo)
2833 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2835 return bo_gem->reusable;
2839 _drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
2841 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2844 for (i = 0; i < bo_gem->reloc_count; i++) {
2845 if (bo_gem->reloc_target_info[i].bo == target_bo)
2847 if (bo == bo_gem->reloc_target_info[i].bo)
2849 if (_drm_intel_gem_bo_references(bo_gem->reloc_target_info[i].bo,
2857 /** Return true if target_bo is referenced by bo's relocation tree. */
2859 drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
2861 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
2863 if (bo == NULL || target_bo == NULL)
2865 if (target_bo_gem->used_as_reloc_target)
2866 return _drm_intel_gem_bo_references(bo, target_bo);
2871 add_bucket(drm_intel_bufmgr_gem *bufmgr_gem, int size)
2873 unsigned int i = bufmgr_gem->num_buckets;
2875 assert(i < ARRAY_SIZE(bufmgr_gem->cache_bucket));
2877 DRMINITLISTHEAD(&bufmgr_gem->cache_bucket[i].head);
2878 bufmgr_gem->cache_bucket[i].size = size;
2879 bufmgr_gem->num_buckets++;
2883 init_cache_buckets(drm_intel_bufmgr_gem *bufmgr_gem)
2885 unsigned long size, cache_max_size = 64 * 1024 * 1024;
2887 /* OK, so power of two buckets was too wasteful of memory.
2888 * Give 3 other sizes between each power of two, to hopefully
2889 * cover things accurately enough. (The alternative is
2890 * probably to just go for exact matching of sizes, and assume
2891 * that for things like composited window resize the tiled
2892 * width/height alignment and rounding of sizes to pages will
2893 * get us useful cache hit rates anyway)
2895 add_bucket(bufmgr_gem, 4096);
2896 add_bucket(bufmgr_gem, 4096 * 2);
2897 add_bucket(bufmgr_gem, 4096 * 3);
2899 /* Initialize the linked lists for BO reuse cache. */
2900 for (size = 4 * 4096; size <= cache_max_size; size *= 2) {
2901 add_bucket(bufmgr_gem, size);
2903 add_bucket(bufmgr_gem, size + size * 1 / 4);
2904 add_bucket(bufmgr_gem, size + size * 2 / 4);
2905 add_bucket(bufmgr_gem, size + size * 3 / 4);
2910 drm_intel_bufmgr_gem_set_vma_cache_size(drm_intel_bufmgr *bufmgr, int limit)
2912 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
2914 bufmgr_gem->vma_max = limit;
2916 drm_intel_gem_bo_purge_vma_cache(bufmgr_gem);
2920 * Get the PCI ID for the device. This can be overridden by setting the
2921 * INTEL_DEVID_OVERRIDE environment variable to the desired ID.
2924 get_pci_device_id(drm_intel_bufmgr_gem *bufmgr_gem)
2926 char *devid_override;
2929 drm_i915_getparam_t gp;
2931 if (geteuid() == getuid()) {
2932 devid_override = getenv("INTEL_DEVID_OVERRIDE");
2933 if (devid_override) {
2934 bufmgr_gem->no_exec = true;
2935 return strtod(devid_override, NULL);
2941 gp.param = I915_PARAM_CHIPSET_ID;
2943 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2945 fprintf(stderr, "get chip id failed: %d [%d]\n", ret, errno);
2946 fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value);
2952 drm_intel_bufmgr_gem_get_devid(drm_intel_bufmgr *bufmgr)
2954 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
2956 return bufmgr_gem->pci_device;
2960 * Sets the AUB filename.
2962 * This function has to be called before drm_intel_bufmgr_gem_set_aub_dump()
2963 * for it to have any effect.
2966 drm_intel_bufmgr_gem_set_aub_filename(drm_intel_bufmgr *bufmgr,
2967 const char *filename)
2969 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
2971 free(bufmgr_gem->aub_filename);
2973 bufmgr_gem->aub_filename = strdup(filename);
2977 * Sets up AUB dumping.
2979 * This is a trace file format that can be used with the simulator.
2980 * Packets are emitted in a format somewhat like GPU command packets.
2981 * You can set up a GTT and upload your objects into the referenced
2982 * space, then send off batchbuffers and get BMPs out the other end.
2985 drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable)
2987 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
2988 int entry = 0x200003;
2990 int gtt_size = 0x10000;
2991 const char *filename;
2994 if (bufmgr_gem->aub_file) {
2995 fclose(bufmgr_gem->aub_file);
2996 bufmgr_gem->aub_file = NULL;
3001 if (geteuid() != getuid())
3004 if (bufmgr_gem->aub_filename)
3005 filename = bufmgr_gem->aub_filename;
3007 filename = "intel.aub";
3008 bufmgr_gem->aub_file = fopen(filename, "w+");
3009 if (!bufmgr_gem->aub_file)
3012 /* Start allocating objects from just after the GTT. */
3013 bufmgr_gem->aub_offset = gtt_size;
3015 /* Start with a (required) version packet. */
3016 aub_out(bufmgr_gem, CMD_AUB_HEADER | (13 - 2));
3018 (4 << AUB_HEADER_MAJOR_SHIFT) |
3019 (0 << AUB_HEADER_MINOR_SHIFT));
3020 for (i = 0; i < 8; i++) {
3021 aub_out(bufmgr_gem, 0); /* app name */
3023 aub_out(bufmgr_gem, 0); /* timestamp */
3024 aub_out(bufmgr_gem, 0); /* timestamp */
3025 aub_out(bufmgr_gem, 0); /* comment len */
3027 /* Set up the GTT. The max we can handle is 256M */
3028 aub_out(bufmgr_gem, CMD_AUB_TRACE_HEADER_BLOCK | ((bufmgr_gem->gen >= 8 ? 6 : 5) - 2));
3029 aub_out(bufmgr_gem, AUB_TRACE_MEMTYPE_NONLOCAL | 0 | AUB_TRACE_OP_DATA_WRITE);
3030 aub_out(bufmgr_gem, 0); /* subtype */
3031 aub_out(bufmgr_gem, 0); /* offset */
3032 aub_out(bufmgr_gem, gtt_size); /* size */
3033 if (bufmgr_gem->gen >= 8)
3034 aub_out(bufmgr_gem, 0);
3035 for (i = 0x000; i < gtt_size; i += 4, entry += 0x1000) {
3036 aub_out(bufmgr_gem, entry);
3041 drm_intel_gem_context_create(drm_intel_bufmgr *bufmgr)
3043 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
3044 struct drm_i915_gem_context_create create;
3045 drm_intel_context *context = NULL;
3048 context = calloc(1, sizeof(*context));
3053 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_CONTEXT_CREATE, &create);
3055 DBG("DRM_IOCTL_I915_GEM_CONTEXT_CREATE failed: %s\n",
3061 context->ctx_id = create.ctx_id;
3062 context->bufmgr = bufmgr;
3068 drm_intel_gem_context_destroy(drm_intel_context *ctx)
3070 drm_intel_bufmgr_gem *bufmgr_gem;
3071 struct drm_i915_gem_context_destroy destroy;
3079 bufmgr_gem = (drm_intel_bufmgr_gem *)ctx->bufmgr;
3080 destroy.ctx_id = ctx->ctx_id;
3081 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_CONTEXT_DESTROY,
3084 fprintf(stderr, "DRM_IOCTL_I915_GEM_CONTEXT_DESTROY failed: %s\n",
3091 drm_intel_get_reset_stats(drm_intel_context *ctx,
3092 uint32_t *reset_count,
3096 drm_intel_bufmgr_gem *bufmgr_gem;
3097 struct drm_i915_reset_stats stats;
3103 memset(&stats, 0, sizeof(stats));
3105 bufmgr_gem = (drm_intel_bufmgr_gem *)ctx->bufmgr;
3106 stats.ctx_id = ctx->ctx_id;
3107 ret = drmIoctl(bufmgr_gem->fd,
3108 DRM_IOCTL_I915_GET_RESET_STATS,
3111 if (reset_count != NULL)
3112 *reset_count = stats.reset_count;
3115 *active = stats.batch_active;
3117 if (pending != NULL)
3118 *pending = stats.batch_pending;
3125 drm_intel_reg_read(drm_intel_bufmgr *bufmgr,
3129 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
3130 struct drm_i915_reg_read reg_read;
3134 reg_read.offset = offset;
3136 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_REG_READ, ®_read);
3138 *result = reg_read.val;
3144 * Annotate the given bo for use in aub dumping.
3146 * \param annotations is an array of drm_intel_aub_annotation objects
3147 * describing the type of data in various sections of the bo. Each
3148 * element of the array specifies the type and subtype of a section of
3149 * the bo, and the past-the-end offset of that section. The elements
3150 * of \c annotations must be sorted so that ending_offset is
3153 * \param count is the number of elements in the \c annotations array.
3154 * If \c count is zero, then \c annotations will not be dereferenced.
3156 * Annotations are copied into a private data structure, so caller may
3157 * re-use the memory pointed to by \c annotations after the call
3160 * Annotations are stored for the lifetime of the bo; to reset to the
3161 * default state (no annotations), call this function with a \c count
3165 drm_intel_bufmgr_gem_set_aub_annotations(drm_intel_bo *bo,
3166 drm_intel_aub_annotation *annotations,
3169 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
3170 unsigned size = sizeof(*annotations) * count;
3171 drm_intel_aub_annotation *new_annotations =
3172 count > 0 ? realloc(bo_gem->aub_annotations, size) : NULL;
3173 if (new_annotations == NULL) {
3174 free(bo_gem->aub_annotations);
3175 bo_gem->aub_annotations = NULL;
3176 bo_gem->aub_annotation_count = 0;
3179 memcpy(new_annotations, annotations, size);
3180 bo_gem->aub_annotations = new_annotations;
3181 bo_gem->aub_annotation_count = count;
3185 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
3186 * and manage map buffer objections.
3188 * \param fd File descriptor of the opened DRM device.
3191 drm_intel_bufmgr_gem_init(int fd, int batch_size)
3193 drm_intel_bufmgr_gem *bufmgr_gem;
3194 struct drm_i915_gem_get_aperture aperture;
3195 drm_i915_getparam_t gp;
3199 bufmgr_gem = calloc(1, sizeof(*bufmgr_gem));
3200 if (bufmgr_gem == NULL)
3203 bufmgr_gem->fd = fd;
3205 if (pthread_mutex_init(&bufmgr_gem->lock, NULL) != 0) {
3210 ret = drmIoctl(bufmgr_gem->fd,
3211 DRM_IOCTL_I915_GEM_GET_APERTURE,
3215 bufmgr_gem->gtt_size = aperture.aper_available_size;
3217 fprintf(stderr, "DRM_IOCTL_I915_GEM_APERTURE failed: %s\n",
3219 bufmgr_gem->gtt_size = 128 * 1024 * 1024;
3220 fprintf(stderr, "Assuming %dkB available aperture size.\n"
3221 "May lead to reduced performance or incorrect "
3223 (int)bufmgr_gem->gtt_size / 1024);
3226 bufmgr_gem->pci_device = get_pci_device_id(bufmgr_gem);
3228 if (IS_GEN2(bufmgr_gem->pci_device))
3229 bufmgr_gem->gen = 2;
3230 else if (IS_GEN3(bufmgr_gem->pci_device))
3231 bufmgr_gem->gen = 3;
3232 else if (IS_GEN4(bufmgr_gem->pci_device))
3233 bufmgr_gem->gen = 4;
3234 else if (IS_GEN5(bufmgr_gem->pci_device))
3235 bufmgr_gem->gen = 5;
3236 else if (IS_GEN6(bufmgr_gem->pci_device))
3237 bufmgr_gem->gen = 6;
3238 else if (IS_GEN7(bufmgr_gem->pci_device))
3239 bufmgr_gem->gen = 7;
3240 else if (IS_GEN8(bufmgr_gem->pci_device))
3241 bufmgr_gem->gen = 8;
3247 if (IS_GEN3(bufmgr_gem->pci_device) &&
3248 bufmgr_gem->gtt_size > 256*1024*1024) {
3249 /* The unmappable part of gtt on gen 3 (i.e. above 256MB) can't
3250 * be used for tiled blits. To simplify the accounting, just
3251 * substract the unmappable part (fixed to 256MB on all known
3252 * gen3 devices) if the kernel advertises it. */
3253 bufmgr_gem->gtt_size -= 256*1024*1024;
3259 gp.param = I915_PARAM_HAS_EXECBUF2;
3260 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3264 gp.param = I915_PARAM_HAS_BSD;
3265 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3266 bufmgr_gem->has_bsd = ret == 0;
3268 gp.param = I915_PARAM_HAS_BLT;
3269 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3270 bufmgr_gem->has_blt = ret == 0;
3272 gp.param = I915_PARAM_HAS_RELAXED_FENCING;
3273 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3274 bufmgr_gem->has_relaxed_fencing = ret == 0;
3276 gp.param = I915_PARAM_HAS_WAIT_TIMEOUT;
3277 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3278 bufmgr_gem->has_wait_timeout = ret == 0;
3280 gp.param = I915_PARAM_HAS_LLC;
3281 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3283 /* Kernel does not supports HAS_LLC query, fallback to GPU
3284 * generation detection and assume that we have LLC on GEN6/7
3286 bufmgr_gem->has_llc = (IS_GEN6(bufmgr_gem->pci_device) |
3287 IS_GEN7(bufmgr_gem->pci_device));
3289 bufmgr_gem->has_llc = *gp.value;
3291 gp.param = I915_PARAM_HAS_VEBOX;
3292 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3293 bufmgr_gem->has_vebox = (ret == 0) & (*gp.value > 0);
3295 if (bufmgr_gem->gen < 4) {
3296 gp.param = I915_PARAM_NUM_FENCES_AVAIL;
3297 gp.value = &bufmgr_gem->available_fences;
3298 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3300 fprintf(stderr, "get fences failed: %d [%d]\n", ret,
3302 fprintf(stderr, "param: %d, val: %d\n", gp.param,
3304 bufmgr_gem->available_fences = 0;
3306 /* XXX The kernel reports the total number of fences,
3307 * including any that may be pinned.
3309 * We presume that there will be at least one pinned
3310 * fence for the scanout buffer, but there may be more
3311 * than one scanout and the user may be manually
3312 * pinning buffers. Let's move to execbuffer2 and
3313 * thereby forget the insanity of using fences...
3315 bufmgr_gem->available_fences -= 2;
3316 if (bufmgr_gem->available_fences < 0)
3317 bufmgr_gem->available_fences = 0;
3321 /* Let's go with one relocation per every 2 dwords (but round down a bit
3322 * since a power of two will mean an extra page allocation for the reloc
3325 * Every 4 was too few for the blender benchmark.
3327 bufmgr_gem->max_relocs = batch_size / sizeof(uint32_t) / 2 - 2;
3329 bufmgr_gem->bufmgr.bo_alloc = drm_intel_gem_bo_alloc;
3330 bufmgr_gem->bufmgr.bo_alloc_for_render =
3331 drm_intel_gem_bo_alloc_for_render;
3332 bufmgr_gem->bufmgr.bo_alloc_tiled = drm_intel_gem_bo_alloc_tiled;
3333 bufmgr_gem->bufmgr.bo_reference = drm_intel_gem_bo_reference;
3334 bufmgr_gem->bufmgr.bo_unreference = drm_intel_gem_bo_unreference;
3335 bufmgr_gem->bufmgr.bo_map = drm_intel_gem_bo_map;
3336 bufmgr_gem->bufmgr.bo_unmap = drm_intel_gem_bo_unmap;
3337 bufmgr_gem->bufmgr.bo_subdata = drm_intel_gem_bo_subdata;
3338 bufmgr_gem->bufmgr.bo_get_subdata = drm_intel_gem_bo_get_subdata;
3339 bufmgr_gem->bufmgr.bo_wait_rendering = drm_intel_gem_bo_wait_rendering;
3340 bufmgr_gem->bufmgr.bo_emit_reloc = drm_intel_gem_bo_emit_reloc;
3341 bufmgr_gem->bufmgr.bo_emit_reloc_fence = drm_intel_gem_bo_emit_reloc_fence;
3342 bufmgr_gem->bufmgr.bo_pin = drm_intel_gem_bo_pin;
3343 bufmgr_gem->bufmgr.bo_unpin = drm_intel_gem_bo_unpin;
3344 bufmgr_gem->bufmgr.bo_get_tiling = drm_intel_gem_bo_get_tiling;
3345 bufmgr_gem->bufmgr.bo_set_tiling = drm_intel_gem_bo_set_tiling;
3346 bufmgr_gem->bufmgr.bo_flink = drm_intel_gem_bo_flink;
3347 /* Use the new one if available */
3349 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec2;
3350 bufmgr_gem->bufmgr.bo_mrb_exec = drm_intel_gem_bo_mrb_exec2;
3352 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec;
3353 bufmgr_gem->bufmgr.bo_busy = drm_intel_gem_bo_busy;
3354 bufmgr_gem->bufmgr.bo_madvise = drm_intel_gem_bo_madvise;
3355 bufmgr_gem->bufmgr.destroy = drm_intel_bufmgr_gem_destroy;
3356 bufmgr_gem->bufmgr.debug = 0;
3357 bufmgr_gem->bufmgr.check_aperture_space =
3358 drm_intel_gem_check_aperture_space;
3359 bufmgr_gem->bufmgr.bo_disable_reuse = drm_intel_gem_bo_disable_reuse;
3360 bufmgr_gem->bufmgr.bo_is_reusable = drm_intel_gem_bo_is_reusable;
3361 bufmgr_gem->bufmgr.get_pipe_from_crtc_id =
3362 drm_intel_gem_get_pipe_from_crtc_id;
3363 bufmgr_gem->bufmgr.bo_references = drm_intel_gem_bo_references;
3365 DRMINITLISTHEAD(&bufmgr_gem->named);
3366 init_cache_buckets(bufmgr_gem);
3368 DRMINITLISTHEAD(&bufmgr_gem->vma_cache);
3369 bufmgr_gem->vma_max = -1; /* unlimited by default */
3371 return &bufmgr_gem->bufmgr;