1 /**************************************************************************
3 * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
28 /* Originally a fake version of the buffer manager so that we can
29 * prototype the changes in a driver fairly quickly, has been fleshed
30 * out to a fully functional interim solution.
32 * Basically wraps the old style memory management in the new
33 * programming interface, but is more expressive and avoids many of
34 * the bugs in the old texture manager.
47 #include "intel_bufmgr.h"
48 #include "intel_bufmgr_priv.h"
53 #include "libdrm_lists.h"
55 /* Support gcc's __FUNCTION__ for people using other compilers */
56 #if !defined(__GNUC__) && !defined(__FUNCTION__)
57 # define __FUNCTION__ __func__ /* C99 */
60 #define DBG(...) do { \
61 if (bufmgr_fake->bufmgr.debug) \
62 drmMsg(__VA_ARGS__); \
67 #define BM_NO_BACKING_STORE 0x00000001
68 #define BM_NO_FENCE_SUBDATA 0x00000002
69 #define BM_PINNED 0x00000004
71 /* Wrapper around mm.c's mem_block, which understands that you must
72 * wait for fences to expire before memory can be freed. This is
73 * specific to our use of memcpy for uploads - an upload that was
74 * processed through the command queue wouldn't need to care about
77 #define MAX_RELOCS 4096
79 struct fake_buffer_reloc {
80 /** Buffer object that the relocation points at. */
81 drm_intel_bo *target_buf;
82 /** Offset of the relocation entry within reloc_buf. */
85 * Cached value of the offset when we last performed this relocation.
87 uint32_t last_target_offset;
88 /** Value added to target_buf's offset to get the relocation entry. */
90 /** Cache domains the target buffer is read into. */
91 uint32_t read_domains;
92 /** Cache domain the target buffer will have dirty cachelines in. */
93 uint32_t write_domain;
97 struct block *next, *prev;
98 struct mem_block *mem; /* BM_MEM_AGP */
101 * Marks that the block is currently in the aperture and has yet to be
104 unsigned on_hardware:1;
106 * Marks that the block is currently fenced (being used by rendering)
107 * and can't be freed until @fence is passed.
111 /** Fence cookie for the block. */
112 unsigned fence; /* Split to read_fence, write_fence */
118 typedef struct _bufmgr_fake {
119 drm_intel_bufmgr bufmgr;
121 pthread_mutex_t lock;
123 unsigned long low_offset;
127 struct mem_block *heap;
129 unsigned buf_nr; /* for generating ids */
132 * List of blocks which are currently in the GART but haven't been
135 struct block on_hardware;
137 * List of blocks which are in the GART and have an active fence on
142 * List of blocks which have an expired fence and are ready to be
147 unsigned int last_fence;
150 unsigned need_fence:1;
154 * Driver callback to emit a fence, returning the cookie.
156 * This allows the driver to hook in a replacement for the DRM usage in
159 * Currently, this also requires that a write flush be emitted before
160 * emitting the fence, but this should change.
162 unsigned int (*fence_emit) (void *private);
163 /** Driver callback to wait for a fence cookie to have passed. */
164 void (*fence_wait) (unsigned int fence, void *private);
168 * Driver callback to execute a buffer.
170 * This allows the driver to hook in a replacement for the DRM usage in
173 int (*exec) (drm_intel_bo *bo, unsigned int used, void *priv);
176 /** Driver-supplied argument to driver callbacks */
179 * Pointer to kernel-updated sarea data for the last completed user irq
181 volatile int *last_dispatch;
187 int performed_rendering;
188 } drm_intel_bufmgr_fake;
190 typedef struct _drm_intel_bo_fake {
193 unsigned id; /* debug only */
198 * has the card written to this buffer - we make need to copy it back
200 unsigned card_dirty:1;
201 unsigned int refcount;
202 /* Flags may consist of any of the DRM_BO flags, plus
203 * DRM_BO_NO_BACKING_STORE and BM_NO_FENCE_SUBDATA, which are the
204 * first two driver private flags.
207 /** Cache domains the target buffer is read into. */
208 uint32_t read_domains;
209 /** Cache domain the target buffer will have dirty cachelines in. */
210 uint32_t write_domain;
212 unsigned int alignment;
213 int is_static, validated;
214 unsigned int map_count;
216 /** relocation list */
217 struct fake_buffer_reloc *relocs;
220 * Total size of the target_bos of this buffer.
222 * Used for estimation in check_aperture.
224 unsigned int child_size;
228 void (*invalidate_cb) (drm_intel_bo *bo, void *ptr);
229 void *invalidate_ptr;
232 static int clear_fenced(drm_intel_bufmgr_fake *bufmgr_fake,
233 unsigned int fence_cookie);
235 #define MAXFENCE 0x7fffffff
238 FENCE_LTE(unsigned a, unsigned b)
243 if (a < b && b - a < (1 << 24))
246 if (a > b && MAXFENCE - a + b < (1 << 24))
253 drm_intel_bufmgr_fake_set_fence_callback(drm_intel_bufmgr *bufmgr,
254 unsigned int (*emit) (void *priv),
255 void (*wait) (unsigned int fence,
259 drm_intel_bufmgr_fake *bufmgr_fake = (drm_intel_bufmgr_fake *) bufmgr;
261 bufmgr_fake->fence_emit = emit;
262 bufmgr_fake->fence_wait = wait;
263 bufmgr_fake->fence_priv = priv;
267 _fence_emit_internal(drm_intel_bufmgr_fake *bufmgr_fake)
269 struct drm_i915_irq_emit ie;
272 if (bufmgr_fake->fence_emit != NULL) {
273 seq = bufmgr_fake->fence_emit(bufmgr_fake->fence_priv);
278 ret = drmCommandWriteRead(bufmgr_fake->fd, DRM_I915_IRQ_EMIT,
281 drmMsg("%s: drm_i915_irq_emit: %d\n", __FUNCTION__, ret);
285 DBG("emit 0x%08x\n", seq);
290 _fence_wait_internal(drm_intel_bufmgr_fake *bufmgr_fake, int seq)
292 struct drm_i915_irq_wait iw;
293 int hw_seq, busy_count = 0;
297 if (bufmgr_fake->fence_wait != NULL) {
298 bufmgr_fake->fence_wait(seq, bufmgr_fake->fence_priv);
299 clear_fenced(bufmgr_fake, seq);
305 DBG("wait 0x%08x\n", iw.irq_seq);
307 /* The kernel IRQ_WAIT implementation is all sorts of broken.
308 * 1) It returns 1 to 0x7fffffff instead of using the full 32-bit
310 * 2) It returns 0 if hw_seq >= seq, not seq - hw_seq < 0 on the 32-bit
312 * 3) It waits if seq < hw_seq, not seq - hw_seq > 0 on the 32-bit
314 * 4) It returns -EBUSY in 3 seconds even if the hardware is still
315 * successfully chewing through buffers.
317 * Assume that in userland we treat sequence numbers as ints, which
318 * makes some of the comparisons convenient, since the sequence
319 * numbers are all postive signed integers.
321 * From this we get several cases we need to handle. Here's a timeline.
322 * 0x2 0x7 0x7ffffff8 0x7ffffffd
324 * ------------------------------------------------------------
326 * A) Normal wait for hw to catch up
329 * ------------------------------------------------------------
330 * seq - hw_seq = 5. If we call IRQ_WAIT, it will wait for hw to
333 * B) Normal wait for a sequence number that's already passed.
336 * ------------------------------------------------------------
337 * seq - hw_seq = -5. If we call IRQ_WAIT, it returns 0 quickly.
339 * C) Hardware has already wrapped around ahead of us
342 * ------------------------------------------------------------
343 * seq - hw_seq = 0x80000000 - 5. If we called IRQ_WAIT, it would wait
344 * for hw_seq >= seq, which may never occur. Thus, we want to catch
345 * this in userland and return 0.
347 * D) We've wrapped around ahead of the hardware.
350 * ------------------------------------------------------------
351 * seq - hw_seq = -(0x80000000 - 5). If we called IRQ_WAIT, it would
352 * return 0 quickly because hw_seq >= seq, even though the hardware
353 * isn't caught up. Thus, we need to catch this early return in
354 * userland and bother the kernel until the hardware really does
357 * E) Hardware might wrap after we test in userland.
360 * ------------------------------------------------------------
361 * seq - hw_seq = 5. If we call IRQ_WAIT, it will likely see seq >=
362 * hw_seq and wait. However, suppose hw_seq wraps before we make it
363 * into the kernel. The kernel sees hw_seq >= seq and waits for 3
364 * seconds then returns -EBUSY. This is case C). We should catch
365 * this and then return successfully.
367 * F) Hardware might take a long time on a buffer.
370 * -------------------------------------------------------------------
371 * seq - hw_seq = 5. If we call IRQ_WAIT, if sequence 2 through 5
372 * take too long, it will return -EBUSY. Batchbuffers in the
373 * gltestperf demo were seen to take up to 7 seconds. We should
374 * catch early -EBUSY return and keep trying.
378 /* Keep a copy of last_dispatch so that if the wait -EBUSYs
379 * because the hardware didn't catch up in 3 seconds, we can
380 * see if it at least made progress and retry.
382 hw_seq = *bufmgr_fake->last_dispatch;
385 if (seq - hw_seq > 0x40000000)
388 ret = drmCommandWrite(bufmgr_fake->fd, DRM_I915_IRQ_WAIT,
391 kernel_lied = (ret == 0) && (seq - *bufmgr_fake->last_dispatch <
396 && (seq - *bufmgr_fake->last_dispatch > 0x40000000))
399 /* Catch case F: Allow up to 15 seconds chewing on one buffer. */
400 if ((ret == -EBUSY) && (hw_seq != *bufmgr_fake->last_dispatch))
404 } while (kernel_lied || ret == -EAGAIN || ret == -EINTR ||
405 (ret == -EBUSY && busy_count < 5));
408 drmMsg("%s:%d: Error waiting for fence: %s.\n", __FILE__,
409 __LINE__, strerror(-ret));
412 clear_fenced(bufmgr_fake, seq);
416 _fence_test(drm_intel_bufmgr_fake *bufmgr_fake, unsigned fence)
418 /* Slight problem with wrap-around:
420 return fence == 0 || FENCE_LTE(fence, bufmgr_fake->last_fence);
424 * Allocate a memory manager block for the buffer.
427 alloc_block(drm_intel_bo *bo)
429 drm_intel_bo_fake *bo_fake = (drm_intel_bo_fake *) bo;
430 drm_intel_bufmgr_fake *bufmgr_fake =
431 (drm_intel_bufmgr_fake *) bo->bufmgr;
432 struct block *block = (struct block *)calloc(sizeof *block, 1);
433 unsigned int align_log2 = ffs(bo_fake->alignment) - 1;
439 sz = (bo->size + bo_fake->alignment - 1) & ~(bo_fake->alignment - 1);
441 block->mem = mmAllocMem(bufmgr_fake->heap, sz, align_log2, 0);
447 DRMINITLISTHEAD(block);
449 /* Insert at head or at tail??? */
450 DRMLISTADDTAIL(block, &bufmgr_fake->lru);
452 block->virtual = (uint8_t *) bufmgr_fake->virtual +
453 block->mem->ofs - bufmgr_fake->low_offset;
456 bo_fake->block = block;
461 /* Release the card storage associated with buf:
464 free_block(drm_intel_bufmgr_fake *bufmgr_fake, struct block *block,
467 drm_intel_bo_fake *bo_fake;
468 DBG("free block %p %08x %d %d\n", block, block->mem->ofs,
469 block->on_hardware, block->fenced);
474 bo_fake = (drm_intel_bo_fake *) block->bo;
476 if (bo_fake->flags & (BM_PINNED | BM_NO_BACKING_STORE))
479 if (!skip_dirty_copy && (bo_fake->card_dirty == 1)) {
480 memcpy(bo_fake->backing_store, block->virtual, block->bo->size);
481 bo_fake->card_dirty = 0;
485 if (block->on_hardware) {
487 } else if (block->fenced) {
490 DBG(" - free immediately\n");
493 mmFreeMem(block->mem);
499 alloc_backing_store(drm_intel_bo *bo)
501 drm_intel_bufmgr_fake *bufmgr_fake =
502 (drm_intel_bufmgr_fake *) bo->bufmgr;
503 drm_intel_bo_fake *bo_fake = (drm_intel_bo_fake *) bo;
504 assert(!bo_fake->backing_store);
505 assert(!(bo_fake->flags & (BM_PINNED | BM_NO_BACKING_STORE)));
507 bo_fake->backing_store = malloc(bo->size);
509 DBG("alloc_backing - buf %d %p %lu\n", bo_fake->id,
510 bo_fake->backing_store, bo->size);
511 assert(bo_fake->backing_store);
515 free_backing_store(drm_intel_bo *bo)
517 drm_intel_bo_fake *bo_fake = (drm_intel_bo_fake *) bo;
519 if (bo_fake->backing_store) {
520 assert(!(bo_fake->flags & (BM_PINNED | BM_NO_BACKING_STORE)));
521 free(bo_fake->backing_store);
522 bo_fake->backing_store = NULL;
527 set_dirty(drm_intel_bo *bo)
529 drm_intel_bufmgr_fake *bufmgr_fake =
530 (drm_intel_bufmgr_fake *) bo->bufmgr;
531 drm_intel_bo_fake *bo_fake = (drm_intel_bo_fake *) bo;
533 if (bo_fake->flags & BM_NO_BACKING_STORE
534 && bo_fake->invalidate_cb != NULL)
535 bo_fake->invalidate_cb(bo, bo_fake->invalidate_ptr);
537 assert(!(bo_fake->flags & BM_PINNED));
539 DBG("set_dirty - buf %d\n", bo_fake->id);
544 evict_lru(drm_intel_bufmgr_fake *bufmgr_fake, unsigned int max_fence)
546 struct block *block, *tmp;
548 DBG("%s\n", __FUNCTION__);
550 DRMLISTFOREACHSAFE(block, tmp, &bufmgr_fake->lru) {
551 drm_intel_bo_fake *bo_fake = (drm_intel_bo_fake *) block->bo;
553 if (bo_fake != NULL && (bo_fake->flags & BM_NO_FENCE_SUBDATA))
556 if (block->fence && max_fence && !FENCE_LTE(block->fence,
560 set_dirty(&bo_fake->bo);
561 bo_fake->block = NULL;
563 free_block(bufmgr_fake, block, 0);
571 evict_mru(drm_intel_bufmgr_fake *bufmgr_fake)
573 struct block *block, *tmp;
575 DBG("%s\n", __FUNCTION__);
577 DRMLISTFOREACHSAFEREVERSE(block, tmp, &bufmgr_fake->lru) {
578 drm_intel_bo_fake *bo_fake = (drm_intel_bo_fake *) block->bo;
580 if (bo_fake && (bo_fake->flags & BM_NO_FENCE_SUBDATA))
583 set_dirty(&bo_fake->bo);
584 bo_fake->block = NULL;
586 free_block(bufmgr_fake, block, 0);
594 * Removes all objects from the fenced list older than the given fence.
597 clear_fenced(drm_intel_bufmgr_fake *bufmgr_fake, unsigned int fence_cookie)
599 struct block *block, *tmp;
602 bufmgr_fake->last_fence = fence_cookie;
603 DRMLISTFOREACHSAFE(block, tmp, &bufmgr_fake->fenced) {
604 assert(block->fenced);
606 if (_fence_test(bufmgr_fake, block->fence)) {
611 DBG("delayed free: offset %x sz %x\n",
612 block->mem->ofs, block->mem->size);
614 mmFreeMem(block->mem);
617 DBG("return to lru: offset %x sz %x\n",
618 block->mem->ofs, block->mem->size);
620 DRMLISTADDTAIL(block, &bufmgr_fake->lru);
625 /* Blocks are ordered by fence, so if one fails, all
626 * from here will fail also:
628 DBG("fence not passed: offset %x sz %x %d %d \n",
629 block->mem->ofs, block->mem->size, block->fence,
630 bufmgr_fake->last_fence);
635 DBG("%s: %d\n", __FUNCTION__, ret);
640 fence_blocks(drm_intel_bufmgr_fake *bufmgr_fake, unsigned fence)
642 struct block *block, *tmp;
644 DRMLISTFOREACHSAFE(block, tmp, &bufmgr_fake->on_hardware) {
645 DBG("Fence block %p (sz 0x%x ofs %x buf %p) with fence %d\n",
646 block, block->mem->size, block->mem->ofs, block->bo, fence);
647 block->fence = fence;
649 block->on_hardware = 0;
652 /* Move to tail of pending list here
655 DRMLISTADDTAIL(block, &bufmgr_fake->fenced);
658 assert(DRMLISTEMPTY(&bufmgr_fake->on_hardware));
662 evict_and_alloc_block(drm_intel_bo *bo)
664 drm_intel_bufmgr_fake *bufmgr_fake =
665 (drm_intel_bufmgr_fake *) bo->bufmgr;
666 drm_intel_bo_fake *bo_fake = (drm_intel_bo_fake *) bo;
668 assert(bo_fake->block == NULL);
670 /* Search for already free memory:
675 /* If we're not thrashing, allow lru eviction to dig deeper into
676 * recently used textures. We'll probably be thrashing soon:
678 if (!bufmgr_fake->thrashing) {
679 while (evict_lru(bufmgr_fake, 0))
684 /* Keep thrashing counter alive?
686 if (bufmgr_fake->thrashing)
687 bufmgr_fake->thrashing = 20;
689 /* Wait on any already pending fences - here we are waiting for any
690 * freed memory that has been submitted to hardware and fenced to
693 while (!DRMLISTEMPTY(&bufmgr_fake->fenced)) {
694 uint32_t fence = bufmgr_fake->fenced.next->fence;
695 _fence_wait_internal(bufmgr_fake, fence);
701 if (!DRMLISTEMPTY(&bufmgr_fake->on_hardware)) {
702 while (!DRMLISTEMPTY(&bufmgr_fake->fenced)) {
703 uint32_t fence = bufmgr_fake->fenced.next->fence;
704 _fence_wait_internal(bufmgr_fake, fence);
707 if (!bufmgr_fake->thrashing) {
710 bufmgr_fake->thrashing = 20;
716 while (evict_mru(bufmgr_fake))
720 DBG("%s 0x%lx bytes failed\n", __FUNCTION__, bo->size);
725 /***********************************************************************
730 * Wait for hardware idle by emitting a fence and waiting for it.
733 drm_intel_bufmgr_fake_wait_idle(drm_intel_bufmgr_fake *bufmgr_fake)
737 cookie = _fence_emit_internal(bufmgr_fake);
738 _fence_wait_internal(bufmgr_fake, cookie);
742 * Wait for rendering to a buffer to complete.
744 * It is assumed that the bathcbuffer which performed the rendering included
745 * the necessary flushing.
748 drm_intel_fake_bo_wait_rendering_locked(drm_intel_bo *bo)
750 drm_intel_bufmgr_fake *bufmgr_fake =
751 (drm_intel_bufmgr_fake *) bo->bufmgr;
752 drm_intel_bo_fake *bo_fake = (drm_intel_bo_fake *) bo;
754 if (bo_fake->block == NULL || !bo_fake->block->fenced)
757 _fence_wait_internal(bufmgr_fake, bo_fake->block->fence);
761 drm_intel_fake_bo_wait_rendering(drm_intel_bo *bo)
763 drm_intel_bufmgr_fake *bufmgr_fake =
764 (drm_intel_bufmgr_fake *) bo->bufmgr;
766 pthread_mutex_lock(&bufmgr_fake->lock);
767 drm_intel_fake_bo_wait_rendering_locked(bo);
768 pthread_mutex_unlock(&bufmgr_fake->lock);
771 /* Specifically ignore texture memory sharing.
772 * -- just evict everything
773 * -- and wait for idle
776 drm_intel_bufmgr_fake_contended_lock_take(drm_intel_bufmgr *bufmgr)
778 drm_intel_bufmgr_fake *bufmgr_fake = (drm_intel_bufmgr_fake *) bufmgr;
779 struct block *block, *tmp;
781 pthread_mutex_lock(&bufmgr_fake->lock);
783 bufmgr_fake->need_fence = 1;
784 bufmgr_fake->fail = 0;
786 /* Wait for hardware idle. We don't know where acceleration has been
787 * happening, so we'll need to wait anyway before letting anything get
788 * put on the card again.
790 drm_intel_bufmgr_fake_wait_idle(bufmgr_fake);
792 /* Check that we hadn't released the lock without having fenced the last
795 assert(DRMLISTEMPTY(&bufmgr_fake->fenced));
796 assert(DRMLISTEMPTY(&bufmgr_fake->on_hardware));
798 DRMLISTFOREACHSAFE(block, tmp, &bufmgr_fake->lru) {
799 assert(_fence_test(bufmgr_fake, block->fence));
800 set_dirty(block->bo);
803 pthread_mutex_unlock(&bufmgr_fake->lock);
806 static drm_intel_bo *
807 drm_intel_fake_bo_alloc(drm_intel_bufmgr *bufmgr,
810 unsigned int alignment)
812 drm_intel_bufmgr_fake *bufmgr_fake;
813 drm_intel_bo_fake *bo_fake;
815 bufmgr_fake = (drm_intel_bufmgr_fake *) bufmgr;
819 bo_fake = calloc(1, sizeof(*bo_fake));
823 bo_fake->bo.size = size;
824 bo_fake->bo.offset = -1;
825 bo_fake->bo.virtual = NULL;
826 bo_fake->bo.bufmgr = bufmgr;
827 bo_fake->refcount = 1;
829 /* Alignment must be a power of two */
830 assert((alignment & (alignment - 1)) == 0);
833 bo_fake->alignment = alignment;
834 bo_fake->id = ++bufmgr_fake->buf_nr;
835 bo_fake->name = name;
837 bo_fake->is_static = 0;
839 DBG("drm_bo_alloc: (buf %d: %s, %lu kb)\n", bo_fake->id, bo_fake->name,
840 bo_fake->bo.size / 1024);
845 static drm_intel_bo *
846 drm_intel_fake_bo_alloc_tiled(drm_intel_bufmgr * bufmgr,
848 int x, int y, int cpp,
849 uint32_t *tiling_mode,
850 unsigned long *pitch,
853 unsigned long stride, aligned_y;
855 /* No runtime tiling support for fake. */
856 *tiling_mode = I915_TILING_NONE;
858 /* Align it for being a render target. Shouldn't need anything else. */
860 stride = ROUND_UP_TO(stride, 64);
862 /* 965 subspan loading alignment */
863 aligned_y = ALIGN(y, 2);
867 return drm_intel_fake_bo_alloc(bufmgr, name, stride * aligned_y,
871 drm_public drm_intel_bo *
872 drm_intel_bo_fake_alloc_static(drm_intel_bufmgr *bufmgr,
874 unsigned long offset,
875 unsigned long size, void *virtual)
877 drm_intel_bufmgr_fake *bufmgr_fake;
878 drm_intel_bo_fake *bo_fake;
880 bufmgr_fake = (drm_intel_bufmgr_fake *) bufmgr;
884 bo_fake = calloc(1, sizeof(*bo_fake));
888 bo_fake->bo.size = size;
889 bo_fake->bo.offset = offset;
890 bo_fake->bo.virtual = virtual;
891 bo_fake->bo.bufmgr = bufmgr;
892 bo_fake->refcount = 1;
893 bo_fake->id = ++bufmgr_fake->buf_nr;
894 bo_fake->name = name;
895 bo_fake->flags = BM_PINNED;
896 bo_fake->is_static = 1;
898 DBG("drm_bo_alloc_static: (buf %d: %s, %lu kb)\n", bo_fake->id,
899 bo_fake->name, bo_fake->bo.size / 1024);
905 drm_intel_fake_bo_reference(drm_intel_bo *bo)
907 drm_intel_bufmgr_fake *bufmgr_fake =
908 (drm_intel_bufmgr_fake *) bo->bufmgr;
909 drm_intel_bo_fake *bo_fake = (drm_intel_bo_fake *) bo;
911 pthread_mutex_lock(&bufmgr_fake->lock);
913 pthread_mutex_unlock(&bufmgr_fake->lock);
917 drm_intel_fake_bo_reference_locked(drm_intel_bo *bo)
919 drm_intel_bo_fake *bo_fake = (drm_intel_bo_fake *) bo;
925 drm_intel_fake_bo_unreference_locked(drm_intel_bo *bo)
927 drm_intel_bufmgr_fake *bufmgr_fake =
928 (drm_intel_bufmgr_fake *) bo->bufmgr;
929 drm_intel_bo_fake *bo_fake = (drm_intel_bo_fake *) bo;
932 if (--bo_fake->refcount == 0) {
933 assert(bo_fake->map_count == 0);
934 /* No remaining references, so free it */
936 free_block(bufmgr_fake, bo_fake->block, 1);
937 free_backing_store(bo);
939 for (i = 0; i < bo_fake->nr_relocs; i++)
940 drm_intel_fake_bo_unreference_locked(bo_fake->relocs[i].
943 DBG("drm_bo_unreference: free buf %d %s\n", bo_fake->id,
946 free(bo_fake->relocs);
952 drm_intel_fake_bo_unreference(drm_intel_bo *bo)
954 drm_intel_bufmgr_fake *bufmgr_fake =
955 (drm_intel_bufmgr_fake *) bo->bufmgr;
957 pthread_mutex_lock(&bufmgr_fake->lock);
958 drm_intel_fake_bo_unreference_locked(bo);
959 pthread_mutex_unlock(&bufmgr_fake->lock);
963 * Set the buffer as not requiring backing store, and instead get the callback
964 * invoked whenever it would be set dirty.
967 drm_intel_bo_fake_disable_backing_store(drm_intel_bo *bo,
968 void (*invalidate_cb) (drm_intel_bo *bo,
972 drm_intel_bufmgr_fake *bufmgr_fake =
973 (drm_intel_bufmgr_fake *) bo->bufmgr;
974 drm_intel_bo_fake *bo_fake = (drm_intel_bo_fake *) bo;
976 pthread_mutex_lock(&bufmgr_fake->lock);
978 if (bo_fake->backing_store)
979 free_backing_store(bo);
981 bo_fake->flags |= BM_NO_BACKING_STORE;
983 DBG("disable_backing_store set buf %d dirty\n", bo_fake->id);
985 bo_fake->invalidate_cb = invalidate_cb;
986 bo_fake->invalidate_ptr = ptr;
988 /* Note that it is invalid right from the start. Also note
989 * invalidate_cb is called with the bufmgr locked, so cannot
990 * itself make bufmgr calls.
992 if (invalidate_cb != NULL)
993 invalidate_cb(bo, ptr);
995 pthread_mutex_unlock(&bufmgr_fake->lock);
999 * Map a buffer into bo->virtual, allocating either card memory space (If
1000 * BM_NO_BACKING_STORE or BM_PINNED) or backing store, as necessary.
1003 drm_intel_fake_bo_map_locked(drm_intel_bo *bo, int write_enable)
1005 drm_intel_bufmgr_fake *bufmgr_fake =
1006 (drm_intel_bufmgr_fake *) bo->bufmgr;
1007 drm_intel_bo_fake *bo_fake = (drm_intel_bo_fake *) bo;
1009 /* Static buffers are always mapped. */
1010 if (bo_fake->is_static) {
1011 if (bo_fake->card_dirty) {
1012 drm_intel_bufmgr_fake_wait_idle(bufmgr_fake);
1013 bo_fake->card_dirty = 0;
1018 /* Allow recursive mapping. Mesa may recursively map buffers with
1019 * nested display loops, and it is used internally in bufmgr_fake
1022 if (bo_fake->map_count++ != 0)
1026 DBG("drm_bo_map: (buf %d: %s, %lu kb)\n", bo_fake->id,
1027 bo_fake->name, bo_fake->bo.size / 1024);
1029 if (bo->virtual != NULL) {
1030 drmMsg("%s: already mapped\n", __FUNCTION__);
1032 } else if (bo_fake->flags & (BM_NO_BACKING_STORE | BM_PINNED)) {
1034 if (!bo_fake->block && !evict_and_alloc_block(bo)) {
1035 DBG("%s: alloc failed\n", __FUNCTION__);
1036 bufmgr_fake->fail = 1;
1039 assert(bo_fake->block);
1042 if (!(bo_fake->flags & BM_NO_FENCE_SUBDATA) &&
1043 bo_fake->block->fenced) {
1044 drm_intel_fake_bo_wait_rendering_locked
1048 bo->virtual = bo_fake->block->virtual;
1054 if (bo_fake->backing_store == 0)
1055 alloc_backing_store(bo);
1057 if ((bo_fake->card_dirty == 1) && bo_fake->block) {
1058 if (bo_fake->block->fenced)
1059 drm_intel_fake_bo_wait_rendering_locked
1062 memcpy(bo_fake->backing_store,
1063 bo_fake->block->virtual,
1064 bo_fake->block->bo->size);
1065 bo_fake->card_dirty = 0;
1068 bo->virtual = bo_fake->backing_store;
1076 drm_intel_fake_bo_map(drm_intel_bo *bo, int write_enable)
1078 drm_intel_bufmgr_fake *bufmgr_fake =
1079 (drm_intel_bufmgr_fake *) bo->bufmgr;
1082 pthread_mutex_lock(&bufmgr_fake->lock);
1083 ret = drm_intel_fake_bo_map_locked(bo, write_enable);
1084 pthread_mutex_unlock(&bufmgr_fake->lock);
1090 drm_intel_fake_bo_unmap_locked(drm_intel_bo *bo)
1092 drm_intel_bufmgr_fake *bufmgr_fake =
1093 (drm_intel_bufmgr_fake *) bo->bufmgr;
1094 drm_intel_bo_fake *bo_fake = (drm_intel_bo_fake *) bo;
1096 /* Static buffers are always mapped. */
1097 if (bo_fake->is_static)
1100 assert(bo_fake->map_count != 0);
1101 if (--bo_fake->map_count != 0)
1104 DBG("drm_bo_unmap: (buf %d: %s, %lu kb)\n", bo_fake->id, bo_fake->name,
1105 bo_fake->bo.size / 1024);
1112 static int drm_intel_fake_bo_unmap(drm_intel_bo *bo)
1114 drm_intel_bufmgr_fake *bufmgr_fake =
1115 (drm_intel_bufmgr_fake *) bo->bufmgr;
1118 pthread_mutex_lock(&bufmgr_fake->lock);
1119 ret = drm_intel_fake_bo_unmap_locked(bo);
1120 pthread_mutex_unlock(&bufmgr_fake->lock);
1126 drm_intel_fake_bo_subdata(drm_intel_bo *bo, unsigned long offset,
1127 unsigned long size, const void *data)
1131 if (size == 0 || data == NULL)
1134 ret = drm_intel_bo_map(bo, 1);
1137 memcpy((unsigned char *)bo->virtual + offset, data, size);
1138 drm_intel_bo_unmap(bo);
1143 drm_intel_fake_kick_all_locked(drm_intel_bufmgr_fake *bufmgr_fake)
1145 struct block *block, *tmp;
1147 bufmgr_fake->performed_rendering = 0;
1148 /* okay for ever BO that is on the HW kick it off.
1149 seriously not afraid of the POLICE right now */
1150 DRMLISTFOREACHSAFE(block, tmp, &bufmgr_fake->on_hardware) {
1151 drm_intel_bo_fake *bo_fake = (drm_intel_bo_fake *) block->bo;
1153 block->on_hardware = 0;
1154 free_block(bufmgr_fake, block, 0);
1155 bo_fake->block = NULL;
1156 bo_fake->validated = 0;
1157 if (!(bo_fake->flags & BM_NO_BACKING_STORE))
1164 drm_intel_fake_bo_validate(drm_intel_bo *bo)
1166 drm_intel_bufmgr_fake *bufmgr_fake;
1167 drm_intel_bo_fake *bo_fake = (drm_intel_bo_fake *) bo;
1169 bufmgr_fake = (drm_intel_bufmgr_fake *) bo->bufmgr;
1171 DBG("drm_bo_validate: (buf %d: %s, %lu kb)\n", bo_fake->id,
1172 bo_fake->name, bo_fake->bo.size / 1024);
1174 /* Sanity check: Buffers should be unmapped before being validated.
1175 * This is not so much of a problem for bufmgr_fake, but TTM refuses,
1176 * and the problem is harder to debug there.
1178 assert(bo_fake->map_count == 0);
1180 if (bo_fake->is_static) {
1181 /* Add it to the needs-fence list */
1182 bufmgr_fake->need_fence = 1;
1186 /* Allocate the card memory */
1187 if (!bo_fake->block && !evict_and_alloc_block(bo)) {
1188 bufmgr_fake->fail = 1;
1189 DBG("Failed to validate buf %d:%s\n", bo_fake->id,
1194 assert(bo_fake->block);
1195 assert(bo_fake->block->bo == &bo_fake->bo);
1197 bo->offset = bo_fake->block->mem->ofs;
1199 /* Upload the buffer contents if necessary */
1200 if (bo_fake->dirty) {
1201 DBG("Upload dirty buf %d:%s, sz %lu offset 0x%x\n", bo_fake->id,
1202 bo_fake->name, bo->size, bo_fake->block->mem->ofs);
1204 assert(!(bo_fake->flags & (BM_NO_BACKING_STORE | BM_PINNED)));
1206 /* Actually, should be able to just wait for a fence on the
1207 * mmory, hich we would be tracking when we free it. Waiting
1208 * for idle is a sufficiently large hammer for now.
1210 drm_intel_bufmgr_fake_wait_idle(bufmgr_fake);
1212 /* we may never have mapped this BO so it might not have any
1213 * backing store if this happens it should be rare, but 0 the
1214 * card memory in any case */
1215 if (bo_fake->backing_store)
1216 memcpy(bo_fake->block->virtual, bo_fake->backing_store,
1219 memset(bo_fake->block->virtual, 0, bo->size);
1224 bo_fake->block->fenced = 0;
1225 bo_fake->block->on_hardware = 1;
1226 DRMLISTDEL(bo_fake->block);
1227 DRMLISTADDTAIL(bo_fake->block, &bufmgr_fake->on_hardware);
1229 bo_fake->validated = 1;
1230 bufmgr_fake->need_fence = 1;
1236 drm_intel_fake_fence_validated(drm_intel_bufmgr *bufmgr)
1238 drm_intel_bufmgr_fake *bufmgr_fake = (drm_intel_bufmgr_fake *) bufmgr;
1239 unsigned int cookie;
1241 cookie = _fence_emit_internal(bufmgr_fake);
1242 fence_blocks(bufmgr_fake, cookie);
1244 DBG("drm_fence_validated: 0x%08x cookie\n", cookie);
1248 drm_intel_fake_destroy(drm_intel_bufmgr *bufmgr)
1250 drm_intel_bufmgr_fake *bufmgr_fake = (drm_intel_bufmgr_fake *) bufmgr;
1252 pthread_mutex_destroy(&bufmgr_fake->lock);
1253 mmDestroy(bufmgr_fake->heap);
1258 drm_intel_fake_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1259 drm_intel_bo *target_bo, uint32_t target_offset,
1260 uint32_t read_domains, uint32_t write_domain)
1262 drm_intel_bufmgr_fake *bufmgr_fake =
1263 (drm_intel_bufmgr_fake *) bo->bufmgr;
1264 struct fake_buffer_reloc *r;
1265 drm_intel_bo_fake *bo_fake = (drm_intel_bo_fake *) bo;
1266 drm_intel_bo_fake *target_fake = (drm_intel_bo_fake *) target_bo;
1269 pthread_mutex_lock(&bufmgr_fake->lock);
1274 if (bo_fake->relocs == NULL) {
1276 malloc(sizeof(struct fake_buffer_reloc) * MAX_RELOCS);
1279 r = &bo_fake->relocs[bo_fake->nr_relocs++];
1281 assert(bo_fake->nr_relocs <= MAX_RELOCS);
1283 drm_intel_fake_bo_reference_locked(target_bo);
1285 if (!target_fake->is_static) {
1286 bo_fake->child_size +=
1287 ALIGN(target_bo->size, target_fake->alignment);
1288 bo_fake->child_size += target_fake->child_size;
1290 r->target_buf = target_bo;
1292 r->last_target_offset = target_bo->offset;
1293 r->delta = target_offset;
1294 r->read_domains = read_domains;
1295 r->write_domain = write_domain;
1297 if (bufmgr_fake->debug) {
1298 /* Check that a conflicting relocation hasn't already been
1301 for (i = 0; i < bo_fake->nr_relocs - 1; i++) {
1302 struct fake_buffer_reloc *r2 = &bo_fake->relocs[i];
1304 assert(r->offset != r2->offset);
1308 pthread_mutex_unlock(&bufmgr_fake->lock);
1314 * Incorporates the validation flags associated with each relocation into
1315 * the combined validation flags for the buffer on this batchbuffer submission.
1318 drm_intel_fake_calculate_domains(drm_intel_bo *bo)
1320 drm_intel_bo_fake *bo_fake = (drm_intel_bo_fake *) bo;
1323 for (i = 0; i < bo_fake->nr_relocs; i++) {
1324 struct fake_buffer_reloc *r = &bo_fake->relocs[i];
1325 drm_intel_bo_fake *target_fake =
1326 (drm_intel_bo_fake *) r->target_buf;
1328 /* Do the same for the tree of buffers we depend on */
1329 drm_intel_fake_calculate_domains(r->target_buf);
1331 target_fake->read_domains |= r->read_domains;
1332 target_fake->write_domain |= r->write_domain;
1337 drm_intel_fake_reloc_and_validate_buffer(drm_intel_bo *bo)
1339 drm_intel_bufmgr_fake *bufmgr_fake =
1340 (drm_intel_bufmgr_fake *) bo->bufmgr;
1341 drm_intel_bo_fake *bo_fake = (drm_intel_bo_fake *) bo;
1344 assert(bo_fake->map_count == 0);
1346 for (i = 0; i < bo_fake->nr_relocs; i++) {
1347 struct fake_buffer_reloc *r = &bo_fake->relocs[i];
1348 drm_intel_bo_fake *target_fake =
1349 (drm_intel_bo_fake *) r->target_buf;
1350 uint32_t reloc_data;
1352 /* Validate the target buffer if that hasn't been done. */
1353 if (!target_fake->validated) {
1355 drm_intel_fake_reloc_and_validate_buffer(r->target_buf);
1357 if (bo->virtual != NULL)
1358 drm_intel_fake_bo_unmap_locked(bo);
1363 /* Calculate the value of the relocation entry. */
1364 if (r->target_buf->offset != r->last_target_offset) {
1365 reloc_data = r->target_buf->offset + r->delta;
1367 if (bo->virtual == NULL)
1368 drm_intel_fake_bo_map_locked(bo, 1);
1370 *(uint32_t *) ((uint8_t *) bo->virtual + r->offset) =
1373 r->last_target_offset = r->target_buf->offset;
1377 if (bo->virtual != NULL)
1378 drm_intel_fake_bo_unmap_locked(bo);
1380 if (bo_fake->write_domain != 0) {
1381 if (!(bo_fake->flags & (BM_NO_BACKING_STORE | BM_PINNED))) {
1382 if (bo_fake->backing_store == 0)
1383 alloc_backing_store(bo);
1385 bo_fake->card_dirty = 1;
1386 bufmgr_fake->performed_rendering = 1;
1389 return drm_intel_fake_bo_validate(bo);
1393 drm_intel_bo_fake_post_submit(drm_intel_bo *bo)
1395 drm_intel_bufmgr_fake *bufmgr_fake =
1396 (drm_intel_bufmgr_fake *) bo->bufmgr;
1397 drm_intel_bo_fake *bo_fake = (drm_intel_bo_fake *) bo;
1400 for (i = 0; i < bo_fake->nr_relocs; i++) {
1401 struct fake_buffer_reloc *r = &bo_fake->relocs[i];
1402 drm_intel_bo_fake *target_fake =
1403 (drm_intel_bo_fake *) r->target_buf;
1405 if (target_fake->validated)
1406 drm_intel_bo_fake_post_submit(r->target_buf);
1408 DBG("%s@0x%08x + 0x%08x -> %s@0x%08x + 0x%08x\n",
1409 bo_fake->name, (uint32_t) bo->offset, r->offset,
1410 target_fake->name, (uint32_t) r->target_buf->offset,
1414 assert(bo_fake->map_count == 0);
1415 bo_fake->validated = 0;
1416 bo_fake->read_domains = 0;
1417 bo_fake->write_domain = 0;
1421 drm_intel_bufmgr_fake_set_exec_callback(drm_intel_bufmgr *bufmgr,
1422 int (*exec) (drm_intel_bo *bo,
1427 drm_intel_bufmgr_fake *bufmgr_fake = (drm_intel_bufmgr_fake *) bufmgr;
1429 bufmgr_fake->exec = exec;
1430 bufmgr_fake->exec_priv = priv;
1434 drm_intel_fake_bo_exec(drm_intel_bo *bo, int used,
1435 drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
1437 drm_intel_bufmgr_fake *bufmgr_fake =
1438 (drm_intel_bufmgr_fake *) bo->bufmgr;
1439 drm_intel_bo_fake *batch_fake = (drm_intel_bo_fake *) bo;
1440 struct drm_i915_batchbuffer batch;
1442 int retry_count = 0;
1444 pthread_mutex_lock(&bufmgr_fake->lock);
1446 bufmgr_fake->performed_rendering = 0;
1448 drm_intel_fake_calculate_domains(bo);
1450 batch_fake->read_domains = I915_GEM_DOMAIN_COMMAND;
1452 /* we've ran out of RAM so blow the whole lot away and retry */
1454 ret = drm_intel_fake_reloc_and_validate_buffer(bo);
1455 if (bufmgr_fake->fail == 1) {
1456 if (retry_count == 0) {
1458 drm_intel_fake_kick_all_locked(bufmgr_fake);
1459 bufmgr_fake->fail = 0;
1461 } else /* dump out the memory here */
1462 mmDumpMemInfo(bufmgr_fake->heap);
1467 if (bufmgr_fake->exec != NULL) {
1468 int ret = bufmgr_fake->exec(bo, used, bufmgr_fake->exec_priv);
1470 pthread_mutex_unlock(&bufmgr_fake->lock);
1474 batch.start = bo->offset;
1476 batch.cliprects = cliprects;
1477 batch.num_cliprects = num_cliprects;
1482 (bufmgr_fake->fd, DRM_I915_BATCHBUFFER, &batch,
1484 drmMsg("DRM_I915_BATCHBUFFER: %d\n", -errno);
1485 pthread_mutex_unlock(&bufmgr_fake->lock);
1490 drm_intel_fake_fence_validated(bo->bufmgr);
1492 drm_intel_bo_fake_post_submit(bo);
1494 pthread_mutex_unlock(&bufmgr_fake->lock);
1500 * Return an error if the list of BOs will exceed the aperture size.
1502 * This is a rough guess and likely to fail, as during the validate sequence we
1503 * may place a buffer in an inopportune spot early on and then fail to fit
1504 * a set smaller than the aperture.
1507 drm_intel_fake_check_aperture_space(drm_intel_bo ** bo_array, int count)
1509 drm_intel_bufmgr_fake *bufmgr_fake =
1510 (drm_intel_bufmgr_fake *) bo_array[0]->bufmgr;
1511 unsigned int sz = 0;
1514 for (i = 0; i < count; i++) {
1515 drm_intel_bo_fake *bo_fake = (drm_intel_bo_fake *) bo_array[i];
1517 if (bo_fake == NULL)
1520 if (!bo_fake->is_static)
1521 sz += ALIGN(bo_array[i]->size, bo_fake->alignment);
1522 sz += bo_fake->child_size;
1525 if (sz > bufmgr_fake->size) {
1526 DBG("check_space: overflowed bufmgr size, %ukb vs %lukb\n",
1527 sz / 1024, bufmgr_fake->size / 1024);
1531 DBG("drm_check_space: sz %ukb vs bufgr %lukb\n", sz / 1024,
1532 bufmgr_fake->size / 1024);
1537 * Evicts all buffers, waiting for fences to pass and copying contents out
1540 * Used by the X Server on LeaveVT, when the card memory is no longer our
1544 drm_intel_bufmgr_fake_evict_all(drm_intel_bufmgr *bufmgr)
1546 drm_intel_bufmgr_fake *bufmgr_fake = (drm_intel_bufmgr_fake *) bufmgr;
1547 struct block *block, *tmp;
1549 pthread_mutex_lock(&bufmgr_fake->lock);
1551 bufmgr_fake->need_fence = 1;
1552 bufmgr_fake->fail = 0;
1554 /* Wait for hardware idle. We don't know where acceleration has been
1555 * happening, so we'll need to wait anyway before letting anything get
1556 * put on the card again.
1558 drm_intel_bufmgr_fake_wait_idle(bufmgr_fake);
1560 /* Check that we hadn't released the lock without having fenced the last
1563 assert(DRMLISTEMPTY(&bufmgr_fake->fenced));
1564 assert(DRMLISTEMPTY(&bufmgr_fake->on_hardware));
1566 DRMLISTFOREACHSAFE(block, tmp, &bufmgr_fake->lru) {
1567 drm_intel_bo_fake *bo_fake = (drm_intel_bo_fake *) block->bo;
1568 /* Releases the memory, and memcpys dirty contents out if
1571 free_block(bufmgr_fake, block, 0);
1572 bo_fake->block = NULL;
1575 pthread_mutex_unlock(&bufmgr_fake->lock);
1579 drm_intel_bufmgr_fake_set_last_dispatch(drm_intel_bufmgr *bufmgr,
1580 volatile unsigned int
1583 drm_intel_bufmgr_fake *bufmgr_fake = (drm_intel_bufmgr_fake *) bufmgr;
1585 bufmgr_fake->last_dispatch = (volatile int *)last_dispatch;
1588 drm_public drm_intel_bufmgr *
1589 drm_intel_bufmgr_fake_init(int fd, unsigned long low_offset,
1590 void *low_virtual, unsigned long size,
1591 volatile unsigned int *last_dispatch)
1593 drm_intel_bufmgr_fake *bufmgr_fake;
1595 bufmgr_fake = calloc(1, sizeof(*bufmgr_fake));
1597 if (pthread_mutex_init(&bufmgr_fake->lock, NULL) != 0) {
1602 /* Initialize allocator */
1603 DRMINITLISTHEAD(&bufmgr_fake->fenced);
1604 DRMINITLISTHEAD(&bufmgr_fake->on_hardware);
1605 DRMINITLISTHEAD(&bufmgr_fake->lru);
1607 bufmgr_fake->low_offset = low_offset;
1608 bufmgr_fake->virtual = low_virtual;
1609 bufmgr_fake->size = size;
1610 bufmgr_fake->heap = mmInit(low_offset, size);
1612 /* Hook in methods */
1613 bufmgr_fake->bufmgr.bo_alloc = drm_intel_fake_bo_alloc;
1614 bufmgr_fake->bufmgr.bo_alloc_for_render = drm_intel_fake_bo_alloc;
1615 bufmgr_fake->bufmgr.bo_alloc_tiled = drm_intel_fake_bo_alloc_tiled;
1616 bufmgr_fake->bufmgr.bo_reference = drm_intel_fake_bo_reference;
1617 bufmgr_fake->bufmgr.bo_unreference = drm_intel_fake_bo_unreference;
1618 bufmgr_fake->bufmgr.bo_map = drm_intel_fake_bo_map;
1619 bufmgr_fake->bufmgr.bo_unmap = drm_intel_fake_bo_unmap;
1620 bufmgr_fake->bufmgr.bo_subdata = drm_intel_fake_bo_subdata;
1621 bufmgr_fake->bufmgr.bo_wait_rendering =
1622 drm_intel_fake_bo_wait_rendering;
1623 bufmgr_fake->bufmgr.bo_emit_reloc = drm_intel_fake_emit_reloc;
1624 bufmgr_fake->bufmgr.destroy = drm_intel_fake_destroy;
1625 bufmgr_fake->bufmgr.bo_exec = drm_intel_fake_bo_exec;
1626 bufmgr_fake->bufmgr.check_aperture_space =
1627 drm_intel_fake_check_aperture_space;
1628 bufmgr_fake->bufmgr.debug = 0;
1630 bufmgr_fake->fd = fd;
1631 bufmgr_fake->last_dispatch = (volatile int *)last_dispatch;
1633 return &bufmgr_fake->bufmgr;