2 * Copyright © 2008-2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 * @file intel_bufmgr.h
31 * Public definitions of Intel-specific bufmgr functions.
34 #ifndef INTEL_BUFMGR_H
35 #define INTEL_BUFMGR_H
43 typedef struct _drm_intel_bufmgr drm_intel_bufmgr;
44 typedef struct _drm_intel_bo drm_intel_bo;
46 struct _drm_intel_bo {
48 * Size in bytes of the buffer object.
50 * The size may be larger than the size originally requested for the
51 * allocation, such as being aligned to page size.
56 * Alignment requirement for object
58 * Used for GTT mapping & pinning the object.
63 * Last seen card virtual address (offset from the beginning of the
64 * aperture) for the object. This should be used to fill relocation
65 * entries when calling drm_intel_bo_emit_reloc()
70 * Virtual address for accessing the buffer data. Only valid while
79 /** Buffer manager context associated with this buffer object */
80 drm_intel_bufmgr *bufmgr;
83 * MM-specific handle for accessing object
88 enum aub_dump_bmp_format {
89 AUB_DUMP_BMP_FORMAT_8BIT = 1,
90 AUB_DUMP_BMP_FORMAT_ARGB_4444 = 4,
91 AUB_DUMP_BMP_FORMAT_ARGB_0888 = 6,
92 AUB_DUMP_BMP_FORMAT_ARGB_8888 = 7,
95 typedef struct _drm_intel_aub_annotation {
98 uint32_t ending_offset;
99 } drm_intel_aub_annotation;
101 #define BO_ALLOC_FOR_RENDER (1<<0)
103 drm_intel_bo *drm_intel_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name,
104 unsigned long size, unsigned int alignment);
105 drm_intel_bo *drm_intel_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
108 unsigned int alignment);
109 drm_intel_bo *drm_intel_bo_alloc_tiled(drm_intel_bufmgr *bufmgr,
111 int x, int y, int cpp,
112 uint32_t *tiling_mode,
113 unsigned long *pitch,
114 unsigned long flags);
115 void drm_intel_bo_reference(drm_intel_bo *bo);
116 void drm_intel_bo_unreference(drm_intel_bo *bo);
117 int drm_intel_bo_map(drm_intel_bo *bo, int write_enable);
118 int drm_intel_bo_unmap(drm_intel_bo *bo);
120 int drm_intel_bo_subdata(drm_intel_bo *bo, unsigned long offset,
121 unsigned long size, const void *data);
122 int drm_intel_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
123 unsigned long size, void *data);
124 void drm_intel_bo_wait_rendering(drm_intel_bo *bo);
126 void drm_intel_bufmgr_set_debug(drm_intel_bufmgr *bufmgr, int enable_debug);
127 void drm_intel_bufmgr_destroy(drm_intel_bufmgr *bufmgr);
128 int drm_intel_bo_exec(drm_intel_bo *bo, int used,
129 struct drm_clip_rect *cliprects, int num_cliprects, int DR4);
130 int drm_intel_bo_mrb_exec(drm_intel_bo *bo, int used,
131 struct drm_clip_rect *cliprects, int num_cliprects, int DR4,
133 int drm_intel_bufmgr_check_aperture_space(drm_intel_bo ** bo_array, int count);
135 int drm_intel_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
136 drm_intel_bo *target_bo, uint32_t target_offset,
137 uint32_t read_domains, uint32_t write_domain);
138 int drm_intel_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
139 drm_intel_bo *target_bo,
140 uint32_t target_offset,
141 uint32_t read_domains, uint32_t write_domain);
142 int drm_intel_bo_pin(drm_intel_bo *bo, uint32_t alignment);
143 int drm_intel_bo_unpin(drm_intel_bo *bo);
144 int drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
146 int drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
147 uint32_t * swizzle_mode);
148 int drm_intel_bo_flink(drm_intel_bo *bo, uint32_t * name);
149 int drm_intel_bo_busy(drm_intel_bo *bo);
150 int drm_intel_bo_madvise(drm_intel_bo *bo, int madv);
152 int drm_intel_bo_disable_reuse(drm_intel_bo *bo);
153 int drm_intel_bo_is_reusable(drm_intel_bo *bo);
154 int drm_intel_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo);
156 /* drm_intel_bufmgr_gem.c */
157 drm_intel_bufmgr *drm_intel_bufmgr_gem_init(int fd, int batch_size);
158 drm_intel_bo *drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
160 unsigned int handle);
161 void drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr);
162 void drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr);
163 void drm_intel_bufmgr_gem_set_vma_cache_size(drm_intel_bufmgr *bufmgr,
165 int drm_intel_gem_bo_map_unsynchronized(drm_intel_bo *bo);
166 int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo);
167 int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo);
169 int drm_intel_gem_bo_get_reloc_count(drm_intel_bo *bo);
170 void drm_intel_gem_bo_clear_relocs(drm_intel_bo *bo, int start);
171 void drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable);
173 void drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable);
174 void drm_intel_gem_bo_aub_dump_bmp(drm_intel_bo *bo,
175 int x1, int y1, int width, int height,
176 enum aub_dump_bmp_format format,
177 int pitch, int offset);
179 drm_intel_bufmgr_gem_set_aub_annotations(drm_intel_bo *bo,
180 drm_intel_aub_annotation *annotations,
183 int drm_intel_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id);
185 int drm_intel_get_aperture_sizes(int fd, size_t *mappable, size_t *total);
186 int drm_intel_bufmgr_gem_get_devid(drm_intel_bufmgr *bufmgr);
188 /* drm_intel_bufmgr_fake.c */
189 drm_intel_bufmgr *drm_intel_bufmgr_fake_init(int fd,
190 unsigned long low_offset,
193 volatile unsigned int
195 void drm_intel_bufmgr_fake_set_last_dispatch(drm_intel_bufmgr *bufmgr,
196 volatile unsigned int
198 void drm_intel_bufmgr_fake_set_exec_callback(drm_intel_bufmgr *bufmgr,
199 int (*exec) (drm_intel_bo *bo,
203 void drm_intel_bufmgr_fake_set_fence_callback(drm_intel_bufmgr *bufmgr,
204 unsigned int (*emit) (void *priv),
205 void (*wait) (unsigned int fence,
208 drm_intel_bo *drm_intel_bo_fake_alloc_static(drm_intel_bufmgr *bufmgr,
210 unsigned long offset,
211 unsigned long size, void *virt);
212 void drm_intel_bo_fake_disable_backing_store(drm_intel_bo *bo,
213 void (*invalidate_cb) (drm_intel_bo
218 void drm_intel_bufmgr_fake_contended_lock_take(drm_intel_bufmgr *bufmgr);
219 void drm_intel_bufmgr_fake_evict_all(drm_intel_bufmgr *bufmgr);
221 struct drm_intel_decode *drm_intel_decode_context_alloc(uint32_t devid);
222 void drm_intel_decode_context_free(struct drm_intel_decode *ctx);
223 void drm_intel_decode_set_batch_pointer(struct drm_intel_decode *ctx,
224 void *data, uint32_t hw_offset,
226 void drm_intel_decode_set_dump_past_end(struct drm_intel_decode *ctx,
228 void drm_intel_decode_set_head_tail(struct drm_intel_decode *ctx,
229 uint32_t head, uint32_t tail);
230 void drm_intel_decode_set_output_file(struct drm_intel_decode *ctx, FILE *out);
231 void drm_intel_decode(struct drm_intel_decode *ctx);
234 /** @{ Compatibility defines to keep old code building despite the symbol rename
235 * from dri_* to drm_intel_*
237 #define dri_bo drm_intel_bo
238 #define dri_bufmgr drm_intel_bufmgr
239 #define dri_bo_alloc drm_intel_bo_alloc
240 #define dri_bo_reference drm_intel_bo_reference
241 #define dri_bo_unreference drm_intel_bo_unreference
242 #define dri_bo_map drm_intel_bo_map
243 #define dri_bo_unmap drm_intel_bo_unmap
244 #define dri_bo_subdata drm_intel_bo_subdata
245 #define dri_bo_get_subdata drm_intel_bo_get_subdata
246 #define dri_bo_wait_rendering drm_intel_bo_wait_rendering
247 #define dri_bufmgr_set_debug drm_intel_bufmgr_set_debug
248 #define dri_bufmgr_destroy drm_intel_bufmgr_destroy
249 #define dri_bo_exec drm_intel_bo_exec
250 #define dri_bufmgr_check_aperture_space drm_intel_bufmgr_check_aperture_space
251 #define dri_bo_emit_reloc(reloc_bo, read, write, target_offset, \
252 reloc_offset, target_bo) \
253 drm_intel_bo_emit_reloc(reloc_bo, reloc_offset, \
254 target_bo, target_offset, \
256 #define dri_bo_pin drm_intel_bo_pin
257 #define dri_bo_unpin drm_intel_bo_unpin
258 #define dri_bo_get_tiling drm_intel_bo_get_tiling
259 #define dri_bo_set_tiling(bo, mode) drm_intel_bo_set_tiling(bo, mode, 0)
260 #define dri_bo_flink drm_intel_bo_flink
261 #define intel_bufmgr_gem_init drm_intel_bufmgr_gem_init
262 #define intel_bo_gem_create_from_name drm_intel_bo_gem_create_from_name
263 #define intel_bufmgr_gem_enable_reuse drm_intel_bufmgr_gem_enable_reuse
264 #define intel_bufmgr_fake_init drm_intel_bufmgr_fake_init
265 #define intel_bufmgr_fake_set_last_dispatch drm_intel_bufmgr_fake_set_last_dispatch
266 #define intel_bufmgr_fake_set_exec_callback drm_intel_bufmgr_fake_set_exec_callback
267 #define intel_bufmgr_fake_set_fence_callback drm_intel_bufmgr_fake_set_fence_callback
268 #define intel_bo_fake_alloc_static drm_intel_bo_fake_alloc_static
269 #define intel_bo_fake_disable_backing_store drm_intel_bo_fake_disable_backing_store
270 #define intel_bufmgr_fake_contended_lock_take drm_intel_bufmgr_fake_contended_lock_take
271 #define intel_bufmgr_fake_evict_all drm_intel_bufmgr_fake_evict_all
275 #endif /* INTEL_BUFMGR_H */