2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 * @file intel_bufmgr.h
31 * Public definitions of Intel-specific bufmgr functions.
34 #ifndef INTEL_BUFMGR_H
35 #define INTEL_BUFMGR_H
39 typedef struct _drm_intel_bufmgr drm_intel_bufmgr;
40 typedef struct _drm_intel_bo drm_intel_bo;
42 struct _drm_intel_bo {
44 * Size in bytes of the buffer object.
46 * The size may be larger than the size originally requested for the
47 * allocation, such as being aligned to page size.
52 * Alignment requirement for object
54 * Used for GTT mapping & pinning the object.
59 * Last seen card virtual address (offset from the beginning of the
60 * aperture) for the object. This should be used to fill relocation
61 * entries when calling drm_intel_bo_emit_reloc()
66 * Virtual address for accessing the buffer data. Only valid while
71 /** Buffer manager context associated with this buffer object */
72 drm_intel_bufmgr *bufmgr;
75 * MM-specific handle for accessing object
80 #define BO_ALLOC_FOR_RENDER (1<<0)
82 drm_intel_bo *drm_intel_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name,
83 unsigned long size, unsigned int alignment);
84 drm_intel_bo *drm_intel_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
87 unsigned int alignment);
88 drm_intel_bo *drm_intel_bo_alloc_tiled(drm_intel_bufmgr *bufmgr,
90 int x, int y, int cpp,
91 uint32_t *tiling_mode,
94 void drm_intel_bo_reference(drm_intel_bo *bo);
95 void drm_intel_bo_unreference(drm_intel_bo *bo);
96 int drm_intel_bo_map(drm_intel_bo *bo, int write_enable);
97 int drm_intel_bo_unmap(drm_intel_bo *bo);
99 int drm_intel_bo_subdata(drm_intel_bo *bo, unsigned long offset,
100 unsigned long size, const void *data);
101 int drm_intel_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
102 unsigned long size, void *data);
103 void drm_intel_bo_wait_rendering(drm_intel_bo *bo);
105 void drm_intel_bufmgr_set_debug(drm_intel_bufmgr *bufmgr, int enable_debug);
106 void drm_intel_bufmgr_destroy(drm_intel_bufmgr *bufmgr);
107 int drm_intel_bo_exec(drm_intel_bo *bo, int used,
108 drm_clip_rect_t * cliprects, int num_cliprects, int DR4);
109 int drm_intel_bufmgr_check_aperture_space(drm_intel_bo ** bo_array, int count);
111 int drm_intel_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
112 drm_intel_bo *target_bo, uint32_t target_offset,
113 uint32_t read_domains, uint32_t write_domain);
114 int drm_intel_bo_pin(drm_intel_bo *bo, uint32_t alignment);
115 int drm_intel_bo_unpin(drm_intel_bo *bo);
116 int drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
118 int drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
119 uint32_t * swizzle_mode);
120 int drm_intel_bo_flink(drm_intel_bo *bo, uint32_t * name);
121 int drm_intel_bo_busy(drm_intel_bo *bo);
122 int drm_intel_bo_madvise(drm_intel_bo *bo, int madv);
124 int drm_intel_bo_disable_reuse(drm_intel_bo *bo);
125 int drm_intel_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo);
127 /* drm_intel_bufmgr_gem.c */
128 drm_intel_bufmgr *drm_intel_bufmgr_gem_init(int fd, int batch_size);
129 drm_intel_bo *drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
131 unsigned int handle);
132 void drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr);
133 int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo);
134 int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo);
135 void drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable);
137 int drm_intel_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id);
139 /* drm_intel_bufmgr_fake.c */
140 drm_intel_bufmgr *drm_intel_bufmgr_fake_init(int fd,
141 unsigned long low_offset,
144 volatile unsigned int
146 void drm_intel_bufmgr_fake_set_last_dispatch(drm_intel_bufmgr *bufmgr,
147 volatile unsigned int
149 void drm_intel_bufmgr_fake_set_exec_callback(drm_intel_bufmgr *bufmgr,
150 int (*exec) (drm_intel_bo *bo,
154 void drm_intel_bufmgr_fake_set_fence_callback(drm_intel_bufmgr *bufmgr,
155 unsigned int (*emit) (void *priv),
156 void (*wait) (unsigned int fence,
159 drm_intel_bo *drm_intel_bo_fake_alloc_static(drm_intel_bufmgr *bufmgr,
161 unsigned long offset,
162 unsigned long size, void *virtual);
163 void drm_intel_bo_fake_disable_backing_store(drm_intel_bo *bo,
164 void (*invalidate_cb) (drm_intel_bo
169 void drm_intel_bufmgr_fake_contended_lock_take(drm_intel_bufmgr *bufmgr);
170 void drm_intel_bufmgr_fake_evict_all(drm_intel_bufmgr *bufmgr);
172 /** @{ Compatibility defines to keep old code building despite the symbol rename
173 * from dri_* to drm_intel_*
175 #define dri_bo drm_intel_bo
176 #define dri_bufmgr drm_intel_bufmgr
177 #define dri_bo_alloc drm_intel_bo_alloc
178 #define dri_bo_reference drm_intel_bo_reference
179 #define dri_bo_unreference drm_intel_bo_unreference
180 #define dri_bo_map drm_intel_bo_map
181 #define dri_bo_unmap drm_intel_bo_unmap
182 #define dri_bo_subdata drm_intel_bo_subdata
183 #define dri_bo_get_subdata drm_intel_bo_get_subdata
184 #define dri_bo_wait_rendering drm_intel_bo_wait_rendering
185 #define dri_bufmgr_set_debug drm_intel_bufmgr_set_debug
186 #define dri_bufmgr_destroy drm_intel_bufmgr_destroy
187 #define dri_bo_exec drm_intel_bo_exec
188 #define dri_bufmgr_check_aperture_space drm_intel_bufmgr_check_aperture_space
189 #define dri_bo_emit_reloc(reloc_bo, read, write, target_offset, \
190 reloc_offset, target_bo) \
191 drm_intel_bo_emit_reloc(reloc_bo, reloc_offset, \
192 target_bo, target_offset, \
194 #define dri_bo_pin drm_intel_bo_pin
195 #define dri_bo_unpin drm_intel_bo_unpin
196 #define dri_bo_get_tiling drm_intel_bo_get_tiling
197 #define dri_bo_set_tiling(bo, mode) drm_intel_bo_set_tiling(bo, mode, 0)
198 #define dri_bo_flink drm_intel_bo_flink
199 #define intel_bufmgr_gem_init drm_intel_bufmgr_gem_init
200 #define intel_bo_gem_create_from_name drm_intel_bo_gem_create_from_name
201 #define intel_bufmgr_gem_enable_reuse drm_intel_bufmgr_gem_enable_reuse
202 #define intel_bufmgr_fake_init drm_intel_bufmgr_fake_init
203 #define intel_bufmgr_fake_set_last_dispatch drm_intel_bufmgr_fake_set_last_dispatch
204 #define intel_bufmgr_fake_set_exec_callback drm_intel_bufmgr_fake_set_exec_callback
205 #define intel_bufmgr_fake_set_fence_callback drm_intel_bufmgr_fake_set_fence_callback
206 #define intel_bo_fake_alloc_static drm_intel_bo_fake_alloc_static
207 #define intel_bo_fake_disable_backing_store drm_intel_bo_fake_disable_backing_store
208 #define intel_bufmgr_fake_contended_lock_take drm_intel_bufmgr_fake_contended_lock_take
209 #define intel_bufmgr_fake_evict_all drm_intel_bufmgr_fake_evict_all
213 #endif /* INTEL_BUFMGR_H */