2 * Copyright © 2008-2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 * @file intel_bufmgr.h
31 * Public definitions of Intel-specific bufmgr functions.
34 #ifndef INTEL_BUFMGR_H
35 #define INTEL_BUFMGR_H
43 typedef struct _drm_intel_bufmgr drm_intel_bufmgr;
44 typedef struct _drm_intel_context drm_intel_context;
45 typedef struct _drm_intel_bo drm_intel_bo;
47 struct _drm_intel_bo {
49 * Size in bytes of the buffer object.
51 * The size may be larger than the size originally requested for the
52 * allocation, such as being aligned to page size.
57 * Alignment requirement for object
59 * Used for GTT mapping & pinning the object.
64 * Deprecated field containing (possibly the low 32-bits of) the last
65 * seen virtual card address. Use offset64 instead.
70 * Virtual address for accessing the buffer data. Only valid while
79 /** Buffer manager context associated with this buffer object */
80 drm_intel_bufmgr *bufmgr;
83 * MM-specific handle for accessing object
88 * Last seen card virtual address (offset from the beginning of the
89 * aperture) for the object. This should be used to fill relocation
90 * entries when calling drm_intel_bo_emit_reloc()
95 enum aub_dump_bmp_format {
96 AUB_DUMP_BMP_FORMAT_8BIT = 1,
97 AUB_DUMP_BMP_FORMAT_ARGB_4444 = 4,
98 AUB_DUMP_BMP_FORMAT_ARGB_0888 = 6,
99 AUB_DUMP_BMP_FORMAT_ARGB_8888 = 7,
102 typedef struct _drm_intel_aub_annotation {
105 uint32_t ending_offset;
106 } drm_intel_aub_annotation;
108 #define BO_ALLOC_FOR_RENDER (1<<0)
110 drm_intel_bo *drm_intel_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name,
111 unsigned long size, unsigned int alignment);
112 drm_intel_bo *drm_intel_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
115 unsigned int alignment);
116 drm_intel_bo *drm_intel_bo_alloc_userptr(drm_intel_bufmgr *bufmgr,
118 void *addr, uint32_t tiling_mode,
119 uint32_t stride, unsigned long size,
120 unsigned long flags);
121 drm_intel_bo *drm_intel_bo_alloc_tiled(drm_intel_bufmgr *bufmgr,
123 int x, int y, int cpp,
124 uint32_t *tiling_mode,
125 unsigned long *pitch,
126 unsigned long flags);
127 void drm_intel_bo_reference(drm_intel_bo *bo);
128 void drm_intel_bo_unreference(drm_intel_bo *bo);
129 int drm_intel_bo_map(drm_intel_bo *bo, int write_enable);
130 int drm_intel_bo_unmap(drm_intel_bo *bo);
132 int drm_intel_bo_subdata(drm_intel_bo *bo, unsigned long offset,
133 unsigned long size, const void *data);
134 int drm_intel_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
135 unsigned long size, void *data);
136 void drm_intel_bo_wait_rendering(drm_intel_bo *bo);
138 void drm_intel_bufmgr_set_debug(drm_intel_bufmgr *bufmgr, int enable_debug);
139 void drm_intel_bufmgr_destroy(drm_intel_bufmgr *bufmgr);
140 int drm_intel_bo_exec(drm_intel_bo *bo, int used,
141 struct drm_clip_rect *cliprects, int num_cliprects, int DR4);
142 int drm_intel_bo_mrb_exec(drm_intel_bo *bo, int used,
143 struct drm_clip_rect *cliprects, int num_cliprects, int DR4,
145 int drm_intel_bufmgr_check_aperture_space(drm_intel_bo ** bo_array, int count);
147 int drm_intel_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
148 drm_intel_bo *target_bo, uint32_t target_offset,
149 uint32_t read_domains, uint32_t write_domain);
150 int drm_intel_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
151 drm_intel_bo *target_bo,
152 uint32_t target_offset,
153 uint32_t read_domains, uint32_t write_domain);
154 int drm_intel_bo_pin(drm_intel_bo *bo, uint32_t alignment);
155 int drm_intel_bo_unpin(drm_intel_bo *bo);
156 int drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
158 int drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
159 uint32_t * swizzle_mode);
160 int drm_intel_bo_flink(drm_intel_bo *bo, uint32_t * name);
161 int drm_intel_bo_busy(drm_intel_bo *bo);
162 int drm_intel_bo_madvise(drm_intel_bo *bo, int madv);
164 int drm_intel_bo_disable_reuse(drm_intel_bo *bo);
165 int drm_intel_bo_is_reusable(drm_intel_bo *bo);
166 int drm_intel_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo);
168 /* drm_intel_bufmgr_gem.c */
169 drm_intel_bufmgr *drm_intel_bufmgr_gem_init(int fd, int batch_size);
170 drm_intel_bo *drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
172 unsigned int handle);
173 void drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr);
174 void drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr);
175 void drm_intel_bufmgr_gem_set_vma_cache_size(drm_intel_bufmgr *bufmgr,
177 int drm_intel_gem_bo_map_unsynchronized(drm_intel_bo *bo);
178 int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo);
179 int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo);
181 int drm_intel_gem_bo_get_reloc_count(drm_intel_bo *bo);
182 void drm_intel_gem_bo_clear_relocs(drm_intel_bo *bo, int start);
183 void drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable);
186 drm_intel_bufmgr_gem_set_aub_filename(drm_intel_bufmgr *bufmgr,
187 const char *filename);
188 void drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable);
189 void drm_intel_gem_bo_aub_dump_bmp(drm_intel_bo *bo,
190 int x1, int y1, int width, int height,
191 enum aub_dump_bmp_format format,
192 int pitch, int offset);
194 drm_intel_bufmgr_gem_set_aub_annotations(drm_intel_bo *bo,
195 drm_intel_aub_annotation *annotations,
198 int drm_intel_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id);
200 int drm_intel_get_aperture_sizes(int fd, size_t *mappable, size_t *total);
201 int drm_intel_bufmgr_gem_get_devid(drm_intel_bufmgr *bufmgr);
202 int drm_intel_gem_bo_wait(drm_intel_bo *bo, int64_t timeout_ns);
204 drm_intel_context *drm_intel_gem_context_create(drm_intel_bufmgr *bufmgr);
205 void drm_intel_gem_context_destroy(drm_intel_context *ctx);
206 int drm_intel_gem_bo_context_exec(drm_intel_bo *bo, drm_intel_context *ctx,
207 int used, unsigned int flags);
209 int drm_intel_bo_gem_export_to_prime(drm_intel_bo *bo, int *prime_fd);
210 drm_intel_bo *drm_intel_bo_gem_create_from_prime(drm_intel_bufmgr *bufmgr,
211 int prime_fd, int size);
213 /* drm_intel_bufmgr_fake.c */
214 drm_intel_bufmgr *drm_intel_bufmgr_fake_init(int fd,
215 unsigned long low_offset,
218 volatile unsigned int
220 void drm_intel_bufmgr_fake_set_last_dispatch(drm_intel_bufmgr *bufmgr,
221 volatile unsigned int
223 void drm_intel_bufmgr_fake_set_exec_callback(drm_intel_bufmgr *bufmgr,
224 int (*exec) (drm_intel_bo *bo,
228 void drm_intel_bufmgr_fake_set_fence_callback(drm_intel_bufmgr *bufmgr,
229 unsigned int (*emit) (void *priv),
230 void (*wait) (unsigned int fence,
233 drm_intel_bo *drm_intel_bo_fake_alloc_static(drm_intel_bufmgr *bufmgr,
235 unsigned long offset,
236 unsigned long size, void *virt);
237 void drm_intel_bo_fake_disable_backing_store(drm_intel_bo *bo,
238 void (*invalidate_cb) (drm_intel_bo
243 void drm_intel_bufmgr_fake_contended_lock_take(drm_intel_bufmgr *bufmgr);
244 void drm_intel_bufmgr_fake_evict_all(drm_intel_bufmgr *bufmgr);
246 struct drm_intel_decode *drm_intel_decode_context_alloc(uint32_t devid);
247 void drm_intel_decode_context_free(struct drm_intel_decode *ctx);
248 void drm_intel_decode_set_batch_pointer(struct drm_intel_decode *ctx,
249 void *data, uint32_t hw_offset,
251 void drm_intel_decode_set_dump_past_end(struct drm_intel_decode *ctx,
253 void drm_intel_decode_set_head_tail(struct drm_intel_decode *ctx,
254 uint32_t head, uint32_t tail);
255 void drm_intel_decode_set_output_file(struct drm_intel_decode *ctx, FILE *out);
256 void drm_intel_decode(struct drm_intel_decode *ctx);
258 int drm_intel_reg_read(drm_intel_bufmgr *bufmgr,
262 int drm_intel_get_reset_stats(drm_intel_context *ctx,
263 uint32_t *reset_count,
267 /** @{ Compatibility defines to keep old code building despite the symbol rename
268 * from dri_* to drm_intel_*
270 #define dri_bo drm_intel_bo
271 #define dri_bufmgr drm_intel_bufmgr
272 #define dri_bo_alloc drm_intel_bo_alloc
273 #define dri_bo_reference drm_intel_bo_reference
274 #define dri_bo_unreference drm_intel_bo_unreference
275 #define dri_bo_map drm_intel_bo_map
276 #define dri_bo_unmap drm_intel_bo_unmap
277 #define dri_bo_subdata drm_intel_bo_subdata
278 #define dri_bo_get_subdata drm_intel_bo_get_subdata
279 #define dri_bo_wait_rendering drm_intel_bo_wait_rendering
280 #define dri_bufmgr_set_debug drm_intel_bufmgr_set_debug
281 #define dri_bufmgr_destroy drm_intel_bufmgr_destroy
282 #define dri_bo_exec drm_intel_bo_exec
283 #define dri_bufmgr_check_aperture_space drm_intel_bufmgr_check_aperture_space
284 #define dri_bo_emit_reloc(reloc_bo, read, write, target_offset, \
285 reloc_offset, target_bo) \
286 drm_intel_bo_emit_reloc(reloc_bo, reloc_offset, \
287 target_bo, target_offset, \
289 #define dri_bo_pin drm_intel_bo_pin
290 #define dri_bo_unpin drm_intel_bo_unpin
291 #define dri_bo_get_tiling drm_intel_bo_get_tiling
292 #define dri_bo_set_tiling(bo, mode) drm_intel_bo_set_tiling(bo, mode, 0)
293 #define dri_bo_flink drm_intel_bo_flink
294 #define intel_bufmgr_gem_init drm_intel_bufmgr_gem_init
295 #define intel_bo_gem_create_from_name drm_intel_bo_gem_create_from_name
296 #define intel_bufmgr_gem_enable_reuse drm_intel_bufmgr_gem_enable_reuse
297 #define intel_bufmgr_fake_init drm_intel_bufmgr_fake_init
298 #define intel_bufmgr_fake_set_last_dispatch drm_intel_bufmgr_fake_set_last_dispatch
299 #define intel_bufmgr_fake_set_exec_callback drm_intel_bufmgr_fake_set_exec_callback
300 #define intel_bufmgr_fake_set_fence_callback drm_intel_bufmgr_fake_set_fence_callback
301 #define intel_bo_fake_alloc_static drm_intel_bo_fake_alloc_static
302 #define intel_bo_fake_disable_backing_store drm_intel_bo_fake_disable_backing_store
303 #define intel_bufmgr_fake_contended_lock_take drm_intel_bufmgr_fake_contended_lock_take
304 #define intel_bufmgr_fake_evict_all drm_intel_bufmgr_fake_evict_all
308 #endif /* INTEL_BUFMGR_H */