2 * Copyright © 2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
39 #include "intel_bufmgr.h"
40 #include "intel_bufmgr_priv.h"
42 /** @file intel_bufmgr.c
44 * Convenience functions for buffer management methods.
47 drm_intel_bo *drm_intel_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name,
48 unsigned long size, unsigned int alignment)
50 return bufmgr->bo_alloc(bufmgr, name, size, alignment);
53 drm_intel_bo *drm_intel_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
56 unsigned int alignment)
58 return bufmgr->bo_alloc_for_render(bufmgr, name, size, alignment);
62 drm_intel_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
63 int x, int y, int cpp, uint32_t *tiling_mode,
64 unsigned long *pitch, unsigned long flags)
66 return bufmgr->bo_alloc_tiled(bufmgr, name, x, y, cpp,
67 tiling_mode, pitch, flags);
70 void drm_intel_bo_reference(drm_intel_bo *bo)
72 bo->bufmgr->bo_reference(bo);
75 void drm_intel_bo_unreference(drm_intel_bo *bo)
80 bo->bufmgr->bo_unreference(bo);
83 int drm_intel_bo_map(drm_intel_bo *buf, int write_enable)
85 return buf->bufmgr->bo_map(buf, write_enable);
88 int drm_intel_bo_unmap(drm_intel_bo *buf)
90 return buf->bufmgr->bo_unmap(buf);
94 drm_intel_bo_subdata(drm_intel_bo *bo, unsigned long offset,
95 unsigned long size, const void *data)
97 return bo->bufmgr->bo_subdata(bo, offset, size, data);
101 drm_intel_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
102 unsigned long size, void *data)
105 if (bo->bufmgr->bo_subdata)
106 return bo->bufmgr->bo_get_subdata(bo, offset, size, data);
108 if (size == 0 || data == NULL)
111 ret = drm_intel_bo_map(bo, 0);
114 memcpy(data, (unsigned char *)bo->virtual + offset, size);
115 drm_intel_bo_unmap(bo);
119 void drm_intel_bo_wait_rendering(drm_intel_bo *bo)
121 bo->bufmgr->bo_wait_rendering(bo);
124 void drm_intel_bufmgr_destroy(drm_intel_bufmgr *bufmgr)
126 bufmgr->destroy(bufmgr);
130 drm_intel_bo_exec(drm_intel_bo *bo, int used,
131 drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
133 return bo->bufmgr->bo_exec(bo, used, cliprects, num_cliprects, DR4);
137 drm_intel_bo_mrb_exec(drm_intel_bo *bo, int used,
138 drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
141 if (bo->bufmgr->bo_mrb_exec)
142 return bo->bufmgr->bo_mrb_exec(bo, used,
143 cliprects, num_cliprects, DR4,
147 return bo->bufmgr->bo_exec(bo, used,
148 cliprects, num_cliprects, DR4);
153 void drm_intel_bufmgr_set_debug(drm_intel_bufmgr *bufmgr, int enable_debug)
155 bufmgr->debug = enable_debug;
158 int drm_intel_bufmgr_check_aperture_space(drm_intel_bo ** bo_array, int count)
160 return bo_array[0]->bufmgr->check_aperture_space(bo_array, count);
163 int drm_intel_bo_flink(drm_intel_bo *bo, uint32_t * name)
165 if (bo->bufmgr->bo_flink)
166 return bo->bufmgr->bo_flink(bo, name);
172 drm_intel_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
173 drm_intel_bo *target_bo, uint32_t target_offset,
174 uint32_t read_domains, uint32_t write_domain)
176 return bo->bufmgr->bo_emit_reloc(bo, offset,
177 target_bo, target_offset,
178 read_domains, write_domain);
181 /* For fence registers, not GL fences */
183 drm_intel_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
184 drm_intel_bo *target_bo, uint32_t target_offset,
185 uint32_t read_domains, uint32_t write_domain)
187 return bo->bufmgr->bo_emit_reloc_fence(bo, offset,
188 target_bo, target_offset,
189 read_domains, write_domain);
193 int drm_intel_bo_pin(drm_intel_bo *bo, uint32_t alignment)
195 if (bo->bufmgr->bo_pin)
196 return bo->bufmgr->bo_pin(bo, alignment);
201 int drm_intel_bo_unpin(drm_intel_bo *bo)
203 if (bo->bufmgr->bo_unpin)
204 return bo->bufmgr->bo_unpin(bo);
209 int drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
212 if (bo->bufmgr->bo_set_tiling)
213 return bo->bufmgr->bo_set_tiling(bo, tiling_mode, stride);
215 *tiling_mode = I915_TILING_NONE;
219 int drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
220 uint32_t * swizzle_mode)
222 if (bo->bufmgr->bo_get_tiling)
223 return bo->bufmgr->bo_get_tiling(bo, tiling_mode, swizzle_mode);
225 *tiling_mode = I915_TILING_NONE;
226 *swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
230 int drm_intel_bo_disable_reuse(drm_intel_bo *bo)
232 if (bo->bufmgr->bo_disable_reuse)
233 return bo->bufmgr->bo_disable_reuse(bo);
237 int drm_intel_bo_is_reusable(drm_intel_bo *bo)
239 if (bo->bufmgr->bo_is_reusable)
240 return bo->bufmgr->bo_is_reusable(bo);
244 int drm_intel_bo_busy(drm_intel_bo *bo)
246 if (bo->bufmgr->bo_busy)
247 return bo->bufmgr->bo_busy(bo);
251 int drm_intel_bo_madvise(drm_intel_bo *bo, int madv)
253 if (bo->bufmgr->bo_madvise)
254 return bo->bufmgr->bo_madvise(bo, madv);
258 int drm_intel_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
260 return bo->bufmgr->bo_references(bo, target_bo);
263 int drm_intel_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id)
265 if (bufmgr->get_pipe_from_crtc_id)
266 return bufmgr->get_pipe_from_crtc_id(bufmgr, crtc_id);