2 * Copyright © 2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
39 #include <pciaccess.h>
41 #include "intel_bufmgr.h"
42 #include "intel_bufmgr_priv.h"
45 /** @file intel_bufmgr.c
47 * Convenience functions for buffer management methods.
50 drm_public drm_intel_bo *
51 drm_intel_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name,
52 unsigned long size, unsigned int alignment)
54 return bufmgr->bo_alloc(bufmgr, name, size, alignment);
57 drm_public drm_intel_bo *
58 drm_intel_bo_alloc_for_render(drm_intel_bufmgr *bufmgr, const char *name,
59 unsigned long size, unsigned int alignment)
61 return bufmgr->bo_alloc_for_render(bufmgr, name, size, alignment);
64 drm_public drm_intel_bo *
65 drm_intel_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
66 int x, int y, int cpp, uint32_t *tiling_mode,
67 unsigned long *pitch, unsigned long flags)
69 return bufmgr->bo_alloc_tiled(bufmgr, name, x, y, cpp,
70 tiling_mode, pitch, flags);
74 drm_intel_bo_reference(drm_intel_bo *bo)
76 bo->bufmgr->bo_reference(bo);
80 drm_intel_bo_unreference(drm_intel_bo *bo)
85 bo->bufmgr->bo_unreference(bo);
89 drm_intel_bo_map(drm_intel_bo *buf, int write_enable)
91 return buf->bufmgr->bo_map(buf, write_enable);
95 drm_intel_bo_unmap(drm_intel_bo *buf)
97 return buf->bufmgr->bo_unmap(buf);
101 drm_intel_bo_subdata(drm_intel_bo *bo, unsigned long offset,
102 unsigned long size, const void *data)
104 return bo->bufmgr->bo_subdata(bo, offset, size, data);
108 drm_intel_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
109 unsigned long size, void *data)
112 if (bo->bufmgr->bo_get_subdata)
113 return bo->bufmgr->bo_get_subdata(bo, offset, size, data);
115 if (size == 0 || data == NULL)
118 ret = drm_intel_bo_map(bo, 0);
121 memcpy(data, (unsigned char *)bo->virtual + offset, size);
122 drm_intel_bo_unmap(bo);
127 drm_intel_bo_wait_rendering(drm_intel_bo *bo)
129 bo->bufmgr->bo_wait_rendering(bo);
133 drm_intel_bufmgr_destroy(drm_intel_bufmgr *bufmgr)
135 bufmgr->destroy(bufmgr);
139 drm_intel_bo_exec(drm_intel_bo *bo, int used,
140 drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
142 return bo->bufmgr->bo_exec(bo, used, cliprects, num_cliprects, DR4);
146 drm_intel_bo_mrb_exec(drm_intel_bo *bo, int used,
147 drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
150 if (bo->bufmgr->bo_mrb_exec)
151 return bo->bufmgr->bo_mrb_exec(bo, used,
152 cliprects, num_cliprects, DR4,
156 case I915_EXEC_DEFAULT:
157 case I915_EXEC_RENDER:
158 return bo->bufmgr->bo_exec(bo, used,
159 cliprects, num_cliprects, DR4);
166 drm_intel_bufmgr_set_debug(drm_intel_bufmgr *bufmgr, int enable_debug)
168 bufmgr->debug = enable_debug;
172 drm_intel_bufmgr_check_aperture_space(drm_intel_bo ** bo_array, int count)
174 return bo_array[0]->bufmgr->check_aperture_space(bo_array, count);
178 drm_intel_bo_flink(drm_intel_bo *bo, uint32_t * name)
180 if (bo->bufmgr->bo_flink)
181 return bo->bufmgr->bo_flink(bo, name);
187 drm_intel_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
188 drm_intel_bo *target_bo, uint32_t target_offset,
189 uint32_t read_domains, uint32_t write_domain)
191 return bo->bufmgr->bo_emit_reloc(bo, offset,
192 target_bo, target_offset,
193 read_domains, write_domain);
196 /* For fence registers, not GL fences */
198 drm_intel_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
199 drm_intel_bo *target_bo, uint32_t target_offset,
200 uint32_t read_domains, uint32_t write_domain)
202 return bo->bufmgr->bo_emit_reloc_fence(bo, offset,
203 target_bo, target_offset,
204 read_domains, write_domain);
209 drm_intel_bo_pin(drm_intel_bo *bo, uint32_t alignment)
211 if (bo->bufmgr->bo_pin)
212 return bo->bufmgr->bo_pin(bo, alignment);
218 drm_intel_bo_unpin(drm_intel_bo *bo)
220 if (bo->bufmgr->bo_unpin)
221 return bo->bufmgr->bo_unpin(bo);
227 drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
230 if (bo->bufmgr->bo_set_tiling)
231 return bo->bufmgr->bo_set_tiling(bo, tiling_mode, stride);
233 *tiling_mode = I915_TILING_NONE;
238 drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
239 uint32_t * swizzle_mode)
241 if (bo->bufmgr->bo_get_tiling)
242 return bo->bufmgr->bo_get_tiling(bo, tiling_mode, swizzle_mode);
244 *tiling_mode = I915_TILING_NONE;
245 *swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
250 drm_intel_bo_disable_reuse(drm_intel_bo *bo)
252 if (bo->bufmgr->bo_disable_reuse)
253 return bo->bufmgr->bo_disable_reuse(bo);
258 drm_intel_bo_is_reusable(drm_intel_bo *bo)
260 if (bo->bufmgr->bo_is_reusable)
261 return bo->bufmgr->bo_is_reusable(bo);
266 drm_intel_bo_busy(drm_intel_bo *bo)
268 if (bo->bufmgr->bo_busy)
269 return bo->bufmgr->bo_busy(bo);
274 drm_intel_bo_madvise(drm_intel_bo *bo, int madv)
276 if (bo->bufmgr->bo_madvise)
277 return bo->bufmgr->bo_madvise(bo, madv);
282 drm_intel_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
284 return bo->bufmgr->bo_references(bo, target_bo);
288 drm_intel_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id)
290 if (bufmgr->get_pipe_from_crtc_id)
291 return bufmgr->get_pipe_from_crtc_id(bufmgr, crtc_id);
296 drm_intel_probe_agp_aperture_size(int fd)
298 struct pci_device *pci_dev;
302 ret = pci_system_init();
306 /* XXX handle multiple adaptors? */
307 pci_dev = pci_device_find_by_slot(0, 0, 2, 0);
311 ret = pci_device_probe(pci_dev);
315 size = pci_dev->regions[2].size;
317 pci_system_cleanup ();
322 drm_intel_get_aperture_sizes(int fd, size_t *mappable, size_t *total)
325 struct drm_i915_gem_get_aperture aperture;
328 ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
333 /* XXX add a query for the kernel value? */
335 *mappable = drm_intel_probe_agp_aperture_size(fd);
337 *mappable = 64 * 1024 * 1024; /* minimum possible value */
338 *total = aperture.aper_size;