2 * Copyright © 2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
39 #include <pciaccess.h>
40 #include "intel_bufmgr.h"
41 #include "intel_bufmgr_priv.h"
44 /** @file intel_bufmgr.c
46 * Convenience functions for buffer management methods.
49 drm_intel_bo *drm_intel_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name,
50 unsigned long size, unsigned int alignment)
52 return bufmgr->bo_alloc(bufmgr, name, size, alignment);
55 drm_intel_bo *drm_intel_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
58 unsigned int alignment)
60 return bufmgr->bo_alloc_for_render(bufmgr, name, size, alignment);
64 drm_intel_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
65 int x, int y, int cpp, uint32_t *tiling_mode,
66 unsigned long *pitch, unsigned long flags)
68 return bufmgr->bo_alloc_tiled(bufmgr, name, x, y, cpp,
69 tiling_mode, pitch, flags);
72 void drm_intel_bo_reference(drm_intel_bo *bo)
74 bo->bufmgr->bo_reference(bo);
77 void drm_intel_bo_unreference(drm_intel_bo *bo)
82 bo->bufmgr->bo_unreference(bo);
85 int drm_intel_bo_map(drm_intel_bo *buf, int write_enable)
87 return buf->bufmgr->bo_map(buf, write_enable);
90 int drm_intel_bo_unmap(drm_intel_bo *buf)
92 return buf->bufmgr->bo_unmap(buf);
96 drm_intel_bo_subdata(drm_intel_bo *bo, unsigned long offset,
97 unsigned long size, const void *data)
99 return bo->bufmgr->bo_subdata(bo, offset, size, data);
103 drm_intel_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
104 unsigned long size, void *data)
107 if (bo->bufmgr->bo_get_subdata)
108 return bo->bufmgr->bo_get_subdata(bo, offset, size, data);
110 if (size == 0 || data == NULL)
113 ret = drm_intel_bo_map(bo, 0);
116 memcpy(data, (unsigned char *)bo->virtual + offset, size);
117 drm_intel_bo_unmap(bo);
121 void drm_intel_bo_wait_rendering(drm_intel_bo *bo)
123 bo->bufmgr->bo_wait_rendering(bo);
126 void drm_intel_bufmgr_destroy(drm_intel_bufmgr *bufmgr)
128 bufmgr->destroy(bufmgr);
132 drm_intel_bo_exec(drm_intel_bo *bo, int used,
133 drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
135 return bo->bufmgr->bo_exec(bo, used, cliprects, num_cliprects, DR4);
139 drm_intel_bo_mrb_exec(drm_intel_bo *bo, int used,
140 drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
143 if (bo->bufmgr->bo_mrb_exec)
144 return bo->bufmgr->bo_mrb_exec(bo, used,
145 cliprects, num_cliprects, DR4,
149 case I915_EXEC_DEFAULT:
150 case I915_EXEC_RENDER:
151 return bo->bufmgr->bo_exec(bo, used,
152 cliprects, num_cliprects, DR4);
158 void drm_intel_bufmgr_set_debug(drm_intel_bufmgr *bufmgr, int enable_debug)
160 bufmgr->debug = enable_debug;
163 int drm_intel_bufmgr_check_aperture_space(drm_intel_bo ** bo_array, int count)
165 return bo_array[0]->bufmgr->check_aperture_space(bo_array, count);
168 int drm_intel_bo_flink(drm_intel_bo *bo, uint32_t * name)
170 if (bo->bufmgr->bo_flink)
171 return bo->bufmgr->bo_flink(bo, name);
177 drm_intel_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
178 drm_intel_bo *target_bo, uint32_t target_offset,
179 uint32_t read_domains, uint32_t write_domain)
181 return bo->bufmgr->bo_emit_reloc(bo, offset,
182 target_bo, target_offset,
183 read_domains, write_domain);
186 /* For fence registers, not GL fences */
188 drm_intel_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
189 drm_intel_bo *target_bo, uint32_t target_offset,
190 uint32_t read_domains, uint32_t write_domain)
192 return bo->bufmgr->bo_emit_reloc_fence(bo, offset,
193 target_bo, target_offset,
194 read_domains, write_domain);
198 int drm_intel_bo_pin(drm_intel_bo *bo, uint32_t alignment)
200 if (bo->bufmgr->bo_pin)
201 return bo->bufmgr->bo_pin(bo, alignment);
206 int drm_intel_bo_unpin(drm_intel_bo *bo)
208 if (bo->bufmgr->bo_unpin)
209 return bo->bufmgr->bo_unpin(bo);
214 int drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
217 if (bo->bufmgr->bo_set_tiling)
218 return bo->bufmgr->bo_set_tiling(bo, tiling_mode, stride);
220 *tiling_mode = I915_TILING_NONE;
224 int drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
225 uint32_t * swizzle_mode)
227 if (bo->bufmgr->bo_get_tiling)
228 return bo->bufmgr->bo_get_tiling(bo, tiling_mode, swizzle_mode);
230 *tiling_mode = I915_TILING_NONE;
231 *swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
235 int drm_intel_bo_disable_reuse(drm_intel_bo *bo)
237 if (bo->bufmgr->bo_disable_reuse)
238 return bo->bufmgr->bo_disable_reuse(bo);
242 int drm_intel_bo_is_reusable(drm_intel_bo *bo)
244 if (bo->bufmgr->bo_is_reusable)
245 return bo->bufmgr->bo_is_reusable(bo);
249 int drm_intel_bo_busy(drm_intel_bo *bo)
251 if (bo->bufmgr->bo_busy)
252 return bo->bufmgr->bo_busy(bo);
256 int drm_intel_bo_madvise(drm_intel_bo *bo, int madv)
258 if (bo->bufmgr->bo_madvise)
259 return bo->bufmgr->bo_madvise(bo, madv);
263 int drm_intel_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
265 return bo->bufmgr->bo_references(bo, target_bo);
268 int drm_intel_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id)
270 if (bufmgr->get_pipe_from_crtc_id)
271 return bufmgr->get_pipe_from_crtc_id(bufmgr, crtc_id);
276 drm_intel_probe_agp_aperture_size(int fd)
278 struct pci_device *pci_dev;
282 ret = pci_system_init();
286 /* XXX handle multiple adaptors? */
287 pci_dev = pci_device_find_by_slot(0, 0, 2, 0);
291 ret = pci_device_probe(pci_dev);
295 size = pci_dev->regions[2].size;
297 pci_system_cleanup ();
301 int drm_intel_get_aperture_sizes(int fd,
306 struct drm_i915_gem_get_aperture aperture;
309 ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
314 /* XXX add a query for the kernel value? */
316 *mappable = drm_intel_probe_agp_aperture_size(fd);
318 *mappable = 64 * 1024 * 1024; /* minimum possible value */
319 *total = aperture.aper_size;