1 /*******************************************************************************
2 * Copyright 2017-2018 Intel Corporation
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
8 * http://www.apache.org/licenses/LICENSE-2.0
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 *******************************************************************************/
17 #ifndef CPU_BARRIER_HPP
18 #define CPU_BARRIER_HPP
22 #include "jit_generator.hpp"
29 namespace simple_barrier {
33 enum { CACHE_LINE_SIZE = 64 };
35 char pad1[CACHE_LINE_SIZE - 1 * sizeof(size_t)];
36 volatile size_t sense;
37 char pad2[CACHE_LINE_SIZE - 1 * sizeof(size_t)];
40 inline void ctx_init(ctx_t *ctx) { *ctx = utils::zero<ctx_t>(); }
41 void barrier(ctx_t *ctx, int nthr);
43 /** injects actual barrier implementation into another jitted code
45 * code -- jit_generator object where the barrier is to be injected
46 * reg_ctx -- read-only register with pointer to the barrier context
47 * reg_nnthr -- read-only register with the # of synchronizing threads
49 void generate(jit_generator &code, Xbyak::Reg64 reg_ctx,
50 Xbyak::Reg64 reg_nthr);
60 // vim: et ts=4 sw=4 cindent cino^=l0,\:0,N-s