1 // Copyright (C) 2018-2019 Intel Corporation
2 // SPDX-License-Identifier: Apache-2.0
5 #include <ie_layouts.h>
7 #include <gtest/gtest.h>
11 #include "mock_allocator.hpp"
13 #include <cpp/ie_cnn_net_reader.h>
14 #include <gmock/gmock-spec-builders.h>
19 #define UNUSED __attribute__((unused))
22 using namespace ::testing;
24 using namespace InferenceEngine;
26 class TensorDescTests: public ::testing::Test {
28 virtual void TearDown() {
31 virtual void SetUp() {
38 TEST_F(TensorDescTests, CreateBlobWithIncorrectLayout) {
39 ASSERT_THROW(make_shared_blob<float>({ Precision::FP32, {1, 3, 32}, Layout::NC }), details::InferenceEngineException);
42 TEST_F(TensorDescTests, CreateBlockedBlobNCHW) {
43 TensorDesc desc(Precision::FP32, {1, 4, 2, 1}, {{1, 2, 2, 1, 2}, {0, 1, 2, 3, 1}});
44 float data[8] = {1, 2, 3, 4, 5, 6, 7, 8};
45 Blob::Ptr blockedBlob = make_shared_blob<float>(desc, data);
46 Blob::Ptr nchwBlob = make_shared_blob<float>({Precision::FP32, {1, 4, 2, 1}, Layout::NCHW}, data);
47 ASSERT_NE(blockedBlob->getTensorDesc().offset(5), nchwBlob->getTensorDesc().offset(5));
48 ASSERT_EQ(6, blockedBlob->getTensorDesc().offset(5));
49 ASSERT_EQ(5, nchwBlob->getTensorDesc().offset(5));
50 ASSERT_EQ(Layout::NCHW, nchwBlob->getTensorDesc().getLayout());
51 ASSERT_EQ(Layout::BLOCKED, blockedBlob->getTensorDesc().getLayout());
54 TEST_F(TensorDescTests, CreateBlockedBlobNCDHW) {
55 TensorDesc desc(Precision::FP32, {1, 4, 2, 2, 1}, {{1, 2, 2, 2, 1, 2}, {0, 1, 2, 3, 4, 1}});
56 float data[8] = {1, 2, 3, 4, 5, 6, 7, 8};
57 Blob::Ptr blockedBlob = make_shared_blob<float>(desc, data);
58 Blob::Ptr ncdhwBlob = make_shared_blob<float>({Precision::FP32, {1, 4, 2, 2, 1}, Layout::NCDHW}, data);
59 ASSERT_NE(blockedBlob->getTensorDesc().offset(6), ncdhwBlob->getTensorDesc().offset(6));
60 ASSERT_EQ(5, blockedBlob->getTensorDesc().offset(6));
61 ASSERT_EQ(6, ncdhwBlob->getTensorDesc().offset(6));
62 ASSERT_EQ(Layout::NCDHW, ncdhwBlob->getTensorDesc().getLayout());
63 ASSERT_EQ(Layout::BLOCKED, blockedBlob->getTensorDesc().getLayout());
66 TEST_F(TensorDescTests, CompareNHWCandNCHWLayouts) {
67 TensorDesc descNCHW(Precision::FP32, {1, 3, 4, 2}, Layout::NCHW);
68 TensorDesc descNHWC(Precision::FP32, {1, 3, 4, 2}, Layout::NHWC);
69 SizeVector nchw = {0, 1, 2, 3};
70 SizeVector nhwc = {0, 2, 3, 1};
72 ASSERT_NE(descNCHW, descNHWC);
73 ASSERT_NE(descNCHW.getBlockingDesc(), descNHWC.getBlockingDesc());
74 ASSERT_NE(descNCHW.getBlockingDesc().getOrder(), descNHWC.getBlockingDesc().getOrder());
75 ASSERT_EQ(descNCHW.getBlockingDesc().getOrder(), nchw);
76 ASSERT_EQ(descNHWC.getBlockingDesc().getOrder(), nhwc);
79 TEST_F(TensorDescTests, CompareNDHWCandNCDHWLayouts) {
80 TensorDesc descNCDHW(Precision::FP32, {1, 3, 4, 4, 2}, Layout::NCDHW);
81 TensorDesc descNDHWC(Precision::FP32, {1, 3, 4, 4, 2}, Layout::NDHWC);
82 SizeVector ncdhw = {0, 1, 2, 3, 4};
83 SizeVector ndhwc = {0, 2, 3, 4, 1};
85 ASSERT_NE(descNCDHW, descNDHWC);
86 ASSERT_NE(descNCDHW.getBlockingDesc(), descNDHWC.getBlockingDesc());
87 ASSERT_NE(descNCDHW.getBlockingDesc().getOrder(), descNDHWC.getBlockingDesc().getOrder());
88 ASSERT_EQ(descNCDHW.getBlockingDesc().getOrder(), ncdhw);
89 ASSERT_EQ(descNDHWC.getBlockingDesc().getOrder(), ndhwc);