inference-engine/tests/functional/inference_engine/ngraph_reader/reorg_yolo_tests.cpp

   1 // Copyright (C) 2018-2020 Intel Corporation
   2 // SPDX-License-Identifier: Apache-2.0
   3 //
   4
   5 #include <string>
   6 #include "ngraph_reader_tests.hpp"
   7
   8 TEST_F(NGraphReaderTests, ReadReorgYoloNetwork) {
   9     std::string model = R"V0G0N(
  10 <net name="frozen_graph" version="10">
  11         <layers>
  12                 <layer id="0" name="yolov2/yolov2_feature/lower_features/downsample/placeholder_port_0" type="Parameter" version="opset1">
  13                         <data shape="1,26,64,26" element_type="f32"/>
  14                         <output>
  15                                 <port id="0" precision="FP32">
  16                                         <dim>1</dim>
  17                                         <dim>26</dim>
  18                                         <dim>64</dim>
  19                                         <dim>26</dim>
  20                                 </port>
  21                         </output>
  22                 </layer>
  23                 <layer id="1" name="yolov2/yolov2_feature/lower_features/downsample" type="ReorgYolo" version="opset2">
  24                         <data stride="2"/>
  25                         <input>
  26                                 <port id="0">
  27                                         <dim>1</dim>
  28                                         <dim>26</dim>
  29                                         <dim>64</dim>
  30                                         <dim>26</dim>
  31                                 </port>
  32                         </input>
  33                         <output>
  34                                 <port id="1" precision="FP32">
  35                                         <dim>1</dim>
  36                                         <dim>104</dim>
  37                                         <dim>32</dim>
  38                                         <dim>13</dim>
  39                                 </port>
  40                         </output>
  41                 </layer>
  42                 <layer id="2" name="365" type="Result" version="opset1">
  43                         <input>
  44                                 <port id="0">
  45                                         <dim>1</dim>
  46                                         <dim>104</dim>
  47                                         <dim>32</dim>
  48                                         <dim>13</dim>
  49                                 </port>
  50                         </input>
  51                 </layer>
  52         </layers>
  53         <edges>
  54                 <edge from-layer="0" from-port="0" to-layer="1" to-port="0"/>
  55                 <edge from-layer="1" from-port="1" to-layer="2" to-port="0"/>
  56         </edges>
  57 </net>
  58 )V0G0N";
  59     std::string modelV7 = R"V0G0N(
  60 <net name="frozen_graph" version="7">
  61         <layers>
  62                 <layer id="0" name="yolov2/yolov2_feature/lower_features/downsample/placeholder_port_0" type="Input" version="opset1">
  63                         <output>
  64                                 <port id="0" precision="FP32">
  65                                         <dim>1</dim>
  66                                         <dim>26</dim>
  67                                         <dim>64</dim>
  68                                         <dim>26</dim>
  69                                 </port>
  70                         </output>
  71                 </layer>
  72                 <layer id="1" name="yolov2/yolov2_feature/lower_features/downsample" type="ReorgYolo" version="opset2">
  73                         <data stride="2"/>
  74                         <input>
  75                                 <port id="0">
  76                                         <dim>1</dim>
  77                                         <dim>26</dim>
  78                                         <dim>64</dim>
  79                                         <dim>26</dim>
  80                                 </port>
  81                         </input>
  82                         <output>
  83                                 <port id="1" precision="FP32">
  84                                         <dim>1</dim>
  85                                         <dim>104</dim>
  86                                         <dim>32</dim>
  87                                         <dim>13</dim>
  88                                 </port>
  89                         </output>
  90                 </layer>
  91         </layers>
  92         <edges>
  93                 <edge from-layer="0" from-port="0" to-layer="1" to-port="0"/>
  94         </edges>
  95 </net>
  96 )V0G0N";
  97     compareIRs(model, modelV7);
  98 }