1 // Copyright (C) 2018-2019 Intel Corporation
2 // SPDX-License-Identifier: Apache-2.0
10 #define SIGMOID_NUM_SEGMENTS 65
11 #define SIGMOID_DOMAIN 10.0f // portion of input to be approximated (-10,10)
12 #define TANH_NUM_SEGMENTS 65
13 #define TANH_DOMAIN 5.0f // portion of input to be approximated (-5,5)
14 #define RELU_NUM_SEGMENTS 2
15 #define LEAKYRELU_SLOPE 0.01
16 #define IDENTITY_NUM_SEGMENTS 3
17 #define IDENTITY_DOMAIN 10.0f
18 #define PWL_MAX_ERR_PERCENT 1.0f
19 #define PWL_MAX_ITERATIONS 2000
20 #define PWL_MAX_NUM_SEGMENTS 128
21 #define PWL_DESIGN_THRESHOLD 0.1f
22 #define PWL_DESIGN_SAMPLES 500
23 #define ACTIVATION_SCALE_FACTOR 2048.0f
24 #define IDENTITY_SCALE_FACTOR 2049.0f
25 #define XBASEMASK 0xFFFFFFFC // only top 30 bits are used
26 #define KALDI_LSTM_CLIP_LOWER (-50.0)
27 #define KALDI_LSTM_CLIP_UPPER (50.0)
39 uint64_t slope_scale = 0;
40 uint32_t slope_scale_index;
41 } pwl_gna_slope_scale_t;
43 double first_deriv_tanh(const double x);
44 double sigmoid(const double x);
45 double first_deriv_sigmoid(const double x);
46 double relu(const double x);
47 double leaky_relu(const double x);
49 double clipping(const double x, const double lbound, const double ubound);
50 void PwlApply16(intel_dnn_component_t *component, const uint32_t num_subset_size);
51 void PwlApply16(intel_dnn_component_t *component,
52 const uint32_t num_row_start,
53 const uint32_t num_row_end,
54 const uint32_t num_col_start,
55 const uint32_t num_col_end);
56 void PwlApply32(intel_dnn_component_t *component, const uint32_t num_subset_size);
57 void PwlApply32(intel_dnn_component_t *component,
58 const uint32_t num_row_start,
59 const uint32_t num_row_end,
60 const uint32_t num_col_start,
61 const uint32_t num_col_end);
62 void PwlDesign16(const DnnActivation activation_type,
63 intel_pwl_segment_t *ptr_segment,
64 const uint32_t num_segments,
66 const float scale_out);
67 void PwlDesignOpt16(const DnnActivation activation_type,
68 std::vector<intel_pwl_segment_t> &ptr_segment,
70 const float scale_out);