1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2012-2013, Xilinx, Michal Simek
6 * Joe Hershberger <joe.hershberger@ni.com>
14 extern struct xilinx_fpga_op zynq_op;
16 #define XILINX_ZYNQ_XC7Z007S 0x3
17 #define XILINX_ZYNQ_XC7Z010 0x2
18 #define XILINX_ZYNQ_XC7Z012S 0x1c
19 #define XILINX_ZYNQ_XC7Z014S 0x8
20 #define XILINX_ZYNQ_XC7Z015 0x1b
21 #define XILINX_ZYNQ_XC7Z020 0x7
22 #define XILINX_ZYNQ_XC7Z030 0xc
23 #define XILINX_ZYNQ_XC7Z035 0x12
24 #define XILINX_ZYNQ_XC7Z045 0x11
25 #define XILINX_ZYNQ_XC7Z100 0x16
27 /* Device Image Sizes */
28 #define XILINX_XC7Z007S_SIZE 16669920/8
29 #define XILINX_XC7Z010_SIZE 16669920/8
30 #define XILINX_XC7Z012S_SIZE 28085344/8
31 #define XILINX_XC7Z014S_SIZE 32364512/8
32 #define XILINX_XC7Z015_SIZE 28085344/8
33 #define XILINX_XC7Z020_SIZE 32364512/8
34 #define XILINX_XC7Z030_SIZE 47839328/8
35 #define XILINX_XC7Z035_SIZE 106571232/8
36 #define XILINX_XC7Z045_SIZE 106571232/8
37 #define XILINX_XC7Z100_SIZE 139330784/8
40 #define XILINX_XC7Z007S_NAME "7z007s"
41 #define XILINX_XC7Z010_NAME "7z010"
42 #define XILINX_XC7Z012S_NAME "7z012s"
43 #define XILINX_XC7Z014S_NAME "7z014s"
44 #define XILINX_XC7Z015_NAME "7z015"
45 #define XILINX_XC7Z020_NAME "7z020"
46 #define XILINX_XC7Z030_NAME "7z030"
47 #define XILINX_XC7Z035_NAME "7z035"
48 #define XILINX_XC7Z045_NAME "7z045"
49 #define XILINX_XC7Z100_NAME "7z100"
51 #if defined(CONFIG_FPGA)
52 #define ZYNQ_DESC(name) { \
53 .idcode = XILINX_ZYNQ_XC##name, \
54 .fpga_size = XILINX_XC##name##_SIZE, \
55 .devicename = XILINX_XC##name##_NAME \
58 #define ZYNQ_DESC(name) { \
59 .idcode = XILINX_ZYNQ_XC##name, \
60 .devicename = XILINX_XC##name##_NAME \
64 #endif /* _ZYNQPL_H_ */