1 /* SPDX-License-Identifier: GPL-2.0 */
3 * (C) Copyright 2015 Xilinx, Inc,
4 * Michal Simek <michal.simek@xilinx.com>
11 #include <linux/bitops.h>
13 #define ZYNQMP_FPGA_OP_INIT (1 << 0)
14 #define ZYNQMP_FPGA_OP_LOAD (1 << 1)
15 #define ZYNQMP_FPGA_OP_DONE (1 << 2)
17 #define ZYNQMP_FPGA_FLAG_AUTHENTICATED BIT(2)
18 #define ZYNQMP_FPGA_FLAG_ENCRYPTED BIT(3)
20 #define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT 15
21 #define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK (0xf << \
22 ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT)
23 #define ZYNQMP_CSU_IDCODE_SVD_SHIFT 12
24 #define ZYNQMP_CSU_IDCODE_SVD_MASK (0x7 << ZYNQMP_CSU_IDCODE_SVD_SHIFT)
26 extern struct xilinx_fpga_op zynqmp_op;
28 #define XILINX_ZYNQMP_DESC \
29 { xilinx_zynqmp, csu_dma, 1, &zynqmp_op, 0, &zynqmp_op }
31 #endif /* _ZYNQMPPL_H_ */