include/zynqmp_firmware.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Xilinx Zynq MPSoC Firmware driver
   4  *
   5  * Copyright (C) 2018-2019 Xilinx, Inc.
   6  */
   7
   8 #ifndef _ZYNQMP_FIRMWARE_H_
   9 #define _ZYNQMP_FIRMWARE_H_
  10
  11 enum pm_api_id {
  12         PM_GET_API_VERSION = 1,
  13         PM_SET_CONFIGURATION = 2,
  14         PM_GET_NODE_STATUS = 3,
  15         PM_GET_OPERATING_CHARACTERISTIC = 4,
  16         PM_REGISTER_NOTIFIER = 5,
  17         /* API for suspending */
  18         PM_REQUEST_SUSPEND = 6,
  19         PM_SELF_SUSPEND = 7,
  20         PM_FORCE_POWERDOWN = 8,
  21         PM_ABORT_SUSPEND = 9,
  22         PM_REQUEST_WAKEUP = 10,
  23         PM_SET_WAKEUP_SOURCE = 11,
  24         PM_SYSTEM_SHUTDOWN = 12,
  25         PM_REQUEST_NODE = 13,
  26         PM_RELEASE_NODE = 14,
  27         PM_SET_REQUIREMENT = 15,
  28         PM_SET_MAX_LATENCY = 16,
  29         /* Direct control API functions: */
  30         PM_RESET_ASSERT = 17,
  31         PM_RESET_GET_STATUS = 18,
  32         PM_MMIO_WRITE = 19,
  33         PM_MMIO_READ = 20,
  34         PM_PM_INIT_FINALIZE = 21,
  35         PM_FPGA_LOAD = 22,
  36         PM_FPGA_GET_STATUS = 23,
  37         PM_GET_CHIPID = 24,
  38         /* ID 25 is been used by U-boot to process secure boot images */
  39         /* Secure library generic API functions */
  40         PM_SECURE_SHA = 26,
  41         PM_SECURE_RSA = 27,
  42         PM_PINCTRL_REQUEST = 28,
  43         PM_PINCTRL_RELEASE = 29,
  44         PM_PINCTRL_GET_FUNCTION = 30,
  45         PM_PINCTRL_SET_FUNCTION = 31,
  46         PM_PINCTRL_CONFIG_PARAM_GET = 32,
  47         PM_PINCTRL_CONFIG_PARAM_SET = 33,
  48         PM_IOCTL = 34,
  49         PM_QUERY_DATA = 35,
  50         PM_CLOCK_ENABLE = 36,
  51         PM_CLOCK_DISABLE = 37,
  52         PM_CLOCK_GETSTATE = 38,
  53         PM_CLOCK_SETDIVIDER = 39,
  54         PM_CLOCK_GETDIVIDER = 40,
  55         PM_CLOCK_SETRATE = 41,
  56         PM_CLOCK_GETRATE = 42,
  57         PM_CLOCK_SETPARENT = 43,
  58         PM_CLOCK_GETPARENT = 44,
  59         PM_SECURE_IMAGE = 45,
  60         PM_FPGA_READ = 46,
  61         PM_SECURE_AES = 47,
  62         PM_CLOCK_PLL_GETPARAM = 49,
  63         /* PM_REGISTER_ACCESS API */
  64         PM_REGISTER_ACCESS = 52,
  65         PM_EFUSE_ACCESS = 53,
  66         PM_FEATURE_CHECK = 63,
  67         PM_API_MAX,
  68 };
  69
  70 enum pm_query_id {
  71         PM_QID_INVALID = 0,
  72         PM_QID_CLOCK_GET_NAME = 1,
  73         PM_QID_CLOCK_GET_TOPOLOGY = 2,
  74         PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS = 3,
  75         PM_QID_CLOCK_GET_PARENTS = 4,
  76         PM_QID_CLOCK_GET_ATTRIBUTES = 5,
  77         PM_QID_PINCTRL_GET_NUM_PINS = 6,
  78         PM_QID_PINCTRL_GET_NUM_FUNCTIONS = 7,
  79         PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS = 8,
  80         PM_QID_PINCTRL_GET_FUNCTION_NAME = 9,
  81         PM_QID_PINCTRL_GET_FUNCTION_GROUPS = 10,
  82         PM_QID_PINCTRL_GET_PIN_GROUPS = 11,
  83         PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
  84         PM_QID_CLOCK_GET_MAX_DIVISOR = 13,
  85 };
  86
  87 enum zynqmp_pm_reset_action {
  88         PM_RESET_ACTION_RELEASE = 0,
  89         PM_RESET_ACTION_ASSERT = 1,
  90         PM_RESET_ACTION_PULSE = 2,
  91 };
  92
  93 enum zynqmp_pm_reset {
  94         ZYNQMP_PM_RESET_START = 1000,
  95         ZYNQMP_PM_RESET_PCIE_CFG = ZYNQMP_PM_RESET_START,
  96         ZYNQMP_PM_RESET_PCIE_BRIDGE = 1001,
  97         ZYNQMP_PM_RESET_PCIE_CTRL = 1002,
  98         ZYNQMP_PM_RESET_DP = 1003,
  99         ZYNQMP_PM_RESET_SWDT_CRF = 1004,
 100         ZYNQMP_PM_RESET_AFI_FM5 = 1005,
 101         ZYNQMP_PM_RESET_AFI_FM4 = 1006,
 102         ZYNQMP_PM_RESET_AFI_FM3 = 1007,
 103         ZYNQMP_PM_RESET_AFI_FM2 = 1008,
 104         ZYNQMP_PM_RESET_AFI_FM1 = 1009,
 105         ZYNQMP_PM_RESET_AFI_FM0 = 1010,
 106         ZYNQMP_PM_RESET_GDMA = 1011,
 107         ZYNQMP_PM_RESET_GPU_PP1 = 1012,
 108         ZYNQMP_PM_RESET_GPU_PP0 = 1013,
 109         ZYNQMP_PM_RESET_GPU = 1014,
 110         ZYNQMP_PM_RESET_GT = 1015,
 111         ZYNQMP_PM_RESET_SATA = 1016,
 112         ZYNQMP_PM_RESET_ACPU3_PWRON = 1017,
 113         ZYNQMP_PM_RESET_ACPU2_PWRON = 1018,
 114         ZYNQMP_PM_RESET_ACPU1_PWRON = 1019,
 115         ZYNQMP_PM_RESET_ACPU0_PWRON = 1020,
 116         ZYNQMP_PM_RESET_APU_L2 = 1021,
 117         ZYNQMP_PM_RESET_ACPU3 = 1022,
 118         ZYNQMP_PM_RESET_ACPU2 = 1023,
 119         ZYNQMP_PM_RESET_ACPU1 = 1024,
 120         ZYNQMP_PM_RESET_ACPU0 = 1025,
 121         ZYNQMP_PM_RESET_DDR = 1026,
 122         ZYNQMP_PM_RESET_APM_FPD = 1027,
 123         ZYNQMP_PM_RESET_SOFT = 1028,
 124         ZYNQMP_PM_RESET_GEM0 = 1029,
 125         ZYNQMP_PM_RESET_GEM1 = 1030,
 126         ZYNQMP_PM_RESET_GEM2 = 1031,
 127         ZYNQMP_PM_RESET_GEM3 = 1032,
 128         ZYNQMP_PM_RESET_QSPI = 1033,
 129         ZYNQMP_PM_RESET_UART0 = 1034,
 130         ZYNQMP_PM_RESET_UART1 = 1035,
 131         ZYNQMP_PM_RESET_SPI0 = 1036,
 132         ZYNQMP_PM_RESET_SPI1 = 1037,
 133         ZYNQMP_PM_RESET_SDIO0 = 1038,
 134         ZYNQMP_PM_RESET_SDIO1 = 1039,
 135         ZYNQMP_PM_RESET_CAN0 = 1040,
 136         ZYNQMP_PM_RESET_CAN1 = 1041,
 137         ZYNQMP_PM_RESET_I2C0 = 1042,
 138         ZYNQMP_PM_RESET_I2C1 = 1043,
 139         ZYNQMP_PM_RESET_TTC0 = 1044,
 140         ZYNQMP_PM_RESET_TTC1 = 1045,
 141         ZYNQMP_PM_RESET_TTC2 = 1046,
 142         ZYNQMP_PM_RESET_TTC3 = 1047,
 143         ZYNQMP_PM_RESET_SWDT_CRL = 1048,
 144         ZYNQMP_PM_RESET_NAND = 1049,
 145         ZYNQMP_PM_RESET_ADMA = 1050,
 146         ZYNQMP_PM_RESET_GPIO = 1051,
 147         ZYNQMP_PM_RESET_IOU_CC = 1052,
 148         ZYNQMP_PM_RESET_TIMESTAMP = 1053,
 149         ZYNQMP_PM_RESET_RPU_R50 = 1054,
 150         ZYNQMP_PM_RESET_RPU_R51 = 1055,
 151         ZYNQMP_PM_RESET_RPU_AMBA = 1056,
 152         ZYNQMP_PM_RESET_OCM = 1057,
 153         ZYNQMP_PM_RESET_RPU_PGE = 1058,
 154         ZYNQMP_PM_RESET_USB0_CORERESET = 1059,
 155         ZYNQMP_PM_RESET_USB1_CORERESET = 1060,
 156         ZYNQMP_PM_RESET_USB0_HIBERRESET = 1061,
 157         ZYNQMP_PM_RESET_USB1_HIBERRESET = 1062,
 158         ZYNQMP_PM_RESET_USB0_APB = 1063,
 159         ZYNQMP_PM_RESET_USB1_APB = 1064,
 160         ZYNQMP_PM_RESET_IPI = 1065,
 161         ZYNQMP_PM_RESET_APM_LPD = 1066,
 162         ZYNQMP_PM_RESET_RTC = 1067,
 163         ZYNQMP_PM_RESET_SYSMON = 1068,
 164         ZYNQMP_PM_RESET_AFI_FM6 = 1069,
 165         ZYNQMP_PM_RESET_LPD_SWDT = 1070,
 166         ZYNQMP_PM_RESET_FPD = 1071,
 167         ZYNQMP_PM_RESET_RPU_DBG1 = 1072,
 168         ZYNQMP_PM_RESET_RPU_DBG0 = 1073,
 169         ZYNQMP_PM_RESET_DBG_LPD = 1074,
 170         ZYNQMP_PM_RESET_DBG_FPD = 1075,
 171         ZYNQMP_PM_RESET_APLL = 1076,
 172         ZYNQMP_PM_RESET_DPLL = 1077,
 173         ZYNQMP_PM_RESET_VPLL = 1078,
 174         ZYNQMP_PM_RESET_IOPLL = 1079,
 175         ZYNQMP_PM_RESET_RPLL = 1080,
 176         ZYNQMP_PM_RESET_GPO3_PL_0 = 1081,
 177         ZYNQMP_PM_RESET_GPO3_PL_1 = 1082,
 178         ZYNQMP_PM_RESET_GPO3_PL_2 = 1083,
 179         ZYNQMP_PM_RESET_GPO3_PL_3 = 1084,
 180         ZYNQMP_PM_RESET_GPO3_PL_4 = 1085,
 181         ZYNQMP_PM_RESET_GPO3_PL_5 = 1086,
 182         ZYNQMP_PM_RESET_GPO3_PL_6 = 1087,
 183         ZYNQMP_PM_RESET_GPO3_PL_7 = 1088,
 184         ZYNQMP_PM_RESET_GPO3_PL_8 = 1089,
 185         ZYNQMP_PM_RESET_GPO3_PL_9 = 1090,
 186         ZYNQMP_PM_RESET_GPO3_PL_10 = 1091,
 187         ZYNQMP_PM_RESET_GPO3_PL_11 = 1092,
 188         ZYNQMP_PM_RESET_GPO3_PL_12 = 1093,
 189         ZYNQMP_PM_RESET_GPO3_PL_13 = 1094,
 190         ZYNQMP_PM_RESET_GPO3_PL_14 = 1095,
 191         ZYNQMP_PM_RESET_GPO3_PL_15 = 1096,
 192         ZYNQMP_PM_RESET_GPO3_PL_16 = 1097,
 193         ZYNQMP_PM_RESET_GPO3_PL_17 = 1098,
 194         ZYNQMP_PM_RESET_GPO3_PL_18 = 1099,
 195         ZYNQMP_PM_RESET_GPO3_PL_19 = 1100,
 196         ZYNQMP_PM_RESET_GPO3_PL_20 = 1101,
 197         ZYNQMP_PM_RESET_GPO3_PL_21 = 1102,
 198         ZYNQMP_PM_RESET_GPO3_PL_22 = 1103,
 199         ZYNQMP_PM_RESET_GPO3_PL_23 = 1104,
 200         ZYNQMP_PM_RESET_GPO3_PL_24 = 1105,
 201         ZYNQMP_PM_RESET_GPO3_PL_25 = 1106,
 202         ZYNQMP_PM_RESET_GPO3_PL_26 = 1107,
 203         ZYNQMP_PM_RESET_GPO3_PL_27 = 1108,
 204         ZYNQMP_PM_RESET_GPO3_PL_28 = 1109,
 205         ZYNQMP_PM_RESET_GPO3_PL_29 = 1110,
 206         ZYNQMP_PM_RESET_GPO3_PL_30 = 1111,
 207         ZYNQMP_PM_RESET_GPO3_PL_31 = 1112,
 208         ZYNQMP_PM_RESET_RPU_LS = 1113,
 209         ZYNQMP_PM_RESET_PS_ONLY = 1114,
 210         ZYNQMP_PM_RESET_PL = 1115,
 211         ZYNQMP_PM_RESET_PS_PL0 = 1116,
 212         ZYNQMP_PM_RESET_PS_PL1 = 1117,
 213         ZYNQMP_PM_RESET_PS_PL2 = 1118,
 214         ZYNQMP_PM_RESET_PS_PL3 = 1119,
 215         ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3
 216 };
 217
 218 #define PM_SIP_SVC      0xc2000000
 219
 220 #define ZYNQMP_PM_VERSION_MAJOR         1
 221 #define ZYNQMP_PM_VERSION_MINOR         0
 222 #define ZYNQMP_PM_VERSION_MAJOR_SHIFT   16
 223 #define ZYNQMP_PM_VERSION_MINOR_MASK    0xFFFF
 224
 225 #define ZYNQMP_PM_VERSION       \
 226         ((ZYNQMP_PM_VERSION_MAJOR << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | \
 227          ZYNQMP_PM_VERSION_MINOR)
 228
 229 #define ZYNQMP_PM_VERSION_INVALID       ~0
 230
 231 #define PMUFW_V1_0      ((1 << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | 0)
 232
 233 /*
 234  * Return payload size
 235  * Not every firmware call expects the same amount of return bytes, however the
 236  * firmware driver always copies 5 bytes from RX buffer to the ret_payload
 237  * buffer. Therefore allocating with this defined value is recommended to avoid
 238  * overflows.
 239  */
 240 #define PAYLOAD_ARG_CNT 5U
 241
 242 unsigned int zynqmp_firmware_version(void);
 243 void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size);
 244 int xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
 245                       u32 arg3, u32 *ret_payload);
 246
 247 #endif /* _ZYNQMP_FIRMWARE_H_ */