4 * Driver for the Vitesse VSC9953 L2 Switch
6 * This software may be used and distributed according to the
7 * terms of the GNU Public License, Version 2, incorporated
10 * Copyright 2013 Freescale Semiconductor, Inc.
19 #include <asm/types.h>
21 #define VSC9953_OFFSET (CONFIG_SYS_CCSRBAR_DEFAULT + 0x800000)
23 #define VSC9953_SYS_OFFSET 0x010000
24 #define VSC9953_REW_OFFSET 0x030000
25 #define VSC9953_DEV_GMII_OFFSET 0x100000
26 #define VSC9953_QSYS_OFFSET 0x200000
27 #define VSC9953_ANA_OFFSET 0x280000
28 #define VSC9953_DEVCPU_GCB 0x070000
29 #define VSC9953_ES0 0x040000
30 #define VSC9953_IS1 0x050000
31 #define VSC9953_IS2 0x060000
33 #define T1040_SWITCH_GMII_DEV_OFFSET 0x010000
34 #define VSC9953_PHY_REGS_OFFST 0x0000AC
36 /* Macros for vsc9953_chip_regs.soft_rst register */
37 #define VSC9953_SOFT_SWC_RST_ENA 0x00000001
39 /* Macros for vsc9953_sys_sys.reset_cfg register */
40 #define VSC9953_CORE_ENABLE 0x80
41 #define VSC9953_MEM_ENABLE 0x40
42 #define VSC9953_MEM_INIT 0x20
44 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ena_cfg register */
45 #define VSC9953_MAC_ENA_CFG 0x00000011
47 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_mode_cfg register */
48 #define VSC9953_MAC_MODE_CFG 0x00000011
50 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ifg_cfg register */
51 #define VSC9953_MAC_IFG_CFG 0x00000515
53 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_hdx_cfg register */
54 #define VSC9953_MAC_HDX_CFG 0x00001043
56 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_maxlen_cfg register */
57 #define VSC9953_MAC_MAX_LEN 0x000005ee
59 /* Macros for vsc9953_dev_gmii_port_mode.clock_cfg register */
60 #define VSC9953_CLOCK_CFG 0x00000001
61 #define VSC9953_CLOCK_CFG_1000M 0x00000001
63 /* Macros for vsc9953_sys_sys.front_port_mode register */
64 #define VSC9953_FRONT_PORT_MODE 0x00000000
66 /* Macros for vsc9953_ana_pfc.pfc_cfg register */
67 #define VSC9953_PFC_FC 0x00000001
68 #define VSC9953_PFC_FC_QSGMII 0x00000000
70 /* Macros for vsc9953_sys_pause_cfg.mac_fc_cfg register */
71 #define VSC9953_MAC_FC_CFG 0x04700000
72 #define VSC9953_MAC_FC_CFG_QSGMII 0x00700000
74 /* Macros for vsc9953_sys_pause_cfg.pause_cfg register */
75 #define VSC9953_PAUSE_CFG 0x001ffffe
77 /* Macros for vsc9953_sys_pause_cfgtot_tail_drop_lvl register */
78 #define VSC9953_TOT_TAIL_DROP_LVL 0x000003ff
80 /* Macros for vsc9953_sys_sys.stat_cfg register */
81 #define VSC9953_STAT_CLEAR_RX 0x00000400
82 #define VSC9953_STAT_CLEAR_TX 0x00000800
83 #define VSC9953_STAT_CLEAR_DR 0x00001000
85 /* Macros for vsc9953_vcap_core_cfg.vcap_mv_cfg register */
86 #define VSC9953_VCAP_MV_CFG 0x0000ffff
87 #define VSC9953_VCAP_UPDATE_CTRL 0x01000004
89 /* Macros for vsc9953_ana_port.vlan_cfg register */
90 #define VSC9953_VLAN_CFG_AWARE_ENA 0x00100000
91 #define VSC9953_VLAN_CFG_POP_CNT_MASK 0x000c0000
92 #define VSC9953_VLAN_CFG_VID_MASK 0x00000fff
94 /* Macros for vsc9953_rew_port.port_vlan_cfg register */
95 #define VSC9953_PORT_VLAN_CFG_VID_MASK 0x00000fff
97 /* Macros for vsc9953_ana_ana_tables.vlan_tidx register */
98 #define VSC9953_ANA_TBL_VID_MASK 0x00000fff
100 /* Macros for vsc9953_ana_ana_tables.vlan_access register */
101 #define VSC9953_VLAN_PORT_MASK 0x00001ffc
102 #define VSC9953_VLAN_CMD_MASK 0x00000003
103 #define VSC9953_VLAN_CMD_IDLE 0x00000000
104 #define VSC9953_VLAN_CMD_READ 0x00000001
105 #define VSC9953_VLAN_CMD_WRITE 0x00000002
106 #define VSC9953_VLAN_CMD_INIT 0x00000003
108 /* Macros for vsc9953_ana_port.port_cfg register */
109 #define VSC9953_PORT_CFG_LEARN_ENA 0x00000080
110 #define VSC9953_PORT_CFG_LEARN_AUTO 0x00000100
111 #define VSC9953_PORT_CFG_LEARN_CPU 0x00000200
112 #define VSC9953_PORT_CFG_LEARN_DROP 0x00000400
114 /* Macros for vsc9953_qsys_sys.switch_port_mode register */
115 #define VSC9953_PORT_ENA 0x00002000
117 /* Macros for vsc9953_ana_ana.adv_learn register */
118 #define VSC9953_VLAN_CHK 0x00000400
120 /* Macros for vsc9953_rew_port.port_tag_cfg register */
121 #define VSC9953_TAG_CFG_MASK 0x00000180
122 #define VSC9953_TAG_CFG_NONE 0x00000000
123 #define VSC9953_TAG_CFG_ALL_BUT_PVID_ZERO 0x00000080
124 #define VSC9953_TAG_CFG_ALL_BUT_ZERO 0x00000100
125 #define VSC9953_TAG_CFG_ALL 0x00000180
127 #define VSC9953_MAX_PORTS 10
128 #define VSC9953_PORT_CHECK(port) \
129 (((port) < 0 || (port) >= VSC9953_MAX_PORTS) ? 0 : 1)
130 #define VSC9953_INTERNAL_PORT_CHECK(port) ( \
132 (port) < VSC9953_MAX_PORTS - 2 || (port) >= VSC9953_MAX_PORTS \
135 #define VSC9953_MAX_VLAN 4096
136 #define VSC9953_VLAN_CHECK(vid) \
137 (((vid) < 0 || (vid) >= VSC9953_MAX_VLAN) ? 0 : 1)
139 #define DEFAULT_VSC9953_MDIO_NAME "VSC9953_MDIO0"
141 #define MIIMIND_OPR_PEND 0x00000004
143 struct vsc9953_mdio_info {
144 struct vsc9953_mii_mng *regs;
148 /* VSC9953 ANA structure */
150 struct vsc9953_ana_port {
155 u32 vcap_s1_key_cfg[3];
157 u32 qos_pcp_dei_map_cfg[16];
159 u32 cpu_fwd_bpdu_cfg;
160 u32 cpu_fwd_garp_cfg;
167 struct vsc9953_ana_pol {
176 struct vsc9953_ana_ana_tables {
187 struct vsc9953_ana_ana {
193 u32 storm_limit_burst;
194 u32 storm_limit_cfg[4];
209 struct vsc9953_ana_pgid {
213 struct vsc9953_ana_pfc {
218 struct vsc9953_ana_pol_misc {
224 struct vsc9953_ana_common {
230 u32 vcap_rng_type_cfg;
231 u32 vcap_rng_val_cfg;
236 struct vsc9953_analyzer {
237 struct vsc9953_ana_port port[11];
239 struct vsc9953_ana_pol pol[164];
240 struct vsc9953_ana_ana_tables ana_tables;
242 struct vsc9953_ana_ana ana;
244 struct vsc9953_ana_pgid port_id_tbl;
246 struct vsc9953_ana_pfc pfc[10];
247 struct vsc9953_ana_pol_misc pol_misc;
249 struct vsc9953_ana_common common;
251 /* END VSC9953 ANA structure t*/
253 /* VSC9953 DEV_GMII structure */
255 struct vsc9953_dev_gmii_port_mode {
262 struct vsc9953_dev_gmii_mac_cfg_status {
270 u32 mac_fc_mac_low_cfg;
271 u32 mac_fc_mac_high_cfg;
275 struct vsc9953_dev_gmii {
276 struct vsc9953_dev_gmii_port_mode port_mode;
277 struct vsc9953_dev_gmii_mac_cfg_status mac_cfg_status;
280 /* END VSC9953 DEV_GMII structure */
282 /* VSC9953 QSYS structure */
284 struct vsc9953_qsys_hsch {
293 struct vsc9953_qsys_sys {
295 u32 switch_port_mode[11];
307 struct vsc9953_qsys_qos_cfg {
312 struct vsc9953_qsys_drop_cfg {
316 struct vsc9953_qsys_mmgt {
321 struct vsc9953_qsys_hsch_misc {
326 struct vsc9953_qsys_res_ctrl {
332 struct vsc9953_qsys_reg {
333 struct vsc9953_qsys_hsch hsch[108];
334 struct vsc9953_qsys_sys sys;
335 struct vsc9953_qsys_qos_cfg qos_cfg;
336 struct vsc9953_qsys_drop_cfg drop_cfg;
337 struct vsc9953_qsys_mmgt mmgt;
338 struct vsc9953_qsys_hsch_misc hsch_misc;
339 struct vsc9953_qsys_res_ctrl res_ctrl[1024];
342 /* END VSC9953 QSYS structure */
344 /* VSC9953 SYS structure */
346 struct vsc9953_rx_cntrs {
360 u32 c_rx_sz_512_1023;
361 u32 c_rx_sz_1024_1526;
375 u32 c_rx_yellow_prio_0;
376 u32 c_rx_yellow_prio_1;
377 u32 c_rx_yellow_prio_2;
378 u32 c_rx_yellow_prio_3;
379 u32 c_rx_yellow_prio_4;
380 u32 c_rx_yellow_prio_5;
381 u32 c_rx_yellow_prio_6;
382 u32 c_rx_yellow_prio_7;
383 u32 c_rx_green_prio_0;
384 u32 c_rx_green_prio_1;
385 u32 c_rx_green_prio_2;
386 u32 c_rx_green_prio_3;
387 u32 c_rx_green_prio_4;
388 u32 c_rx_green_prio_5;
389 u32 c_rx_green_prio_6;
390 u32 c_rx_green_prio_7;
394 struct vsc9953_tx_cntrs {
406 u32 c_tx_sz_512_1023;
407 u32 c_tx_sz_1024_1526;
409 u32 c_tx_yellow_prio_0;
410 u32 c_tx_yellow_prio_1;
411 u32 c_tx_yellow_prio_2;
412 u32 c_tx_yellow_prio_3;
413 u32 c_tx_yellow_prio_4;
414 u32 c_tx_yellow_prio_5;
415 u32 c_tx_yellow_prio_6;
416 u32 c_tx_yellow_prio_7;
417 u32 c_tx_green_prio_0;
418 u32 c_tx_green_prio_1;
419 u32 c_tx_green_prio_2;
420 u32 c_tx_green_prio_3;
421 u32 c_tx_green_prio_4;
422 u32 c_tx_green_prio_5;
423 u32 c_tx_green_prio_6;
424 u32 c_tx_green_prio_7;
429 struct vsc9953_drop_cntrs {
432 u32 c_dr_yellow_prio_0;
433 u32 c_dr_yellow_prio_1;
434 u32 c_dr_yellow_prio_2;
435 u32 c_dr_yellow_prio_3;
436 u32 c_dr_yellow_prio_4;
437 u32 c_dr_yellow_prio_5;
438 u32 c_dr_yellow_prio_6;
439 u32 c_dr_yellow_prio_7;
440 u32 c_dr_green_prio_0;
441 u32 c_dr_green_prio_1;
442 u32 c_dr_green_prio_2;
443 u32 c_dr_green_prio_3;
444 u32 c_dr_green_prio_4;
445 u32 c_dr_green_prio_5;
446 u32 c_dr_green_prio_6;
447 u32 c_dr_green_prio_7;
451 struct vsc9953_sys_stat {
452 struct vsc9953_rx_cntrs rx_cntrs;
453 struct vsc9953_tx_cntrs tx_cntrs;
454 struct vsc9953_drop_cntrs drop_cntrs;
458 struct vsc9953_sys_sys {
463 u32 front_port_mode[10];
469 struct vsc9953_sys_pause_cfg {
472 u32 tail_drop_level[11];
473 u32 tot_tail_drop_lvl;
477 struct vsc9953_sys_mmgt {
481 struct vsc9953_system_reg {
482 struct vsc9953_sys_stat stat;
483 struct vsc9953_sys_sys sys;
484 struct vsc9953_sys_pause_cfg pause_cfg;
485 struct vsc9953_sys_mmgt mmgt;
488 /* END VSC9953 SYS structure */
490 /* VSC9953 REW structure */
492 struct vsc9953_rew_port {
497 u32 port_pcp_dei_qos_map_cfg[16];
501 struct vsc9953_rew_common {
503 u32 dscp_remap_dp1_cfg[64];
504 u32 dscp_remap_cfg[64];
507 struct vsc9953_rew_reg {
508 struct vsc9953_rew_port port[12];
509 struct vsc9953_rew_common common;
512 /* END VSC9953 REW structure */
514 /* VSC9953 DEVCPU_GCB structure */
516 struct vsc9953_chip_regs {
522 struct vsc9953_gpio {
523 u32 gpio_out_set[10];
524 u32 gpio_out_clr[10];
529 struct vsc9953_mii_mng {
537 u32 miiscan_lst_rslts;
538 u32 miiscan_lst_rslts_valid;
541 struct vsc9953_mii_read_scan {
542 u32 mii_scan_results_sticky[2];
545 struct vsc9953_devcpu_gcb {
546 struct vsc9953_chip_regs chip_regs;
547 struct vsc9953_gpio gpio;
548 struct vsc9953_mii_mng mii_mng[2];
549 struct vsc9953_mii_read_scan mii_read_scan;
552 /* END VSC9953 DEVCPU_GCB structure */
554 /* VSC9953 IS* structure */
556 struct vsc9953_vcap_core_cfg {
557 u32 vcap_update_ctrl;
561 struct vsc9953_vcap {
562 struct vsc9953_vcap_core_cfg vcap_core_cfg;
565 /* END VSC9953 IS* structure */
567 #define VSC9953_PORT_INFO_INITIALIZER(idx) \
573 .enet_if = PHY_INTERFACE_MODE_NONE, \
578 /* Structure to describe a VSC9953 port */
579 struct vsc9953_port_info {
584 phy_interface_t enet_if;
586 struct phy_device *phydev;
589 /* Structure to describe a VSC9953 switch */
590 struct vsc9953_info {
591 struct vsc9953_port_info port[VSC9953_MAX_PORTS];
594 void vsc9953_init(bd_t *bis);
596 void vsc9953_port_info_set_mdio(int port_no, struct mii_dev *bus);
597 void vsc9953_port_info_set_phy_address(int port_no, int address);
598 void vsc9953_port_enable(int port_no);
599 void vsc9953_port_disable(int port_no);
600 void vsc9953_port_info_set_phy_int(int port_no, phy_interface_t phy_int);
602 #endif /* _VSC9953_H_ */