4 * Driver for the Vitesse VSC9953 L2 Switch
6 * This software may be used and distributed according to the
7 * terms of the GNU Public License, Version 2, incorporated
10 * Copyright 2013 Freescale Semiconductor, Inc.
19 #include <asm/types.h>
21 #define VSC9953_OFFSET (CONFIG_SYS_CCSRBAR_DEFAULT + 0x800000)
23 #define VSC9953_SYS_OFFSET 0x010000
24 #define VSC9953_REW_OFFSET 0x030000
25 #define VSC9953_DEV_GMII_OFFSET 0x100000
26 #define VSC9953_QSYS_OFFSET 0x200000
27 #define VSC9953_ANA_OFFSET 0x280000
28 #define VSC9953_DEVCPU_GCB 0x070000
29 #define VSC9953_ES0 0x040000
30 #define VSC9953_IS1 0x050000
31 #define VSC9953_IS2 0x060000
33 #define T1040_SWITCH_GMII_DEV_OFFSET 0x010000
34 #define VSC9953_PHY_REGS_OFFST 0x0000AC
36 /* Macros for vsc9953_chip_regs.soft_rst register */
37 #define VSC9953_SOFT_SWC_RST_ENA 0x00000001
39 /* Macros for vsc9953_sys_sys.reset_cfg register */
40 #define VSC9953_CORE_ENABLE 0x80
41 #define VSC9953_MEM_ENABLE 0x40
42 #define VSC9953_MEM_INIT 0x20
44 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ena_cfg register */
45 #define VSC9953_MAC_ENA_CFG 0x00000011
47 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_mode_cfg register */
48 #define VSC9953_MAC_MODE_CFG 0x00000011
50 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ifg_cfg register */
51 #define VSC9953_MAC_IFG_CFG 0x00000515
53 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_hdx_cfg register */
54 #define VSC9953_MAC_HDX_CFG 0x00001043
56 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_maxlen_cfg register */
57 #define VSC9953_MAC_MAX_LEN 0x000005ee
59 /* Macros for vsc9953_dev_gmii_port_mode.clock_cfg register */
60 #define VSC9953_CLOCK_CFG 0x00000001
61 #define VSC9953_CLOCK_CFG_1000M 0x00000001
63 /* Macros for vsc9953_sys_sys.front_port_mode register */
64 #define VSC9953_FRONT_PORT_MODE 0x00000000
66 /* Macros for vsc9953_ana_pfc.pfc_cfg register */
67 #define VSC9953_PFC_FC 0x00000001
68 #define VSC9953_PFC_FC_QSGMII 0x00000000
70 /* Macros for vsc9953_sys_pause_cfg.mac_fc_cfg register */
71 #define VSC9953_MAC_FC_CFG 0x04700000
72 #define VSC9953_MAC_FC_CFG_QSGMII 0x00700000
74 /* Macros for vsc9953_sys_pause_cfg.pause_cfg register */
75 #define VSC9953_PAUSE_CFG 0x001ffffe
77 /* Macros for vsc9953_sys_pause_cfgtot_tail_drop_lvl register */
78 #define VSC9953_TOT_TAIL_DROP_LVL 0x000003ff
80 /* Macros for vsc9953_sys_sys.stat_cfg register */
81 #define VSC9953_STAT_CLEAR_RX 0x00000400
82 #define VSC9953_STAT_CLEAR_TX 0x00000800
83 #define VSC9953_STAT_CLEAR_DR 0x00001000
85 /* Macros for vsc9953_vcap_core_cfg.vcap_mv_cfg register */
86 #define VSC9953_VCAP_MV_CFG 0x0000ffff
87 #define VSC9953_VCAP_UPDATE_CTRL 0x01000004
89 /* Macros for register vsc9953_ana_ana_tables.mac_access register */
90 #define VSC9953_MAC_CMD_IDLE 0x00000000
91 #define VSC9953_MAC_CMD_LEARN 0x00000001
92 #define VSC9953_MAC_CMD_FORGET 0x00000002
93 #define VSC9953_MAC_CMD_AGE 0x00000003
94 #define VSC9953_MAC_CMD_NEXT 0x00000004
95 #define VSC9953_MAC_CMD_READ 0x00000006
96 #define VSC9953_MAC_CMD_WRITE 0x00000007
97 #define VSC9953_MAC_CMD_MASK 0x00000007
98 #define VSC9953_MAC_CMD_VALID 0x00000800
99 #define VSC9953_MAC_ENTRYTYPE_NORMAL 0x00000000
100 #define VSC9953_MAC_ENTRYTYPE_LOCKED 0x00000200
101 #define VSC9953_MAC_ENTRYTYPE_IPV4MCAST 0x00000400
102 #define VSC9953_MAC_ENTRYTYPE_IPV6MCAST 0x00000600
103 #define VSC9953_MAC_ENTRYTYPE_MASK 0x00000600
104 #define VSC9953_MAC_DESTIDX_MASK 0x000001f8
105 #define VSC9953_MAC_VID_MASK 0x1fff0000
106 #define VSC9953_MAC_MACH_MASK 0x0000ffff
108 /* Macros for vsc9953_ana_port.vlan_cfg register */
109 #define VSC9953_VLAN_CFG_AWARE_ENA 0x00100000
110 #define VSC9953_VLAN_CFG_POP_CNT_MASK 0x000c0000
111 #define VSC9953_VLAN_CFG_POP_CNT_NONE 0x00000000
112 #define VSC9953_VLAN_CFG_POP_CNT_ONE 0x00040000
113 #define VSC9953_VLAN_CFG_VID_MASK 0x00000fff
115 /* Macros for vsc9953_rew_port.port_vlan_cfg register */
116 #define VSC9953_PORT_VLAN_CFG_VID_MASK 0x00000fff
118 /* Macros for vsc9953_ana_ana_tables.vlan_tidx register */
119 #define VSC9953_ANA_TBL_VID_MASK 0x00000fff
121 /* Macros for vsc9953_ana_ana_tables.vlan_access register */
122 #define VSC9953_VLAN_PORT_MASK 0x00001ffc
123 #define VSC9953_VLAN_CMD_MASK 0x00000003
124 #define VSC9953_VLAN_CMD_IDLE 0x00000000
125 #define VSC9953_VLAN_CMD_READ 0x00000001
126 #define VSC9953_VLAN_CMD_WRITE 0x00000002
127 #define VSC9953_VLAN_CMD_INIT 0x00000003
129 /* Macros for vsc9953_ana_port.port_cfg register */
130 #define VSC9953_PORT_CFG_LEARN_ENA 0x00000080
131 #define VSC9953_PORT_CFG_LEARN_AUTO 0x00000100
132 #define VSC9953_PORT_CFG_LEARN_CPU 0x00000200
133 #define VSC9953_PORT_CFG_LEARN_DROP 0x00000400
135 /* Macros for vsc9953_qsys_sys.switch_port_mode register */
136 #define VSC9953_PORT_ENA 0x00002000
138 /* Macros for vsc9953_ana_ana.adv_learn register */
139 #define VSC9953_VLAN_CHK 0x00000400
141 /* Macros for vsc9953_rew_port.port_tag_cfg register */
142 #define VSC9953_TAG_CFG_MASK 0x00000180
143 #define VSC9953_TAG_CFG_NONE 0x00000000
144 #define VSC9953_TAG_CFG_ALL_BUT_PVID_ZERO 0x00000080
145 #define VSC9953_TAG_CFG_ALL_BUT_ZERO 0x00000100
146 #define VSC9953_TAG_CFG_ALL 0x00000180
147 #define VSC9953_TAG_VID_PVID 0x00000010
149 /* Macros for vsc9953_ana_ana.anag_efil register */
150 #define VSC9953_AGE_PORT_EN 0x00080000
151 #define VSC9953_AGE_PORT_MASK 0x0007c000
152 #define VSC9953_AGE_VID_EN 0x00002000
153 #define VSC9953_AGE_VID_MASK 0x00001fff
155 /* Macros for vsc9953_ana_ana_tables.mach_data register */
156 #define VSC9953_MACHDATA_VID_MASK 0x1fff0000
158 #define VSC9953_MAX_PORTS 10
159 #define VSC9953_PORT_CHECK(port) \
160 (((port) < 0 || (port) >= VSC9953_MAX_PORTS) ? 0 : 1)
161 #define VSC9953_INTERNAL_PORT_CHECK(port) ( \
163 (port) < VSC9953_MAX_PORTS - 2 || (port) >= VSC9953_MAX_PORTS \
166 #define VSC9953_MAX_VLAN 4096
167 #define VSC9953_VLAN_CHECK(vid) \
168 (((vid) < 0 || (vid) >= VSC9953_MAX_VLAN) ? 0 : 1)
170 #define DEFAULT_VSC9953_MDIO_NAME "VSC9953_MDIO0"
172 #define MIIMIND_OPR_PEND 0x00000004
174 struct vsc9953_mdio_info {
175 struct vsc9953_mii_mng *regs;
179 /* VSC9953 ANA structure */
181 struct vsc9953_ana_port {
186 u32 vcap_s1_key_cfg[3];
188 u32 qos_pcp_dei_map_cfg[16];
190 u32 cpu_fwd_bpdu_cfg;
191 u32 cpu_fwd_garp_cfg;
198 struct vsc9953_ana_pol {
207 struct vsc9953_ana_ana_tables {
218 struct vsc9953_ana_ana {
224 u32 storm_limit_burst;
225 u32 storm_limit_cfg[4];
240 struct vsc9953_ana_pgid {
244 struct vsc9953_ana_pfc {
249 struct vsc9953_ana_pol_misc {
255 struct vsc9953_ana_common {
261 u32 vcap_rng_type_cfg;
262 u32 vcap_rng_val_cfg;
267 struct vsc9953_analyzer {
268 struct vsc9953_ana_port port[11];
270 struct vsc9953_ana_pol pol[164];
271 struct vsc9953_ana_ana_tables ana_tables;
273 struct vsc9953_ana_ana ana;
275 struct vsc9953_ana_pgid port_id_tbl;
277 struct vsc9953_ana_pfc pfc[10];
278 struct vsc9953_ana_pol_misc pol_misc;
280 struct vsc9953_ana_common common;
282 /* END VSC9953 ANA structure t*/
284 /* VSC9953 DEV_GMII structure */
286 struct vsc9953_dev_gmii_port_mode {
293 struct vsc9953_dev_gmii_mac_cfg_status {
301 u32 mac_fc_mac_low_cfg;
302 u32 mac_fc_mac_high_cfg;
306 struct vsc9953_dev_gmii {
307 struct vsc9953_dev_gmii_port_mode port_mode;
308 struct vsc9953_dev_gmii_mac_cfg_status mac_cfg_status;
311 /* END VSC9953 DEV_GMII structure */
313 /* VSC9953 QSYS structure */
315 struct vsc9953_qsys_hsch {
324 struct vsc9953_qsys_sys {
326 u32 switch_port_mode[11];
338 struct vsc9953_qsys_qos_cfg {
343 struct vsc9953_qsys_drop_cfg {
347 struct vsc9953_qsys_mmgt {
352 struct vsc9953_qsys_hsch_misc {
357 struct vsc9953_qsys_res_ctrl {
363 struct vsc9953_qsys_reg {
364 struct vsc9953_qsys_hsch hsch[108];
365 struct vsc9953_qsys_sys sys;
366 struct vsc9953_qsys_qos_cfg qos_cfg;
367 struct vsc9953_qsys_drop_cfg drop_cfg;
368 struct vsc9953_qsys_mmgt mmgt;
369 struct vsc9953_qsys_hsch_misc hsch_misc;
370 struct vsc9953_qsys_res_ctrl res_ctrl[1024];
373 /* END VSC9953 QSYS structure */
375 /* VSC9953 SYS structure */
377 struct vsc9953_rx_cntrs {
391 u32 c_rx_sz_512_1023;
392 u32 c_rx_sz_1024_1526;
406 u32 c_rx_yellow_prio_0;
407 u32 c_rx_yellow_prio_1;
408 u32 c_rx_yellow_prio_2;
409 u32 c_rx_yellow_prio_3;
410 u32 c_rx_yellow_prio_4;
411 u32 c_rx_yellow_prio_5;
412 u32 c_rx_yellow_prio_6;
413 u32 c_rx_yellow_prio_7;
414 u32 c_rx_green_prio_0;
415 u32 c_rx_green_prio_1;
416 u32 c_rx_green_prio_2;
417 u32 c_rx_green_prio_3;
418 u32 c_rx_green_prio_4;
419 u32 c_rx_green_prio_5;
420 u32 c_rx_green_prio_6;
421 u32 c_rx_green_prio_7;
425 struct vsc9953_tx_cntrs {
437 u32 c_tx_sz_512_1023;
438 u32 c_tx_sz_1024_1526;
440 u32 c_tx_yellow_prio_0;
441 u32 c_tx_yellow_prio_1;
442 u32 c_tx_yellow_prio_2;
443 u32 c_tx_yellow_prio_3;
444 u32 c_tx_yellow_prio_4;
445 u32 c_tx_yellow_prio_5;
446 u32 c_tx_yellow_prio_6;
447 u32 c_tx_yellow_prio_7;
448 u32 c_tx_green_prio_0;
449 u32 c_tx_green_prio_1;
450 u32 c_tx_green_prio_2;
451 u32 c_tx_green_prio_3;
452 u32 c_tx_green_prio_4;
453 u32 c_tx_green_prio_5;
454 u32 c_tx_green_prio_6;
455 u32 c_tx_green_prio_7;
460 struct vsc9953_drop_cntrs {
463 u32 c_dr_yellow_prio_0;
464 u32 c_dr_yellow_prio_1;
465 u32 c_dr_yellow_prio_2;
466 u32 c_dr_yellow_prio_3;
467 u32 c_dr_yellow_prio_4;
468 u32 c_dr_yellow_prio_5;
469 u32 c_dr_yellow_prio_6;
470 u32 c_dr_yellow_prio_7;
471 u32 c_dr_green_prio_0;
472 u32 c_dr_green_prio_1;
473 u32 c_dr_green_prio_2;
474 u32 c_dr_green_prio_3;
475 u32 c_dr_green_prio_4;
476 u32 c_dr_green_prio_5;
477 u32 c_dr_green_prio_6;
478 u32 c_dr_green_prio_7;
482 struct vsc9953_sys_stat {
483 struct vsc9953_rx_cntrs rx_cntrs;
484 struct vsc9953_tx_cntrs tx_cntrs;
485 struct vsc9953_drop_cntrs drop_cntrs;
489 struct vsc9953_sys_sys {
494 u32 front_port_mode[10];
500 struct vsc9953_sys_pause_cfg {
503 u32 tail_drop_level[11];
504 u32 tot_tail_drop_lvl;
508 struct vsc9953_sys_mmgt {
512 struct vsc9953_system_reg {
513 struct vsc9953_sys_stat stat;
514 struct vsc9953_sys_sys sys;
515 struct vsc9953_sys_pause_cfg pause_cfg;
516 struct vsc9953_sys_mmgt mmgt;
519 /* END VSC9953 SYS structure */
521 /* VSC9953 REW structure */
523 struct vsc9953_rew_port {
528 u32 port_pcp_dei_qos_map_cfg[16];
532 struct vsc9953_rew_common {
534 u32 dscp_remap_dp1_cfg[64];
535 u32 dscp_remap_cfg[64];
538 struct vsc9953_rew_reg {
539 struct vsc9953_rew_port port[12];
540 struct vsc9953_rew_common common;
543 /* END VSC9953 REW structure */
545 /* VSC9953 DEVCPU_GCB structure */
547 struct vsc9953_chip_regs {
553 struct vsc9953_gpio {
554 u32 gpio_out_set[10];
555 u32 gpio_out_clr[10];
560 struct vsc9953_mii_mng {
568 u32 miiscan_lst_rslts;
569 u32 miiscan_lst_rslts_valid;
572 struct vsc9953_mii_read_scan {
573 u32 mii_scan_results_sticky[2];
576 struct vsc9953_devcpu_gcb {
577 struct vsc9953_chip_regs chip_regs;
578 struct vsc9953_gpio gpio;
579 struct vsc9953_mii_mng mii_mng[2];
580 struct vsc9953_mii_read_scan mii_read_scan;
583 /* END VSC9953 DEVCPU_GCB structure */
585 /* VSC9953 IS* structure */
587 struct vsc9953_vcap_core_cfg {
588 u32 vcap_update_ctrl;
592 struct vsc9953_vcap {
593 struct vsc9953_vcap_core_cfg vcap_core_cfg;
596 /* END VSC9953 IS* structure */
598 #define VSC9953_PORT_INFO_INITIALIZER(idx) \
604 .enet_if = PHY_INTERFACE_MODE_NONE, \
609 /* Structure to describe a VSC9953 port */
610 struct vsc9953_port_info {
615 phy_interface_t enet_if;
617 struct phy_device *phydev;
620 /* Structure to describe a VSC9953 switch */
621 struct vsc9953_info {
622 struct vsc9953_port_info port[VSC9953_MAX_PORTS];
625 void vsc9953_init(bd_t *bis);
627 void vsc9953_port_info_set_mdio(int port_no, struct mii_dev *bus);
628 void vsc9953_port_info_set_phy_address(int port_no, int address);
629 void vsc9953_port_enable(int port_no);
630 void vsc9953_port_disable(int port_no);
631 void vsc9953_port_info_set_phy_int(int port_no, phy_interface_t phy_int);
633 #endif /* _VSC9953_H_ */