ARM: OMAP: GPIO: Fix valid range and enable usage of all GPIOs on OMAP5
[platform/kernel/u-boot.git] / include / video_ad7176.h
1 /*
2  * (C) Copyright 2000
3  * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
4  *
5  * See file CREDITS for list of people who contributed to this
6  * project.
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License as
10  * published by the Free Software Foundation; either version 2 of
11  * the License, or (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21  * MA 02111-1307 USA
22  */
23
24 #ifndef _VIDEO_AD7176_H_
25 #define _VIDEO_AD7176_H_
26
27 #define VIDEO_ENCODER_NAME      "Analog Devices AD7176"
28
29 #define VIDEO_ENCODER_I2C_RATE  100000  /* Max rate is 100 kHz          */
30 #define VIDEO_ENCODER_CB_Y_CR_Y         /* Use CB Y CR Y format...      */
31
32 #define VIDEO_MODE_YUYV         /* The only mode supported by this encoder */
33 #undef  VIDEO_MODE_RGB
34 #define VIDEO_MODE_BPP          16
35
36 #ifdef  VIDEO_MODE_PAL
37 #define VIDEO_ACTIVE_COLS       720
38 #define VIDEO_ACTIVE_ROWS       576
39 #define VIDEO_VISIBLE_COLS      640
40 #define VIDEO_VISIBLE_ROWS      480
41 #endif
42
43 #ifdef  VIDEO_MODE_NTSC
44 #define VIDEO_ACTIVE_COLS       720
45 #define VIDEO_ACTIVE_ROWS       525
46 #define VIDEO_VISIBLE_COLS      640
47 #define VIDEO_VISIBLE_ROWS      400
48 #endif
49
50 static unsigned char video_encoder_data[] = {
51 #ifdef VIDEO_MODE_NTSC
52                                         0x04, /* Mode Register 0        */
53 #ifdef VIDEO_DEBUG_COLORBARS
54                                         0x82,
55 #else
56                                         0x02, /* Mode Register 1        */
57 #endif  /* VIDEO_DEBUG_COLORBARS */
58                                         0x16, /* Subcarrier Freq 0      */
59                                         0x7c, /* Subcarrier Freq 1      */
60                                         0xf0, /* Subcarrier Freq 2      */
61                                         0x21, /* Subcarrier Freq 3      */
62                                         0x00, /* Subcarrier phase       */
63                                         0x02, /* Timing Register 0      */
64                                         0x00, /* Extended Captioning 0  */
65                                         0x00, /* Extended Captioning 1  */
66                                         0x00, /* Closed Captioning 0    */
67                                         0x00, /* Closed Captioning 1    */
68                                         0x00, /* Timing Register 1      */
69                                         0x08, /* Mode Register 2        */
70                                         0x00, /* Pedestal Register 0    */
71                                         0x00, /* Pedestal Register 1    */
72                                         0x00, /* Pedestal Register 2    */
73                                         0x00, /* Pedestal Register 3    */
74                                         0x00  /* Mode Register 3        */
75
76 #endif  /* VIDEO_MODE_NTSC */
77
78 #ifdef VIDEO_MODE_PAL
79                                         0x05, /* Mode Register 0        */
80 #ifdef VIDEO_DEBUG_COLORBARS
81                                         0x82,
82 #else
83                                         0x02, /* Mode Register 1 (2)    */
84 #endif  /* VIDEO_DEBUG_COLORBARS */
85                                         0xcb, /* Subcarrier Freq 0      */
86                                         0x8a, /* Subcarrier Freq 1      */
87                                         0x09, /* Subcarrier Freq 2      */
88                                         0x2a, /* Subcarrier Freq 3      */
89                                         0x00, /* Subcarrier phase       */
90                                         0x0a, /* Timing Register 0 (a)  */
91                                         0x00, /* Extended Captioning 0  */
92                                         0x00, /* Extended Captioning 1  */
93                                         0x00, /* Closed Captioning 0    */
94                                         0x00, /* Closed Captioning 1    */
95                                         0x00, /* Timing Register 1      */
96                                         0x08, /* Mode Register 2 (8)    */
97                                         0x00, /* Pedestal Register 0    */
98                                         0x00, /* Pedestal Register 1    */
99                                         0x00, /* Pedestal Register 2    */
100                                         0x00, /* Pedestal Register 3    */
101                                         0x00  /* Mode Register 3        */
102 #endif  /* VIDEO_MODE_PAL */
103 } ;
104
105 #endif  /* _VIDEO_AD7176_H_ */